From patchwork Sun Oct 22 15:18:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 13431860 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F156CC00A8F for ; Sun, 22 Oct 2023 15:24:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229500AbjJVPYX (ORCPT ); Sun, 22 Oct 2023 11:24:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231876AbjJVPYW (ORCPT ); Sun, 22 Oct 2023 11:24:22 -0400 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6BC1CF3; Sun, 22 Oct 2023 08:24:19 -0700 (PDT) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 39MFMJVR032675; Sun, 22 Oct 2023 23:22:19 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Sun, 22 Oct 2023 23:22:15 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 01/13] riscv: errata: Rename defines for Andes Date: Sun, 22 Oct 2023 23:18:46 +0800 Message-ID: <20231022151858.2479969-2-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231022151858.2479969-1-peterlin@andestech.com> References: <20231022151858.2479969-1-peterlin@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 39MFMJVR032675 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Using "ANDES" rather than "ANDESTECH" to unify the naming convention with directory, file names, Kconfig options and other definitions. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Charles Ci-Jyun Wu Reviewed-by: Leo Yu-Chi Liang --- Changes v1 -> v2: - No change Changes v2 -> v3: - Rewrote commit message (suggested by Conor) --- arch/riscv/errata/andes/errata.c | 10 +++++----- arch/riscv/include/asm/errata_list.h | 4 ++-- arch/riscv/include/asm/vendorid_list.h | 2 +- arch/riscv/kernel/alternative.c | 2 +- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c index 197db68cc8da..d2e1abcac967 100644 --- a/arch/riscv/errata/andes/errata.c +++ b/arch/riscv/errata/andes/errata.c @@ -18,9 +18,9 @@ #include #include -#define ANDESTECH_AX45MP_MARCHID 0x8000000000008a45UL -#define ANDESTECH_AX45MP_MIMPID 0x500UL -#define ANDESTECH_SBI_EXT_ANDES 0x0900031E +#define ANDES_AX45MP_MARCHID 0x8000000000008a45UL +#define ANDES_AX45MP_MIMPID 0x500UL +#define ANDES_SBI_EXT_ANDES 0x0900031E #define ANDES_SBI_EXT_IOCP_SW_WORKAROUND 1 @@ -32,7 +32,7 @@ static long ax45mp_iocp_sw_workaround(void) * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and * cache is controllable only then CMO will be applied to the platform. */ - ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND, + ret = sbi_ecall(ANDES_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND, 0, 0, 0, 0, 0, 0); return ret.error ? 0 : ret.value; @@ -43,7 +43,7 @@ static bool errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigne if (!IS_ENABLED(CONFIG_ERRATA_ANDES_CMO)) return false; - if (arch_id != ANDESTECH_AX45MP_MARCHID || impid != ANDESTECH_AX45MP_MIMPID) + if (arch_id != ANDES_AX45MP_MARCHID || impid != ANDES_AX45MP_MIMPID) return false; if (!ax45mp_iocp_sw_workaround()) diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index b55b434f0059..c190393aa9db 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -12,8 +12,8 @@ #include #ifdef CONFIG_ERRATA_ANDES -#define ERRATA_ANDESTECH_NO_IOCP 0 -#define ERRATA_ANDESTECH_NUMBER 1 +#define ERRATA_ANDES_NO_IOCP 0 +#define ERRATA_ANDES_NUMBER 1 #endif #ifdef CONFIG_ERRATA_SIFIVE diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h index e55407ace0c3..2f2bb0c84f9a 100644 --- a/arch/riscv/include/asm/vendorid_list.h +++ b/arch/riscv/include/asm/vendorid_list.h @@ -5,7 +5,7 @@ #ifndef ASM_VENDOR_LIST_H #define ASM_VENDOR_LIST_H -#define ANDESTECH_VENDOR_ID 0x31e +#define ANDES_VENDOR_ID 0x31e #define SIFIVE_VENDOR_ID 0x489 #define THEAD_VENDOR_ID 0x5b7 diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c index 319a1da0358b..0128b161bfda 100644 --- a/arch/riscv/kernel/alternative.c +++ b/arch/riscv/kernel/alternative.c @@ -43,7 +43,7 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufacturer_info_t *cpu_mfr_info switch (cpu_mfr_info->vendor_id) { #ifdef CONFIG_ERRATA_ANDES - case ANDESTECH_VENDOR_ID: + case ANDES_VENDOR_ID: cpu_mfr_info->patch_func = andes_errata_patch_func; break; #endif From patchwork Sun Oct 22 15:18:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 13431859 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3ED32CDB474 for ; Sun, 22 Oct 2023 15:24:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231859AbjJVPYW (ORCPT ); Sun, 22 Oct 2023 11:24:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231481AbjJVPYV (ORCPT ); Sun, 22 Oct 2023 11:24:21 -0400 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 579778E; Sun, 22 Oct 2023 08:24:18 -0700 (PDT) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 39MFMOhW032691; Sun, 22 Oct 2023 23:22:24 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Sun, 22 Oct 2023 23:22:20 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [RFC PATCH v3 02/13] irqchip/riscv-intc: Allow large non-standard hwirq number Date: Sun, 22 Oct 2023 23:18:47 +0800 Message-ID: <20231022151858.2479969-3-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231022151858.2479969-1-peterlin@andestech.com> References: <20231022151858.2479969-1-peterlin@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 39MFMOhW032691 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Currently, the implementation of the RISC-V INTC driver uses the interrupt cause as hwirq and has a limitation of supporting a maximum of 64 hwirqs. However, according to the privileged spec, interrupt causes >= 16 are defined for platform use. This limitation prevents us from fully utilizing the available local interrupt sources. Additionally, the hwirqs used on RISC-V are sparse, with only interrupt numbers 1, 5 and 9 (plus Sscofpmf or T-Head's PMU irq) being currently used for supervisor mode. The patch switches to using irq_domain_create_tree() which creates the radix tree map, allowing us to handle a larger number of hwirqs. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Charles Ci-Jyun Wu Reviewed-by: Leo Yu-Chi Liang --- Changes v1 -> v2: - Fixed irq mapping failure checking (suggested by Clément and Anup) Changes v2 -> v3: - No change --- drivers/irqchip/irq-riscv-intc.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index e8d01b14ccdd..79d049105384 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -24,10 +24,8 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs) { unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; - if (unlikely(cause >= BITS_PER_LONG)) - panic("unexpected interrupt cause"); - - generic_handle_domain_irq(intc_domain, cause); + if (generic_handle_domain_irq(intc_domain, cause)) + pr_warn("Failed to handle interrupt (cause: %ld)\n", cause); } /* @@ -117,8 +115,8 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn) { int rc; - intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG, - &riscv_intc_domain_ops, NULL); + intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, + NULL); if (!intc_domain) { pr_err("unable to add IRQ domain\n"); return -ENXIO; @@ -132,8 +130,6 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn) riscv_set_intc_hwnode_fn(riscv_intc_hwnode); - pr_info("%d local interrupts mapped\n", BITS_PER_LONG); - return 0; } From patchwork Sun Oct 22 15:18:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 13431862 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB8F6C25B41 for ; Sun, 22 Oct 2023 15:24:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231981AbjJVPY0 (ORCPT ); Sun, 22 Oct 2023 11:24:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231936AbjJVPYZ (ORCPT ); Sun, 22 Oct 2023 11:24:25 -0400 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B7718E; Sun, 22 Oct 2023 08:24:22 -0700 (PDT) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 39MFMTJX032707; Sun, 22 Oct 2023 23:22:29 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Sun, 22 Oct 2023 23:22:25 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [RFC PATCH v3 03/13] irqchip/riscv-intc: Introduce Andes IRQ chip Date: Sun, 22 Oct 2023 23:18:48 +0800 Message-ID: <20231022151858.2479969-4-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231022151858.2479969-1-peterlin@andestech.com> References: <20231022151858.2479969-1-peterlin@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 39MFMTJX032707 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org This commit adds support for the Andes IRQ chip, which provides IRQ mask/unmask functions to access the custom CSR (SLIE) where the non-standard S-mode local interrupt enable bits are located. The Andes INTC requires the "andestech,cpu-intc" compatible string to be present in interrupt-controller of cpu node. e.g., cpu0: cpu@0 { compatible = "andestech,ax45mp", "riscv"; ... cpu0-intc: interrupt-controller { #interrupt-cells = <0x01>; compatible = "andestech,cpu-intc", "riscv,cpu-intc"; interrupt-controller; }; }; Signed-off-by: Yu Chien Peter Lin Reviewed-by: Charles Ci-Jyun Wu Reviewed-by: Leo Yu-Chi Liang --- Changes v1 -> v2: - New patch Changes v2 -> v3: - Return -ENXIO if no valid compatible INTC found - Allow falling back to generic RISC-V INTC --- drivers/irqchip/irq-riscv-intc.c | 51 +++++++++++++++++++++++++- include/linux/irqchip/irq-riscv-intc.h | 12 ++++++ 2 files changed, 61 insertions(+), 2 deletions(-) create mode 100644 include/linux/irqchip/irq-riscv-intc.h diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index 79d049105384..a0efd645a142 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -45,6 +46,26 @@ static void riscv_intc_irq_unmask(struct irq_data *d) csr_set(CSR_IE, BIT(d->hwirq)); } +static void andes_intc_irq_mask(struct irq_data *d) +{ + unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); + + if (d->hwirq < ANDES_SLI_CAUSE_BASE) + csr_clear(CSR_IE, mask); + else + csr_clear(ANDES_CSR_SLIE, mask); +} + +static void andes_intc_irq_unmask(struct irq_data *d) +{ + unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); + + if (d->hwirq < ANDES_SLI_CAUSE_BASE) + csr_set(CSR_IE, mask); + else + csr_set(ANDES_CSR_SLIE, mask); +} + static void riscv_intc_irq_eoi(struct irq_data *d) { /* @@ -68,12 +89,37 @@ static struct irq_chip riscv_intc_chip = { .irq_eoi = riscv_intc_irq_eoi, }; +static struct irq_chip andes_intc_chip = { + .name = "RISC-V INTC", + .irq_mask = andes_intc_irq_mask, + .irq_unmask = andes_intc_irq_unmask, + .irq_eoi = riscv_intc_irq_eoi, +}; + static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { + struct fwnode_handle *fn = riscv_get_intc_hwnode(); + struct irq_chip *chip; + const char *cp; + int rc; + irq_set_percpu_devid(irq); - irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data, - handle_percpu_devid_irq, NULL, NULL); + + rc = fwnode_property_read_string(fn, "compatible", &cp); + if (rc) + return rc; + + if (strcmp(cp, "riscv,cpu-intc") == 0) + chip = &riscv_intc_chip; + else if (strcmp(cp, "andestech,cpu-intc") == 0) + chip = &andes_intc_chip; + else + return -ENXIO; + + irq_domain_set_info(d, irq, hwirq, chip, + d->host_data, handle_percpu_devid_irq, NULL, + NULL); return 0; } @@ -166,6 +212,7 @@ static int __init riscv_intc_init(struct device_node *node, } IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init); +IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init); #ifdef CONFIG_ACPI diff --git a/include/linux/irqchip/irq-riscv-intc.h b/include/linux/irqchip/irq-riscv-intc.h new file mode 100644 index 000000000000..87c105b5b545 --- /dev/null +++ b/include/linux/irqchip/irq-riscv-intc.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 Andes Technology Corporation + */ +#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_RISCV_INTC_H +#define __INCLUDE_LINUX_IRQCHIP_IRQ_RISCV_INTC_H + +#define ANDES_SLI_CAUSE_BASE 256 +#define ANDES_CSR_SLIE 0x9c4 +#define ANDES_CSR_SLIP 0x9c5 + +#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_RISCV_INTC_H */ From patchwork Sun Oct 22 15:18:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 13431858 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F6C3C001DF for ; Sun, 22 Oct 2023 15:24:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231616AbjJVPYV (ORCPT ); Sun, 22 Oct 2023 11:24:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229500AbjJVPYV (ORCPT ); Sun, 22 Oct 2023 11:24:21 -0400 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67A22EE; Sun, 22 Oct 2023 08:24:18 -0700 (PDT) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 39MFMYWu032724; Sun, 22 Oct 2023 23:22:34 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Sun, 22 Oct 2023 23:22:30 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string Date: Sun, 22 Oct 2023 23:18:49 +0800 Message-ID: <20231022151858.2479969-5-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231022151858.2479969-1-peterlin@andestech.com> References: <20231022151858.2479969-1-peterlin@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 39MFMYWu032724 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add "andestech,cpu-intc" compatible string which indicates that Andes specific local interrupt is supported on the core, e.g. AX45MP cores have 3 types of non-standard local interrupt can be handled in supervisor mode: - Slave port ECC error interrupt - Bus write transaction error interrupt - Performance monitor overflow interrupt These interrupts are enabled/disabled via a custom register SLIE instead of the standard interrupt enable register SIE. Signed-off-by: Yu Chien Peter Lin --- Changes v1 -> v2: - New patch Changes v2 -> v3: - Updated commit message - Fixed possible compatibles for Andes INTC --- Documentation/devicetree/bindings/riscv/cpus.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 97e8441eda1c..4c1bbcf07406 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -99,7 +99,12 @@ properties: const: 1 compatible: - const: riscv,cpu-intc + oneOf: + - items: + - enum: + - andestech,cpu-intc + - const: riscv,cpu-intc + - const: riscv,cpu-intc interrupt-controller: true From patchwork Sun Oct 22 15:18:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 13431863 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02C96CDB474 for ; Sun, 22 Oct 2023 15:24:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232202AbjJVPYj (ORCPT ); Sun, 22 Oct 2023 11:24:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48622 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232181AbjJVPYi (ORCPT ); Sun, 22 Oct 2023 11:24:38 -0400 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8046135; Sun, 22 Oct 2023 08:24:28 -0700 (PDT) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 39MFMdii032740; Sun, 22 Oct 2023 23:22:39 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Sun, 22 Oct 2023 23:22:35 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 05/13] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Date: Sun, 22 Oct 2023 23:18:50 +0800 Message-ID: <20231022151858.2479969-6-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231022151858.2479969-1-peterlin@andestech.com> References: <20231022151858.2479969-1-peterlin@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 39MFMdii032740 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org The Andes INTC allows AX45MP cores to handle custom local interrupts, such as the performance monitor overflow interrupt. Signed-off-by: Yu Chien Peter Lin --- Changes v1 -> v2: - New patch Changes v2 -> v3: - Fixed possible compatibles for Andes INTC --- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index 8a726407fb76..dfe27550af11 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -37,7 +37,7 @@ cpu0: cpu@0 { cpu0_intc: interrupt-controller { #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; + compatible = "andestech,cpu-intc", "riscv,cpu-intc"; interrupt-controller; }; };