From patchwork Wed Oct 25 12:05:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mukesh Ojha X-Patchwork-Id: 13436051 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26B29C0032E for ; Wed, 25 Oct 2023 12:05:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232666AbjJYMFb (ORCPT ); Wed, 25 Oct 2023 08:05:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234811AbjJYMF3 (ORCPT ); Wed, 25 Oct 2023 08:05:29 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF20E129; Wed, 25 Oct 2023 05:05:27 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39PAcYgi012244; Wed, 25 Oct 2023 12:05:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=vyQecuOeIjnpfvPPigrXzUOcLJ/f+FhVUGhffoBskJg=; b=XBkZVQ/wi3nM9ycUdH3vjGCw3/MdW0J1QLPxrwLQE16ORBwBCUe20+9HGPfoYfx/CSIV VxKVpMCPkUQcK2etAIKhy9KYjW5kQg50NtgGacTGN2vhK3SY/iyvSeOo7AkrKvmGmmp6 bahT0aQU3ToYxvMFbdMxDSDmyYSTeRw7pFuLeIG/HKnepEGwvBXldDNGDdZx3ZDGlPy9 bBxRsITQwpfH1Qi6/vG/NJKEFfRsp7Zviy4DE2ajkHwKAf1G/UOhbXsSGKUs/rWbegwT O5ZB0xm5WLeUuB7brSQ3L5x9gUG8xwS9wFmUeOjpj8DcHxFfxHQQHLVLVWTdHY4DxC8R DA== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3txngvher1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 25 Oct 2023 12:05:22 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39PC5LLL004621 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 25 Oct 2023 12:05:21 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Wed, 25 Oct 2023 05:05:19 -0700 From: Mukesh Ojha To: , , , CC: , , , Mukesh Ojha Subject: [PATCH v8 1/3] firmware: qcom_scm: provide a read-modify-write function Date: Wed, 25 Oct 2023 17:35:04 +0530 Message-ID: <1698235506-16993-2-git-send-email-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1698235506-16993-1-git-send-email-quic_mojha@quicinc.com> References: <1698235506-16993-1-git-send-email-quic_mojha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: bu1smIRz_zTzZpzVLpcAQ66OOdUZE5sd X-Proofpoint-ORIG-GUID: bu1smIRz_zTzZpzVLpcAQ66OOdUZE5sd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-25_01,2023-10-25_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 malwarescore=0 clxscore=1015 adultscore=0 spamscore=0 bulkscore=0 mlxlogscore=874 impostorscore=0 mlxscore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310170001 definitions=main-2310250104 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org It was realized by Srinivas K. that there is a need of read-modify-write scm exported function so that it can be used by multiple clients. Let's introduce qcom_scm_io_rmw() which masks out the bits and write the passed value to that bit-offset. Suggested-by: Srinivas Kandagatla Signed-off-by: Mukesh Ojha Tested-by: Kathiravan Thirumoorthy # IPQ9574 and IPQ5332 --- drivers/firmware/qcom/qcom_scm.c | 26 ++++++++++++++++++++++++++ include/linux/firmware/qcom/qcom_scm.h | 1 + 2 files changed, 27 insertions(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 520de9b5633a..25549178a30f 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -41,6 +42,8 @@ struct qcom_scm { int scm_vote_count; u64 dload_mode_addr; + /* Atomic context only */ + spinlock_t lock; }; struct qcom_scm_current_perm_info { @@ -481,6 +484,28 @@ static int qcom_scm_disable_sdi(void) return ret ? : res.result[0]; } +int qcom_scm_io_rmw(phys_addr_t addr, unsigned int mask, unsigned int val) +{ + unsigned int old, new; + int ret; + + if (!__scm) + return -EINVAL; + + spin_lock(&__scm->lock); + ret = qcom_scm_io_readl(addr, &old); + if (ret) + goto unlock; + + new = (old & ~mask) | (val & mask); + + ret = qcom_scm_io_writel(addr, new); +unlock: + spin_unlock(&__scm->lock); + return ret; +} +EXPORT_SYMBOL_GPL(qcom_scm_io_rmw); + static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) { struct qcom_scm_desc desc = { @@ -1824,6 +1849,7 @@ static int qcom_scm_probe(struct platform_device *pdev) return ret; mutex_init(&scm->scm_bw_lock); + spin_lock_init(&scm->lock); scm->path = devm_of_icc_get(&pdev->dev, NULL); if (IS_ERR(scm->path)) diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h index ccaf28846054..3a8bb2e603b3 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -82,6 +82,7 @@ bool qcom_scm_pas_supported(u32 peripheral); int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); +int qcom_scm_io_rmw(phys_addr_t addr, unsigned int mask, unsigned int val); bool qcom_scm_restore_sec_cfg_available(void); int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare); From patchwork Wed Oct 25 12:05:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mukesh Ojha X-Patchwork-Id: 13436052 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94A31C25B6F for ; Wed, 25 Oct 2023 12:05:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343547AbjJYMFd (ORCPT ); Wed, 25 Oct 2023 08:05:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49776 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234817AbjJYMFc (ORCPT ); Wed, 25 Oct 2023 08:05:32 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05F8713D; Wed, 25 Oct 2023 05:05:29 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39PBtLM8022310; Wed, 25 Oct 2023 12:05:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=vSKofYPsa03RJbREi08tRc0R0iEJlsOrG/RNjzwWdkc=; b=jvHwNNxmQx2aKrtny0U751r3ZO9j4apk1QIYPbI2wYT+kSfyAPrS7fiQXy/nAI0sMcn8 HXBE2Qyjri+y+yjCfEYHlkHCkMrNjIsXVQ/cse3ruNS6ajfskcKZ4LULAeHt47S4fxjN UQF0cA9cd7IMacanhfK/F/CEvmWxyzNpuJMytcS4dyeiFizu/lAkYl7WAhdwlq5JN7wf pbekD45uBiPmjpTeVPeRWuuRw4RmK82cQpaO3Pe+fMsLtxw3MbKrTHXDzfDm3JeJxIMz owO8WGkm4xQ7S56jqnontNEATZXJRHTtCbDNIbN7CGwZK3/Firtq8p9tugBWx15dYl5w SA== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3txuj7gtex-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 25 Oct 2023 12:05:26 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39PC5PSx023855 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 25 Oct 2023 12:05:25 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Wed, 25 Oct 2023 05:05:22 -0700 From: Mukesh Ojha To: , , , CC: , , , Mukesh Ojha , Poovendhan Selvaraj Subject: [PATCH v8 2/3] firmware: scm: Modify only the download bits in TCSR register Date: Wed, 25 Oct 2023 17:35:05 +0530 Message-ID: <1698235506-16993-3-git-send-email-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1698235506-16993-1-git-send-email-quic_mojha@quicinc.com> References: <1698235506-16993-1-git-send-email-quic_mojha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: spmp6QsPpnqI3g8NIrOm01asoLUmEUzO X-Proofpoint-GUID: spmp6QsPpnqI3g8NIrOm01asoLUmEUzO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-25_01,2023-10-25_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 spamscore=0 malwarescore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 mlxscore=0 adultscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310170001 definitions=main-2310250104 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Crashdump collection is done based on DLOAD bits of TCSR register. To retain other bits, scm driver need to read the register and modify only the DLOAD bits, as other bits in TCSR may have their own significance. Co-developed-by: Poovendhan Selvaraj Signed-off-by: Poovendhan Selvaraj Signed-off-by: Mukesh Ojha Tested-by: Kathiravan Thirumoorthy # IPQ9574 and IPQ5332 Reviewed-by: Dmitry Baryshkov --- drivers/firmware/qcom/qcom_scm.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 25549178a30f..f1c4a9f9a53f 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -4,6 +4,8 @@ */ #include +#include +#include #include #include #include @@ -117,6 +119,10 @@ static const u8 qcom_scm_cpu_warm_bits[QCOM_SCM_BOOT_MAX_CPUS] = { #define QCOM_SMC_WAITQ_FLAG_WAKE_ONE BIT(0) #define QCOM_SMC_WAITQ_FLAG_WAKE_ALL BIT(1) +#define QCOM_DLOAD_MASK GENMASK(5, 4) +#define QCOM_DLOAD_FULLDUMP 0x1 +#define QCOM_DLOAD_NODUMP 0x0 + static const char * const qcom_scm_convention_names[] = { [SMC_CONVENTION_UNKNOWN] = "unknown", [SMC_CONVENTION_ARM_32] = "smc arm 32", @@ -523,6 +529,7 @@ static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) static void qcom_scm_set_download_mode(bool enable) { + u32 val = enable ? QCOM_DLOAD_FULLDUMP : QCOM_DLOAD_NODUMP; bool avail; int ret = 0; @@ -532,8 +539,9 @@ static void qcom_scm_set_download_mode(bool enable) if (avail) { ret = __qcom_scm_set_dload_mode(__scm->dev, enable); } else if (__scm->dload_mode_addr) { - ret = qcom_scm_io_writel(__scm->dload_mode_addr, - enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0); + ret = qcom_scm_io_rmw(__scm->dload_mode_addr, + QCOM_DLOAD_MASK, + FIELD_PREP(QCOM_DLOAD_MASK, val)); } else { dev_err(__scm->dev, "No available mechanism for setting download mode\n"); From patchwork Wed Oct 25 12:05:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mukesh Ojha X-Patchwork-Id: 13436053 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B435C25B6D for ; Wed, 25 Oct 2023 12:05:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234128AbjJYMFg (ORCPT ); Wed, 25 Oct 2023 08:05:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343638AbjJYMFe (ORCPT ); Wed, 25 Oct 2023 08:05:34 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5800913A; Wed, 25 Oct 2023 05:05:32 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39PBt9ZS026441; Wed, 25 Oct 2023 12:05:28 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=o8EiwvG5EpeclZ0ydgq4Pl+Rn+5NagwHWfLIAQpsoFI=; b=OAw1P5GnGpZhCv3yGoIMyrUj7aHuC4aCUTwcDtPmn4jfV1OAgjECshqFHUt0PV/2Ua66 RxPGf666akLMfj0iIs7mrrLh9014CoYDh6x2DBhamEx/OxLmkWqxjlygrmfB0GjgITmQ XQ76j9MrLH6kGr3GZ2C/9RF/RKdmzX6lXVHlnpxWUI74PHlUyscbL+B8iD5TzG9LzUOU YaTTSOp3kV/lwrl/FIbYjxkBmTSDJB+OeSj+IHXZ6Ln2J5Lxy1EbkpPArA4Lp3qZzrBy giuwAGSIFo5wlAz+M7b+dqYFkgzQ+6G9vcfd64NaGGSn1VNRxrR+BQLTY3jRvdEf/4C1 oQ== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3txtbf0ypy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 25 Oct 2023 12:05:28 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39PC5SuB023867 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 25 Oct 2023 12:05:28 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Wed, 25 Oct 2023 05:05:25 -0700 From: Mukesh Ojha To: , , , CC: , , , Mukesh Ojha Subject: [PATCH v8 3/3] pinctrl: qcom: Use qcom_scm_io_rmw() function Date: Wed, 25 Oct 2023 17:35:06 +0530 Message-ID: <1698235506-16993-4-git-send-email-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1698235506-16993-1-git-send-email-quic_mojha@quicinc.com> References: <1698235506-16993-1-git-send-email-quic_mojha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: hV-R2xh34a-yxG32YEq9y5pO-Kk9T0LD X-Proofpoint-ORIG-GUID: hV-R2xh34a-yxG32YEq9y5pO-Kk9T0LD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-25_01,2023-10-25_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 clxscore=1015 bulkscore=0 phishscore=0 adultscore=0 mlxlogscore=739 spamscore=0 suspectscore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310170001 definitions=main-2310250104 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use qcom_scm_io_rmw() exported function in pinctrl-msm driver. Signed-off-by: Mukesh Ojha Acked-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-msm.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 395040346d0f..9323b916cd7c 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -1078,22 +1078,20 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) if (g->intr_target_width) intr_target_mask = GENMASK(g->intr_target_width - 1, 0); + intr_target_mask <<= g->intr_target_bit; if (pctrl->intr_target_use_scm) { u32 addr = pctrl->phys_base[0] + g->intr_target_reg; int ret; - qcom_scm_io_readl(addr, &val); - val &= ~(intr_target_mask << g->intr_target_bit); - val |= g->intr_target_kpss_val << g->intr_target_bit; - - ret = qcom_scm_io_writel(addr, val); + val = g->intr_target_kpss_val << g->intr_target_bit; + ret = qcom_scm_io_rmw(addr, intr_target_mask, val); if (ret) dev_err(pctrl->dev, "Failed routing %lu interrupt to Apps proc", d->hwirq); } else { val = msm_readl_intr_target(pctrl, g); - val &= ~(intr_target_mask << g->intr_target_bit); + val &= ~intr_target_mask; val |= g->intr_target_kpss_val << g->intr_target_bit; msm_writel_intr_target(val, pctrl, g); }