From patchwork Wed Oct 25 19:29:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Edwin Torok X-Patchwork-Id: 13436607 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8ACC5C25B6B for ; Wed, 25 Oct 2023 19:30:26 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.623191.970804 (Exim 4.92) (envelope-from ) id 1qvjZs-0001my-QW; Wed, 25 Oct 2023 19:30:04 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 623191.970804; Wed, 25 Oct 2023 19:30:04 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qvjZs-0001mj-N8; Wed, 25 Oct 2023 19:30:04 +0000 Received: by outflank-mailman (input) for mailman id 623191; Wed, 25 Oct 2023 19:30:03 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qvjZr-0001Lv-5e for xen-devel@lists.xenproject.org; Wed, 25 Oct 2023 19:30:03 +0000 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [2a00:1450:4864:20::536]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id e27fa6c8-736c-11ee-9b0e-b553b5be7939; Wed, 25 Oct 2023 21:29:59 +0200 (CEST) Received: by mail-ed1-x536.google.com with SMTP id 4fb4d7f45d1cf-53e3b8f906fso97551a12.2 for ; Wed, 25 Oct 2023 12:29:59 -0700 (PDT) Received: from edvint-x-u.eng.citrite.net ([185.25.67.249]) by smtp.gmail.com with ESMTPSA id hv6-20020a17090760c600b00985ed2f1584sm10408710ejc.187.2023.10.25.12.29.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 12:29:57 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e27fa6c8-736c-11ee-9b0e-b553b5be7939 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1698262198; x=1698866998; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/A/ZtRiyebqcEugV20RrAicCfJuzgWaLmL2OdhFzID8=; b=iGK4fpP2GLTiW/3k9ajlXfm6NcidMdRUgjNXW4VZKN7sX37tkBbqSujxdpG61O7DKC L+Yec4mpB+7S7V0DTeqYC+FD9L13FYZMAq0kd1L++tuF+RrrmjVgmrlRzouDx9DigsrJ +nsSSLOlGDUof1c4u33KJ68PYJpyumkl0uSBM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698262198; x=1698866998; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/A/ZtRiyebqcEugV20RrAicCfJuzgWaLmL2OdhFzID8=; b=XdybLkpFsGrUYeU/q7csb7GXdz8DottBhECHjgpXJFCjKxu976GOQar77i1+qMC44B g2D0M6gCxBFimHYA/16zQy21qm2+xldOaGlxycekiH7uYS8rdff02/p4CW3AZjLW4yex XkDOSKarJgNsIeLFH6rcAHdjXAs1v8jr79Me2JJS0o8g+uQI41/AuYj0SEOkrqEc7U+z NP6HB0NURNh74bMpDLjTgl69oZwFOBHKxsE3q/P2I0GOjs05BuTXj9DHxNR/8TrVVPBG wxdMXz1d4MGxYCbjSmqUTYdwdpf0pkVVVRn0Fpp+eXuyfUIH7pK9FVFLQDmXgwW+Ti1l lZ3w== X-Gm-Message-State: AOJu0YxOF+1q/HmvCTJxbEcMNJ+D6YU/jlzStzu/NY7vGOr8naYZpkan bJvjT71cQLtBNGGbmNdVGZyaG+hg4T2lcuQqP3c6UFSb X-Google-Smtp-Source: AGHT+IEzv3+OZXF7rpkTdLtgQRfAeXrM3F1CjoGpIFODMCInYL1OGkCIJ/S/jPBsn4pEyCpibdOo+w== X-Received: by 2002:a17:907:720f:b0:9ae:6a60:81a2 with SMTP id dr15-20020a170907720f00b009ae6a6081a2mr11358501ejc.25.1698262198095; Wed, 25 Oct 2023 12:29:58 -0700 (PDT) From: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [RFC PATCH 01/22] x86/msr: MSR_PLATFORM_INFO shouldn't claim that turbo is programmable Date: Wed, 25 Oct 2023 20:29:31 +0100 Message-Id: <17a99e1da838a2edeeffa5a988e22c6fcb31406b.1698261255.git.edwin.torok@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Edwin Török Xen forbids writes to the various turbo control MSRs, however MSR_PLATFORM_INFO claims that these MSRs are writable. Override MSR_PLATFORM_INFO bits to indicate lack of support. See Intel SDM Volume 4, 2.17.6 "MSRs Introduced in the Intel Xeon Scaslable Processor Family", which describes that MSR_PLATFORM_INFO.[28] = 1 implies that MSR_TURBO_RATIO_LIMIT is R/W, and similarly bit 29 for TDP control, and bit 30 for MSR_TEMPERATURE_TARGET. These bits were not all present on earlier processors, however where missing the bits were reserved, and when present they are always present in the same bits. (Curiously bit 31 that Xen uses is not documented anywhere in this manual but a separate one). Backport: 4.0+ Signed-off-by: Edwin Török --- xen/arch/x86/cpu-policy.c | 8 ++++++++ xen/include/xen/lib/x86/cpu-policy.h | 5 ++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index 81e574390f..64c8857a61 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -407,6 +407,14 @@ static void __init calculate_host_policy(void) /* 0x000000ce MSR_INTEL_PLATFORM_INFO */ /* probe_cpuid_faulting() sanity checks presence of MISC_FEATURES_ENABLES */ p->platform_info.cpuid_faulting = cpu_has_cpuid_faulting; + + /* Xen denies write access to turbo control MSRs, however natively the CPU may support them + and advertise those MSRs as writable by having bits 28 to 30 set to 1 in MSR_PLATFORM_INFO. + Set these bits to 0 to avoid confusing guests on the availability of turbo controls. + */ + p->platform_info.programmable_ratio_turbo = 0; + p->platform_info.programmable_tdp_turbo = 0; + p->platform_info.programmable_tj_offset = 0; } static void __init guest_common_max_feature_adjustments(uint32_t *fs) diff --git a/xen/include/xen/lib/x86/cpu-policy.h b/xen/include/xen/lib/x86/cpu-policy.h index bab3eecda6..70479689f2 100644 --- a/xen/include/xen/lib/x86/cpu-policy.h +++ b/xen/include/xen/lib/x86/cpu-policy.h @@ -339,7 +339,10 @@ struct cpu_policy union { uint32_t raw; struct { - uint32_t :31; + uint32_t :28; + bool programmable_ratio_turbo:1; + bool programmable_tdp_turbo:1; + bool programmable_tj_offset:1; bool cpuid_faulting:1; }; } platform_info; From patchwork Wed Oct 25 19:29:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Edwin Torok X-Patchwork-Id: 13436605 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7FEECC0032E for ; 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Wed, 25 Oct 2023 12:29:59 -0700 (PDT) From: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [RFC PATCH 02/22] x86/msr: implement MSR_SMI_COUNT for Dom0 on Intel Date: Wed, 25 Oct 2023 20:29:32 +0100 Message-Id: <9d950b3c5502b5fb5fad62845b56b15d1bacc2d6.1698261255.git.edwin.torok@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Edwin Török Dom0 should always be able to read this MSR: it is useful when investigating performance issues in production. Although the count is Thread scoped, in practice all cores were observed to return the same count (perhaps due to implementation details of SMM), so do not require the cpu to be pinned in order to read it. This MSR exists on Intel since Nehalem. Backport: 4.15+ Signed-off-by: Edwin Török --- xen/arch/x86/include/asm/msr-index.h | 3 +++ xen/arch/x86/msr.c | 7 +++++++ 2 files changed, 10 insertions(+) diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 82a81bd0a2..2853a276ca 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -641,6 +641,9 @@ #define MSR_NHL_LBR_SELECT 0x000001c8 #define MSR_NHL_LASTBRANCH_TOS 0x000001c9 +/* Nehalem and newer other MSRs */ +#define MSR_SMI_COUNT 0x00000034 + /* Skylake (and newer) last-branch recording */ #define MSR_SKL_LASTBRANCH_0_FROM_IP 0x00000680 #define MSR_SKL_LASTBRANCH_0_TO_IP 0x000006c0 diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index c33dc78cd8..0bf6d263e7 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -139,6 +139,13 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val) *val = msrs->misc_features_enables.raw; break; + case MSR_SMI_COUNT: + if ( cp->x86_vendor != X86_VENDOR_INTEL ) + goto gp_fault; + if ( is_hardware_domain(d) && !rdmsr_safe(msr, *val) ) + break; + return X86EMUL_UNHANDLEABLE; + case MSR_P5_MC_ADDR: case MSR_P5_MC_TYPE: case MSR_IA32_MCG_CAP ... MSR_IA32_MCG_CTL: /* 0x179 -> 0x17b */ From patchwork Wed Oct 25 19:29:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Edwin Torok X-Patchwork-Id: 13436600 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72B69C07545 for ; Wed, 25 Oct 2023 19:30:17 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.623190.970794 (Exim 4.92) (envelope-from ) id 1qvjZq-0001D9-D8; Wed, 25 Oct 2023 19:30:02 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 623190.970794; Wed, 25 Oct 2023 19:30:02 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qvjZq-0001Ce-93; Wed, 25 Oct 2023 19:30:02 +0000 Received: by outflank-mailman (input) for mailman id 623190; Wed, 25 Oct 2023 19:30:01 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qvjZp-0000YO-9H for xen-devel@lists.xenproject.org; Wed, 25 Oct 2023 19:30:01 +0000 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [2a00:1450:4864:20::633]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id e3990980-736c-11ee-98d5-6d05b1d4d9a1; Wed, 25 Oct 2023 21:30:00 +0200 (CEST) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-9b9faf05f51so19301666b.2 for ; Wed, 25 Oct 2023 12:30:00 -0700 (PDT) Received: from edvint-x-u.eng.citrite.net ([185.25.67.249]) by smtp.gmail.com with ESMTPSA id hv6-20020a17090760c600b00985ed2f1584sm10408710ejc.187.2023.10.25.12.29.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 12:29:59 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e3990980-736c-11ee-98d5-6d05b1d4d9a1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1698262200; x=1698867000; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AV8cFJRyXmuzAeVTWIZF+6fXtuxkE7JeXBoOk4GQqQ8=; b=V/jd0DiPJPJKN3g1eoVykvl5A/YVdmmGz2H3XsZHtWsaMe2Xa5ty2rqPg3k+D0r9ef 2uaNPhSPcyy7m78YmgwGajYkfyr1uvXcdnTr0aoSCGNvtjFRTbdfpHMwQSRSK6mzkkT0 3BAnPfdMND2AifhfbuqUzgimLo9kJg13MQA1I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698262200; x=1698867000; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AV8cFJRyXmuzAeVTWIZF+6fXtuxkE7JeXBoOk4GQqQ8=; b=uNM+D314ZyHry0IuVEG5icCPDOR6dadA0T3lnsxtUuYyMfDsEFuRBpy+Ardt2XMFTC BQVSCU/C1ECGWz6bWxtwqtGULZ51n5ORyxekkbpPLSV3qr9RY18c1aGsT0KpVSGqmujv HSu4mZEXYSTZNJ6KUPjmU82vuyDEhZOm1NiCG2ZsFJ3d1nPQfOigTUI78wTGJr+IrwM7 fpShYJfo5KAyxCXYLeYtH7U6bjMogFsbHwe1P5RHTSpQdh9/cgqEE+NFo9Y+8dQVlLgF k7R06Ae1kj4bbTKt+P2lV+SXY1/upL1iPl9eE3VCHT401NcQwP5DsoUBHZ7//ID1J8Mc Inkw== X-Gm-Message-State: AOJu0YxWXIdT8bAJ5t5nhnuued8BaMxu3j2KPDcykx8LPZ0gJQgnnFBX b/Bb1UWuhENCsFzP9dr2VbCZkuQ43TJl4NYbdszeqRVp X-Google-Smtp-Source: AGHT+IFSB91m9XecdFlMZKXJ8BhUA1FJUNNvHyj1W5JVQeJmoQQHkNyOpxuPm6OLRRZhj961GioxLQ== X-Received: by 2002:a17:906:fe48:b0:9c4:4b20:44a1 with SMTP id wz8-20020a170906fe4800b009c44b2044a1mr12987267ejb.65.1698262200084; Wed, 25 Oct 2023 12:30:00 -0700 (PDT) From: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , Jun Nakajima , Kevin Tian Subject: [RFC PATCH 03/22] x86/msr: always allow a pinned Dom0 to read any unknown MSR Date: Wed, 25 Oct 2023 20:29:33 +0100 Message-Id: <4c04e5661688cf1de3e3fd668b0a78b23b6d7b2e.1698261255.git.edwin.torok@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Edwin Török This can be useful if you realize you have to inspect the value of an MSR in production, without having to change into a new Xen first that handles the MSR. E.g. SMI count didn't use to be explicitly allowed in the past (it now is, see a previous commit), but there could be other MSRs that are useful when tracking down issues. Backport: 4.15+ Signed-off-by: Edwin Török --- xen/arch/x86/hvm/svm/svm.c | 3 +++ xen/arch/x86/hvm/vmx/vmx.c | 3 +++ xen/arch/x86/pv/emul-priv-op.c | 3 +++ 3 files changed, 9 insertions(+) diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 24c417ca71..45f8e1ffd1 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -1933,6 +1933,9 @@ static int cf_check svm_msr_read_intercept( break; default: + if ( is_hwdom_pinned_vcpu(v) && !rdmsr_safe(msr, *msr_content) ) + break; + if ( d->arch.msr_relaxed && !rdmsr_safe(msr, tmp) ) { *msr_content = 0; diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 1edc7f1e91..f6e5123f66 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -3377,6 +3377,9 @@ static int cf_check vmx_msr_read_intercept( if ( vmx_read_guest_msr(curr, msr, msr_content) == 0 ) break; + if ( is_hwdom_pinned_vcpu(curr) && !rdmsr_safe(msr, *msr_content) ) + return X86EMUL_OKAY; + if ( is_last_branch_msr(msr) ) { *msr_content = 0; diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index 0d9f84f458..978ae679a2 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -985,6 +985,9 @@ static int cf_check read_msr( } /* fall through */ default: + if ( is_hwdom_pinned_vcpu(curr) && !rdmsr_safe(reg, *val) ) + return X86EMUL_OKAY; + if ( currd->arch.msr_relaxed && !rdmsr_safe(reg, tmp) ) { *val = 0; From patchwork Wed Oct 25 19:29:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Edwin Torok X-Patchwork-Id: 13436599 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C27CAC0032E for ; Wed, 25 Oct 2023 19:30:16 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.623192.970807 (Exim 4.92) (envelope-from ) id 1qvjZt-0001qN-4u; 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Wed, 25 Oct 2023 12:30:01 -0700 (PDT) From: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [RFC PATCH 04/22] x86/msr-index: add references to vendor manuals Date: Wed, 25 Oct 2023 20:29:34 +0100 Message-Id: <7e4418cfb1daa172e78fc47098a4018ae0493e23.1698261255.git.edwin.torok@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Edwin Török To more easily lookup the semantics of these MSRs add references to vendor manuals. Signed-off-by: Edwin Török --- xen/arch/x86/include/asm/msr-index.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 2853a276ca..8601f8f426 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -13,6 +13,16 @@ * Blocks of related constants should be sorted by MSR index. The constant * names should be as concise as possible, and the bit names may have an * abbreviated name. Exceptions will be considered on a case-by-case basis. + * + * References: + * - https://software.intel.com/content/www/us/en/develop/articles/intel-sdm.html + * Intel(R) 64 and IA-32 architectures SDM volume 4: Model-specific registers + * Chapter 2, "Model-Specific Registers (MSRs)" + * + * - https://developer.amd.com/resources/developer-guides-manuals/ + * AMD64 Architecture Programmer’s Manual Volume 2: System Programming + * Appendix A "MSR Cross-Reference" + * */ #define MSR_P5_MC_ADDR 0 From patchwork Wed Oct 25 19:29:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Edwin Torok X-Patchwork-Id: 13436609 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BF8FCC0032E for ; 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Wed, 25 Oct 2023 12:30:01 -0700 (PDT) From: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= , Jun Nakajima , Kevin Tian , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [RFC PATCH 05/22] x86/PMUv1: report correct information in 0xa CPUID Date: Wed, 25 Oct 2023 20:29:35 +0100 Message-Id: <4a00165999a0cc250f097fc8eaab0649f1c05ac0.1698261255.git.edwin.torok@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Edwin Török The 0xa CPUID leaf has to report supported number of: - fixed performance counters - general purpose performance counters - architectural predefined events And the PMU version (which was already limited to 3). Type punning is used, which should be safe due to -fno-strict-aliasing. This limits the number of arch events supported when vpmu=arch on Icelake. Backport: 4.0+ Signed-off-by: Edwin Török --- xen/arch/x86/cpu/vpmu_intel.c | 2 +- xen/arch/x86/cpuid.c | 39 ++++++++++++++++++++++++++++++--- xen/arch/x86/include/asm/vpmu.h | 4 ++++ 3 files changed, 41 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index fa5b40c65c..9602728f1b 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -66,7 +66,7 @@ static bool_t __read_mostly full_width_write; #define ARCH_CNTR_PIN_CONTROL (1ULL << 19) /* Number of general-purpose and fixed performance counters */ -static unsigned int __read_mostly arch_pmc_cnt, fixed_pmc_cnt; +unsigned int __read_mostly arch_pmc_cnt, fixed_pmc_cnt; /* Masks used for testing whether and MSR is valid */ #define ARCH_CTRL_MASK (~((1ull << 32) - 1) | (1ull << 21) | ARCH_CNTR_PIN_CONTROL) diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c index 455a09b2dd..dfbcd1b3a4 100644 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -304,9 +304,42 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf, *res = EMPTY_LEAF; else { - /* Report at most v3 since that's all we currently emulate. */ - if ( (res->a & 0xff) > 3 ) - res->a = (res->a & ~0xff) | 3; + union { + uint32_t eax; + struct { + uint8_t version; + uint8_t general_nr; + uint8_t general_width; + uint8_t arch_nr; + }; + } u; + u.eax = res->a; + + /* Report at most VPMU_VERSION_MAX since that's all we currently emulate. */ + if ( u.version > VPMU_VERSION_MAX ) { + gdprintk(XENLOG_WARNING, "Limiting PMU version to %d (actual %d)", VPMU_VERSION_MAX, u.version); + u.version = VPMU_VERSION_MAX; + } + + if ( u.general_nr > arch_pmc_cnt ) { + gdprintk(XENLOG_WARNING, "Limiting general purpose PMU count to %d (actual %d)", arch_pmc_cnt, u.general_nr); + u.general_nr = arch_pmc_cnt; + } + + if ( vpmu_features & (XENPMU_FEATURE_IPC_ONLY | + XENPMU_FEATURE_ARCH_ONLY) ) { + unsigned limit = ( vpmu_features & XENPMU_FEATURE_ARCH_ONLY ) ? 7 : 3; + if (limit < u.arch_nr) { + gdprintk(XENLOG_WARNING, "Limiting architectural PMU events to %d (actual %d)", limit, u.arch_nr); + u.arch_nr = limit; + } + } + + res->a = u.eax; + + /* We only implement 3 fixed function counters */ + if ( (res->d & 0x1f) > fixed_pmc_cnt ) + res->d = (res->d & ~0x1f) | fixed_pmc_cnt; } break; diff --git a/xen/arch/x86/include/asm/vpmu.h b/xen/arch/x86/include/asm/vpmu.h index b165acc6c2..1ef6089ccb 100644 --- a/xen/arch/x86/include/asm/vpmu.h +++ b/xen/arch/x86/include/asm/vpmu.h @@ -74,6 +74,8 @@ struct vpmu_struct { #define VPMU_CPU_HAS_DS 0x1000 /* Has Debug Store */ #define VPMU_CPU_HAS_BTS 0x2000 /* Has Branch Trace Store */ +#define VPMU_VERSION_MAX 0x3 + static inline void vpmu_set(struct vpmu_struct *vpmu, const u32 mask) { vpmu->flags |= mask; @@ -118,6 +120,8 @@ static inline int vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content) extern unsigned int vpmu_mode; extern unsigned int vpmu_features; +extern unsigned int arch_pmc_cnt; +extern unsigned int fixed_pmc_cnt; /* Context switch */ static inline void vpmu_switch_from(struct vcpu *prev) From patchwork Wed Oct 25 19:29:36 2023 Content-Type: text/plain; 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Wed, 25 Oct 2023 12:30:02 -0700 (PDT) From: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= , Jun Nakajima , Kevin Tian , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [RFC PATCH 06/22] x86/PMUv1: limit arch PMCs to 4 for non-Dom0 Date: Wed, 25 Oct 2023 20:29:36 +0100 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Edwin Török Only PERFEVTSEL{0-3} are architectural MSRs and Thread scoped. PERFEVTSEL{4-7} are Core scoped, and we cannot allow using them if more than 1 guest can attempt to modify them: if they program them with different events (quite likely when multiplexing) then one of the VMs would sample the wrong PMCs. For now only allow this when Dom0 is the only one using the PMU, i.e. in vpmu mode `all`. We could also allow this when sched_gran >= SCHED_GRAN_core, but we don't have access to the cpupool here. There is some indication that this was causing bugs, e.g. `pcm` mentions about a bug with perf counters beyond 3 on AWS: https://github.com/opcm/pcm/commit/02f3b00f304401c723131372e09b71798df613ff Backport: 4.0+ Signed-off-by: Edwin Török --- xen/arch/x86/cpu/vpmu_intel.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index 9602728f1b..ec9ab01fde 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -926,6 +926,16 @@ const struct arch_vpmu_ops *__init core2_vpmu_init(void) } arch_pmc_cnt = core2_get_arch_pmc_count(); + if ( arch_pmc_cnt > 4 && + vpmu_mode != XENPMU_MODE_ALL ) + { + /* Architectural PMCs 0-3 are Thread scoped, but 4+ are Core scoped. + * We can only allow using them if we know that we have at most one guest using a PMU + * on all siblings threads on a core. */ + printk(XENLOG_INFO "VPMU: limiting architectural PMCs to 4\n"); + arch_pmc_cnt = 4; + } + fixed_pmc_cnt = core2_get_fixed_pmc_count(); if ( cpu_has_pdcm ) From patchwork Wed Oct 25 19:29:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Edwin Torok X-Patchwork-Id: 13436611 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4DC8CC07545 for ; Wed, 25 Oct 2023 19:30:34 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.623195.970843 (Exim 4.92) (envelope-from ) id 1qvjZw-00030V-H3; Wed, 25 Oct 2023 19:30:08 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 623195.970843; Wed, 25 Oct 2023 19:30:08 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qvjZw-0002z1-AO; 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Wed, 25 Oct 2023 12:30:03 -0700 (PDT) From: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= , Jun Nakajima , Kevin Tian , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [RFC PATCH 07/22] x86/PMUv1: allow topdown slots arch perf event Date: Wed, 25 Oct 2023 20:29:37 +0100 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Edwin Török This is part of 'Architectural Performance Monitoring Version 1' and implemented on Icelake. Backport: 4.13+ Signed-off-by: Edwin Török --- xen/arch/x86/cpu/vpmu_intel.c | 1 + xen/arch/x86/cpuid.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index ec9ab01fde..44a1ed5b10 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -645,6 +645,7 @@ static int cf_check core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content) case 0x412e: /* Last Level Cache Misses */ case 0x00c4: /* Branch Instructions Retired */ case 0x00c5: /* All Branch Mispredict Retired */ + case 0x01a4: /* Topdown Slots */ blocked = 0; break; } diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c index dfbcd1b3a4..51ee89afc4 100644 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -328,7 +328,7 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf, if ( vpmu_features & (XENPMU_FEATURE_IPC_ONLY | XENPMU_FEATURE_ARCH_ONLY) ) { - unsigned limit = ( vpmu_features & XENPMU_FEATURE_ARCH_ONLY ) ? 7 : 3; + unsigned limit = ( vpmu_features & XENPMU_FEATURE_ARCH_ONLY ) ? 8 : 3; if (limit < u.arch_nr) { gdprintk(XENLOG_WARNING, "Limiting architectural PMU events to %d (actual %d)", limit, u.arch_nr); u.arch_nr = limit; From patchwork Wed Oct 25 19:29:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Edwin Torok X-Patchwork-Id: 13436602 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D0F32C25B6B for ; Wed, 25 Oct 2023 19:30:19 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.623196.970849 (Exim 4.92) (envelope-from ) id 1qvjZx-00037A-6x; Wed, 25 Oct 2023 19:30:09 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 623196.970849; Wed, 25 Oct 2023 19:30:09 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qvjZw-00035p-OP; Wed, 25 Oct 2023 19:30:08 +0000 Received: by outflank-mailman (input) for mailman id 623196; Wed, 25 Oct 2023 19:30:07 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qvjZv-0001Lv-QS for xen-devel@lists.xenproject.org; Wed, 25 Oct 2023 19:30:07 +0000 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [2a00:1450:4864:20::636]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id e659d384-736c-11ee-9b0e-b553b5be7939; Wed, 25 Oct 2023 21:30:05 +0200 (CEST) Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-98377c5d53eso22281666b.0 for ; Wed, 25 Oct 2023 12:30:05 -0700 (PDT) Received: from edvint-x-u.eng.citrite.net ([185.25.67.249]) by smtp.gmail.com with ESMTPSA id hv6-20020a17090760c600b00985ed2f1584sm10408710ejc.187.2023.10.25.12.30.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 12:30:03 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e659d384-736c-11ee-9b0e-b553b5be7939 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1698262205; x=1698867005; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fyM84Qdg+WVAc6W6qy0lJuiinDdESDwhb8Pnza3zSdg=; b=TREcwNwslcqulnMJM9Y6FLewz5cHe1Hz4X+rjmMCi/K/8iqnFKZInoxPSbmIcwLNhp iT8GzVo/CcyQvtenaoxKN/aHbOy0inyQVricThg5p9q1hGCrEcx9GXH8KiwarYm8PaYH GGT95TTX9HRg0kp9fLAZfAmjdH2abr7fM6oUA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698262205; x=1698867005; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fyM84Qdg+WVAc6W6qy0lJuiinDdESDwhb8Pnza3zSdg=; b=cAJdkvqmHWpOKv7f8VoNnU71oRp8TneYrVpLZSxn84LEQ9R8TFvAotzUvoIOSoeJj5 tlF/gjVBSzLIM/p5vTzhsLiBuEMmNk22iO63i/VmlAIWOU3lH6X8X6tkcl1qW+KBHCP3 Us5WEbBNltLARvfYxgpoHl943gRzca7v9tDyd8R2kCABlfwIY0qapyYEV9vMXxLWB88m yr7BF/0FemFQ5ZQHxGVPJLXTYOJWsg4+9IGQVPrP00lp/gCtndniDAePODoS6Qh6nGGl MXbidWR0Le/ay1R+veYvSEOWOS+5HDghaoFuUoN5DGK9Qpt9C6dO0OrT99qLz+QtC0KS +OEA== X-Gm-Message-State: AOJu0Yw14JIYIhdMtk+OmvSH7QValAYpC1fZ73FONoxPX+Q+gWqPiVat SC2VSUePgbwJqI7RyO4VBxbvO+HFSoHZbwSrzWMxxcXR X-Google-Smtp-Source: AGHT+IFgN/mYcpUyc35YlHMAiXwlT37k7ePUjpzOqHB9F7IC7ofILTlN4WwhoN+j9LJVlHLG4MDqlA== X-Received: by 2002:a17:907:97d4:b0:9bf:63b2:b6f0 with SMTP id js20-20020a17090797d400b009bf63b2b6f0mr12183499ejc.29.1698262204605; Wed, 25 Oct 2023 12:30:04 -0700 (PDT) From: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= , Jun Nakajima , Kevin Tian , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [RFC PATCH 08/22] x86/PMUv1: define macro for max number of events Date: Wed, 25 Oct 2023 20:29:38 +0100 Message-Id: <6f53f17afdf80b63bed4bc0c0d599ae0d8e7af5a.1698261255.git.edwin.torok@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Edwin Török This is needed so we can expose the maximum supported in CPUID, without cpuid.c and vpmu_intel.c going out of sync. The macros defined here take a parameter that controls how the enum values are used: either to generate case statements or to count how many elements we have. They are a variation on https://en.wikipedia.org/wiki/X_Macro No functional change. Could be backported to 4.13. Signed-off-by: Edwin Török --- xen/arch/x86/cpu/vpmu_intel.c | 16 ++-------------- xen/arch/x86/cpuid.c | 2 +- xen/arch/x86/include/asm/vpmu.h | 27 +++++++++++++++++++++++++++ 3 files changed, 30 insertions(+), 15 deletions(-) diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index 44a1ed5b10..ef8d69a0d6 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -622,15 +622,7 @@ static int cf_check core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content) blocked = 1; switch ( umaskevent ) { - /* - * See the Pre-Defined Architectural Performance Events table - * from the Intel 64 and IA-32 Architectures Software - * Developer's Manual, Volume 3B, System Programming Guide, - * Part 2. - */ - case 0x003c: /* UnHalted Core Cycles */ - case 0x013c: /* UnHalted Reference Cycles */ - case 0x00c0: /* Instructions Retired */ + VPMU_IPC_EVENTS(DEFCASE) blocked = 0; break; } @@ -641,11 +633,7 @@ static int cf_check core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content) /* Additional counters beyond IPC only; blocked already set. */ switch ( umaskevent ) { - case 0x4f2e: /* Last Level Cache References */ - case 0x412e: /* Last Level Cache Misses */ - case 0x00c4: /* Branch Instructions Retired */ - case 0x00c5: /* All Branch Mispredict Retired */ - case 0x01a4: /* Topdown Slots */ + VPMU_ARCH_EVENTS(DEFCASE) blocked = 0; break; } diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c index 51ee89afc4..12e768ae87 100644 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -328,7 +328,7 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf, if ( vpmu_features & (XENPMU_FEATURE_IPC_ONLY | XENPMU_FEATURE_ARCH_ONLY) ) { - unsigned limit = ( vpmu_features & XENPMU_FEATURE_ARCH_ONLY ) ? 8 : 3; + unsigned limit = VPMU_IPC_EVENTS_MAX + ( vpmu_features & XENPMU_FEATURE_ARCH_ONLY ) ? VPMU_ARCH_EVENTS_MAX : 0; if (limit < u.arch_nr) { gdprintk(XENLOG_WARNING, "Limiting architectural PMU events to %d (actual %d)", limit, u.arch_nr); u.arch_nr = limit; diff --git a/xen/arch/x86/include/asm/vpmu.h b/xen/arch/x86/include/asm/vpmu.h index 1ef6089ccb..49c3e8c19a 100644 --- a/xen/arch/x86/include/asm/vpmu.h +++ b/xen/arch/x86/include/asm/vpmu.h @@ -146,5 +146,32 @@ static inline int vpmu_allocate_context(struct vcpu *v) } #endif +/* + * See "20.2.1.2 Pre-Defined Architectural Performance Events" + * from the Intel 64 and IA-32 Architectures Software + * Developer's Manual, Volume 3B, System Programming Guide, + * Part 2. + */ +#define VPMU_IPC_EVENTS(DEF) \ + DEF(0x003c) /* UnHalted Core Cycles */\ + DEF(0x00c0) /* Instructions Retired */\ + DEF(0x013c) /* UnHalted Reference Cycles */\ + + +#define VPMU_ARCH_EVENTS(DEF) \ + VPMU_IPC_EVENTS(DEF)\ + DEF(0x4f2e) /* Last Level Cache References */\ + DEF(0x412e) /* Last Level Cache Misses */\ + DEF(0x00c4) /* Branch Instructions Retired */\ + DEF(0x00c5) /* All Branch Mispredict Retired */\ + DEF(0x01a4) /* Topdown Slots */\ + +#define DEFCASE(x) case (x): +#define DEFSUM(x) +1 +#define DEFCOUNT(X) (0+X(DEFSUM)) + +#define VPMU_IPC_EVENTS_MAX DEFCOUNT(VPMU_IPC_EVENTS) +#define VPMU_ARCH_EVENTS_MAX DEFCOUNT(VPMU_ARCH_EVENTS) + #endif /* __ASM_X86_HVM_VPMU_H_*/ From patchwork Wed Oct 25 19:29:39 2023 Content-Type: text/plain; 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Wed, 25 Oct 2023 12:30:05 -0700 (PDT) From: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= , Jun Nakajima , Kevin Tian , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [RFC PATCH 09/22] x86/PMUv1: consistently use 8 perf counters in Dom0 Date: Wed, 25 Oct 2023 20:29:39 +0100 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Edwin Török The code is currently inconsistent: supports 4 on read and 8 on write. Sandy Bridge+ supports 8 of these, and the MSR range is architecturally reserved, so always support 8. Make it a macro to ensure we use the same value everywhere. Although DomUs are now restricted to only 4 PMCs, we may still want to use all 8 in Dom0 when available, and since the default rdwmsr restrictions Dom0 would be prevented to read these MSRs as well. Depends on: "x86/PMUv1: limit arch PMCs to 4 for non-Dom0" Backport: 4.15+ Signed-off-by: Edwin Török --- xen/arch/x86/hvm/vmx/vmx.c | 8 ++++---- xen/arch/x86/include/asm/msr-index.h | 3 +++ xen/arch/x86/pv/emul-priv-op.c | 8 ++++---- 3 files changed, 11 insertions(+), 8 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index f6e5123f66..7d51addf7a 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -3360,8 +3360,8 @@ static int cf_check vmx_msr_read_intercept( MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL; /* Perhaps vpmu will change some bits. */ /* FALLTHROUGH */ - case MSR_P6_PERFCTR(0)...MSR_P6_PERFCTR(7): - case MSR_P6_EVNTSEL(0)...MSR_P6_EVNTSEL(3): + case MSR_P6_PERFCTR(0)...MSR_P6_PERFCTR_LAST: + case MSR_P6_EVNTSEL(0)...MSR_P6_EVNTSEL_LAST: case MSR_CORE_PERF_FIXED_CTR0...MSR_CORE_PERF_FIXED_CTR2: case MSR_CORE_PERF_FIXED_CTR_CTRL...MSR_CORE_PERF_GLOBAL_OVF_CTRL: case MSR_IA32_PEBS_ENABLE: @@ -3678,8 +3678,8 @@ static int cf_check vmx_msr_write_intercept( goto gp_fault; break; - case MSR_P6_PERFCTR(0)...MSR_P6_PERFCTR(7): - case MSR_P6_EVNTSEL(0)...MSR_P6_EVNTSEL(7): + case MSR_P6_PERFCTR(0)...MSR_P6_PERFCTR_LAST: + case MSR_P6_EVNTSEL(0)...MSR_P6_EVNTSEL_LAST: case MSR_CORE_PERF_FIXED_CTR0...MSR_CORE_PERF_FIXED_CTR2: case MSR_CORE_PERF_FIXED_CTR_CTRL...MSR_CORE_PERF_GLOBAL_OVF_CTRL: case MSR_IA32_PEBS_ENABLE: diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 8601f8f426..011a926e0e 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -521,8 +521,11 @@ #define MSR_IA32_PSR_MBA_MASK(n) (0x00000d50 + (n)) /* Intel Model 6 */ +#define MSR_P6_PERFCTR_MAX 8 #define MSR_P6_PERFCTR(n) (0x000000c1 + (n)) #define MSR_P6_EVNTSEL(n) (0x00000186 + (n)) +#define MSR_P6_PERFCTR_LAST MSR_P6_PERFCTR(MSR_P6_PERFCTR_MAX-1) +#define MSR_P6_EVNTSEL_LAST MSR_P6_EVNTSEL(MSR_P6_PERFCTR_MAX-1) /* P4/Xeon+ specific */ #define MSR_IA32_MCG_EAX 0x00000180 diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index 978ae679a2..301a70f5ea 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -965,8 +965,8 @@ static int cf_check read_msr( *val = 0; return X86EMUL_OKAY; - case MSR_P6_PERFCTR(0) ... MSR_P6_PERFCTR(7): - case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(3): + case MSR_P6_PERFCTR(0) ... MSR_P6_PERFCTR_LAST: + case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL_LAST: case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR2: case MSR_CORE_PERF_FIXED_CTR_CTRL ... MSR_CORE_PERF_GLOBAL_OVF_CTRL: if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ) @@ -1145,8 +1145,8 @@ static int cf_check write_msr( return X86EMUL_OKAY; break; - case MSR_P6_PERFCTR(0) ... MSR_P6_PERFCTR(7): - case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(3): + case MSR_P6_PERFCTR(0) ... MSR_P6_PERFCTR_LAST: + case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL_LAST: case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR2: case MSR_CORE_PERF_FIXED_CTR_CTRL ... MSR_CORE_PERF_GLOBAL_OVF_CTRL: if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ) From patchwork Wed Oct 25 19:29:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Edwin Torok X-Patchwork-Id: 13436603 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A0961C07545 for ; Wed, 25 Oct 2023 19:30:20 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.623198.970862 (Exim 4.92) (envelope-from ) id 1qvjZy-0003Vl-RV; Wed, 25 Oct 2023 19:30:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 623198.970862; Wed, 25 Oct 2023 19:30:10 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qvjZy-0003UU-A3; Wed, 25 Oct 2023 19:30:10 +0000 Received: by outflank-mailman (input) for mailman id 623198; Wed, 25 Oct 2023 19:30:09 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qvjZw-0001Lv-Ss for xen-devel@lists.xenproject.org; Wed, 25 Oct 2023 19:30:08 +0000 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [2a00:1450:4864:20::633]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id e7481c41-736c-11ee-9b0e-b553b5be7939; Wed, 25 Oct 2023 21:30:07 +0200 (CEST) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-9ae2cc4d17eso21097666b.1 for ; Wed, 25 Oct 2023 12:30:07 -0700 (PDT) Received: from edvint-x-u.eng.citrite.net ([185.25.67.249]) by smtp.gmail.com with ESMTPSA id hv6-20020a17090760c600b00985ed2f1584sm10408710ejc.187.2023.10.25.12.30.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 12:30:05 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e7481c41-736c-11ee-9b0e-b553b5be7939 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1698262206; x=1698867006; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D82wmWFWuZgLhPScx6tmxAejKAf/fYGX9l7CCjPm+Oo=; b=ULkatCeWK9jQmpyjDgMgKixwzGyuXq2l1yzIOLYs8GwqZyry++ffLxtKAF7z8HdJiQ ecQ38gA6EjVYLLGrNUKFkN6T1ByXInlH1+lyoYfMCkWlmTsIppagQZp19Zygdv2O3kPF BHwD6wUiULhyewKYJpaStPyUp9rRNl3L+QcoI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698262206; x=1698867006; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D82wmWFWuZgLhPScx6tmxAejKAf/fYGX9l7CCjPm+Oo=; b=n3mr/gtC1T9bJyqpUhlgyRtwNMUMD6MADnieOwD9UuBlv1s5o2YTjjdn2MfITmEwH/ u+kQMYWKmegJDMiL6rqRVE9pr4PfjISGIXvrDsuo7e1IrWwcDsDE6d38uqlSg2o+Xj8g 1HeyeOmp/N663JaO46UM7NIF22Z5t4+DZY/ojwEPpqGOOC4oCUnfbLFf7ULZkVkdvJG/ mOuqUj9bb089sJIPho4KbOiVIFG7y5TT44NmS++kxoaaRLn2L0qM38B4QOzNnBPvJ8/5 W/sUJlgxdGaRMWiUQnSx6cmi4KH2Zc8PsIZWUKOPQskDzcshMyuLWX9tSV9RPia68ycF lpTg== X-Gm-Message-State: AOJu0YyzVkPUhuhRRZ2eYJQat/jEtxKiR8LIPu9bWb2+RpPK6Kx7ou61 EUa6ps2TEm7BXaeRrunvCyNVy7Kad0vCb5y0jJiFJPfd X-Google-Smtp-Source: AGHT+IGxIhlT5o2lKJUs542MRxudBPnqUQuDNUOXjeN1e2xFqN7Z69EXUfiEly59AXLoO4KqwiV4CQ== X-Received: by 2002:a17:907:762d:b0:9c8:f128:2fdb with SMTP id jy13-20020a170907762d00b009c8f1282fdbmr7527403ejc.13.1698262206404; Wed, 25 Oct 2023 12:30:06 -0700 (PDT) From: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= , Jun Nakajima , Kevin Tian , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [RFC PATCH 10/22] x86/PMUv2: limit number of fixed perf counters to 3 Date: Wed, 25 Oct 2023 20:29:40 +0100 Message-Id: <0355493e5b5771e663381b163efb21d210f56c42.1698261255.git.edwin.torok@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Edwin Török There are only 3 architectural fixed function counters defined, however Icelake introduces a 4th. So we'll need to report the number of fixed counter implemented in CPUID correctly for Icelake, define a macro to ensure we are consistent about which counter is last. Note: simply adding MSR_CORE_PERF_FIXED_CTR3 is not enough, Icelake also defines MSR_PERF_METRICS and there are some ordering constraints on restoring the MSR, and atomicity constraints on IA32_PERF_GLOBAL_CTRL, so this is not implemented yet. Backport: 4.13+ Signed-off-by: Edwin Török --- xen/arch/x86/cpu/vpmu_intel.c | 6 ++++++ xen/arch/x86/hvm/vmx/vmx.c | 4 ++-- xen/arch/x86/include/asm/msr-index.h | 4 ++-- xen/arch/x86/pv/emul-priv-op.c | 4 ++-- 4 files changed, 12 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index ef8d69a0d6..4c0776cee7 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -926,6 +926,12 @@ const struct arch_vpmu_ops *__init core2_vpmu_init(void) } fixed_pmc_cnt = core2_get_fixed_pmc_count(); +#define PERF_FIXED_CTR_MAX (MSR_CORE_PERF_FIXED_CTRn - MSR_CORE_PERF_FIXED_CTR0 + 1) + if ( fixed_pmc_cnt > PERF_FIXED_CTR_MAX ) + { + printk(XENLOG_INFO "VPMU: limiting fixed perf counters to %d\n", PERF_FIXED_CTR_MAX); + fixed_pmc_cnt = PERF_FIXED_CTR_MAX; + } if ( cpu_has_pdcm ) { diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 7d51addf7a..1510e980dd 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -3362,7 +3362,7 @@ static int cf_check vmx_msr_read_intercept( /* FALLTHROUGH */ case MSR_P6_PERFCTR(0)...MSR_P6_PERFCTR_LAST: case MSR_P6_EVNTSEL(0)...MSR_P6_EVNTSEL_LAST: - case MSR_CORE_PERF_FIXED_CTR0...MSR_CORE_PERF_FIXED_CTR2: + case MSR_CORE_PERF_FIXED_CTR0...MSR_CORE_PERF_FIXED_CTRn: case MSR_CORE_PERF_FIXED_CTR_CTRL...MSR_CORE_PERF_GLOBAL_OVF_CTRL: case MSR_IA32_PEBS_ENABLE: case MSR_IA32_DS_AREA: @@ -3680,7 +3680,7 @@ static int cf_check vmx_msr_write_intercept( case MSR_P6_PERFCTR(0)...MSR_P6_PERFCTR_LAST: case MSR_P6_EVNTSEL(0)...MSR_P6_EVNTSEL_LAST: - case MSR_CORE_PERF_FIXED_CTR0...MSR_CORE_PERF_FIXED_CTR2: + case MSR_CORE_PERF_FIXED_CTR0...MSR_CORE_PERF_FIXED_CTRn: case MSR_CORE_PERF_FIXED_CTR_CTRL...MSR_CORE_PERF_GLOBAL_OVF_CTRL: case MSR_IA32_PEBS_ENABLE: case MSR_IA32_DS_AREA: diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 011a926e0e..8a881a8a6f 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -674,8 +674,8 @@ /* Intel Core-based CPU performance counters */ #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 -#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a -#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b +#define MSR_CORE_PERF_FIXED_CTRn 0x0000030b + #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index 301a70f5ea..a8472fc779 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -967,7 +967,7 @@ static int cf_check read_msr( case MSR_P6_PERFCTR(0) ... MSR_P6_PERFCTR_LAST: case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL_LAST: - case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR2: + case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTRn: case MSR_CORE_PERF_FIXED_CTR_CTRL ... MSR_CORE_PERF_GLOBAL_OVF_CTRL: if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ) { @@ -1147,7 +1147,7 @@ static int cf_check write_msr( case MSR_P6_PERFCTR(0) ... MSR_P6_PERFCTR_LAST: case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL_LAST: - case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR2: + case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTRn: case MSR_CORE_PERF_FIXED_CTR_CTRL ... MSR_CORE_PERF_GLOBAL_OVF_CTRL: if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ) { From patchwork Wed Oct 25 19:29:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Edwin Torok X-Patchwork-Id: 13436614 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EDF28C25B6B for ; Wed, 25 Oct 2023 19:30:34 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.623197.970856 (Exim 4.92) (envelope-from ) id 1qvjZy-0003O3-0G; Wed, 25 Oct 2023 19:30:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 623197.970856; Wed, 25 Oct 2023 19:30:09 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qvjZx-0003Ki-O8; Wed, 25 Oct 2023 19:30:09 +0000 Received: by outflank-mailman (input) for mailman id 623197; Wed, 25 Oct 2023 19:30:08 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qvjZw-0000YO-K6 for xen-devel@lists.xenproject.org; Wed, 25 Oct 2023 19:30:08 +0000 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [2a00:1450:4864:20::62f]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id e7e438ec-736c-11ee-98d5-6d05b1d4d9a1; Wed, 25 Oct 2023 21:30:08 +0200 (CEST) Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-9bdf5829000so24754666b.0 for ; Wed, 25 Oct 2023 12:30:08 -0700 (PDT) Received: from edvint-x-u.eng.citrite.net ([185.25.67.249]) by smtp.gmail.com with ESMTPSA id hv6-20020a17090760c600b00985ed2f1584sm10408710ejc.187.2023.10.25.12.30.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 12:30:06 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e7e438ec-736c-11ee-98d5-6d05b1d4d9a1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1698262207; x=1698867007; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D26h79W0uIiar9apEu5I8y2IaailVn2qskwn4HTwx6M=; b=QbiW5/Go6RCvbYnKe+hqpGo5NRPq2Nzb1yZHzP/wYSeeH5X6FamF0fVyXb0l/eDgLE pSlQw/M9mwTVuzQ0E8vjDywzeqMi+SnDwOvQltPKrUaTqqvv3UkStr5gyHJJwu6lfDsN cRS6Vapqsu/acduE/GNAK0kxXjgaHGe6U2qa4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698262207; x=1698867007; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D26h79W0uIiar9apEu5I8y2IaailVn2qskwn4HTwx6M=; b=Kyw7EPugo1Ks3BluFSZLxZibbYy43aLvVXs5zlrpAyJT3A8/uFshVl/3gaiCZiaXXR 41HY1mSkvjwVlFGMfzSw6iMKK1O7/F/z6pEfz3tHlsP0HcGTv+wptPf0COgqlI8sVXJO A7D1f2jlMQ859RX1MFrUow5s4n174KrAqB6Q7cF2IETfqezipTjQnucA9D7GYkv5ftNU oZEHeguht555SE9Kw+20234XN0w66I1HtEnTrUf54lzB1jymmW1lqtPuVjYOB3Lg4K1f 9NwAQoxHOdSzVhDQblJuSTcBX87Fr0/ATDK2Up7TKuD1ndmJfATvbPQQKo93oZ/8i4Oh ALTQ== X-Gm-Message-State: AOJu0YyR5NNX+XNJhShWFGI+9Vw82o1ti3FyoHJUyFhoI/1hQR1asILc aamVabxWH/9tSeQICOfwugCVc4XCPmF7x0bU68V3tlHY X-Google-Smtp-Source: AGHT+IFA7BksNHd8kthUX3uqbV5iFjWiTjpdglNpTm6OMMEu96h5FNd6/mqRyoOx7YpZdrWseSba+A== X-Received: by 2002:a17:906:da82:b0:9c7:5db4:c943 with SMTP id xh2-20020a170906da8200b009c75db4c943mr13931963ejb.40.1698262207467; Wed, 25 Oct 2023 12:30:07 -0700 (PDT) From: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= , Jun Nakajima , Kevin Tian , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [RFC PATCH 11/22] x86/PMUv2: freeze support in IA32_DEBUGCTL Date: Wed, 25 Oct 2023 20:29:41 +0100 Message-Id: <53246128214e8bc91e4a6d765935936efa8cd2f0.1698261255.git.edwin.torok@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Edwin Török This is not yet exposed by HVM policies, but PMU version 2 requires that if PDCM is supported in CPUID then these 2 bits would work. Signed-off-by: Edwin Török --- xen/arch/x86/hvm/vmx/vmx.c | 4 ++++ xen/arch/x86/include/asm/msr-index.h | 4 +++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 1510e980dd..f1f8a9afa2 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -3601,6 +3601,10 @@ static int cf_check vmx_msr_write_intercept( IA32_DEBUGCTLMSR_BTS_OFF_USR); } + if (cp->basic.pmu_version >= 2 && cpu_has(¤t_cpu_data, X86_FEATURE_PDCM)) { + rsvd &= ~(IA32_DEBUGCTLMSR_FREEZE_LBRS_ON_PMI | IA32_DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI); + } + if ( cp->feat.rtm ) rsvd &= ~IA32_DEBUGCTLMSR_RTM; diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 8a881a8a6f..0dfb5b499f 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -305,7 +305,9 @@ #define IA32_DEBUGCTLMSR_BTINT (1<<8) /* Branch Trace Interrupt */ #define IA32_DEBUGCTLMSR_BTS_OFF_OS (1<<9) /* BTS off if CPL 0 */ #define IA32_DEBUGCTLMSR_BTS_OFF_USR (1<<10) /* BTS off if CPL > 0 */ -#define IA32_DEBUGCTLMSR_RTM (1<<15) /* RTM debugging enable */ +#define IA32_DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1<<11) /* LBR stack frozen on PMI */ +#define IA32_DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1<<12) /* Global counter control ENABLE bit frozen on PMI */ +#define IA32_DEBUGCTLMSR_RTM (1<<15) /* RTM debugging enable */ #define MSR_IA32_LASTBRANCHFROMIP 0x000001db #define MSR_IA32_LASTBRANCHTOIP 0x000001dc From patchwork Wed Oct 25 19:29:42 2023 Content-Type: text/plain; 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Wed, 25 Oct 2023 12:30:08 -0700 (PDT) From: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [RFC PATCH 12/22] x86/msr-index: define more architectural MSRs Date: Wed, 25 Oct 2023 20:29:42 +0100 Message-Id: <4675c236ea5f66bfce36eb98ac5806ee0468b4fe.1698261255.git.edwin.torok@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Edwin Török Add most architectural MSRs, except those behind CPUID features that are not yet implemented, such as TME, SGX. Based on "2.1 Architectural MSRs" of Intel SDM volume 4 Signed-off-by: Edwin Török --- xen/arch/x86/include/asm/msr-index.h | 54 +++++++++++++++++++++++++--- 1 file changed, 50 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 0dfb5b499f..061b07c7ae 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -58,6 +58,14 @@ #define PRED_CMD_IBPB (_AC(1, ULL) << 0) #define PRED_CMD_SBPB (_AC(1, ULL) << 7) +#define MSR_IA32_SMM_MONITOR_CTL 0x0000009b +#define MSR_IA32_SMBASE 0x0000009e +#define MSR_IA32_SMRR_PHYSBASE 0x000001f2 +#define MSR_IA32_SMRR_PHYSMASK 0x000001f3 +#define MSR_IA32_PLATFORM_DCA_CAP 0x000001f8 +#define MSR_IA32_CPU_DCA_CAP 0x000001f9 +#define MSR_IA32_DCA_0_CAP 0x000001fa + #define MSR_PPIN_CTL 0x0000004e #define PPIN_LOCKOUT (_AC(1, ULL) << 0) #define PPIN_ENABLE (_AC(1, ULL) << 1) @@ -267,13 +275,21 @@ #define MSR_IA32_MCG_CAP 0x00000179 #define MSR_IA32_MCG_STATUS 0x0000017a #define MSR_IA32_MCG_CTL 0x0000017b -#define MSR_IA32_MCG_EXT_CTL 0x000004d0 +#define MSR_IA32_MCG_EXT_CTL 0x000004d0 #define MSR_IA32_PEBS_ENABLE 0x000003f1 #define MSR_IA32_DS_AREA 0x00000600 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 /* Lower 6 bits define the format of the address in the LBR stack */ -#define MSR_IA32_PERF_CAP_LBR_FORMAT 0x3f +#define MSR_IA32_PERF_CAP_LBR_FORMAT 0x3f +#define MSR_IA32_PERF_CAP_PEBS_TRAP (_AC(1,ULL) << 6) +#define MSR_IA32_PERF_CAP_PEBS_SAVE_ARCH_REGS (_AC(1,ULL) << 7) +#define MSR_IA32_PERF_CAP_PEBS_RECORD_FORMAT 0xf00 +#define MSR_IA32_PERF_CAP_FREEZE_WHILE_SMM (_AC(1,ULL) << 12) +#define MSR_IA32_PERF_CAP_FULLWIDTH_PMC (_AC(1,ULL) << 13) +#define MSR_IA32_PERF_CAP_PEBS_BASELINE (_AC(1,ULL) << 14) +#define MSR_IA32_PERF_CAP_PERF_METRICS (_AC(1,ULL) << 15) +#define MSR_IA32_PERF_CAP_PEBS_TO_PT (_AC(1,ULL) << 16) #define MSR_IA32_BNDCFGS 0x00000d90 #define IA32_BNDCFGS_ENABLE 0x00000001 @@ -307,6 +323,8 @@ #define IA32_DEBUGCTLMSR_BTS_OFF_USR (1<<10) /* BTS off if CPL > 0 */ #define IA32_DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1<<11) /* LBR stack frozen on PMI */ #define IA32_DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1<<12) /* Global counter control ENABLE bit frozen on PMI */ +#define IA32_DEBUGCTLMSR_ENABLE_UNCORE_PMI (1<<13) /* Enable uncore PMI */ +#define IA32_DEBUGCTLMSR_FREEZE_WHILE_SMM (1<<14) /* Freeze perfmon/trace while in SMM */ #define IA32_DEBUGCTLMSR_RTM (1<<15) /* RTM debugging enable */ #define MSR_IA32_LASTBRANCHFROMIP 0x000001db @@ -469,6 +487,7 @@ #define MSR_VIA_RNG 0x0000110b /* Intel defined MSRs. */ +#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006 #define MSR_IA32_TSC 0x00000010 #define MSR_IA32_PLATFORM_ID 0x00000017 #define MSR_IA32_EBL_CR_POWERON 0x0000002a @@ -491,6 +510,7 @@ #define MSR_IA32_PERF_STATUS 0x00000198 #define MSR_IA32_PERF_CTL 0x00000199 +#define MSR_IA32_UMWAIT_CONTROL 0x000000e1 #define MSR_IA32_MPERF 0x000000e7 #define MSR_IA32_APERF 0x000000e8 @@ -498,6 +518,7 @@ #define MSR_IA32_THERM_INTERRUPT 0x0000019b #define MSR_IA32_THERM_STATUS 0x0000019c #define MSR_IA32_MISC_ENABLE 0x000001a0 +#define MSR_IA32_MISC_ENABLE_FAST_STRINGS (1<<0) #define MSR_IA32_MISC_ENABLE_PERF_AVAIL (1<<7) #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1<<11) #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12) @@ -508,15 +529,38 @@ #define MSR_IA32_MISC_ENABLE_TURBO_DISENGAGE (_AC(1, ULL) << 38) #define MSR_IA32_TSC_DEADLINE 0x000006E0 + +#define MSR_IA32_PM_ENABLE 0x00000770 +#define MSR_IA32_HWP_CAPABILITIES 0x00000771 +#define MSR_IA32_HWP_REQUEST_PKG 0x00000772 +#define MSR_IA32_HWP_INTERRUPT 0x00000773 +#define MSR_IA32_HWP_REQUEST 0x00000774 +#define MSR_IA32_PECI_HWP_REQUEST_INFO 0x00000775 +#define MSR_IA32_HWP_STATUS 0x00000777 + +#define MSR_IA32_PKG_HDC_CTL 0x00000db0 +#define MSR_IA32_PM_CTL1 0x00000db1 +#define MSR_IA32_THREAD_STALL 0x00000db2 +#define MSR_IA32_HW_FEEDBACK_PTR 0x000017d0 +#define MSR_IA32_HW_FEEDBACK_CONFIG 0x000017d1 + +#define MSR_TEMPERATURE_TARGET 0x000001a2 +#define MSR_TURBO_RATIO_LIMIT 0x000001ad +#define MSR_TURBO_RATIO_LIMIT1 0x000001ae +#define MSR_TURBO_RATIO_LIMIT2 0x000001af + #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 +#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 +#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 /* Platform Shared Resource MSRs */ +#define MSR_IA32_PSR_L3_QOS_CFG 0x00000c81 +#define MSR_IA32_PSR_L2_QOS_CFG 0x00000c82 #define MSR_IA32_CMT_EVTSEL 0x00000c8d #define MSR_IA32_CMT_EVTSEL_UE_MASK 0x0000ffff #define MSR_IA32_CMT_CTR 0x00000c8e #define MSR_IA32_PSR_ASSOC 0x00000c8f -#define MSR_IA32_PSR_L3_QOS_CFG 0x00000c81 -#define MSR_IA32_PSR_L3_MASK(n) (0x00000c90 + (n)) +#define MSR_IA32_PSR_L3_MASK(n) (0x00000c90 + (n)) #define MSR_IA32_PSR_L3_MASK_CODE(n) (0x00000c90 + (n) * 2 + 1) #define MSR_IA32_PSR_L3_MASK_DATA(n) (0x00000c90 + (n) * 2) #define MSR_IA32_PSR_L2_MASK(n) (0x00000d10 + (n)) @@ -682,6 +726,8 @@ #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 +#define MSR_CORE_PERF_GLOBAL_STATUS_SET 0x00000391 +#define MSR_CORE_PERF_GLOBAL_INUSE 0x00000392 /* Intel cpuid spoofing MSRs */ #define MSR_INTEL_MASK_V1_CPUID1 0x00000478 From patchwork Wed Oct 25 19:29:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Edwin Torok X-Patchwork-Id: 13436606 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B2F0C07545 for ; Wed, 25 Oct 2023 19:30:26 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.623202.970892 (Exim 4.92) (envelope-from ) id 1qvja3-0004TR-7R; Wed, 25 Oct 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X-Google-Smtp-Source: AGHT+IHwxJOyWh8HPzL13+/SLwBO0U3Pr25AoXriqxxqHT9GvDNBp5XYykfO6ItnsgbolB5QJU60nQ== X-Received: by 2002:a17:906:dace:b0:9c6:64be:a3ac with SMTP id xi14-20020a170906dace00b009c664bea3acmr13083067ejb.49.1698262208791; Wed, 25 Oct 2023 12:30:08 -0700 (PDT) From: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , Jun Nakajima , Kevin Tian Subject: [RFC PATCH 13/22] x86/vpmu: expose PDCM and IA32_PERF_CAPABILITIES when vpmu is enabled Date: Wed, 25 Oct 2023 20:29:43 +0100 Message-Id: <208464149217bcda9f774db7b906a597f9bde6db.1698261255.git.edwin.torok@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Edwin Török Marked as exposed by default, but then hidden if vpmu is not available. TODO: the interaction between vpmu and policy might need some changes. Only expose LBR and the full-width MSR capabilities, and not PEBS. Backport: 4.15+ Signed-off-by: Edwin Török --- xen/arch/x86/cpu-policy.c | 10 ++++++++-- xen/arch/x86/hvm/vmx/vmx.c | 2 +- xen/arch/x86/msr.c | 8 ++++++++ xen/arch/x86/pv/emul-priv-op.c | 5 ----- xen/include/public/arch-x86/cpufeatureset.h | 2 +- 5 files changed, 18 insertions(+), 9 deletions(-) diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index 64c8857a61..e38b648f7d 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -388,8 +388,10 @@ static void __init calculate_host_policy(void) recalculate_misc(p); /* When vPMU is disabled, drop it from the host policy. */ - if ( vpmu_mode == XENPMU_MODE_OFF ) + if ( vpmu_mode == XENPMU_MODE_OFF ) { p->basic.raw[0xa] = EMPTY_LEAF; + p->basic.pdcm = 0; + } if ( p->extd.svm ) { @@ -899,8 +901,12 @@ void recalculate_cpuid_policy(struct domain *d) } if ( vpmu_mode == XENPMU_MODE_OFF || - ((vpmu_mode & XENPMU_MODE_ALL) && !is_hardware_domain(d)) ) + ((vpmu_mode & XENPMU_MODE_ALL) && !is_hardware_domain(d)) ) { p->basic.raw[0xa] = EMPTY_LEAF; + p->basic.pdcm = 0; + } + if ( vpmu_features & (XENPMU_FEATURE_IPC_ONLY | XENPMU_FEATURE_ARCH_ONLY) ) + p->basic.pdcm = 0; if ( !p->extd.svm ) p->extd.raw[0xa] = EMPTY_LEAF; diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index f1f8a9afa2..fefd01be40 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -3602,7 +3602,7 @@ static int cf_check vmx_msr_write_intercept( } if (cp->basic.pmu_version >= 2 && cpu_has(¤t_cpu_data, X86_FEATURE_PDCM)) { - rsvd &= ~(IA32_DEBUGCTLMSR_FREEZE_LBRS_ON_PMI | IA32_DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI); + rsvd &= ~(IA32_DEBUGCTLMSR_FREEZE_LBRS_ON_PMI | IA32_DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI | IA32_DEBUGCTLMSR_FREEZE_WHILE_SMM); } if ( cp->feat.rtm ) diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 0bf6d263e7..483b5e4f70 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -186,6 +186,14 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val) goto gp_fault; goto get_reg; + case MSR_IA32_PERF_CAPABILITIES: + if ( cp->x86_vendor != X86_VENDOR_INTEL ) + goto gp_fault; + if ( !cp->basic.pdcm || rdmsr_safe(msr, *val) ) + goto gp_fault; + *val &= (MSR_IA32_PERF_CAP_LBR_FORMAT | MSR_IA32_PERF_CAP_FREEZE_WHILE_SMM | MSR_IA32_PERF_CAP_FULLWIDTH_PMC); + break; + case MSR_X2APIC_FIRST ... MSR_X2APIC_LAST: if ( !is_hvm_domain(d) || v != curr ) goto gp_fault; diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index a8472fc779..e623e57b55 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -960,11 +960,6 @@ static int cf_check read_msr( *val = guest_misc_enable(*val); return X86EMUL_OKAY; - case MSR_IA32_PERF_CAPABILITIES: - /* No extra capabilities are supported. */ - *val = 0; - return X86EMUL_OKAY; - case MSR_P6_PERFCTR(0) ... MSR_P6_PERFCTR_LAST: case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL_LAST: case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTRn: diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 6b6ce2745c..0aa3251397 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -118,7 +118,7 @@ XEN_CPUFEATURE(SSSE3, 1*32+ 9) /*A Supplemental Streaming SIMD Extensio XEN_CPUFEATURE(FMA, 1*32+12) /*A Fused Multiply Add */ XEN_CPUFEATURE(CX16, 1*32+13) /*A CMPXCHG16B */ XEN_CPUFEATURE(XTPR, 1*32+14) /* Send Task Priority Messages */ -XEN_CPUFEATURE(PDCM, 1*32+15) /* Perf/Debug Capability MSR */ +XEN_CPUFEATURE(PDCM, 1*32+15) /*A Perf/Debug Capability MSR */ XEN_CPUFEATURE(PCID, 1*32+17) /*H Process Context ID */ XEN_CPUFEATURE(DCA, 1*32+18) /* Direct Cache Access */ XEN_CPUFEATURE(SSE4_1, 1*32+19) /*A Streaming SIMD Extensions 4.1 */ From patchwork Wed Oct 25 19:29:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Edwin Torok X-Patchwork-Id: 13436612 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C008AC0032E for ; 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Wed, 25 Oct 2023 12:30:09 -0700 (PDT) From: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= , Jun Nakajima , Kevin Tian , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [RFC PATCH 14/22] x86/msr: RO MSR_TURBO_RATIO_LIMIT{,1,2}, MSR_TEMPERATURE_TARGET Date: Wed, 25 Oct 2023 20:29:44 +0100 Message-Id: <85b2230c2c40789f6c8548ae9978cea244daf2c3.1698261255.git.edwin.torok@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Edwin Török Expose MSR_TURBO_RATIO_LIMIT{,1,2} and MSR_TEMPERATURE_TARGET to guest as RO. Although these are not architectural MSRs they are in the same place currently on all supported CPUs. They also have the same meaning, except for 06_55H and 06_5C where they have a different meaning (turbo core count). It is safe to expose this to the guest by default: they are only statically defined limits and don't expose runtime measurements. It has been observed that some drivers BSOD on an unguarded read on MSR 1ADH (e.g. socwatch). Also we read as zero the actual temperature, so reporting the temp target as 0 might lead to 0/0. Backport: 4.15+ Signed-off-by: Edwin Török --- xen/arch/x86/hvm/vmx/vmx.c | 9 +++++++++ xen/arch/x86/pv/emul-priv-op.c | 4 ++++ 2 files changed, 13 insertions(+) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index fefd01be40..cd772585fe 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -3353,6 +3353,15 @@ static int cf_check vmx_msr_read_intercept( if ( !nvmx_msr_read_intercept(msr, msr_content) ) goto gp_fault; break; + + case MSR_TEMPERATURE_TARGET: + case MSR_TURBO_RATIO_LIMIT...MSR_TURBO_RATIO_LIMIT2: + if ( !rdmsr_safe(msr, *msr_content) ) + break; + /* RO for guests, MSR_PLATFORM_INFO bits set accordingly in msr.c to indicate lack of write + * support. */ + goto gp_fault; + case MSR_IA32_MISC_ENABLE: rdmsrl(MSR_IA32_MISC_ENABLE, *msr_content); /* Debug Trace Store is not supported. */ diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index e623e57b55..09bfde1060 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -960,6 +960,10 @@ static int cf_check read_msr( *val = guest_misc_enable(*val); return X86EMUL_OKAY; + case MSR_TEMPERATURE_TARGET: + case MSR_TURBO_RATIO_LIMIT...MSR_TURBO_RATIO_LIMIT2: + goto normal; + case MSR_P6_PERFCTR(0) ... MSR_P6_PERFCTR_LAST: case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL_LAST: case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTRn: From patchwork Wed Oct 25 19:29:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Edwin Torok X-Patchwork-Id: 13436613 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9079C25B6E for ; Wed, 25 Oct 2023 19:30:36 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.623203.970904 (Exim 4.92) (envelope-from ) id 1qvja4-0004ju-UF; Wed, 25 Oct 2023 19:30:16 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 623203.970904; Wed, 25 Oct 2023 19:30:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qvja3-0004ge-Mp; Wed, 25 Oct 2023 19:30:15 +0000 Received: by outflank-mailman (input) for mailman id 623203; Wed, 25 Oct 2023 19:30:11 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qvjZz-0000YO-KV for xen-devel@lists.xenproject.org; Wed, 25 Oct 2023 19:30:11 +0000 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [2a00:1450:4864:20::62d]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id e99200bc-736c-11ee-98d5-6d05b1d4d9a1; Wed, 25 Oct 2023 21:30:10 +0200 (CEST) Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-99c3d3c3db9so20953666b.3 for ; Wed, 25 Oct 2023 12:30:10 -0700 (PDT) Received: from edvint-x-u.eng.citrite.net ([185.25.67.249]) by smtp.gmail.com with ESMTPSA id hv6-20020a17090760c600b00985ed2f1584sm10408710ejc.187.2023.10.25.12.30.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 12:30:09 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e99200bc-736c-11ee-98d5-6d05b1d4d9a1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1698262210; x=1698867010; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JKhNYdlAE8EwCefQAQkVbnFvAytz3pPS6IXrLO8Y8Kc=; b=Zj5TlKrfu78SyOouz/U6bZK7akCc/JA5uk9YTxf/aY26CRq6ywHAvfl8AI5DGK0g5K v8udYmuyW8ActQt3/VU8dABPF6djXSnebETFYe9sdybDPSE/VLPRZYeXnEYWRxb7zik1 7VUsiMqcjvWU+d4dq4c5qqtotAvLyBAfbhUzk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698262210; x=1698867010; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JKhNYdlAE8EwCefQAQkVbnFvAytz3pPS6IXrLO8Y8Kc=; b=q+bL6ZX7srzrFeLoR1tPosAWurZDwuXArvqMuszIFjpBm9AC9XP1iSjJGzgdE8Hh5E 7GZwvdkxdtkF7liuu9aEEERfxd6RIDAbKUlG4PXi5Ow7f6un8eWY95NLbt3/3ST5PFjr NtD6rGpCeg/jFWWJiVClLHq/y8NU2SRosJuGNiEvI0h18hqSAMoR+PypP99+Irqh1ohg u5ZJ+brJQHu1dAep1jRgiK5p5euaFu6+AZvDfPEdZZvO4q8DLAaaISqjY5E1AYmfFesb +GwWla481kfQD62iDESEEDMj/F7aX6Amr2WWg1JgHSDwvpsqcs4BCh7RV2krwCDoMi4G +gLA== X-Gm-Message-State: AOJu0YxywVeMoeqx5aehlDQwMvTLG+fIo8KgJP45MlMJxxRzLdV1utaE u56Zh/hxihRFakFE/vI+rOBQUMkJmgltvk7getIexA== X-Google-Smtp-Source: AGHT+IFzYgBWUL9afBd9LOeukhnEP1/3SxzWsrc9BUVmSazeXCKhKucA6bNJ0btH7zgnlcBmxZGpDQ== X-Received: by 2002:a17:906:eec6:b0:9b6:f0e2:3c00 with SMTP id wu6-20020a170906eec600b009b6f0e23c00mr13472824ejb.71.1698262210271; Wed, 25 Oct 2023 12:30:10 -0700 (PDT) From: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= , Jun Nakajima , Kevin Tian , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [RFC PATCH 15/22] x86/VPMU: use macros for max supported VPMU version Date: Wed, 25 Oct 2023 20:29:45 +0100 Message-Id: <9ed0302bf1cce2dc65d6311c4508bfa4cfe4f8b7.1698261255.git.edwin.torok@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Edwin Török This ensures consistency between the 2 pieces of code that check for VPMU version. No functional change. Signed-off-by: Edwin Török --- xen/arch/x86/cpu/vpmu_intel.c | 20 ++++++-------------- xen/arch/x86/include/asm/vpmu.h | 1 + 2 files changed, 7 insertions(+), 14 deletions(-) diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index 4c0776cee7..82cd2656ea 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -810,7 +810,7 @@ static int cf_check core2_vpmu_initialise(struct vcpu *v) static bool_t ds_warned; if ( v->domain->arch.cpuid->basic.pmu_version <= 1 || - v->domain->arch.cpuid->basic.pmu_version >= 6 ) + v->domain->arch.cpuid->basic.pmu_version >= VPMU_VERSION_MAX_SUPPORTED ) return -EINVAL; if ( (arch_pmc_cnt + fixed_pmc_cnt) == 0 ) @@ -890,22 +890,14 @@ const struct arch_vpmu_ops *__init core2_vpmu_init(void) if ( current_cpu_data.cpuid_level >= 0xa ) version = MASK_EXTR(cpuid_eax(0xa), PMU_VERSION_MASK); - switch ( version ) - { - case 4: - case 5: - printk(XENLOG_INFO "VPMU: PMU version %u is not fully supported. " - "Emulating version 3\n", version); - /* FALLTHROUGH */ - - case 2: - case 3: - break; - - default: + if ( version <= 1 || + version > VPMU_VERSION_MAX_SUPPORTED ) { printk(XENLOG_WARNING "VPMU: PMU version %u is not supported\n", version); return ERR_PTR(-EINVAL); + } else if ( version > VPMU_VERSION_MAX ) { + printk(XENLOG_INFO "VPMU: PMU version %u is not fully supported. " + "Emulating version %d\n", version, VPMU_VERSION_MAX); } if ( current_cpu_data.x86 != 6 ) diff --git a/xen/arch/x86/include/asm/vpmu.h b/xen/arch/x86/include/asm/vpmu.h index 49c3e8c19a..79f7f4a09e 100644 --- a/xen/arch/x86/include/asm/vpmu.h +++ b/xen/arch/x86/include/asm/vpmu.h @@ -75,6 +75,7 @@ struct vpmu_struct { #define VPMU_CPU_HAS_BTS 0x2000 /* Has Branch Trace Store */ #define VPMU_VERSION_MAX 0x3 +#define VPMU_VERSION_MAX_SUPPORTED 0x5 static inline void vpmu_set(struct vpmu_struct *vpmu, const u32 mask) { From patchwork Wed Oct 25 19:29:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Edwin Torok X-Patchwork-Id: 13436615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6277C07545 for ; Wed, 25 Oct 2023 19:30:38 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.623205.970920 (Exim 4.92) (envelope-from ) id 1qvja7-0005K1-CE; Wed, 25 Oct 2023 19:30:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 623205.970920; Wed, 25 Oct 2023 19:30:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qvja6-0005Ei-8l; Wed, 25 Oct 2023 19:30:18 +0000 Received: by outflank-mailman (input) for mailman id 623205; Wed, 25 Oct 2023 19:30:13 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qvja1-0001Lv-5R for xen-devel@lists.xenproject.org; Wed, 25 Oct 2023 19:30:13 +0000 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [2a00:1450:4864:20::633]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id ea0aa2ec-736c-11ee-9b0e-b553b5be7939; Wed, 25 Oct 2023 21:30:11 +0200 (CEST) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-9c75ceea588so19150266b.3 for ; Wed, 25 Oct 2023 12:30:11 -0700 (PDT) Received: from edvint-x-u.eng.citrite.net ([185.25.67.249]) by smtp.gmail.com with ESMTPSA id hv6-20020a17090760c600b00985ed2f1584sm10408710ejc.187.2023.10.25.12.30.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 12:30:10 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ea0aa2ec-736c-11ee-9b0e-b553b5be7939 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1698262211; x=1698867011; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kNVXTwATT/U7ZeWv6JLd9rx3MTxnLYLpL+s2D1g+Bxc=; b=ft9ZC6bJvD2onqxSZOO1t3iW5F57NHY9BEOk1EopiiMIlksqk51HgbrMwUu4AlwQPp fp6eEtVttWkbhufCBQFZBGJqpveCx3pEmntf+XgN7611htdw/2KBBwREWX6p3ZnHWaBO MRHCLb8KZJt8OwnMtl4tUznTHFLDFCOtJOL2U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698262211; x=1698867011; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kNVXTwATT/U7ZeWv6JLd9rx3MTxnLYLpL+s2D1g+Bxc=; b=Hk9Vr/bjeZi/5v/pvbKwfYjbglskIyY3NHxFE6r+56eLYBl+8aDQPMlEH9djzG2wDl Q4L0e8vMQuzWdGE9qBk7aWbrt2jW1K1XOFdOkV2j3vFu7vRlaX/x0oah2UKhgVYQjlB9 EfGEPRck6UTGz5E/Jld7NO4du6Ivu2o3tNRCrsPFACbr1YXSPkPvXhkD06s1Cr+hn6pM 95copJ24dbXVjlMzVHkvoqfY9l+QCsh8Ktrwqpjw77HmdhT/gR/rsRijsngSUQ2/QrrK Oc0GKqlI85HBunjNZJRdeAlBUKDh011rk4BZUhptjyZKr0pxD0NEVzBGbYJXW7a68iQo pDNA== X-Gm-Message-State: AOJu0YyxSZIgJcjiRxozGx2X06OTg86AJVIxM70u52huR7sBZKyG/RNC 3vwfYAQpxIpX9zYSbJySGVLLf37SoC24Qaa4svcUAQ== X-Google-Smtp-Source: AGHT+IHZPaAqI5dIYhGEutHuI0UKgf8zTmT3qls1UH0sZReCZbarM7SWYWihEiRZ2iSymWXGSACL4A== X-Received: by 2002:a17:906:da88:b0:9be:7de2:927c with SMTP id xh8-20020a170906da8800b009be7de2927cmr11982723ejb.70.1698262210978; Wed, 25 Oct 2023 12:30:10 -0700 (PDT) From: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= , Jun Nakajima , Kevin Tian , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [RFC PATCH 16/22] x86/PMUv4: support LBR_Frz and CTR_Frz Date: Wed, 25 Oct 2023 20:29:46 +0100 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Edwin Török The behaviour is changed from Legacy to Streamlined for the LBR and PERFMON freeze bits. See "17.4.7 Freezing LBR and Performance Counters on PMI". Instead of clearing the freeze bits through DEBUGCTL they are now cleared through MSR 0x390 like everything else. Signed-off-by: Edwin Török --- xen/arch/x86/cpu/vpmu_intel.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index 82cd2656ea..923fe42a0b 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -952,6 +952,13 @@ const struct arch_vpmu_ops *__init core2_vpmu_init(void) */ global_ovf_ctrl_mask &= ~(1ULL << 61); + if ( version >= 4) + /* On PMU version 4 bits 58 and 59 are defined in + * IA32_PERF_GLOBAL_STATUS_RESET (same MSR as IA32_PERF_GLOBAL_STATUS). + * Also allow clearing overflow for processor trace, even if we don't support it yet. + * */ + global_ovf_ctrl_mask &= ~((3ULL << 58) | (1ULL << 55)); + regs_sz = (sizeof(struct xen_pmu_intel_ctxt) - regs_off) + sizeof(uint64_t) * fixed_pmc_cnt + sizeof(struct xen_pmu_cntr_pair) * arch_pmc_cnt; From patchwork Wed Oct 25 19:29:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Edwin Torok X-Patchwork-Id: 13436608 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 09CC8C25B70 for ; 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Wed, 25 Oct 2023 12:30:11 -0700 (PDT) From: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= , Jun Nakajima , Kevin Tian , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [RFC PATCH 17/22] x86/PMUv4: IA32_PERF_GLOBAL_{STATUS_SET, INUSE} support Date: Wed, 25 Oct 2023 20:29:47 +0100 Message-Id: <586661cb0604d638972e57de039456c85371ed97.1698261255.git.edwin.torok@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Edwin Török Expose thse MSRs to the guest when PMU version is >= 4. Signed-off-by: Edwin Török --- xen/arch/x86/cpu/vpmu_intel.c | 20 +++++++++++++++++++- xen/arch/x86/hvm/vmx/vmx.c | 5 +++++ xen/arch/x86/pv/emul-priv-op.c | 5 +++++ 3 files changed, 29 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index 923fe42a0b..5e660af395 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -171,6 +171,8 @@ static int is_core2_vpmu_msr(u32 msr_index, int *type, int *index) case MSR_CORE_PERF_GLOBAL_CTRL: case MSR_CORE_PERF_GLOBAL_STATUS: case MSR_CORE_PERF_GLOBAL_OVF_CTRL: + case MSR_CORE_PERF_GLOBAL_STATUS_SET: + case MSR_CORE_PERF_GLOBAL_INUSE: *type = MSR_TYPE_GLOBAL; return 1; @@ -545,10 +547,21 @@ static int cf_check core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content) core2_vpmu_cxt->global_status &= ~msr_content; wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, msr_content); return 0; + case MSR_CORE_PERF_GLOBAL_STATUS_SET: + if ( (v->domain->arch.cpuid->basic.pmu_version < 4) || + (msr_content & global_ovf_ctrl_mask) ) + return -EINVAL; + core2_vpmu_cxt->global_status |= msr_content; + wrmsrl(MSR_CORE_PERF_GLOBAL_STATUS_SET, msr_content); + return 0; case MSR_CORE_PERF_GLOBAL_STATUS: gdprintk(XENLOG_INFO, "Can not write readonly MSR: " "MSR_PERF_GLOBAL_STATUS(0x38E)!\n"); return -EINVAL; + case MSR_CORE_PERF_GLOBAL_INUSE: + gdprintk(XENLOG_INFO, "Can not write readonly MSR: " + "MSR_PERF_GLOBAL_INUSE(0x392)!\n"); + return -EINVAL; case MSR_IA32_PEBS_ENABLE: if ( vpmu_features & (XENPMU_FEATURE_IPC_ONLY | XENPMU_FEATURE_ARCH_ONLY) ) @@ -688,7 +701,8 @@ static int cf_check core2_vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content) core2_vpmu_cxt = vpmu->context; switch ( msr ) { - case MSR_CORE_PERF_GLOBAL_OVF_CTRL: + case MSR_CORE_PERF_GLOBAL_OVF_CTRL: /* FALLTHROUGH */ + case MSR_CORE_PERF_GLOBAL_STATUS_SET: *msr_content = 0; break; case MSR_CORE_PERF_GLOBAL_STATUS: @@ -700,6 +714,10 @@ static int cf_check core2_vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content) else rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, *msr_content); break; + case MSR_CORE_PERF_GLOBAL_INUSE: + if ( v->domain->arch.cpuid->basic.pmu_version < 4 ) + return -EINVAL; + /* FALLTHROUGH */ default: rdmsrl(msr, *msr_content); } diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index cd772585fe..af70ed8f30 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -3375,6 +3375,8 @@ static int cf_check vmx_msr_read_intercept( case MSR_CORE_PERF_FIXED_CTR_CTRL...MSR_CORE_PERF_GLOBAL_OVF_CTRL: case MSR_IA32_PEBS_ENABLE: case MSR_IA32_DS_AREA: + case MSR_CORE_PERF_GLOBAL_STATUS_SET: + case MSR_CORE_PERF_GLOBAL_INUSE: if ( vpmu_do_rdmsr(msr, msr_content) ) goto gp_fault; break; @@ -3698,6 +3700,9 @@ static int cf_check vmx_msr_write_intercept( case MSR_IA32_PEBS_ENABLE: case MSR_IA32_DS_AREA: if ( vpmu_do_wrmsr(msr, msr_content) ) + case MSR_CORE_PERF_GLOBAL_STATUS_SET: + case MSR_CORE_PERF_GLOBAL_INUSE: + if ( vpmu_do_wrmsr(msr, msr_content) ) goto gp_fault; break; diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index 09bfde1060..105485bb1e 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -968,6 +968,9 @@ static int cf_check read_msr( case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL_LAST: case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTRn: case MSR_CORE_PERF_FIXED_CTR_CTRL ... MSR_CORE_PERF_GLOBAL_OVF_CTRL: + case MSR_IA32_PEBS_ENABLE: + case MSR_CORE_PERF_GLOBAL_STATUS_SET: + case MSR_CORE_PERF_GLOBAL_INUSE: if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ) { vpmu_msr = true; @@ -1148,6 +1151,8 @@ static int cf_check write_msr( case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL_LAST: case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTRn: case MSR_CORE_PERF_FIXED_CTR_CTRL ... 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We can save/restore its state when saving/loading vPMU state, and otherwise let the guest read it directly. This is an optimization, perhaps it'd need a flag to disable it for debugging purposes. Signed-off-by: Edwin Török --- xen/arch/x86/cpu/vpmu_intel.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index 5e660af395..59d0b2ca36 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -67,6 +67,7 @@ static bool_t __read_mostly full_width_write; /* Number of general-purpose and fixed performance counters */ unsigned int __read_mostly arch_pmc_cnt, fixed_pmc_cnt; +static unsigned int __read_mostly vpmu_version; /* Masks used for testing whether and MSR is valid */ #define ARCH_CTRL_MASK (~((1ull << 32) - 1) | (1ull << 21) | ARCH_CNTR_PIN_CONTROL) @@ -228,6 +229,9 @@ static void core2_vpmu_set_msr_bitmap(struct vcpu *v) vmx_clear_msr_intercept(v, MSR_CORE_PERF_FIXED_CTR_CTRL, VMX_MSR_R); vmx_clear_msr_intercept(v, MSR_IA32_DS_AREA, VMX_MSR_R); + + if ( vpmu_version >= 4 ) + vmx_clear_msr_intercept(v, MSR_CORE_PERF_GLOBAL_STATUS, VMX_MSR_R); } static void core2_vpmu_unset_msr_bitmap(struct vcpu *v) @@ -250,6 +254,9 @@ static void core2_vpmu_unset_msr_bitmap(struct vcpu *v) vmx_set_msr_intercept(v, MSR_CORE_PERF_FIXED_CTR_CTRL, VMX_MSR_R); vmx_set_msr_intercept(v, MSR_IA32_DS_AREA, VMX_MSR_R); + + if ( vpmu_version >= 4 ) + vmx_set_msr_intercept(v, MSR_CORE_PERF_GLOBAL_STATUS, VMX_MSR_R); } static inline void __core2_vpmu_save(struct vcpu *v) @@ -268,7 +275,7 @@ static inline void __core2_vpmu_save(struct vcpu *v) rdmsrl(MSR_P6_EVNTSEL(i), xen_pmu_cntr_pair[i].control); } - if ( !is_hvm_vcpu(v) ) + if ( !is_hvm_vcpu(v) || vpmu_version >= 4 ) rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, core2_vpmu_cxt->global_status); /* Save MSR to private context to make it fork-friendly */ else if ( mem_sharing_enabled(v->domain) ) @@ -338,6 +345,15 @@ static inline void __core2_vpmu_load(struct vcpu *v) else if ( mem_sharing_is_fork(v->domain) ) vmx_write_guest_msr(v, MSR_CORE_PERF_GLOBAL_CTRL, core2_vpmu_cxt->global_ctrl); + + if ( vpmu_version >= 4 ) { + const uint64_t global_status = core2_vpmu_cxt->global_status; + const uint64_t reset = (~global_status) & global_ovf_ctrl_mask ; + if ( reset ) + wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, reset); + if ( global_status ) + wrmsrl(MSR_CORE_PERF_GLOBAL_STATUS_SET, global_status); + } } static int core2_vpmu_verify(struct vcpu *v) @@ -917,6 +933,7 @@ const struct arch_vpmu_ops *__init core2_vpmu_init(void) printk(XENLOG_INFO "VPMU: PMU version %u is not fully supported. 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Wed, 25 Oct 2023 12:30:14 -0700 (PDT) From: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [RFC PATCH 20/22] x86/PMUv5: limit available fixed PMCs and enable support Date: Wed, 25 Oct 2023 20:29:50 +0100 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Edwin Török AnyThread deprecation means a bit in 0xa edx, which we pass through. (we could also avoid doing the anythread masking, but we need that for version <= 4 support). Fixed Counter enumeration means we need to limit fixed counters if we hide any. Domain separation needs no action from the hypervisor AFAICT. Signed-off-by: Edwin Török --- xen/arch/x86/cpuid.c | 3 ++- xen/arch/x86/include/asm/vpmu.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c index 12e768ae87..8900943bcd 100644 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -338,7 +338,8 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf, res->a = u.eax; /* We only implement 3 fixed function counters */ - if ( (res->d & 0x1f) > fixed_pmc_cnt ) + res->c &= ~((1 << fixed_pmc_cnt) - 1); + if ( (res->d & 0x1f) > fixed_pmc_cnt) res->d = (res->d & ~0x1f) | fixed_pmc_cnt; } break; diff --git a/xen/arch/x86/include/asm/vpmu.h b/xen/arch/x86/include/asm/vpmu.h index eaededadb5..f066b17e45 100644 --- a/xen/arch/x86/include/asm/vpmu.h +++ b/xen/arch/x86/include/asm/vpmu.h @@ -74,7 +74,7 @@ struct vpmu_struct { #define VPMU_CPU_HAS_DS 0x1000 /* Has Debug Store */ #define VPMU_CPU_HAS_BTS 0x2000 /* Has Branch Trace Store */ -#define VPMU_VERSION_MAX 0x4 +#define VPMU_VERSION_MAX 0x5 #define VPMU_VERSION_MAX_SUPPORTED 0x5 static inline void vpmu_set(struct vpmu_struct *vpmu, const u32 mask) From patchwork Wed Oct 25 19:29:51 2023 Content-Type: text/plain; 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Wed, 25 Oct 2023 12:30:15 -0700 (PDT) From: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [RFC PATCH 21/22] x86/AMD: fix CPUID for PerfCtr{4,5} Date: Wed, 25 Oct 2023 20:29:51 +0100 Message-Id: <29b4fbb1045bb7cb49facfe2bc3e470fd74234bf.1698261255.git.edwin.torok@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Edwin Török These are available, but were hidden by CPUID previously. There are IR (all guests), NB and L2I (dom0 only) performance counters too that need to be implemented, add placeholder entries for them. Signed-off-by: Edwin Török --- xen/arch/x86/cpu-policy.c | 14 +++++++++++--- xen/arch/x86/hvm/svm/svm.c | 1 + xen/arch/x86/pv/emul-priv-op.c | 1 + xen/include/public/arch-x86/cpufeatureset.h | 4 ++++ 4 files changed, 17 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index e38b648f7d..4242a21e1d 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -340,9 +340,16 @@ static void recalculate_misc(struct cpu_policy *p) p->extd.raw[0x1e] = EMPTY_LEAF; /* TopoExt APIC ID/Core/Node */ p->extd.raw[0x1f] = EMPTY_LEAF; /* SEV */ p->extd.raw[0x20] = EMPTY_LEAF; /* Platform QoS */ - break; - } -} + + /* These are not implemented yet, hide from CPUID. + * When they become implemented, make them available when full vpmu is on */ + p->extd.irperf = 0; + p->extd.perfctrextnb = 0; + p->extd.perfctrextl2i = 0; + + break; + } + } void calculate_raw_cpu_policy(void) { @@ -391,6 +398,7 @@ static void __init calculate_host_policy(void) if ( vpmu_mode == XENPMU_MODE_OFF ) { p->basic.raw[0xa] = EMPTY_LEAF; p->basic.pdcm = 0; + p->extd.perfctrextcore = 0; } if ( p->extd.svm ) diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 45f8e1ffd1..ecb6184f51 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -1905,6 +1905,7 @@ static int cf_check svm_msr_read_intercept( case MSR_AMD_FAM15H_EVNTSEL3: case MSR_AMD_FAM15H_EVNTSEL4: case MSR_AMD_FAM15H_EVNTSEL5: + /* TODO: IRPerfCnt, L2I_* and NB_* support */ if ( vpmu_do_rdmsr(msr, msr_content) ) goto gpf; break; diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index 105485bb1e..8d802b5df0 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -1156,6 +1156,7 @@ static int cf_check write_msr( if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ) { vpmu_msr = true; + /* fall-through */ case MSR_AMD_FAM15H_EVNTSEL0 ... MSR_AMD_FAM15H_PERFCTR5: case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3: if ( vpmu_msr || (boot_cpu_data.x86_vendor & diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 0aa3251397..5faca0bf7a 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -166,7 +166,10 @@ XEN_CPUFEATURE(FMA4, 3*32+16) /*A 4 operands MAC instructions */ XEN_CPUFEATURE(NODEID_MSR, 3*32+19) /* NodeId MSR */ XEN_CPUFEATURE(TBM, 3*32+21) /*A trailing bit manipulations */ XEN_CPUFEATURE(TOPOEXT, 3*32+22) /* topology extensions CPUID leafs */ +XEN_CPUFEATURE(PERFCTREXTCORE, 3*32+23) /*A! Extended core performance event-select registers */ +XEN_CPUFEATURE(PERFCTREXTNB, 3*32+24) /* Extended Northbridge performance counters */ XEN_CPUFEATURE(DBEXT, 3*32+26) /*A data breakpoint extension */ +XEN_CPUFEATURE(PERFCTREXTL2I, 3*32+28) /* Extended L2 cache performance counters */ XEN_CPUFEATURE(MONITORX, 3*32+29) /* MONITOR extension (MONITORX/MWAITX) */ /* Intel-defined CPU features, CPUID level 0x0000000D:1.eax, word 4 */ @@ -238,6 +241,7 @@ XEN_CPUFEATURE(EFRO, 7*32+10) /* APERF/MPERF Read Only interface */ /* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */ XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */ +XEN_CPUFEATURE(IRPERF, 8*32+ 1) /* Instruction Retired Performance Counter */ XEN_CPUFEATURE(RSTR_FP_ERR_PTRS, 8*32+ 2) /*A (F)X{SAVE,RSTOR} always saves/restores FPU Error pointers */ XEN_CPUFEATURE(WBNOINVD, 8*32+ 9) /* WBNOINVD instruction */ XEN_CPUFEATURE(IBPB, 8*32+12) /*A IBPB support only (no IBRS, used by AMD) */ From patchwork Wed Oct 25 19:29:52 2023 Content-Type: text/plain; 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Wed, 25 Oct 2023 12:30:15 -0700 (PDT) From: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?b?RWR3aW4gVMO2csO2aw==?= , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [RFC PATCH 22/22] x86/AMD: add IRPerf support Date: Wed, 25 Oct 2023 20:29:52 +0100 Message-Id: <6cd765e98fa4888b9e94215f3572a94e95fe2a4b.1698261255.git.edwin.torok@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Edwin Török Instruction retired perf counter, enabled by writing to a bit in HWCR. Signed-off-by: Edwin Török --- xen/arch/x86/include/asm/msr-index.h | 1 + xen/arch/x86/msr.c | 7 +++++++ xen/include/public/arch-x86/cpufeatureset.h | 2 +- 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 061b07c7ae..1d94fe3a5b 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -393,6 +393,7 @@ #define MSR_K8_HWCR 0xc0010015 #define K8_HWCR_TSC_FREQ_SEL (1ULL << 24) +#define K8_HWCR_IRPERF_EN (1ULL << 30) #define K8_HWCR_CPUID_USER_DIS (1ULL << 35) #define MSR_K7_FID_VID_CTL 0xc0010041 diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 483b5e4f70..b3cd851d9d 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -584,6 +584,13 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) } break; + case MSR_K8_HWCR: + if ( !(cp->x86_vendor & X86_VENDOR_AMD) || + (val & ~K8_HWCR_IRPERF_EN) || + wrmsr_safe(msr, val) != 0 ) + goto gp_fault; + break; + case MSR_AMD64_DE_CFG: /* * OpenBSD 6.7 will panic if writing to DE_CFG triggers a #GP: diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 5faca0bf7a..40f74cd5e8 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -241,7 +241,7 @@ XEN_CPUFEATURE(EFRO, 7*32+10) /* APERF/MPERF Read Only interface */ /* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */ XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */ -XEN_CPUFEATURE(IRPERF, 8*32+ 1) /* Instruction Retired Performance Counter */ +XEN_CPUFEATURE(IRPERF, 8*32+ 1) /*A! Instruction Retired Performance Counter */ XEN_CPUFEATURE(RSTR_FP_ERR_PTRS, 8*32+ 2) /*A (F)X{SAVE,RSTOR} always saves/restores FPU Error pointers */ XEN_CPUFEATURE(WBNOINVD, 8*32+ 9) /* WBNOINVD instruction */ XEN_CPUFEATURE(IBPB, 8*32+12) /*A IBPB support only (no IBRS, used by AMD) */