From patchwork Sun Oct 29 06:03:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13439709 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3051C4708E for ; Sun, 29 Oct 2023 06:05:52 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qwyuG-0002Bm-H1; Sun, 29 Oct 2023 02:04:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwyuE-0002Ai-9y for qemu-devel@nongnu.org; Sun, 29 Oct 2023 02:04:15 -0400 Received: from mail-pf1-f172.google.com ([209.85.210.172]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwyuA-0001m3-TC for qemu-devel@nongnu.org; Sun, 29 Oct 2023 02:04:14 -0400 Received: by mail-pf1-f172.google.com with SMTP id d2e1a72fcca58-6b26a3163acso2884004b3a.2 for ; Sat, 28 Oct 2023 23:04:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698559449; x=1699164249; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uly2GlWW76uVdEBogdnvfJFvgrZfN8PqNdxFiox0Dc0=; b=rvxa4k21fD4CsmGEUGxdMjkvKZVDLO/RWQV/wlJWMX4iWuoheqyJLosw/xfHCbWXMP PaRFSLm3UPLyYz616Vj5OIo6PD5L9iqbjhcYWlr3ZOCqMdPtmF0shVV5C93JYZwk7unl r2mrXDU5Tzh3DVeMAnkQmfhqzc4nlHBGciwUqzYDhR5Q6TYh8R4AqdOvXB/YWnaOwmmn U6Vgt/MRTDJTNxuJp21fsYoUJdB9Yv+r/T7v2hGMzBPD9xOH+TScRi1oSei1KD7iXdq0 9m5808egT3GA8APuMG3arPekkLW7LmtVrPaUH08fZNaQ4kLMjfCImw6P3FJFD0gVmG9A z/+A== X-Gm-Message-State: AOJu0YxVndCX3P9IPubyyPr3XH1Uwlwu64067Gimg1buA5V1Ld8Riall rsq9xIAxDtQUmEDaZMXwB2bIMtfPE8LqqA== X-Google-Smtp-Source: AGHT+IE4YdFreAIEEILqTQ9HfOKGgWOH9D/HuJDzhp7CBmpTqEcidnNDz76E2tv2sVxExehxUNxm0Q== X-Received: by 2002:a05:6a20:938f:b0:17d:f127:d435 with SMTP id x15-20020a056a20938f00b0017df127d435mr7507268pzh.45.1698559449020; Sat, 28 Oct 2023 23:04:09 -0700 (PDT) Received: from localhost.localdomain ([2601:642:4c02:6ead:344e:2b1:f5a5:58c6]) by smtp.gmail.com with ESMTPSA id u12-20020a17090341cc00b001b8943b37a5sm4019518ple.24.2023.10.28.23.04.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 28 Oct 2023 23:04:08 -0700 (PDT) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Stefan Berger , Stefan Berger Subject: [PATCH v3 01/14] tpm_crb: refactor common code Date: Sat, 28 Oct 2023 23:03:14 -0700 Message-ID: <20231029060404.71196-2-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231029060404.71196-1-j@getutm.app> References: <20231029060404.71196-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.210.172; envelope-from=osy86dev@gmail.com; helo=mail-pf1-f172.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In preparation for the SysBus variant, we move common code styled after the TPM TIS devices. To maintain compatibility, we do not rename the existing tpm-crb device. Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- docs/specs/tpm.rst | 1 + hw/tpm/tpm_crb.h | 76 +++++++++++ hw/tpm/tpm_crb.c | 270 ++++++---------------------------------- hw/tpm/tpm_crb_common.c | 216 ++++++++++++++++++++++++++++++++ hw/tpm/meson.build | 1 + hw/tpm/trace-events | 2 +- 6 files changed, 331 insertions(+), 235 deletions(-) create mode 100644 hw/tpm/tpm_crb.h create mode 100644 hw/tpm/tpm_crb_common.c diff --git a/docs/specs/tpm.rst b/docs/specs/tpm.rst index efe124a148..2bc29c9804 100644 --- a/docs/specs/tpm.rst +++ b/docs/specs/tpm.rst @@ -45,6 +45,7 @@ operating system. QEMU files related to TPM CRB interface: - ``hw/tpm/tpm_crb.c`` + - ``hw/tpm/tpm_crb_common.c`` SPAPR interface --------------- diff --git a/hw/tpm/tpm_crb.h b/hw/tpm/tpm_crb.h new file mode 100644 index 0000000000..da3a0cf256 --- /dev/null +++ b/hw/tpm/tpm_crb.h @@ -0,0 +1,76 @@ +/* + * tpm_crb.h - QEMU's TPM CRB interface emulator + * + * Copyright (c) 2018 Red Hat, Inc. + * + * Authors: + * Marc-André Lureau + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + * tpm_crb is a device for TPM 2.0 Command Response Buffer (CRB) Interface + * as defined in TCG PC Client Platform TPM Profile (PTP) Specification + * Family “2.0” Level 00 Revision 01.03 v22 + */ +#ifndef TPM_TPM_CRB_H +#define TPM_TPM_CRB_H + +#include "exec/memory.h" +#include "hw/acpi/tpm.h" +#include "sysemu/tpm_backend.h" +#include "tpm_ppi.h" + +#define CRB_CTRL_CMD_SIZE (TPM_CRB_ADDR_SIZE - A_CRB_DATA_BUFFER) + +typedef struct TPMCRBState { + TPMBackend *tpmbe; + TPMBackendCmd cmd; + uint32_t regs[TPM_CRB_R_MAX]; + MemoryRegion mmio; + MemoryRegion cmdmem; + + size_t be_buffer_size; + + bool ppi_enabled; + TPMPPI ppi; +} TPMCRBState; + +#define CRB_INTF_TYPE_CRB_ACTIVE 0b1 +#define CRB_INTF_VERSION_CRB 0b1 +#define CRB_INTF_CAP_LOCALITY_0_ONLY 0b0 +#define CRB_INTF_CAP_IDLE_FAST 0b0 +#define CRB_INTF_CAP_XFER_SIZE_64 0b11 +#define CRB_INTF_CAP_FIFO_NOT_SUPPORTED 0b0 +#define CRB_INTF_CAP_CRB_SUPPORTED 0b1 +#define CRB_INTF_IF_SELECTOR_CRB 0b1 + +enum crb_loc_ctrl { + CRB_LOC_CTRL_REQUEST_ACCESS = BIT(0), + CRB_LOC_CTRL_RELINQUISH = BIT(1), + CRB_LOC_CTRL_SEIZE = BIT(2), + CRB_LOC_CTRL_RESET_ESTABLISHMENT_BIT = BIT(3), +}; + +enum crb_ctrl_req { + CRB_CTRL_REQ_CMD_READY = BIT(0), + CRB_CTRL_REQ_GO_IDLE = BIT(1), +}; + +enum crb_start { + CRB_START_INVOKE = BIT(0), +}; + +enum crb_cancel { + CRB_CANCEL_INVOKE = BIT(0), +}; + +#define TPM_CRB_NO_LOCALITY 0xff + +void tpm_crb_request_completed(TPMCRBState *s, int ret); +enum TPMVersion tpm_crb_get_version(TPMCRBState *s); +int tpm_crb_pre_save(TPMCRBState *s); +void tpm_crb_reset(TPMCRBState *s, uint64_t baseaddr); +void tpm_crb_init_memory(Object *obj, TPMCRBState *s, Error **errp); + +#endif /* TPM_TPM_CRB_H */ diff --git a/hw/tpm/tpm_crb.c b/hw/tpm/tpm_crb.c index ea930da545..3ef4977fb5 100644 --- a/hw/tpm/tpm_crb.c +++ b/hw/tpm/tpm_crb.c @@ -31,257 +31,62 @@ #include "tpm_ppi.h" #include "trace.h" #include "qom/object.h" +#include "tpm_crb.h" struct CRBState { DeviceState parent_obj; - TPMBackend *tpmbe; - TPMBackendCmd cmd; - uint32_t regs[TPM_CRB_R_MAX]; - MemoryRegion mmio; - MemoryRegion cmdmem; - - size_t be_buffer_size; - - bool ppi_enabled; - TPMPPI ppi; + TPMCRBState state; }; typedef struct CRBState CRBState; DECLARE_INSTANCE_CHECKER(CRBState, CRB, TYPE_TPM_CRB) -#define CRB_INTF_TYPE_CRB_ACTIVE 0b1 -#define CRB_INTF_VERSION_CRB 0b1 -#define CRB_INTF_CAP_LOCALITY_0_ONLY 0b0 -#define CRB_INTF_CAP_IDLE_FAST 0b0 -#define CRB_INTF_CAP_XFER_SIZE_64 0b11 -#define CRB_INTF_CAP_FIFO_NOT_SUPPORTED 0b0 -#define CRB_INTF_CAP_CRB_SUPPORTED 0b1 -#define CRB_INTF_IF_SELECTOR_CRB 0b1 - -#define CRB_CTRL_CMD_SIZE (TPM_CRB_ADDR_SIZE - A_CRB_DATA_BUFFER) - -enum crb_loc_ctrl { - CRB_LOC_CTRL_REQUEST_ACCESS = BIT(0), - CRB_LOC_CTRL_RELINQUISH = BIT(1), - CRB_LOC_CTRL_SEIZE = BIT(2), - CRB_LOC_CTRL_RESET_ESTABLISHMENT_BIT = BIT(3), -}; - -enum crb_ctrl_req { - CRB_CTRL_REQ_CMD_READY = BIT(0), - CRB_CTRL_REQ_GO_IDLE = BIT(1), -}; - -enum crb_start { - CRB_START_INVOKE = BIT(0), -}; - -enum crb_cancel { - CRB_CANCEL_INVOKE = BIT(0), -}; - -#define TPM_CRB_NO_LOCALITY 0xff - -static uint64_t tpm_crb_mmio_read(void *opaque, hwaddr addr, - unsigned size) -{ - CRBState *s = CRB(opaque); - void *regs = (void *)&s->regs + (addr & ~3); - unsigned offset = addr & 3; - uint32_t val = *(uint32_t *)regs >> (8 * offset); - - switch (addr) { - case A_CRB_LOC_STATE: - val |= !tpm_backend_get_tpm_established_flag(s->tpmbe); - break; - } - - trace_tpm_crb_mmio_read(addr, size, val); - - return val; -} - -static uint8_t tpm_crb_get_active_locty(CRBState *s) -{ - if (!ARRAY_FIELD_EX32(s->regs, CRB_LOC_STATE, locAssigned)) { - return TPM_CRB_NO_LOCALITY; - } - return ARRAY_FIELD_EX32(s->regs, CRB_LOC_STATE, activeLocality); -} - -static void tpm_crb_mmio_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - CRBState *s = CRB(opaque); - uint8_t locty = addr >> 12; - - trace_tpm_crb_mmio_write(addr, size, val); - - switch (addr) { - case A_CRB_CTRL_REQ: - switch (val) { - case CRB_CTRL_REQ_CMD_READY: - ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, - tpmIdle, 0); - break; - case CRB_CTRL_REQ_GO_IDLE: - ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, - tpmIdle, 1); - break; - } - break; - case A_CRB_CTRL_CANCEL: - if (val == CRB_CANCEL_INVOKE && - s->regs[R_CRB_CTRL_START] & CRB_START_INVOKE) { - tpm_backend_cancel_cmd(s->tpmbe); - } - break; - case A_CRB_CTRL_START: - if (val == CRB_START_INVOKE && - !(s->regs[R_CRB_CTRL_START] & CRB_START_INVOKE) && - tpm_crb_get_active_locty(s) == locty) { - void *mem = memory_region_get_ram_ptr(&s->cmdmem); - - s->regs[R_CRB_CTRL_START] |= CRB_START_INVOKE; - s->cmd = (TPMBackendCmd) { - .in = mem, - .in_len = MIN(tpm_cmd_get_size(mem), s->be_buffer_size), - .out = mem, - .out_len = s->be_buffer_size, - }; - - tpm_backend_deliver_request(s->tpmbe, &s->cmd); - } - break; - case A_CRB_LOC_CTRL: - switch (val) { - case CRB_LOC_CTRL_RESET_ESTABLISHMENT_BIT: - /* not loc 3 or 4 */ - break; - case CRB_LOC_CTRL_RELINQUISH: - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, - locAssigned, 0); - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, - Granted, 0); - break; - case CRB_LOC_CTRL_REQUEST_ACCESS: - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, - Granted, 1); - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, - beenSeized, 0); - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, - locAssigned, 1); - break; - } - break; - } -} - -static const MemoryRegionOps tpm_crb_memory_ops = { - .read = tpm_crb_mmio_read, - .write = tpm_crb_mmio_write, - .endianness = DEVICE_LITTLE_ENDIAN, - .valid = { - .min_access_size = 1, - .max_access_size = 4, - }, -}; - -static void tpm_crb_request_completed(TPMIf *ti, int ret) +static void tpm_crb_none_request_completed(TPMIf *ti, int ret) { CRBState *s = CRB(ti); - s->regs[R_CRB_CTRL_START] &= ~CRB_START_INVOKE; - if (ret != 0) { - ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, - tpmSts, 1); /* fatal error */ - } - memory_region_set_dirty(&s->cmdmem, 0, CRB_CTRL_CMD_SIZE); + tpm_crb_request_completed(&s->state, ret); } -static enum TPMVersion tpm_crb_get_version(TPMIf *ti) +static enum TPMVersion tpm_crb_none_get_version(TPMIf *ti) { CRBState *s = CRB(ti); - return tpm_backend_get_tpm_version(s->tpmbe); + return tpm_crb_get_version(&s->state); } -static int tpm_crb_pre_save(void *opaque) +static int tpm_crb_none_pre_save(void *opaque) { CRBState *s = opaque; - tpm_backend_finish_sync(s->tpmbe); - - return 0; + return tpm_crb_pre_save(&s->state); } -static const VMStateDescription vmstate_tpm_crb = { +static const VMStateDescription vmstate_tpm_crb_none = { .name = "tpm-crb", - .pre_save = tpm_crb_pre_save, + .pre_save = tpm_crb_none_pre_save, .fields = (VMStateField[]) { - VMSTATE_UINT32_ARRAY(regs, CRBState, TPM_CRB_R_MAX), + VMSTATE_UINT32_ARRAY(state.regs, CRBState, TPM_CRB_R_MAX), VMSTATE_END_OF_LIST(), } }; -static Property tpm_crb_properties[] = { - DEFINE_PROP_TPMBE("tpmdev", CRBState, tpmbe), - DEFINE_PROP_BOOL("ppi", CRBState, ppi_enabled, true), +static Property tpm_crb_none_properties[] = { + DEFINE_PROP_TPMBE("tpmdev", CRBState, state.tpmbe), + DEFINE_PROP_BOOL("ppi", CRBState, state.ppi_enabled, true), DEFINE_PROP_END_OF_LIST(), }; -static void tpm_crb_reset(void *dev) +static void tpm_crb_none_reset(void *dev) { CRBState *s = CRB(dev); - if (s->ppi_enabled) { - tpm_ppi_reset(&s->ppi); - } - tpm_backend_reset(s->tpmbe); - - memset(s->regs, 0, sizeof(s->regs)); - - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, - tpmRegValidSts, 1); - ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, - tpmIdle, 1); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, - InterfaceType, CRB_INTF_TYPE_CRB_ACTIVE); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, - InterfaceVersion, CRB_INTF_VERSION_CRB); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, - CapLocality, CRB_INTF_CAP_LOCALITY_0_ONLY); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, - CapCRBIdleBypass, CRB_INTF_CAP_IDLE_FAST); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, - CapDataXferSizeSupport, CRB_INTF_CAP_XFER_SIZE_64); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, - CapFIFO, CRB_INTF_CAP_FIFO_NOT_SUPPORTED); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, - CapCRB, CRB_INTF_CAP_CRB_SUPPORTED); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, - InterfaceSelector, CRB_INTF_IF_SELECTOR_CRB); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, - RID, 0b0000); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID2, - VID, PCI_VENDOR_ID_IBM); - - s->regs[R_CRB_CTRL_CMD_SIZE] = CRB_CTRL_CMD_SIZE; - s->regs[R_CRB_CTRL_CMD_LADDR] = TPM_CRB_ADDR_BASE + A_CRB_DATA_BUFFER; - s->regs[R_CRB_CTRL_RSP_SIZE] = CRB_CTRL_CMD_SIZE; - s->regs[R_CRB_CTRL_RSP_ADDR] = TPM_CRB_ADDR_BASE + A_CRB_DATA_BUFFER; - - s->be_buffer_size = MIN(tpm_backend_get_buffer_size(s->tpmbe), - CRB_CTRL_CMD_SIZE); - - if (tpm_backend_startup_tpm(s->tpmbe, s->be_buffer_size) < 0) { - exit(1); - } + return tpm_crb_reset(&s->state, TPM_CRB_ADDR_BASE); } -static void tpm_crb_realize(DeviceState *dev, Error **errp) +static void tpm_crb_none_realize(DeviceState *dev, Error **errp) { CRBState *s = CRB(dev); @@ -289,64 +94,61 @@ static void tpm_crb_realize(DeviceState *dev, Error **errp) error_setg(errp, "at most one TPM device is permitted"); return; } - if (!s->tpmbe) { + if (!s->state.tpmbe) { error_setg(errp, "'tpmdev' property is required"); return; } - memory_region_init_io(&s->mmio, OBJECT(s), &tpm_crb_memory_ops, s, - "tpm-crb-mmio", sizeof(s->regs)); - memory_region_init_ram(&s->cmdmem, OBJECT(s), - "tpm-crb-cmd", CRB_CTRL_CMD_SIZE, errp); + tpm_crb_init_memory(OBJECT(s), &s->state, errp); memory_region_add_subregion(get_system_memory(), - TPM_CRB_ADDR_BASE, &s->mmio); + TPM_CRB_ADDR_BASE, &s->state.mmio); memory_region_add_subregion(get_system_memory(), - TPM_CRB_ADDR_BASE + sizeof(s->regs), &s->cmdmem); + TPM_CRB_ADDR_BASE + sizeof(s->state.regs), &s->state.cmdmem); - if (s->ppi_enabled) { - tpm_ppi_init(&s->ppi, get_system_memory(), + if (s->state.ppi_enabled) { + tpm_ppi_init(&s->state.ppi, get_system_memory(), TPM_PPI_ADDR_BASE, OBJECT(s)); } if (xen_enabled()) { - tpm_crb_reset(dev); + tpm_crb_none_reset(dev); } else { - qemu_register_reset(tpm_crb_reset, dev); + qemu_register_reset(tpm_crb_none_reset, dev); } } -static void tpm_crb_class_init(ObjectClass *klass, void *data) +static void tpm_crb_none_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); TPMIfClass *tc = TPM_IF_CLASS(klass); - dc->realize = tpm_crb_realize; - device_class_set_props(dc, tpm_crb_properties); - dc->vmsd = &vmstate_tpm_crb; + dc->realize = tpm_crb_none_realize; + device_class_set_props(dc, tpm_crb_none_properties); + dc->vmsd = &vmstate_tpm_crb_none; dc->user_creatable = true; tc->model = TPM_MODEL_TPM_CRB; - tc->get_version = tpm_crb_get_version; - tc->request_completed = tpm_crb_request_completed; + tc->get_version = tpm_crb_none_get_version; + tc->request_completed = tpm_crb_none_request_completed; set_bit(DEVICE_CATEGORY_MISC, dc->categories); } -static const TypeInfo tpm_crb_info = { +static const TypeInfo tpm_crb_none_info = { .name = TYPE_TPM_CRB, /* could be TYPE_SYS_BUS_DEVICE (or LPC etc) */ .parent = TYPE_DEVICE, .instance_size = sizeof(CRBState), - .class_init = tpm_crb_class_init, + .class_init = tpm_crb_none_class_init, .interfaces = (InterfaceInfo[]) { { TYPE_TPM_IF }, { } } }; -static void tpm_crb_register(void) +static void tpm_crb_none_register(void) { - type_register_static(&tpm_crb_info); + type_register_static(&tpm_crb_none_info); } -type_init(tpm_crb_register) +type_init(tpm_crb_none_register) diff --git a/hw/tpm/tpm_crb_common.c b/hw/tpm/tpm_crb_common.c new file mode 100644 index 0000000000..fa463f295f --- /dev/null +++ b/hw/tpm/tpm_crb_common.c @@ -0,0 +1,216 @@ +/* + * tpm_crb.c - QEMU's TPM CRB interface emulator + * + * Copyright (c) 2018 Red Hat, Inc. + * + * Authors: + * Marc-André Lureau + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + * tpm_crb is a device for TPM 2.0 Command Response Buffer (CRB) Interface + * as defined in TCG PC Client Platform TPM Profile (PTP) Specification + * Family “2.0” Level 00 Revision 01.03 v22 + */ + +#include "qemu/osdep.h" + +#include "qemu/module.h" +#include "qapi/error.h" +#include "exec/address-spaces.h" +#include "hw/qdev-properties.h" +#include "hw/pci/pci_ids.h" +#include "hw/acpi/tpm.h" +#include "migration/vmstate.h" +#include "sysemu/tpm_backend.h" +#include "sysemu/tpm_util.h" +#include "tpm_prop.h" +#include "tpm_ppi.h" +#include "trace.h" +#include "qom/object.h" +#include "tpm_crb.h" + +static uint64_t tpm_crb_mmio_read(void *opaque, hwaddr addr, + unsigned size) +{ + TPMCRBState *s = opaque; + void *regs = (void *)&s->regs + (addr & ~3); + unsigned offset = addr & 3; + uint32_t val = *(uint32_t *)regs >> (8 * offset); + + switch (addr) { + case A_CRB_LOC_STATE: + val |= !tpm_backend_get_tpm_established_flag(s->tpmbe); + break; + } + + trace_tpm_crb_mmio_read(addr, size, val); + + return val; +} + +static uint8_t tpm_crb_get_active_locty(TPMCRBState *s) +{ + if (!ARRAY_FIELD_EX32(s->regs, CRB_LOC_STATE, locAssigned)) { + return TPM_CRB_NO_LOCALITY; + } + return ARRAY_FIELD_EX32(s->regs, CRB_LOC_STATE, activeLocality); +} + +static void tpm_crb_mmio_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + TPMCRBState *s = opaque; + uint8_t locty = addr >> 12; + + trace_tpm_crb_mmio_write(addr, size, val); + + switch (addr) { + case A_CRB_CTRL_REQ: + switch (val) { + case CRB_CTRL_REQ_CMD_READY: + ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, + tpmIdle, 0); + break; + case CRB_CTRL_REQ_GO_IDLE: + ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, + tpmIdle, 1); + break; + } + break; + case A_CRB_CTRL_CANCEL: + if (val == CRB_CANCEL_INVOKE && + s->regs[R_CRB_CTRL_START] & CRB_START_INVOKE) { + tpm_backend_cancel_cmd(s->tpmbe); + } + break; + case A_CRB_CTRL_START: + if (val == CRB_START_INVOKE && + !(s->regs[R_CRB_CTRL_START] & CRB_START_INVOKE) && + tpm_crb_get_active_locty(s) == locty) { + void *mem = memory_region_get_ram_ptr(&s->cmdmem); + + s->regs[R_CRB_CTRL_START] |= CRB_START_INVOKE; + s->cmd = (TPMBackendCmd) { + .in = mem, + .in_len = MIN(tpm_cmd_get_size(mem), s->be_buffer_size), + .out = mem, + .out_len = s->be_buffer_size, + }; + + tpm_backend_deliver_request(s->tpmbe, &s->cmd); + } + break; + case A_CRB_LOC_CTRL: + switch (val) { + case CRB_LOC_CTRL_RESET_ESTABLISHMENT_BIT: + /* not loc 3 or 4 */ + break; + case CRB_LOC_CTRL_RELINQUISH: + ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, + locAssigned, 0); + ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, + Granted, 0); + break; + case CRB_LOC_CTRL_REQUEST_ACCESS: + ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, + Granted, 1); + ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, + beenSeized, 0); + ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, + locAssigned, 1); + break; + } + break; + } +} + +const MemoryRegionOps tpm_crb_memory_ops = { + .read = tpm_crb_mmio_read, + .write = tpm_crb_mmio_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 4, + }, +}; + +void tpm_crb_request_completed(TPMCRBState *s, int ret) +{ + s->regs[R_CRB_CTRL_START] &= ~CRB_START_INVOKE; + if (ret != 0) { + ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, + tpmSts, 1); /* fatal error */ + } + memory_region_set_dirty(&s->cmdmem, 0, CRB_CTRL_CMD_SIZE); +} + +enum TPMVersion tpm_crb_get_version(TPMCRBState *s) +{ + return tpm_backend_get_tpm_version(s->tpmbe); +} + +int tpm_crb_pre_save(TPMCRBState *s) +{ + tpm_backend_finish_sync(s->tpmbe); + + return 0; +} + +void tpm_crb_reset(TPMCRBState *s, uint64_t baseaddr) +{ + if (s->ppi_enabled) { + tpm_ppi_reset(&s->ppi); + } + tpm_backend_reset(s->tpmbe); + + memset(s->regs, 0, sizeof(s->regs)); + + ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, + tpmRegValidSts, 1); + ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, + tpmIdle, 1); + ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + InterfaceType, CRB_INTF_TYPE_CRB_ACTIVE); + ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + InterfaceVersion, CRB_INTF_VERSION_CRB); + ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + CapLocality, CRB_INTF_CAP_LOCALITY_0_ONLY); + ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + CapCRBIdleBypass, CRB_INTF_CAP_IDLE_FAST); + ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + CapDataXferSizeSupport, CRB_INTF_CAP_XFER_SIZE_64); + ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + CapFIFO, CRB_INTF_CAP_FIFO_NOT_SUPPORTED); + ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + CapCRB, CRB_INTF_CAP_CRB_SUPPORTED); + ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + InterfaceSelector, CRB_INTF_IF_SELECTOR_CRB); + ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + RID, 0b0000); + ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID2, + VID, PCI_VENDOR_ID_IBM); + + baseaddr += A_CRB_DATA_BUFFER; + s->regs[R_CRB_CTRL_CMD_SIZE] = CRB_CTRL_CMD_SIZE; + s->regs[R_CRB_CTRL_CMD_LADDR] = (uint32_t)baseaddr; + s->regs[R_CRB_CTRL_CMD_HADDR] = (uint32_t)(baseaddr >> 32); + s->regs[R_CRB_CTRL_RSP_SIZE] = CRB_CTRL_CMD_SIZE; + s->regs[R_CRB_CTRL_RSP_ADDR] = (uint32_t)baseaddr; + + s->be_buffer_size = MIN(tpm_backend_get_buffer_size(s->tpmbe), + CRB_CTRL_CMD_SIZE); + + if (tpm_backend_startup_tpm(s->tpmbe, s->be_buffer_size) < 0) { + exit(1); + } +} + +void tpm_crb_init_memory(Object *obj, TPMCRBState *s, Error **errp) +{ + memory_region_init_io(&s->mmio, obj, &tpm_crb_memory_ops, s, + "tpm-crb-mmio", sizeof(s->regs)); + memory_region_init_ram(&s->cmdmem, obj, + "tpm-crb-cmd", CRB_CTRL_CMD_SIZE, errp); +} diff --git a/hw/tpm/meson.build b/hw/tpm/meson.build index 6968e60b3f..cb8204d5bc 100644 --- a/hw/tpm/meson.build +++ b/hw/tpm/meson.build @@ -3,6 +3,7 @@ system_ss.add(when: 'CONFIG_TPM_TIS_ISA', if_true: files('tpm_tis_isa.c')) system_ss.add(when: 'CONFIG_TPM_TIS_SYSBUS', if_true: files('tpm_tis_sysbus.c')) system_ss.add(when: 'CONFIG_TPM_TIS_I2C', if_true: files('tpm_tis_i2c.c')) system_ss.add(when: 'CONFIG_TPM_CRB', if_true: files('tpm_crb.c')) +system_ss.add(when: 'CONFIG_TPM_CRB', if_true: files('tpm_crb_common.c')) system_ss.add(when: 'CONFIG_TPM_TIS', if_true: files('tpm_ppi.c')) system_ss.add(when: 'CONFIG_TPM_CRB', if_true: files('tpm_ppi.c')) diff --git a/hw/tpm/trace-events b/hw/tpm/trace-events index fa882dfefe..3ab1bdb97b 100644 --- a/hw/tpm/trace-events +++ b/hw/tpm/trace-events @@ -1,6 +1,6 @@ # See docs/devel/tracing.rst for syntax documentation. -# tpm_crb.c +# tpm_crb_common.c tpm_crb_mmio_read(uint64_t addr, unsigned size, uint32_t val) "CRB read 0x%016" PRIx64 " len:%u val: 0x%" PRIx32 tpm_crb_mmio_write(uint64_t addr, unsigned size, uint32_t val) "CRB write 0x%016" PRIx64 " len:%u val: 0x%" PRIx32 From patchwork Sun Oct 29 06:03:15 2023 Content-Type: text/plain; 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Tsirkin" , Igor Mammedov , Ani Sinha , Thomas Huth , Laurent Vivier , Paolo Bonzini Subject: [PATCH v3 02/14] tpm_crb: CTRL_RSP_ADDR is 64-bits wide Date: Sat, 28 Oct 2023 23:03:15 -0700 Message-ID: <20231029060404.71196-3-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231029060404.71196-1-j@getutm.app> References: <20231029060404.71196-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.169; envelope-from=osy86dev@gmail.com; helo=mail-pl1-f169.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The register is actually 64-bits but in order to make this more clear than the specification, we define two 32-bit registers: CTRL_RSP_LADDR and CTRL_RSP_HADDR to match the CTRL_CMD_* naming. This deviates from the specs but is way more clear. Previously, the only CRB device uses a fixed system address so this was not an issue. However, once we support SysBus CRB device, the address can be anywhere in 64-bit space. Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- include/hw/acpi/tpm.h | 3 ++- hw/tpm/tpm_crb_common.c | 3 ++- tests/qtest/tpm-crb-test.c | 2 +- tests/qtest/tpm-util.c | 2 +- 4 files changed, 6 insertions(+), 4 deletions(-) diff --git a/include/hw/acpi/tpm.h b/include/hw/acpi/tpm.h index 579c45f5ba..f60bfe2789 100644 --- a/include/hw/acpi/tpm.h +++ b/include/hw/acpi/tpm.h @@ -174,7 +174,8 @@ REG32(CRB_CTRL_CMD_SIZE, 0x58) REG32(CRB_CTRL_CMD_LADDR, 0x5C) REG32(CRB_CTRL_CMD_HADDR, 0x60) REG32(CRB_CTRL_RSP_SIZE, 0x64) -REG32(CRB_CTRL_RSP_ADDR, 0x68) +REG32(CRB_CTRL_RSP_LADDR, 0x68) +REG32(CRB_CTRL_RSP_HADDR, 0x6C) REG32(CRB_DATA_BUFFER, 0x80) #define TPM_CRB_ADDR_BASE 0xFED40000 diff --git a/hw/tpm/tpm_crb_common.c b/hw/tpm/tpm_crb_common.c index fa463f295f..01b35808f6 100644 --- a/hw/tpm/tpm_crb_common.c +++ b/hw/tpm/tpm_crb_common.c @@ -197,7 +197,8 @@ void tpm_crb_reset(TPMCRBState *s, uint64_t baseaddr) s->regs[R_CRB_CTRL_CMD_LADDR] = (uint32_t)baseaddr; s->regs[R_CRB_CTRL_CMD_HADDR] = (uint32_t)(baseaddr >> 32); s->regs[R_CRB_CTRL_RSP_SIZE] = CRB_CTRL_CMD_SIZE; - s->regs[R_CRB_CTRL_RSP_ADDR] = (uint32_t)baseaddr; + s->regs[R_CRB_CTRL_RSP_LADDR] = (uint32_t)baseaddr; + s->regs[R_CRB_CTRL_RSP_HADDR] = (uint32_t)(baseaddr >> 32); s->be_buffer_size = MIN(tpm_backend_get_buffer_size(s->tpmbe), CRB_CTRL_CMD_SIZE); diff --git a/tests/qtest/tpm-crb-test.c b/tests/qtest/tpm-crb-test.c index 396ae3f91c..9d30fe8293 100644 --- a/tests/qtest/tpm-crb-test.c +++ b/tests/qtest/tpm-crb-test.c @@ -28,7 +28,7 @@ static void tpm_crb_test(const void *data) uint32_t csize = readl(TPM_CRB_ADDR_BASE + A_CRB_CTRL_CMD_SIZE); uint64_t caddr = readq(TPM_CRB_ADDR_BASE + A_CRB_CTRL_CMD_LADDR); uint32_t rsize = readl(TPM_CRB_ADDR_BASE + A_CRB_CTRL_RSP_SIZE); - uint64_t raddr = readq(TPM_CRB_ADDR_BASE + A_CRB_CTRL_RSP_ADDR); + uint64_t raddr = readq(TPM_CRB_ADDR_BASE + A_CRB_CTRL_RSP_LADDR); uint8_t locstate = readb(TPM_CRB_ADDR_BASE + A_CRB_LOC_STATE); uint32_t locctrl = readl(TPM_CRB_ADDR_BASE + A_CRB_LOC_CTRL); uint32_t locsts = readl(TPM_CRB_ADDR_BASE + A_CRB_LOC_STS); diff --git a/tests/qtest/tpm-util.c b/tests/qtest/tpm-util.c index 1c0319e6e7..dd02057fc0 100644 --- a/tests/qtest/tpm-util.c +++ b/tests/qtest/tpm-util.c @@ -25,7 +25,7 @@ void tpm_util_crb_transfer(QTestState *s, unsigned char *rsp, size_t rsp_size) { uint64_t caddr = qtest_readq(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_CMD_LADDR); - uint64_t raddr = qtest_readq(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_RSP_ADDR); + uint64_t raddr = qtest_readq(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_RSP_LADDR); qtest_writeb(s, TPM_CRB_ADDR_BASE + A_CRB_LOC_CTRL, 1); From patchwork Sun Oct 29 06:03:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13439717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A3B9FC4332F for ; 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Sat, 28 Oct 2023 23:04:11 -0700 (PDT) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Stefan Berger , Stefan Berger Subject: [PATCH v3 03/14] tpm_ppi: refactor memory space initialization Date: Sat, 28 Oct 2023 23:03:16 -0700 Message-ID: <20231029060404.71196-4-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231029060404.71196-1-j@getutm.app> References: <20231029060404.71196-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.172; envelope-from=osy86dev@gmail.com; helo=mail-pl1-f172.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Instead of calling `memory_region_add_subregion` directly, we defer to the caller to do it. This allows us to re-use the code for a SysBus device. Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- hw/tpm/tpm_ppi.h | 10 +++------- hw/tpm/tpm_crb.c | 4 ++-- hw/tpm/tpm_crb_common.c | 3 +++ hw/tpm/tpm_ppi.c | 5 +---- hw/tpm/tpm_tis_isa.c | 5 +++-- 5 files changed, 12 insertions(+), 15 deletions(-) diff --git a/hw/tpm/tpm_ppi.h b/hw/tpm/tpm_ppi.h index bf5d4a300f..30863c6438 100644 --- a/hw/tpm/tpm_ppi.h +++ b/hw/tpm/tpm_ppi.h @@ -20,17 +20,13 @@ typedef struct TPMPPI { } TPMPPI; /** - * tpm_ppi_init: + * tpm_ppi_init_memory: * @tpmppi: a TPMPPI - * @m: the address-space / MemoryRegion to use - * @addr: the address of the PPI region * @obj: the owner object * - * Register the TPM PPI memory region at @addr on the given address - * space for the object @obj. + * Creates the TPM PPI memory region. **/ -void tpm_ppi_init(TPMPPI *tpmppi, MemoryRegion *m, - hwaddr addr, Object *obj); +void tpm_ppi_init_memory(TPMPPI *tpmppi, Object *obj); /** * tpm_ppi_reset: diff --git a/hw/tpm/tpm_crb.c b/hw/tpm/tpm_crb.c index 3ef4977fb5..598c3e0161 100644 --- a/hw/tpm/tpm_crb.c +++ b/hw/tpm/tpm_crb.c @@ -107,8 +107,8 @@ static void tpm_crb_none_realize(DeviceState *dev, Error **errp) TPM_CRB_ADDR_BASE + sizeof(s->state.regs), &s->state.cmdmem); if (s->state.ppi_enabled) { - tpm_ppi_init(&s->state.ppi, get_system_memory(), - TPM_PPI_ADDR_BASE, OBJECT(s)); + memory_region_add_subregion(get_system_memory(), + TPM_PPI_ADDR_BASE, &s->state.ppi.ram); } if (xen_enabled()) { diff --git a/hw/tpm/tpm_crb_common.c b/hw/tpm/tpm_crb_common.c index 01b35808f6..bee0b71fee 100644 --- a/hw/tpm/tpm_crb_common.c +++ b/hw/tpm/tpm_crb_common.c @@ -214,4 +214,7 @@ void tpm_crb_init_memory(Object *obj, TPMCRBState *s, Error **errp) "tpm-crb-mmio", sizeof(s->regs)); memory_region_init_ram(&s->cmdmem, obj, "tpm-crb-cmd", CRB_CTRL_CMD_SIZE, errp); + if (s->ppi_enabled) { + tpm_ppi_init_memory(&s->ppi, obj); + } } diff --git a/hw/tpm/tpm_ppi.c b/hw/tpm/tpm_ppi.c index 7f74e26ec6..40cab59afa 100644 --- a/hw/tpm/tpm_ppi.c +++ b/hw/tpm/tpm_ppi.c @@ -44,14 +44,11 @@ void tpm_ppi_reset(TPMPPI *tpmppi) } } -void tpm_ppi_init(TPMPPI *tpmppi, MemoryRegion *m, - hwaddr addr, Object *obj) +void tpm_ppi_init_memory(TPMPPI *tpmppi, Object *obj) { tpmppi->buf = qemu_memalign(qemu_real_host_page_size(), HOST_PAGE_ALIGN(TPM_PPI_ADDR_SIZE)); memory_region_init_ram_device_ptr(&tpmppi->ram, obj, "tpm-ppi", TPM_PPI_ADDR_SIZE, tpmppi->buf); vmstate_register_ram(&tpmppi->ram, DEVICE(obj)); - - memory_region_add_subregion(m, addr, &tpmppi->ram); } diff --git a/hw/tpm/tpm_tis_isa.c b/hw/tpm/tpm_tis_isa.c index 0367401586..d596f38c0f 100644 --- a/hw/tpm/tpm_tis_isa.c +++ b/hw/tpm/tpm_tis_isa.c @@ -134,8 +134,9 @@ static void tpm_tis_isa_realizefn(DeviceState *dev, Error **errp) TPM_TIS_ADDR_BASE, &s->mmio); if (s->ppi_enabled) { - tpm_ppi_init(&s->ppi, isa_address_space(ISA_DEVICE(dev)), - TPM_PPI_ADDR_BASE, OBJECT(dev)); + tpm_ppi_init_memory(&s->ppi, OBJECT(dev)); + memory_region_add_subregion(isa_address_space(ISA_DEVICE(dev)), + TPM_PPI_ADDR_BASE, &s->ppi.ram); } } From patchwork Sun Oct 29 06:03:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13439719 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72667C4332F for ; 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Sat, 28 Oct 2023 23:04:14 -0700 (PDT) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Stefan Berger Subject: [PATCH v3 04/14] tpm_crb: use a single read-as-mem/write-as-mmio mapping Date: Sat, 28 Oct 2023 23:03:17 -0700 Message-ID: <20231029060404.71196-5-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231029060404.71196-1-j@getutm.app> References: <20231029060404.71196-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.210.178; envelope-from=osy86dev@gmail.com; helo=mail-pf1-f178.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Apple Silicon, when Windows performs a LDP on the CRB MMIO space, the exception is not decoded by hardware and we cannot trap the MMIO read. This led to the idea from @agraf to use the same mapping type as ROM devices: namely that reads should be seen as memory type and writes should trap as MMIO. Once that was done, the second memory mapping of the command buffer region was redundent and was removed. A note about the removal of the read trap for `CRB_LOC_STATE`: The only usage was to return the most up-to-date value for `tpmEstablished`. However, `tpmEstablished` is only cleared when a TPM2_HashStart operation is called which only exists for locality 4. We do not handle locality 4. Indeed, the comment for the write handler of `CRB_LOC_CTRL` makes the same argument for why it is not calling the backend to reset the `tpmEstablished` bit (to 1). As this bit is unused, we do not need to worry about updating it for reads. In order to maintain migration compatibility with older versions of QEMU, we store a copy of the register data and command data which is used only during save/restore. Signed-off-by: Joelle van Dyne --- hw/tpm/tpm_crb.h | 5 +- hw/tpm/tpm_crb.c | 30 ++++++++- hw/tpm/tpm_crb_common.c | 143 +++++++++++++++++++++++----------------- 3 files changed, 112 insertions(+), 66 deletions(-) diff --git a/hw/tpm/tpm_crb.h b/hw/tpm/tpm_crb.h index da3a0cf256..36863e1664 100644 --- a/hw/tpm/tpm_crb.h +++ b/hw/tpm/tpm_crb.h @@ -26,9 +26,7 @@ typedef struct TPMCRBState { TPMBackend *tpmbe; TPMBackendCmd cmd; - uint32_t regs[TPM_CRB_R_MAX]; MemoryRegion mmio; - MemoryRegion cmdmem; size_t be_buffer_size; @@ -72,5 +70,8 @@ enum TPMVersion tpm_crb_get_version(TPMCRBState *s); int tpm_crb_pre_save(TPMCRBState *s); void tpm_crb_reset(TPMCRBState *s, uint64_t baseaddr); void tpm_crb_init_memory(Object *obj, TPMCRBState *s, Error **errp); +void tpm_crb_mem_save(TPMCRBState *s, uint32_t *saved_regs, void *saved_cmdmem); +void tpm_crb_mem_load(TPMCRBState *s, const uint32_t *saved_regs, + const void *saved_cmdmem); #endif /* TPM_TPM_CRB_H */ diff --git a/hw/tpm/tpm_crb.c b/hw/tpm/tpm_crb.c index 598c3e0161..99c64dd72a 100644 --- a/hw/tpm/tpm_crb.c +++ b/hw/tpm/tpm_crb.c @@ -37,6 +37,10 @@ struct CRBState { DeviceState parent_obj; TPMCRBState state; + + /* These states are only for migration */ + uint32_t saved_regs[TPM_CRB_R_MAX]; + MemoryRegion saved_cmdmem; }; typedef struct CRBState CRBState; @@ -57,18 +61,36 @@ static enum TPMVersion tpm_crb_none_get_version(TPMIf *ti) return tpm_crb_get_version(&s->state); } +/** + * For migrating to an older version of QEMU + */ static int tpm_crb_none_pre_save(void *opaque) { CRBState *s = opaque; + void *saved_cmdmem = memory_region_get_ram_ptr(&s->saved_cmdmem); + tpm_crb_mem_save(&s->state, s->saved_regs, saved_cmdmem); return tpm_crb_pre_save(&s->state); } +/** + * For migrating from an older version of QEMU + */ +static int tpm_crb_none_post_load(void *opaque, int version_id) +{ + CRBState *s = opaque; + void *saved_cmdmem = memory_region_get_ram_ptr(&s->saved_cmdmem); + + tpm_crb_mem_load(&s->state, s->saved_regs, saved_cmdmem); + return 0; +} + static const VMStateDescription vmstate_tpm_crb_none = { .name = "tpm-crb", .pre_save = tpm_crb_none_pre_save, + .post_load = tpm_crb_none_post_load, .fields = (VMStateField[]) { - VMSTATE_UINT32_ARRAY(state.regs, CRBState, TPM_CRB_R_MAX), + VMSTATE_UINT32_ARRAY(saved_regs, CRBState, TPM_CRB_R_MAX), VMSTATE_END_OF_LIST(), } }; @@ -101,10 +123,12 @@ static void tpm_crb_none_realize(DeviceState *dev, Error **errp) tpm_crb_init_memory(OBJECT(s), &s->state, errp); + /* only used for migration */ + memory_region_init_ram(&s->saved_cmdmem, OBJECT(s), + "tpm-crb-cmd", CRB_CTRL_CMD_SIZE, errp); + memory_region_add_subregion(get_system_memory(), TPM_CRB_ADDR_BASE, &s->state.mmio); - memory_region_add_subregion(get_system_memory(), - TPM_CRB_ADDR_BASE + sizeof(s->state.regs), &s->state.cmdmem); if (s->state.ppi_enabled) { memory_region_add_subregion(get_system_memory(), diff --git a/hw/tpm/tpm_crb_common.c b/hw/tpm/tpm_crb_common.c index bee0b71fee..605e8576e9 100644 --- a/hw/tpm/tpm_crb_common.c +++ b/hw/tpm/tpm_crb_common.c @@ -31,31 +31,12 @@ #include "qom/object.h" #include "tpm_crb.h" -static uint64_t tpm_crb_mmio_read(void *opaque, hwaddr addr, - unsigned size) +static uint8_t tpm_crb_get_active_locty(TPMCRBState *s, uint32_t *regs) { - TPMCRBState *s = opaque; - void *regs = (void *)&s->regs + (addr & ~3); - unsigned offset = addr & 3; - uint32_t val = *(uint32_t *)regs >> (8 * offset); - - switch (addr) { - case A_CRB_LOC_STATE: - val |= !tpm_backend_get_tpm_established_flag(s->tpmbe); - break; - } - - trace_tpm_crb_mmio_read(addr, size, val); - - return val; -} - -static uint8_t tpm_crb_get_active_locty(TPMCRBState *s) -{ - if (!ARRAY_FIELD_EX32(s->regs, CRB_LOC_STATE, locAssigned)) { + if (!ARRAY_FIELD_EX32(regs, CRB_LOC_STATE, locAssigned)) { return TPM_CRB_NO_LOCALITY; } - return ARRAY_FIELD_EX32(s->regs, CRB_LOC_STATE, activeLocality); + return ARRAY_FIELD_EX32(regs, CRB_LOC_STATE, activeLocality); } static void tpm_crb_mmio_write(void *opaque, hwaddr addr, @@ -63,35 +44,47 @@ static void tpm_crb_mmio_write(void *opaque, hwaddr addr, { TPMCRBState *s = opaque; uint8_t locty = addr >> 12; + uint32_t *regs; + void *mem; trace_tpm_crb_mmio_write(addr, size, val); + regs = memory_region_get_ram_ptr(&s->mmio); + mem = ®s[R_CRB_DATA_BUFFER]; + assert(regs); + + if (addr >= A_CRB_DATA_BUFFER) { + assert(addr + size <= TPM_CRB_ADDR_SIZE); + assert(size <= sizeof(val)); + memcpy(mem + addr - A_CRB_DATA_BUFFER, &val, size); + memory_region_set_dirty(&s->mmio, addr, size); + return; + } switch (addr) { case A_CRB_CTRL_REQ: switch (val) { case CRB_CTRL_REQ_CMD_READY: - ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, + ARRAY_FIELD_DP32(regs, CRB_CTRL_STS, tpmIdle, 0); break; case CRB_CTRL_REQ_GO_IDLE: - ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, + ARRAY_FIELD_DP32(regs, CRB_CTRL_STS, tpmIdle, 1); break; } break; case A_CRB_CTRL_CANCEL: if (val == CRB_CANCEL_INVOKE && - s->regs[R_CRB_CTRL_START] & CRB_START_INVOKE) { + regs[R_CRB_CTRL_START] & CRB_START_INVOKE) { tpm_backend_cancel_cmd(s->tpmbe); } break; case A_CRB_CTRL_START: if (val == CRB_START_INVOKE && - !(s->regs[R_CRB_CTRL_START] & CRB_START_INVOKE) && - tpm_crb_get_active_locty(s) == locty) { - void *mem = memory_region_get_ram_ptr(&s->cmdmem); + !(regs[R_CRB_CTRL_START] & CRB_START_INVOKE) && + tpm_crb_get_active_locty(s, regs) == locty) { - s->regs[R_CRB_CTRL_START] |= CRB_START_INVOKE; + regs[R_CRB_CTRL_START] |= CRB_START_INVOKE; s->cmd = (TPMBackendCmd) { .in = mem, .in_len = MIN(tpm_cmd_get_size(mem), s->be_buffer_size), @@ -108,26 +101,27 @@ static void tpm_crb_mmio_write(void *opaque, hwaddr addr, /* not loc 3 or 4 */ break; case CRB_LOC_CTRL_RELINQUISH: - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, + ARRAY_FIELD_DP32(regs, CRB_LOC_STATE, locAssigned, 0); - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, + ARRAY_FIELD_DP32(regs, CRB_LOC_STS, Granted, 0); break; case CRB_LOC_CTRL_REQUEST_ACCESS: - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, + ARRAY_FIELD_DP32(regs, CRB_LOC_STS, Granted, 1); - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, + ARRAY_FIELD_DP32(regs, CRB_LOC_STS, beenSeized, 0); - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, + ARRAY_FIELD_DP32(regs, CRB_LOC_STATE, locAssigned, 1); break; } break; } + + memory_region_set_dirty(&s->mmio, 0, A_CRB_DATA_BUFFER); } const MemoryRegionOps tpm_crb_memory_ops = { - .read = tpm_crb_mmio_read, .write = tpm_crb_mmio_write, .endianness = DEVICE_LITTLE_ENDIAN, .valid = { @@ -138,12 +132,16 @@ const MemoryRegionOps tpm_crb_memory_ops = { void tpm_crb_request_completed(TPMCRBState *s, int ret) { - s->regs[R_CRB_CTRL_START] &= ~CRB_START_INVOKE; + uint32_t *regs = memory_region_get_ram_ptr(&s->mmio); + + assert(regs); + regs[R_CRB_CTRL_START] &= ~CRB_START_INVOKE; if (ret != 0) { - ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, + ARRAY_FIELD_DP32(regs, CRB_CTRL_STS, tpmSts, 1); /* fatal error */ } - memory_region_set_dirty(&s->cmdmem, 0, CRB_CTRL_CMD_SIZE); + + memory_region_set_dirty(&s->mmio, 0, TPM_CRB_ADDR_SIZE); } enum TPMVersion tpm_crb_get_version(TPMCRBState *s) @@ -160,45 +158,50 @@ int tpm_crb_pre_save(TPMCRBState *s) void tpm_crb_reset(TPMCRBState *s, uint64_t baseaddr) { + uint32_t *regs = memory_region_get_ram_ptr(&s->mmio); + + assert(regs); if (s->ppi_enabled) { tpm_ppi_reset(&s->ppi); } tpm_backend_reset(s->tpmbe); - memset(s->regs, 0, sizeof(s->regs)); + memset(regs, 0, TPM_CRB_ADDR_SIZE); - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, + ARRAY_FIELD_DP32(regs, CRB_LOC_STATE, tpmRegValidSts, 1); - ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, + ARRAY_FIELD_DP32(regs, CRB_LOC_STATE, + tpmEstablished, 1); + ARRAY_FIELD_DP32(regs, CRB_CTRL_STS, tpmIdle, 1); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + ARRAY_FIELD_DP32(regs, CRB_INTF_ID, InterfaceType, CRB_INTF_TYPE_CRB_ACTIVE); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + ARRAY_FIELD_DP32(regs, CRB_INTF_ID, InterfaceVersion, CRB_INTF_VERSION_CRB); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + ARRAY_FIELD_DP32(regs, CRB_INTF_ID, CapLocality, CRB_INTF_CAP_LOCALITY_0_ONLY); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + ARRAY_FIELD_DP32(regs, CRB_INTF_ID, CapCRBIdleBypass, CRB_INTF_CAP_IDLE_FAST); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + ARRAY_FIELD_DP32(regs, CRB_INTF_ID, CapDataXferSizeSupport, CRB_INTF_CAP_XFER_SIZE_64); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + ARRAY_FIELD_DP32(regs, CRB_INTF_ID, CapFIFO, CRB_INTF_CAP_FIFO_NOT_SUPPORTED); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + ARRAY_FIELD_DP32(regs, CRB_INTF_ID, CapCRB, CRB_INTF_CAP_CRB_SUPPORTED); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + ARRAY_FIELD_DP32(regs, CRB_INTF_ID, InterfaceSelector, CRB_INTF_IF_SELECTOR_CRB); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + ARRAY_FIELD_DP32(regs, CRB_INTF_ID, RID, 0b0000); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID2, + ARRAY_FIELD_DP32(regs, CRB_INTF_ID2, VID, PCI_VENDOR_ID_IBM); baseaddr += A_CRB_DATA_BUFFER; - s->regs[R_CRB_CTRL_CMD_SIZE] = CRB_CTRL_CMD_SIZE; - s->regs[R_CRB_CTRL_CMD_LADDR] = (uint32_t)baseaddr; - s->regs[R_CRB_CTRL_CMD_HADDR] = (uint32_t)(baseaddr >> 32); - s->regs[R_CRB_CTRL_RSP_SIZE] = CRB_CTRL_CMD_SIZE; - s->regs[R_CRB_CTRL_RSP_LADDR] = (uint32_t)baseaddr; - s->regs[R_CRB_CTRL_RSP_HADDR] = (uint32_t)(baseaddr >> 32); + regs[R_CRB_CTRL_CMD_SIZE] = CRB_CTRL_CMD_SIZE; + regs[R_CRB_CTRL_CMD_LADDR] = (uint32_t)baseaddr; + regs[R_CRB_CTRL_CMD_HADDR] = (uint32_t)(baseaddr >> 32); + regs[R_CRB_CTRL_RSP_SIZE] = CRB_CTRL_CMD_SIZE; + regs[R_CRB_CTRL_RSP_LADDR] = (uint32_t)baseaddr; + regs[R_CRB_CTRL_RSP_HADDR] = (uint32_t)(baseaddr >> 32); s->be_buffer_size = MIN(tpm_backend_get_buffer_size(s->tpmbe), CRB_CTRL_CMD_SIZE); @@ -206,15 +209,33 @@ void tpm_crb_reset(TPMCRBState *s, uint64_t baseaddr) if (tpm_backend_startup_tpm(s->tpmbe, s->be_buffer_size) < 0) { exit(1); } + + memory_region_rom_device_set_romd(&s->mmio, true); + memory_region_set_dirty(&s->mmio, 0, TPM_CRB_ADDR_SIZE); } void tpm_crb_init_memory(Object *obj, TPMCRBState *s, Error **errp) { - memory_region_init_io(&s->mmio, obj, &tpm_crb_memory_ops, s, - "tpm-crb-mmio", sizeof(s->regs)); - memory_region_init_ram(&s->cmdmem, obj, - "tpm-crb-cmd", CRB_CTRL_CMD_SIZE, errp); + memory_region_init_rom_device_nomigrate(&s->mmio, obj, &tpm_crb_memory_ops, + s, "tpm-crb-mem", TPM_CRB_ADDR_SIZE, errp); if (s->ppi_enabled) { tpm_ppi_init_memory(&s->ppi, obj); } } + +void tpm_crb_mem_save(TPMCRBState *s, uint32_t *saved_regs, void *saved_cmdmem) +{ + uint32_t *regs = memory_region_get_ram_ptr(&s->mmio); + + memcpy(saved_regs, regs, TPM_CRB_R_MAX); + memcpy(saved_cmdmem, ®s[R_CRB_DATA_BUFFER], A_CRB_DATA_BUFFER); +} + +void tpm_crb_mem_load(TPMCRBState *s, const uint32_t *saved_regs, + const void *saved_cmdmem) +{ + uint32_t *regs = memory_region_get_ram_ptr(&s->mmio); + + memcpy(regs, saved_regs, TPM_CRB_R_MAX); + memcpy(®s[R_CRB_DATA_BUFFER], saved_cmdmem, A_CRB_DATA_BUFFER); +} From patchwork Sun Oct 29 06:03:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13439715 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3B906C4332F for ; Sun, 29 Oct 2023 06:06:41 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qwyuP-0002Ec-6U; Sun, 29 Oct 2023 02:04:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwyuN-0002EQ-FJ for qemu-devel@nongnu.org; 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Sat, 28 Oct 2023 23:04:19 -0700 (PDT) Received: from localhost.localdomain ([2601:642:4c02:6ead:344e:2b1:f5a5:58c6]) by smtp.gmail.com with ESMTPSA id u12-20020a17090341cc00b001b8943b37a5sm4019518ple.24.2023.10.28.23.04.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 28 Oct 2023 23:04:18 -0700 (PDT) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Stefan Berger , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum , Stefan Berger Subject: [PATCH v3 05/14] tpm_crb: move ACPI table building to device interface Date: Sat, 28 Oct 2023 23:03:18 -0700 Message-ID: <20231029060404.71196-6-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231029060404.71196-1-j@getutm.app> References: <20231029060404.71196-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.181; envelope-from=osy86dev@gmail.com; helo=mail-pg1-f181.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This logic is similar to TPM TIS ISA device. Since TPM CRB can only support TPM 2.0 backends, we check for this in realize. Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- hw/tpm/tpm_crb.h | 2 ++ hw/i386/acpi-build.c | 23 ----------------------- hw/tpm/tpm_crb.c | 16 ++++++++++++++++ hw/tpm/tpm_crb_common.c | 19 +++++++++++++++++++ 4 files changed, 37 insertions(+), 23 deletions(-) diff --git a/hw/tpm/tpm_crb.h b/hw/tpm/tpm_crb.h index 36863e1664..e6a86e3fd1 100644 --- a/hw/tpm/tpm_crb.h +++ b/hw/tpm/tpm_crb.h @@ -73,5 +73,7 @@ void tpm_crb_init_memory(Object *obj, TPMCRBState *s, Error **errp); void tpm_crb_mem_save(TPMCRBState *s, uint32_t *saved_regs, void *saved_cmdmem); void tpm_crb_mem_load(TPMCRBState *s, const uint32_t *saved_regs, const void *saved_cmdmem); +void tpm_crb_build_aml(TPMIf *ti, Aml *scope, uint32_t baseaddr, uint32_t size, + bool build_ppi); #endif /* TPM_TPM_CRB_H */ diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 80db183b78..ce3f7b2d91 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1441,9 +1441,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, uint32_t nr_mem = machine->ram_slots; int root_bus_limit = 0xFF; PCIBus *bus = NULL; -#ifdef CONFIG_TPM - TPMIf *tpm = tpm_find(); -#endif bool cxl_present = false; int i; VMBusBridge *vmbus_bridge = vmbus_bridge_find(); @@ -1790,26 +1787,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, } } -#ifdef CONFIG_TPM - if (TPM_IS_CRB(tpm)) { - dev = aml_device("TPM"); - aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); - aml_append(dev, aml_name_decl("_STR", - aml_string("TPM 2.0 Device"))); - crs = aml_resource_template(); - aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, - TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); - aml_append(dev, aml_name_decl("_CRS", crs)); - - aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); - aml_append(dev, aml_name_decl("_UID", aml_int(1))); - - tpm_build_ppi_acpi(tpm, dev); - - aml_append(sb_scope, dev); - } -#endif - if (pcms->sgx_epc.size != 0) { uint64_t epc_base = pcms->sgx_epc.base; uint64_t epc_size = pcms->sgx_epc.size; diff --git a/hw/tpm/tpm_crb.c b/hw/tpm/tpm_crb.c index 99c64dd72a..8d57295b15 100644 --- a/hw/tpm/tpm_crb.c +++ b/hw/tpm/tpm_crb.c @@ -19,6 +19,8 @@ #include "qemu/module.h" #include "qapi/error.h" #include "exec/address-spaces.h" +#include "hw/acpi/acpi_aml_interface.h" +#include "hw/acpi/tpm.h" #include "hw/qdev-properties.h" #include "hw/pci/pci_ids.h" #include "hw/acpi/tpm.h" @@ -121,6 +123,11 @@ static void tpm_crb_none_realize(DeviceState *dev, Error **errp) return; } + if (tpm_crb_none_get_version(TPM_IF(s)) != TPM_VERSION_2_0) { + error_setg(errp, "TPM CRB only supports TPM 2.0 backends"); + return; + } + tpm_crb_init_memory(OBJECT(s), &s->state, errp); /* only used for migration */ @@ -142,10 +149,17 @@ static void tpm_crb_none_realize(DeviceState *dev, Error **errp) } } +static void build_tpm_crb_none_aml(AcpiDevAmlIf *adev, Aml *scope) +{ + tpm_crb_build_aml(TPM_IF(adev), scope, TPM_CRB_ADDR_BASE, TPM_CRB_ADDR_SIZE, + true); +} + static void tpm_crb_none_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); TPMIfClass *tc = TPM_IF_CLASS(klass); + AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); dc->realize = tpm_crb_none_realize; device_class_set_props(dc, tpm_crb_none_properties); @@ -154,6 +168,7 @@ static void tpm_crb_none_class_init(ObjectClass *klass, void *data) tc->model = TPM_MODEL_TPM_CRB; tc->get_version = tpm_crb_none_get_version; tc->request_completed = tpm_crb_none_request_completed; + adevc->build_dev_aml = build_tpm_crb_none_aml; set_bit(DEVICE_CATEGORY_MISC, dc->categories); } @@ -166,6 +181,7 @@ static const TypeInfo tpm_crb_none_info = { .class_init = tpm_crb_none_class_init, .interfaces = (InterfaceInfo[]) { { TYPE_TPM_IF }, + { TYPE_ACPI_DEV_AML_IF }, { } } }; diff --git a/hw/tpm/tpm_crb_common.c b/hw/tpm/tpm_crb_common.c index 605e8576e9..4fff0c6b59 100644 --- a/hw/tpm/tpm_crb_common.c +++ b/hw/tpm/tpm_crb_common.c @@ -239,3 +239,22 @@ void tpm_crb_mem_load(TPMCRBState *s, const uint32_t *saved_regs, memcpy(regs, saved_regs, TPM_CRB_R_MAX); memcpy(®s[R_CRB_DATA_BUFFER], saved_cmdmem, A_CRB_DATA_BUFFER); } + +void tpm_crb_build_aml(TPMIf *ti, Aml *scope, uint32_t baseaddr, uint32_t size, + bool build_ppi) +{ + Aml *dev, *crs; + + dev = aml_device("TPM"); + aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); + aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device"))); + aml_append(dev, aml_name_decl("_UID", aml_int(1))); + aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); + crs = aml_resource_template(); + aml_append(crs, aml_memory32_fixed(baseaddr, size, AML_READ_WRITE)); + aml_append(dev, aml_name_decl("_CRS", crs)); + if (build_ppi) { + tpm_build_ppi_acpi(ti, dev); + } + aml_append(scope, dev); +} From patchwork Sun Oct 29 06:03:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13439705 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED1D1C4332F for ; Sun, 29 Oct 2023 06:05:52 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qwyuS-0002F4-4Z; Sun, 29 Oct 2023 02:04:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwyuO-0002Ea-Ll for qemu-devel@nongnu.org; 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Sat, 28 Oct 2023 23:04:21 -0700 (PDT) Received: from localhost.localdomain ([2601:642:4c02:6ead:344e:2b1:f5a5:58c6]) by smtp.gmail.com with ESMTPSA id u12-20020a17090341cc00b001b8943b37a5sm4019518ple.24.2023.10.28.23.04.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 28 Oct 2023 23:04:20 -0700 (PDT) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Stefan Berger Subject: [PATCH v3 06/14] tpm-sysbus: add plug handler for TPM on SysBus Date: Sat, 28 Oct 2023 23:03:19 -0700 Message-ID: <20231029060404.71196-7-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231029060404.71196-1-j@getutm.app> References: <20231029060404.71196-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.174; envelope-from=osy86dev@gmail.com; helo=mail-pg1-f174.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org TPM needs to know its own base address in order to generate its DSDT device entry. Signed-off-by: Joelle van Dyne --- include/sysemu/tpm.h | 4 ++++ hw/tpm/tpm-sysbus.c | 33 +++++++++++++++++++++++++++++++++ hw/tpm/meson.build | 1 + 3 files changed, 38 insertions(+) create mode 100644 hw/tpm/tpm-sysbus.c diff --git a/include/sysemu/tpm.h b/include/sysemu/tpm.h index 1ee568b3b6..ffd300e607 100644 --- a/include/sysemu/tpm.h +++ b/include/sysemu/tpm.h @@ -12,6 +12,8 @@ #ifndef QEMU_TPM_H #define QEMU_TPM_H +#include "qemu/osdep.h" +#include "exec/hwaddr.h" #include "qapi/qapi-types-tpm.h" #include "qom/object.h" @@ -78,6 +80,8 @@ static inline TPMVersion tpm_get_version(TPMIf *ti) return TPM_IF_GET_CLASS(ti)->get_version(ti); } +void tpm_sysbus_plug(TPMIf *tpmif, Object *pbus, hwaddr pbus_base); + #else /* CONFIG_TPM */ #define tpm_init() (0) diff --git a/hw/tpm/tpm-sysbus.c b/hw/tpm/tpm-sysbus.c new file mode 100644 index 0000000000..ef0592b837 --- /dev/null +++ b/hw/tpm/tpm-sysbus.c @@ -0,0 +1,33 @@ +#include "sysemu/tpm.h" +#include "hw/platform-bus.h" +#include "hw/sysbus.h" +#include "qapi/error.h" + +void tpm_sysbus_plug(TPMIf *tpmif, Object *pbus, hwaddr pbus_base) +{ + PlatformBusDevice *pbusdev = PLATFORM_BUS_DEVICE(pbus); + SysBusDevice *sbdev = SYS_BUS_DEVICE(tpmif); + MemoryRegion *sbdev_mr; + hwaddr tpm_base; + uint64_t tpm_size; + + /* exit early if TPM is not a sysbus device */ + if (!object_dynamic_cast(OBJECT(tpmif), TYPE_SYS_BUS_DEVICE)) { + return; + } + + assert(object_dynamic_cast(pbus, TYPE_PLATFORM_BUS_DEVICE)); + + tpm_base = platform_bus_get_mmio_addr(pbusdev, sbdev, 0); + assert(tpm_base != -1); + + tpm_base += pbus_base; + + sbdev_mr = sysbus_mmio_get_region(sbdev, 0); + tpm_size = memory_region_size(sbdev_mr); + + object_property_set_uint(OBJECT(sbdev), "x-baseaddr", + tpm_base, &error_abort); + object_property_set_uint(OBJECT(sbdev), "x-size", + tpm_size, &error_abort); +} diff --git a/hw/tpm/meson.build b/hw/tpm/meson.build index cb8204d5bc..3060ac05e8 100644 --- a/hw/tpm/meson.build +++ b/hw/tpm/meson.build @@ -1,6 +1,7 @@ system_ss.add(when: 'CONFIG_TPM_TIS', if_true: files('tpm_tis_common.c')) system_ss.add(when: 'CONFIG_TPM_TIS_ISA', if_true: files('tpm_tis_isa.c')) system_ss.add(when: 'CONFIG_TPM_TIS_SYSBUS', if_true: files('tpm_tis_sysbus.c')) +system_ss.add(when: 'CONFIG_TPM_TIS_SYSBUS', if_true: files('tpm-sysbus.c')) system_ss.add(when: 'CONFIG_TPM_TIS_I2C', if_true: files('tpm_tis_i2c.c')) system_ss.add(when: 'CONFIG_TPM_CRB', if_true: files('tpm_crb.c')) system_ss.add(when: 'CONFIG_TPM_CRB', if_true: files('tpm_crb_common.c')) From patchwork Sun Oct 29 06:03:20 2023 Content-Type: text/plain; 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Sat, 28 Oct 2023 23:04:22 -0700 (PDT) Received: from localhost.localdomain ([2601:642:4c02:6ead:344e:2b1:f5a5:58c6]) by smtp.gmail.com with ESMTPSA id u12-20020a17090341cc00b001b8943b37a5sm4019518ple.24.2023.10.28.23.04.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 28 Oct 2023 23:04:22 -0700 (PDT) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Peter Maydell , qemu-arm@nongnu.org (open list:Virt) Subject: [PATCH v3 07/14] hw/arm/virt: connect TPM to platform bus Date: Sat, 28 Oct 2023 23:03:20 -0700 Message-ID: <20231029060404.71196-8-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231029060404.71196-1-j@getutm.app> References: <20231029060404.71196-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.179; envelope-from=osy86dev@gmail.com; helo=mail-pl1-f179.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- hw/arm/virt.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 529f1c089c..f1a161b0ea 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2806,6 +2806,13 @@ static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, vms->virtio_iommu_bdf = pci_get_bdf(pdev); create_virtio_iommu_dt_bindings(vms); } + +#ifdef CONFIG_TPM + if (object_dynamic_cast(OBJECT(dev), TYPE_TPM_IF)) { + tpm_sysbus_plug(TPM_IF(dev), OBJECT(vms->platform_bus_dev), + vms->memmap[VIRT_PLATFORM_BUS].base); + } +#endif } static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, From patchwork Sun Oct 29 06:03:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13439714 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 079DBC4167D for ; Sun, 29 Oct 2023 06:06:22 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qwyuT-0002GB-JX; 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Sat, 28 Oct 2023 23:04:24 -0700 (PDT) Received: from localhost.localdomain ([2601:642:4c02:6ead:344e:2b1:f5a5:58c6]) by smtp.gmail.com with ESMTPSA id u12-20020a17090341cc00b001b8943b37a5sm4019518ple.24.2023.10.28.23.04.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 28 Oct 2023 23:04:23 -0700 (PDT) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Paolo Bonzini , Song Gao Subject: [PATCH v3 08/14] hw/loongarch/virt: connect TPM to platform bus Date: Sat, 28 Oct 2023 23:03:21 -0700 Message-ID: <20231029060404.71196-9-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231029060404.71196-1-j@getutm.app> References: <20231029060404.71196-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.179; envelope-from=osy86dev@gmail.com; helo=mail-pg1-f179.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- hw/loongarch/virt.c | 7 +++++++ hw/loongarch/Kconfig | 1 + 2 files changed, 8 insertions(+) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 4b7dc67a2d..feed0f8bbf 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -1004,6 +1004,13 @@ static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev, } else if (memhp_type_supported(dev)) { virt_mem_plug(hotplug_dev, dev, errp); } + +#ifdef CONFIG_TPM + if (object_dynamic_cast(OBJECT(dev), TYPE_TPM_IF)) { + tpm_sysbus_plug(TPM_IF(dev), OBJECT(lams->platform_bus_dev), + VIRT_PLATFORM_BUS_BASEADDRESS); + } +#endif } static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index 5727efed6d..25da190ffc 100644 --- a/hw/loongarch/Kconfig +++ b/hw/loongarch/Kconfig @@ -5,6 +5,7 @@ config LOONGARCH_VIRT imply VIRTIO_VGA imply PCI_DEVICES imply NVDIMM + imply TPM_TIS_SYSBUS select SERIAL select VIRTIO_PCI select PLATFORM_BUS From patchwork Sun Oct 29 06:03:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13439716 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 36F47C4332F for ; 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Sat, 28 Oct 2023 23:04:25 -0700 (PDT) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Peter Maydell , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha , Shannon Zhao , Song Gao , Stefan Berger , qemu-arm@nongnu.org (open list:Virt) Subject: [PATCH v3 09/14] tpm_tis_sysbus: move DSDT AML generation to device Date: Sat, 28 Oct 2023 23:03:22 -0700 Message-ID: <20231029060404.71196-10-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231029060404.71196-1-j@getutm.app> References: <20231029060404.71196-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.210.182; envelope-from=osy86dev@gmail.com; helo=mail-pf1-f182.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This reduces redundent code in different machine types with ACPI table generation. Additionally, this will allow us to support different TPM interfaces with the same AML logic. Finally, this matches up with the TPM TIS ISA implementation. Ideally, we would be able to call `qbus_build_aml` and avoid any TPM specific code in the ACPI table generation. However, currently we still have to call `build_tpm2` anyways and it does not look like most other ACPI devices support the `ACPI_DEV_AML_IF` interface. Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- hw/arm/virt-acpi-build.c | 38 ++------------------------------------ hw/loongarch/acpi-build.c | 38 ++------------------------------------ hw/tpm/tpm_tis_sysbus.c | 37 +++++++++++++++++++++++++++++++++++++ 3 files changed, 41 insertions(+), 72 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 9ce136cd88..3efbe6bd09 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -35,6 +35,7 @@ #include "target/arm/cpu.h" #include "hw/acpi/acpi-defs.h" #include "hw/acpi/acpi.h" +#include "hw/acpi/acpi_aml_interface.h" #include "hw/nvram/fw_cfg.h" #include "hw/acpi/bios-linker-loader.h" #include "hw/acpi/aml-build.h" @@ -208,41 +209,6 @@ static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, aml_append(scope, dev); } -#ifdef CONFIG_TPM -static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms) -{ - PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); - hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base; - SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find()); - MemoryRegion *sbdev_mr; - hwaddr tpm_base; - - if (!sbdev) { - return; - } - - tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); - assert(tpm_base != -1); - - tpm_base += pbus_base; - - sbdev_mr = sysbus_mmio_get_region(sbdev, 0); - - Aml *dev = aml_device("TPM0"); - aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); - aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device"))); - aml_append(dev, aml_name_decl("_UID", aml_int(0))); - - Aml *crs = aml_resource_template(); - aml_append(crs, - aml_memory32_fixed(tpm_base, - (uint32_t)memory_region_size(sbdev_mr), - AML_READ_WRITE)); - aml_append(dev, aml_name_decl("_CRS", crs)); - aml_append(scope, dev); -} -#endif - #define ID_MAPPING_ENTRY_SIZE 20 #define SMMU_V3_ENTRY_SIZE 68 #define ROOT_COMPLEX_ENTRY_SIZE 36 @@ -891,7 +857,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) acpi_dsdt_add_power_button(scope); #ifdef CONFIG_TPM - acpi_dsdt_add_tpm(scope, vms); + call_dev_aml_func(DEVICE(tpm_find()), scope); #endif aml_append(dsdt, scope); diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c index ae292fc543..1969bfc8f9 100644 --- a/hw/loongarch/acpi-build.c +++ b/hw/loongarch/acpi-build.c @@ -14,6 +14,7 @@ #include "target/loongarch/cpu.h" #include "hw/acpi/acpi-defs.h" #include "hw/acpi/acpi.h" +#include "hw/acpi/acpi_aml_interface.h" #include "hw/nvram/fw_cfg.h" #include "hw/acpi/bios-linker-loader.h" #include "migration/vmstate.h" @@ -328,41 +329,6 @@ static void build_flash_aml(Aml *scope, LoongArchMachineState *lams) aml_append(scope, dev); } -#ifdef CONFIG_TPM -static void acpi_dsdt_add_tpm(Aml *scope, LoongArchMachineState *vms) -{ - PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); - hwaddr pbus_base = VIRT_PLATFORM_BUS_BASEADDRESS; - SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find()); - MemoryRegion *sbdev_mr; - hwaddr tpm_base; - - if (!sbdev) { - return; - } - - tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); - assert(tpm_base != -1); - - tpm_base += pbus_base; - - sbdev_mr = sysbus_mmio_get_region(sbdev, 0); - - Aml *dev = aml_device("TPM0"); - aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); - aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device"))); - aml_append(dev, aml_name_decl("_UID", aml_int(0))); - - Aml *crs = aml_resource_template(); - aml_append(crs, - aml_memory32_fixed(tpm_base, - (uint32_t)memory_region_size(sbdev_mr), - AML_READ_WRITE)); - aml_append(dev, aml_name_decl("_CRS", crs)); - aml_append(scope, dev); -} -#endif - /* build DSDT */ static void build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine) @@ -379,7 +345,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine) build_la_ged_aml(dsdt, machine); build_flash_aml(dsdt, lams); #ifdef CONFIG_TPM - acpi_dsdt_add_tpm(dsdt, lams); + call_dev_aml_func(DEVICE(tpm_find()), dsdt); #endif /* System State Package */ scope = aml_scope("\\"); diff --git a/hw/tpm/tpm_tis_sysbus.c b/hw/tpm/tpm_tis_sysbus.c index 2fc550f119..462b0e1571 100644 --- a/hw/tpm/tpm_tis_sysbus.c +++ b/hw/tpm/tpm_tis_sysbus.c @@ -30,6 +30,7 @@ #include "hw/sysbus.h" #include "tpm_tis.h" #include "qom/object.h" +#include "hw/acpi/acpi_aml_interface.h" struct TPMStateSysBus { /*< private >*/ @@ -37,6 +38,8 @@ struct TPMStateSysBus { /*< public >*/ TPMState state; /* not a QOM object */ + uint64_t baseaddr; + uint64_t size; }; OBJECT_DECLARE_SIMPLE_TYPE(TPMStateSysBus, TPM_TIS_SYSBUS) @@ -93,6 +96,10 @@ static void tpm_tis_sysbus_reset(DeviceState *dev) static Property tpm_tis_sysbus_properties[] = { DEFINE_PROP_UINT32("irq", TPMStateSysBus, state.irq_num, TPM_TIS_IRQ), DEFINE_PROP_TPMBE("tpmdev", TPMStateSysBus, state.be_driver), + DEFINE_PROP_UINT64("x-baseaddr", TPMStateSysBus, baseaddr, + TPM_TIS_ADDR_BASE), + DEFINE_PROP_UINT64("x-size", TPMStateSysBus, size, + TPM_TIS_ADDR_SIZE), DEFINE_PROP_END_OF_LIST(), }; @@ -125,10 +132,38 @@ static void tpm_tis_sysbus_realizefn(DeviceState *dev, Error **errp) } } +static void build_tpm_tis_sysbus_aml(AcpiDevAmlIf *adev, Aml *scope) +{ + Aml *dev, *crs; + TPMStateSysBus *sbdev = TPM_TIS_SYSBUS(adev); + TPMIf *ti = TPM_IF(sbdev); + + dev = aml_device("TPM"); + if (tpm_tis_sysbus_get_tpm_version(ti) == TPM_VERSION_2_0) { + aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); + aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device"))); + } else { + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31"))); + } + aml_append(dev, aml_name_decl("_UID", aml_int(0))); + aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); + crs = aml_resource_template(); + aml_append(crs, aml_memory32_fixed(sbdev->baseaddr, sbdev->size, + AML_READ_WRITE)); + /* + * FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, + * fix default TPM_TIS_IRQ value there to use some unused IRQ + */ + /* aml_append(crs, aml_irq_no_flags(sbdev->state.irq_num)); */ + aml_append(dev, aml_name_decl("_CRS", crs)); + aml_append(scope, dev); +} + static void tpm_tis_sysbus_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); TPMIfClass *tc = TPM_IF_CLASS(klass); + AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); device_class_set_props(dc, tpm_tis_sysbus_properties); dc->vmsd = &vmstate_tpm_tis_sysbus; @@ -139,6 +174,7 @@ static void tpm_tis_sysbus_class_init(ObjectClass *klass, void *data) tc->request_completed = tpm_tis_sysbus_request_completed; tc->get_version = tpm_tis_sysbus_get_tpm_version; set_bit(DEVICE_CATEGORY_MISC, dc->categories); + adevc->build_dev_aml = build_tpm_tis_sysbus_aml; } static const TypeInfo tpm_tis_sysbus_info = { @@ -149,6 +185,7 @@ static const TypeInfo tpm_tis_sysbus_info = { .class_init = tpm_tis_sysbus_class_init, .interfaces = (InterfaceInfo[]) { { TYPE_TPM_IF }, + { TYPE_ACPI_DEV_AML_IF }, { } } }; From patchwork Sun Oct 29 06:03:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13439713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2CCFCC4332F for ; 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Sat, 28 Oct 2023 23:04:26 -0700 (PDT) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha Subject: [PATCH v3 10/14] tests: acpi: prepare for TPM CRB tests Date: Sat, 28 Oct 2023 23:03:23 -0700 Message-ID: <20231029060404.71196-11-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231029060404.71196-1-j@getutm.app> References: <20231029060404.71196-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.210.181; envelope-from=osy86dev@gmail.com; helo=mail-pf1-f181.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- tests/qtest/bios-tables-test-allowed-diff.h | 4 ++++ tests/data/acpi/q35/DSDT.crb.tpm2 | 0 tests/data/acpi/q35/TPM2.crb.tpm2 | 0 tests/data/acpi/virt/DSDT.crb-device.tpm2 | 0 tests/data/acpi/virt/TPM2.crb-device.tpm2 | 0 5 files changed, 4 insertions(+) create mode 100644 tests/data/acpi/q35/DSDT.crb.tpm2 create mode 100644 tests/data/acpi/q35/TPM2.crb.tpm2 create mode 100644 tests/data/acpi/virt/DSDT.crb-device.tpm2 create mode 100644 tests/data/acpi/virt/TPM2.crb-device.tpm2 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..c2d1924c2f 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,5 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/q35/DSDT.crb.tpm2", +"tests/data/acpi/q35/TPM2.crb.tpm2", +"tests/data/acpi/virt/DSDT.crb.tpm2", +"tests/data/acpi/virt/TPM2.crb.tpm2", diff --git a/tests/data/acpi/q35/DSDT.crb.tpm2 b/tests/data/acpi/q35/DSDT.crb.tpm2 new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/q35/TPM2.crb.tpm2 b/tests/data/acpi/q35/TPM2.crb.tpm2 new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/virt/DSDT.crb-device.tpm2 b/tests/data/acpi/virt/DSDT.crb-device.tpm2 new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/virt/TPM2.crb-device.tpm2 b/tests/data/acpi/virt/TPM2.crb-device.tpm2 new file mode 100644 index 0000000000..e69de29bb2 From patchwork Sun Oct 29 06:03:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13439718 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4EED0C4167B for ; Sun, 29 Oct 2023 06:07:44 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qwyud-0002Iv-NL; Sun, 29 Oct 2023 02:04:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwyua-0002Hz-1C; Sun, 29 Oct 2023 02:04:36 -0400 Received: from mail-pl1-f169.google.com ([209.85.214.169]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwyuX-0001qP-Oo; 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Sat, 28 Oct 2023 23:04:30 -0700 (PDT) Received: from localhost.localdomain ([2601:642:4c02:6ead:344e:2b1:f5a5:58c6]) by smtp.gmail.com with ESMTPSA id u12-20020a17090341cc00b001b8943b37a5sm4019518ple.24.2023.10.28.23.04.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 28 Oct 2023 23:04:30 -0700 (PDT) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Stefan Berger , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha , Paolo Bonzini , Peter Maydell , Song Gao , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-arm@nongnu.org (open list:ARM TCG CPUs), qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Subject: [PATCH v3 11/14] tpm_crb_sysbus: introduce TPM CRB SysBus device Date: Sat, 28 Oct 2023 23:03:24 -0700 Message-ID: <20231029060404.71196-12-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231029060404.71196-1-j@getutm.app> References: <20231029060404.71196-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.169; envelope-from=osy86dev@gmail.com; helo=mail-pl1-f169.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This SysBus variant of the CRB interface supports dynamically locating the MMIO interface so that Virt machines can use it. This interface is currently the only one supported by QEMU that works on Windows 11 ARM64 as 'tpm-tis-device' does not work with current Windows drivers. We largely follow that device as a template. To try out this device with Windows 11 before OVMF is updated, you will need to modify `sysbud-fdt.c` and change the added line from: ```c TYPE_BINDING(TYPE_TPM_CRB_SYSBUS, no_fdt_node), ``` to ```c TYPE_BINDING(TYPE_TPM_CRB_SYSBUS, add_tpm_tis_fdt_node), ``` This change was not included because it can confuse Linux (although from testing, it seems like Linux is able to properly ignore the device from the TPM TIS driver and recognize it from the ACPI device in the TPM CRB driver). A proper fix would require OVMF to recognize the ACPI device and not depend on the FDT node for recognizing TPM. The command line to try out this device with SWTPM is: ``` $ qemu-system-aarch64 \ -chardev socket,id=chrtpm0,path=tpm.sock \ -tpmdev emulator,id=tpm0,chardev=chrtpm0 \ -device tpm-crb-device,tpmdev=tpm0 ``` along with SWTPM: ``` $ swtpm \ --ctrl type=unixio,path=tpm.sock,terminate \ --tpmstate backend-uri=file://tpm.data \ --tpm2 ``` Signed-off-by: Joelle van Dyne --- docs/specs/tpm.rst | 1 + include/sysemu/tpm.h | 3 + hw/acpi/aml-build.c | 7 +- hw/arm/virt.c | 1 + hw/core/sysbus-fdt.c | 1 + hw/loongarch/virt.c | 1 + hw/riscv/virt.c | 1 + hw/tpm/tpm_crb_sysbus.c | 161 ++++++++++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + hw/loongarch/Kconfig | 1 + hw/riscv/Kconfig | 1 + hw/tpm/Kconfig | 5 ++ hw/tpm/meson.build | 3 + 13 files changed, 186 insertions(+), 1 deletion(-) create mode 100644 hw/tpm/tpm_crb_sysbus.c diff --git a/docs/specs/tpm.rst b/docs/specs/tpm.rst index 2bc29c9804..95aeb49220 100644 --- a/docs/specs/tpm.rst +++ b/docs/specs/tpm.rst @@ -46,6 +46,7 @@ operating system. QEMU files related to TPM CRB interface: - ``hw/tpm/tpm_crb.c`` - ``hw/tpm/tpm_crb_common.c`` + - ``hw/tpm/tpm_crb_sysbus.c`` SPAPR interface --------------- diff --git a/include/sysemu/tpm.h b/include/sysemu/tpm.h index ffd300e607..bab30fa546 100644 --- a/include/sysemu/tpm.h +++ b/include/sysemu/tpm.h @@ -49,6 +49,7 @@ struct TPMIfClass { #define TYPE_TPM_TIS_ISA "tpm-tis" #define TYPE_TPM_TIS_SYSBUS "tpm-tis-device" #define TYPE_TPM_CRB "tpm-crb" +#define TYPE_TPM_CRB_SYSBUS "tpm-crb-device" #define TYPE_TPM_SPAPR "tpm-spapr" #define TYPE_TPM_TIS_I2C "tpm-tis-i2c" @@ -58,6 +59,8 @@ struct TPMIfClass { object_dynamic_cast(OBJECT(chr), TYPE_TPM_TIS_SYSBUS) #define TPM_IS_CRB(chr) \ object_dynamic_cast(OBJECT(chr), TYPE_TPM_CRB) +#define TPM_IS_CRB_SYSBUS(chr) \ + object_dynamic_cast(OBJECT(chr), TYPE_TPM_CRB_SYSBUS) #define TPM_IS_SPAPR(chr) \ object_dynamic_cast(OBJECT(chr), TYPE_TPM_SPAPR) #define TPM_IS_TIS_I2C(chr) \ diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index af66bde0f5..acc654382e 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -31,6 +31,7 @@ #include "hw/pci/pci_bus.h" #include "hw/pci/pci_bridge.h" #include "qemu/cutils.h" +#include "qom/object.h" static GArray *build_alloc_array(void) { @@ -2218,7 +2219,7 @@ void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, { uint8_t start_method_params[12] = {}; unsigned log_addr_offset; - uint64_t control_area_start_address; + uint64_t baseaddr, control_area_start_address; TPMIf *tpmif = tpm_find(); uint32_t start_method; AcpiTable table = { .sig = "TPM2", .rev = 4, @@ -2236,6 +2237,10 @@ void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, } else if (TPM_IS_CRB(tpmif)) { control_area_start_address = TPM_CRB_ADDR_CTRL; start_method = TPM2_START_METHOD_CRB; + } else if (TPM_IS_CRB_SYSBUS(tpmif)) { + baseaddr = object_property_get_uint(OBJECT(tpmif), "x-baseaddr", NULL); + control_area_start_address = baseaddr + A_CRB_CTRL_REQ; + start_method = TPM2_START_METHOD_CRB; } else { g_assert_not_reached(); } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index f1a161b0ea..22e147f71a 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2950,6 +2950,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); #ifdef CONFIG_TPM machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_CRB_SYSBUS); #endif mc->block_default_type = IF_VIRTIO; mc->no_cdrom = 1; diff --git a/hw/core/sysbus-fdt.c b/hw/core/sysbus-fdt.c index eebcd28f9a..9c783f88eb 100644 --- a/hw/core/sysbus-fdt.c +++ b/hw/core/sysbus-fdt.c @@ -493,6 +493,7 @@ static const BindingEntry bindings[] = { #endif #ifdef CONFIG_TPM TYPE_BINDING(TYPE_TPM_TIS_SYSBUS, add_tpm_tis_fdt_node), + TYPE_BINDING(TYPE_TPM_CRB_SYSBUS, no_fdt_node), #endif TYPE_BINDING(TYPE_RAMFB_DEVICE, no_fdt_node), TYPE_BINDING("", NULL), /* last element */ diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index feed0f8bbf..9d5ad2bc8e 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -1114,6 +1114,7 @@ static void loongarch_class_init(ObjectClass *oc, void *data) machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); #ifdef CONFIG_TPM machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_CRB_SYSBUS); #endif } diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 9de578c756..c0d2cd1d60 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1702,6 +1702,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); #ifdef CONFIG_TPM machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_CRB_SYSBUS); #endif diff --git a/hw/tpm/tpm_crb_sysbus.c b/hw/tpm/tpm_crb_sysbus.c new file mode 100644 index 0000000000..c10a8b5639 --- /dev/null +++ b/hw/tpm/tpm_crb_sysbus.c @@ -0,0 +1,161 @@ +/* + * tpm_crb_sysbus.c - QEMU's TPM CRB interface emulator + * + * Copyright (c) 2018 Red Hat, Inc. + * + * Authors: + * Marc-André Lureau + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + * tpm_crb is a device for TPM 2.0 Command Response Buffer (CRB) Interface + * as defined in TCG PC Client Platform TPM Profile (PTP) Specification + * Family “2.0” Level 00 Revision 01.03 v22 + */ + +#include "qemu/osdep.h" +#include "hw/acpi/acpi_aml_interface.h" +#include "hw/acpi/tpm.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" +#include "tpm_prop.h" +#include "hw/sysbus.h" +#include "qapi/visitor.h" +#include "qom/object.h" +#include "sysemu/tpm_util.h" +#include "trace.h" +#include "tpm_crb.h" + +struct TPMCRBStateSysBus { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + TPMCRBState state; + uint64_t baseaddr; + uint64_t size; +}; + +OBJECT_DECLARE_SIMPLE_TYPE(TPMCRBStateSysBus, TPM_CRB_SYSBUS) + +static void tpm_crb_sysbus_request_completed(TPMIf *ti, int ret) +{ + TPMCRBStateSysBus *s = TPM_CRB_SYSBUS(ti); + + return tpm_crb_request_completed(&s->state, ret); +} + +static enum TPMVersion tpm_crb_sysbus_get_tpm_version(TPMIf *ti) +{ + TPMCRBStateSysBus *s = TPM_CRB_SYSBUS(ti); + + return tpm_crb_get_version(&s->state); +} + +static int tpm_crb_sysbus_pre_save(void *opaque) +{ + TPMCRBStateSysBus *s = opaque; + + return tpm_crb_pre_save(&s->state); +} + +static const VMStateDescription vmstate_tpm_crb_sysbus = { + .name = "tpm-crb-sysbus", + .pre_save = tpm_crb_sysbus_pre_save, + .fields = (VMStateField[]) { + VMSTATE_END_OF_LIST(), + } +}; + +static Property tpm_crb_sysbus_properties[] = { + DEFINE_PROP_TPMBE("tpmdev", TPMCRBStateSysBus, state.tpmbe), + DEFINE_PROP_UINT64("x-baseaddr", TPMCRBStateSysBus, + baseaddr, TPM_CRB_ADDR_BASE), + DEFINE_PROP_UINT64("x-size", TPMCRBStateSysBus, + size, TPM_CRB_ADDR_SIZE), + DEFINE_PROP_END_OF_LIST(), +}; + +static void tpm_crb_sysbus_initfn(Object *obj) +{ + TPMCRBStateSysBus *s = TPM_CRB_SYSBUS(obj); + + tpm_crb_init_memory(obj, &s->state, NULL); + + vmstate_register_ram(&s->state.mmio, DEVICE(obj)); + + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->state.mmio); +} + +static void tpm_crb_sysbus_reset(DeviceState *dev) +{ + TPMCRBStateSysBus *s = TPM_CRB_SYSBUS(dev); + + return tpm_crb_reset(&s->state, s->baseaddr); +} + +static void tpm_crb_sysbus_realizefn(DeviceState *dev, Error **errp) +{ + TPMCRBStateSysBus *s = TPM_CRB_SYSBUS(dev); + + if (!tpm_find()) { + error_setg(errp, "at most one TPM device is permitted"); + return; + } + + if (!s->state.tpmbe) { + error_setg(errp, "'tpmdev' property is required"); + return; + } + + if (tpm_crb_sysbus_get_tpm_version(TPM_IF(s)) != TPM_VERSION_2_0) { + error_setg(errp, "TPM CRB only supports TPM 2.0 backends"); + return; + } +} + +static void build_tpm_crb_sysbus_aml(AcpiDevAmlIf *adev, Aml *scope) +{ + TPMCRBStateSysBus *s = TPM_CRB_SYSBUS(adev); + + tpm_crb_build_aml(TPM_IF(adev), scope, s->baseaddr, s->size, false); +} + +static void tpm_crb_sysbus_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + TPMIfClass *tc = TPM_IF_CLASS(klass); + AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); + + device_class_set_props(dc, tpm_crb_sysbus_properties); + dc->vmsd = &vmstate_tpm_crb_sysbus; + tc->model = TPM_MODEL_TPM_CRB; + dc->realize = tpm_crb_sysbus_realizefn; + dc->user_creatable = true; + dc->reset = tpm_crb_sysbus_reset; + tc->request_completed = tpm_crb_sysbus_request_completed; + tc->get_version = tpm_crb_sysbus_get_tpm_version; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + adevc->build_dev_aml = build_tpm_crb_sysbus_aml; +} + +static const TypeInfo tpm_crb_sysbus_info = { + .name = TYPE_TPM_CRB_SYSBUS, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(TPMCRBStateSysBus), + .instance_init = tpm_crb_sysbus_initfn, + .class_init = tpm_crb_sysbus_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TPM_IF }, + { TYPE_ACPI_DEV_AML_IF }, + { } + } +}; + +static void tpm_crb_sysbus_register(void) +{ + type_register_static(&tpm_crb_sysbus_info); +} + +type_init(tpm_crb_sysbus_register) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 7e68348440..efe1beaa7b 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -5,6 +5,7 @@ config ARM_VIRT imply VFIO_AMD_XGBE imply VFIO_PLATFORM imply VFIO_XGMAC + imply TPM_CRB_SYSBUS imply TPM_TIS_SYSBUS imply TPM_TIS_I2C imply NVDIMM diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index 25da190ffc..70544f3ce5 100644 --- a/hw/loongarch/Kconfig +++ b/hw/loongarch/Kconfig @@ -6,6 +6,7 @@ config LOONGARCH_VIRT imply PCI_DEVICES imply NVDIMM imply TPM_TIS_SYSBUS + imply TPM_CRB_SYSBUS select SERIAL select VIRTIO_PCI select PLATFORM_BUS diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index b6a5eb4452..d824cb58f9 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -29,6 +29,7 @@ config RISCV_VIRT imply PCI_DEVICES imply VIRTIO_VGA imply TEST_DEVICES + imply TPM_CRB_SYSBUS imply TPM_TIS_SYSBUS select RISCV_NUMA select GOLDFISH_RTC diff --git a/hw/tpm/Kconfig b/hw/tpm/Kconfig index a46663288c..28139c456a 100644 --- a/hw/tpm/Kconfig +++ b/hw/tpm/Kconfig @@ -25,6 +25,11 @@ config TPM_CRB depends on TPM && PC select TPM_BACKEND +config TPM_CRB_SYSBUS + bool + depends on TPM + select TPM_BACKEND + config TPM_SPAPR bool default y diff --git a/hw/tpm/meson.build b/hw/tpm/meson.build index 3060ac05e8..f2536c99e3 100644 --- a/hw/tpm/meson.build +++ b/hw/tpm/meson.build @@ -5,6 +5,9 @@ system_ss.add(when: 'CONFIG_TPM_TIS_SYSBUS', if_true: files('tpm-sysbus.c')) system_ss.add(when: 'CONFIG_TPM_TIS_I2C', if_true: files('tpm_tis_i2c.c')) system_ss.add(when: 'CONFIG_TPM_CRB', if_true: files('tpm_crb.c')) system_ss.add(when: 'CONFIG_TPM_CRB', if_true: files('tpm_crb_common.c')) +system_ss.add(when: 'CONFIG_TPM_CRB_SYSBUS', if_true: files('tpm_crb_sysbus.c')) +system_ss.add(when: 'CONFIG_TPM_CRB_SYSBUS', if_true: files('tpm_crb_common.c')) +system_ss.add(when: 'CONFIG_TPM_CRB_SYSBUS', if_true: files('tpm-sysbus.c')) system_ss.add(when: 'CONFIG_TPM_TIS', if_true: files('tpm_ppi.c')) system_ss.add(when: 'CONFIG_TPM_CRB', if_true: files('tpm_ppi.c')) From patchwork Sun Oct 29 06:03:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13439712 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4602EC4167B for ; Sun, 29 Oct 2023 06:06:11 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qwyua-0002IF-Rp; Sun, 29 Oct 2023 02:04:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwyuZ-0002Hh-3L for qemu-devel@nongnu.org; Sun, 29 Oct 2023 02:04:35 -0400 Received: from mail-pl1-f178.google.com ([209.85.214.178]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwyuX-0001qw-H4 for qemu-devel@nongnu.org; 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Tsirkin" , Igor Mammedov , Ani Sinha Subject: [PATCH v3 12/14] tests: acpi: implement TPM CRB tests for ARM virt Date: Sat, 28 Oct 2023 23:03:25 -0700 Message-ID: <20231029060404.71196-13-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231029060404.71196-1-j@getutm.app> References: <20231029060404.71196-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.178; envelope-from=osy86dev@gmail.com; helo=mail-pl1-f178.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- tests/qtest/bios-tables-test.c | 43 ++++++++++++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 2 deletions(-) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 9f4bc15aab..c63bad0205 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1345,6 +1345,28 @@ static void test_acpi_piix4_tcg_numamem(void) uint64_t tpm_tis_base_addr; +static test_data tcg_tpm_test_data(const char *machine) +{ + if (g_strcmp0(machine, "virt") == 0) { + test_data data = { + .machine = "virt", + .tcg_only = true, + .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 = "pc-bios/edk2-arm-vars.fd", + .cd = + "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2", + .ram_start = 0x40000000ULL, + .scan_len = 128ULL * 1024 * 1024, + }; + return data; + } else { + test_data data = { + .machine = machine, + }; + return data; + } +} + static void test_acpi_tcg_tpm(const char *machine, const char *tpm_if, uint64_t base, enum TPMVersion tpm_version) { @@ -1352,7 +1374,7 @@ static void test_acpi_tcg_tpm(const char *machine, const char *tpm_if, machine, tpm_if); char *tmp_path = g_dir_make_tmp(tmp_dir_name, NULL); TPMTestState test; - test_data data = {}; + test_data data = tcg_tpm_test_data(machine); GThread *thread; const char *suffix = tpm_version == TPM_VERSION_2_0 ? "tpm2" : "tpm12"; char *args, *variant = g_strdup_printf(".%s.%s", tpm_if, suffix); @@ -1372,13 +1394,14 @@ static void test_acpi_tcg_tpm(const char *machine, const char *tpm_if, thread = g_thread_new(NULL, tpm_emu_ctrl_thread, &test); tpm_emu_test_wait_cond(&test); - data.machine = machine; data.variant = variant; args = g_strdup_printf( + " %s" " -chardev socket,id=chr,path=%s" " -tpmdev emulator,id=dev,chardev=chr" " -device tpm-%s,tpmdev=dev", + g_strcmp0(machine, "virt") == 0 ? "-cpu cortex-a57" : "", test.addr->u.q_unix.path, tpm_if); test_acpi_one(args, &data); @@ -1404,6 +1427,16 @@ static void test_acpi_q35_tcg_tpm12_tis(void) test_acpi_tcg_tpm("q35", "tis", 0xFED40000, TPM_VERSION_1_2); } +static void test_acpi_q35_tcg_tpm2_crb(void) +{ + test_acpi_tcg_tpm("q35", "crb", 0xFED40000, TPM_VERSION_2_0); +} + +static void test_acpi_virt_tcg_tpm2_crb(void) +{ + test_acpi_tcg_tpm("virt", "crb-device", 0xFED40000, TPM_VERSION_2_0); +} + static void test_acpi_tcg_dimm_pxm(const char *machine) { test_data data = {}; @@ -2110,6 +2143,9 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/q35/tpm12-tis", test_acpi_q35_tcg_tpm12_tis); } + if (tpm_model_is_available("-machine q35", "tpm-crb")) { + qtest_add_func("acpi/q35/tpm2-crb", test_acpi_q35_tcg_tpm2_crb); + } qtest_add_func("acpi/q35/bridge", test_acpi_q35_tcg_bridge); qtest_add_func("acpi/q35/no-acpi-hotplug", test_acpi_q35_tcg_no_acpi_hotplug); @@ -2191,6 +2227,9 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/virt/viot", test_acpi_virt_viot); } } + if (tpm_model_is_available("-machine virt", "tpm-crb")) { + qtest_add_func("acpi/virt/tpm2-crb", test_acpi_virt_tcg_tpm2_crb); + } } ret = g_test_run(); boot_sector_cleanup(disk); From patchwork Sun Oct 29 06:03:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13439711 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 54946C4332F for ; Sun, 29 Oct 2023 06:06:07 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qwyug-0002KB-FS; Sun, 29 Oct 2023 02:04:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwyud-0002Il-5m for qemu-devel@nongnu.org; Sun, 29 Oct 2023 02:04:39 -0400 Received: from mail-pf1-f175.google.com ([209.85.210.175]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwyub-0001t3-87 for qemu-devel@nongnu.org; Sun, 29 Oct 2023 02:04:38 -0400 Received: by mail-pf1-f175.google.com with SMTP id d2e1a72fcca58-6be840283ceso3143284b3a.3 for ; Sat, 28 Oct 2023 23:04:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698559474; x=1699164274; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KbcInts6uJjUbWdfAwLSHERZRGkdHynJLINGdCPwRNY=; b=R2sXiPotWGB4UnazcYLK+ImNUt0ea/HiZl2SGTDR6gsxyLzMVLKUiqhB4cqouO/XTJ yVmN1W0jOowiJE+bF56xdqdl9OeqfrbLi20DP60R6suBW3DxlbMaSK9LFvLgWTSeMu6i 3dVjQubkl/8yIPAaM2o0vkG5Ow2lHWeReXgd17tteNWU4wZ9aSUS8TIKgFWHlG/FCp+D znlW9QrhlGFalYed55fB7pYptBJ7ZvY+lIYVa95bY2RdU6Gj3VHcXaAUab82XIjsSqfy SNIgTrtvn6aFb5FQklAKHEat40dkigi6LBUyD+DvKECLUSPKtQXzmmWoOiSJ0FqtHLJ8 80Dg== X-Gm-Message-State: AOJu0YxZbJVpWoGrFMarrYE5y24N0E9R/Bigu0bT+JW27t3NHe8LtEvH GEeOpgVhPnWuDl+rfBqc3O8aolEf2N8mXQ== X-Google-Smtp-Source: AGHT+IEjfhQJtTq66yb//II3l2q7r1y/k4eflgTXbgibRYkx9TFLrYjS0FXo+PElYdXcUdkgEtGxqw== X-Received: by 2002:a05:6a20:7486:b0:140:c838:2b2e with SMTP id p6-20020a056a20748600b00140c8382b2emr6019916pzd.22.1698559473745; Sat, 28 Oct 2023 23:04:33 -0700 (PDT) Received: from localhost.localdomain ([2601:642:4c02:6ead:344e:2b1:f5a5:58c6]) by smtp.gmail.com with ESMTPSA id u12-20020a17090341cc00b001b8943b37a5sm4019518ple.24.2023.10.28.23.04.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 28 Oct 2023 23:04:33 -0700 (PDT) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha Subject: [PATCH v3 13/14] tests: acpi: updated expected blobs for TPM CRB Date: Sat, 28 Oct 2023 23:03:26 -0700 Message-ID: <20231029060404.71196-14-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231029060404.71196-1-j@getutm.app> References: <20231029060404.71196-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.210.175; envelope-from=osy86dev@gmail.com; helo=mail-pf1-f175.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Joelle van Dyne --- tests/qtest/bios-tables-test-allowed-diff.h | 4 ---- tests/data/acpi/q35/DSDT.crb.tpm2 | Bin 0 -> 8981 bytes tests/data/acpi/q35/TPM2.crb.tpm2 | Bin 0 -> 76 bytes tests/data/acpi/virt/DSDT.crb-device.tpm2 | Bin 0 -> 5276 bytes tests/data/acpi/virt/TPM2.crb-device.tpm2 | Bin 0 -> 76 bytes 5 files changed, 4 deletions(-) diff --git a/tests/data/acpi/q35/DSDT.crb.tpm2 b/tests/data/acpi/q35/DSDT.crb.tpm2 index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..0f04f48f0bb378f035773211b0e70ad50094f95f 100644 GIT binary patch literal 8981 zcmb7KO>7&-8J*>iv|28u6-D_!HeoycOW;sa;sgznmfYo^B}yxjw$soBmy+Gec7QCB zxQJsIkQE?t3>1jXI_RYU6EH<@?V;$k26}0M9(*v607VZ4+Dm|5S`;yQu=>6kjy*$C zK*hsyzuEWZn>VvNZ#hG+?loqQF=qTdzv7nbnfzFF1@~2D2&o_ckg5aGG1EU?Xwa=WpYwhs;o530*(3Q2&vgpLgrCarU ztGTr@<-3)v*(z5&J9pnQ&6X?9qGl`S)tK2jUGZ3YX}q;kcVo9MGuJyi*IkZxHl}AR zr&;~W!q-O*egBiQ@8s^i^2LvCUAAHX%;Vd{_d-aA;96iE4!X{r&PC%o(fPHx?#!JI zzbwiex)KId@~JI~sH(Z%<@92_;MJ?i?#a$27EVVE7IY8X5e>Ni;-CIef8o9A?Y&=B z_y57I_JZ#C-HTSF7lhW0n*n1eIMlghjfbgtge6&kzIcPNcGwmdn_Dk=wVccKC;eqV z>t^Sm*{#*5k64F3+{>6v9Z#R%Y;SM>UYs)LDsz_7C#Val`xEMous_;X3?oK?o6i6um}C zcn9KOur&j!_5MHw;hGo*)33NimbP2?Ho^^x zoUJnk^{?Z8#qUtR*6>q{Z*Qg&u>^80EiV?BI5%)!WGS1qo=_a8g|3JV0egOw`Y@5zYj*9}!bRBaAZvWphTalw?0N2ux?({zq;ri6~^IuWWm$2Fbfn$B@u zCqh-Hsp&K|ou;l6p{jF2(>bB(oX~Y5RCQXKPD|5i={garIun}Cgr+m0>qMyPv^AZ! zrqkASB2;xIHJwRKXHwURP}Mo9>73MbPU<=lsye4Mol~05DP1Q*Ri~rrbTplgt`niE zb6V3mt?8WBbs|)CrZk-?O=n8iiBQ!!qv@Q{bk68H5vn@Vn$EPQGp*}HsOp^6bk1rz zXLX$jRh@e@oqIH$dvu)$Rh_UgF=z2vX|JYpudWlJs&k*FbDySjpRN<3s&hYQ=K3?? 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zZL8u&aPzw=k^-_pYRk9&{nzux%svzG^sjR94>Ch%H& zqyx>-2Q`g)rgu(B?@w~Cjvrdz;7TPJT{)S0bsUW|r*rz^BRyE3KRx(4YtHMNR89|y z9}Jp)$3D4WX7k7D?|=I%Uw3|({--nho7Xu>9)F=u^D)cPJ1lf{>|V=f)u}jwX_hz5i`WhhEEXZI_FSgVvpX@{tbio#c+6-E(xm_q@B;YdDAdN3;5Xex5vY zFWBwa{cb0mNXOskyA@Zj0ixf{;6k~&?3SAko;c?|5v<@85#X!<1dKp25F12;fCB>q4~S+55hwtp;-WK12mq){ B2mt^9 literal 0 HcmV?d00001 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index c2d1924c2f..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,5 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/q35/DSDT.crb.tpm2", -"tests/data/acpi/q35/TPM2.crb.tpm2", -"tests/data/acpi/virt/DSDT.crb.tpm2", -"tests/data/acpi/virt/TPM2.crb.tpm2", From patchwork Sun Oct 29 06:03:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13439710 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F0D23C41535 for ; Sun, 29 Oct 2023 06:05:52 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qwyum-0002LF-3L; Sun, 29 Oct 2023 02:04:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwyuf-0002Jb-9l for qemu-devel@nongnu.org; Sun, 29 Oct 2023 02:04:41 -0400 Received: from mail-pf1-f177.google.com ([209.85.210.177]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwyuc-0001tW-G6 for qemu-devel@nongnu.org; Sun, 29 Oct 2023 02:04:41 -0400 Received: by mail-pf1-f177.google.com with SMTP id d2e1a72fcca58-6be0277c05bso2977328b3a.0 for ; Sat, 28 Oct 2023 23:04:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698559477; x=1699164277; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cFBKtoEcKUMOYHSMLFAIsLL4AHCBFnIuRPcTZq6xV4M=; b=mN9nF31hTI8vbadM8yWsfo9jT+okdrGAgRl/vaRHRfe5Hdtfvr2kmpcnhtwuJlCApn Ewy+q1e0dXmK9JzQIwtL40EZljGTvvrZbmPiFcY0qGU9NZez5qPwPU9XKjnYeytshCiT qtUfEQ7YirQbtmsvgShF89HKtNrNmucnnZSmprJBNR1reoFrTJwO56kKIOcZ5RiWorAG hE1/2ITo4F4nowtUlXxepZDgd0aoqJYEn2ymtGigrbr59mVCgSt1SX8zGl68kmExQ2xL sqFv6xuzDPi3L8g8Dvxa3xr2LrnFtTCwRa2EL7GW0L9oeXqLmUv8MIFvTawNBOqicSlN sLDQ== X-Gm-Message-State: AOJu0YzHCkwtJ0sOK7Ew1gfmjVVkN2SOSdVwKixk3zrMnMn3GP97UKLC LqqNNQq/ZdckWFUW3RZpNne4vg9WtBv/PQ== X-Google-Smtp-Source: AGHT+IFxPiC7wRKl+NOUqWJlKoPspTRIrlmDRO9gzJljw569BfOZRZpkQAv0t5/ESeZwOuy8h1/ThA== X-Received: by 2002:a05:6a20:160b:b0:159:c24f:5fa4 with SMTP id l11-20020a056a20160b00b00159c24f5fa4mr7028433pzj.1.1698559476846; Sat, 28 Oct 2023 23:04:36 -0700 (PDT) Received: from localhost.localdomain ([2601:642:4c02:6ead:344e:2b1:f5a5:58c6]) by smtp.gmail.com with ESMTPSA id u12-20020a17090341cc00b001b8943b37a5sm4019518ple.24.2023.10.28.23.04.34 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 28 Oct 2023 23:04:34 -0700 (PDT) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha , Thomas Huth , Laurent Vivier , Paolo Bonzini , Stefan Berger Subject: [PATCH v3 14/14] tests: add TPM-CRB sysbus tests for aarch64 Date: Sat, 28 Oct 2023 23:03:27 -0700 Message-ID: <20231029060404.71196-15-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231029060404.71196-1-j@getutm.app> References: <20231029060404.71196-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.210.177; envelope-from=osy86dev@gmail.com; helo=mail-pf1-f177.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org - Factor out common test code from tpm-crb-test.c -> tpm-tests.c - Store device addr in `tpm_device_base_addr` (unify with TIS tests) - Add new tests for aarch64 Signed-off-by: Joelle van Dyne --- tests/qtest/tpm-tests.h | 2 + tests/qtest/tpm-util.h | 4 +- tests/qtest/bios-tables-test.c | 4 +- tests/qtest/tpm-crb-device-swtpm-test.c | 72 ++++++++++++++ tests/qtest/tpm-crb-device-test.c | 71 ++++++++++++++ tests/qtest/tpm-crb-swtpm-test.c | 2 + tests/qtest/tpm-crb-test.c | 121 +----------------------- tests/qtest/tpm-tests.c | 121 ++++++++++++++++++++++++ tests/qtest/tpm-tis-device-swtpm-test.c | 2 +- tests/qtest/tpm-tis-device-test.c | 2 +- tests/qtest/tpm-tis-i2c-test.c | 3 + tests/qtest/tpm-tis-swtpm-test.c | 2 +- tests/qtest/tpm-tis-test.c | 2 +- tests/qtest/tpm-util.c | 16 ++-- tests/qtest/meson.build | 4 + 15 files changed, 295 insertions(+), 133 deletions(-) create mode 100644 tests/qtest/tpm-crb-device-swtpm-test.c create mode 100644 tests/qtest/tpm-crb-device-test.c diff --git a/tests/qtest/tpm-tests.h b/tests/qtest/tpm-tests.h index 07ba60d26e..c1bfb2f914 100644 --- a/tests/qtest/tpm-tests.h +++ b/tests/qtest/tpm-tests.h @@ -24,4 +24,6 @@ void tpm_test_swtpm_migration_test(const char *src_tpm_path, const char *ifmodel, const char *machine_options); +void tpm_test_crb(const void *data); + #endif /* TESTS_TPM_TESTS_H */ diff --git a/tests/qtest/tpm-util.h b/tests/qtest/tpm-util.h index 0cb28dd6e5..c99380684e 100644 --- a/tests/qtest/tpm-util.h +++ b/tests/qtest/tpm-util.h @@ -15,10 +15,10 @@ #include "io/channel-socket.h" -extern uint64_t tpm_tis_base_addr; +extern uint64_t tpm_device_base_addr; #define TIS_REG(LOCTY, REG) \ - (tpm_tis_base_addr + ((LOCTY) << 12) + REG) + (tpm_device_base_addr + ((LOCTY) << 12) + REG) typedef void (tx_func)(QTestState *s, const unsigned char *req, size_t req_size, diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index c63bad0205..dea2a18158 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1343,7 +1343,7 @@ static void test_acpi_piix4_tcg_numamem(void) free_test_data(&data); } -uint64_t tpm_tis_base_addr; +uint64_t tpm_device_base_addr; static test_data tcg_tpm_test_data(const char *machine) { @@ -1379,7 +1379,7 @@ static void test_acpi_tcg_tpm(const char *machine, const char *tpm_if, const char *suffix = tpm_version == TPM_VERSION_2_0 ? "tpm2" : "tpm12"; char *args, *variant = g_strdup_printf(".%s.%s", tpm_if, suffix); - tpm_tis_base_addr = base; + tpm_device_base_addr = base; module_call_init(MODULE_INIT_QOM); diff --git a/tests/qtest/tpm-crb-device-swtpm-test.c b/tests/qtest/tpm-crb-device-swtpm-test.c new file mode 100644 index 0000000000..332add5ca6 --- /dev/null +++ b/tests/qtest/tpm-crb-device-swtpm-test.c @@ -0,0 +1,72 @@ +/* + * QTest testcase for TPM CRB talking to external swtpm and swtpm migration + * + * Copyright (c) 2018 IBM Corporation + * with parts borrowed from migration-test.c that is: + * Copyright (c) 2016-2018 Red Hat, Inc. and/or its affiliates + * + * Authors: + * Stefan Berger + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" + +#include "libqtest.h" +#include "qemu/module.h" +#include "tpm-tests.h" +#include "hw/acpi/tpm.h" + +uint64_t tpm_device_base_addr = 0xc000000; +#define MACHINE_OPTIONS "-machine virt,gic-version=max -accel tcg" + +typedef struct TestState { + char *src_tpm_path; + char *dst_tpm_path; + char *uri; +} TestState; + +static void tpm_crb_swtpm_test(const void *data) +{ + const TestState *ts = data; + + tpm_test_swtpm_test(ts->src_tpm_path, tpm_util_crb_transfer, + "tpm-crb-device", MACHINE_OPTIONS); +} + +static void tpm_crb_swtpm_migration_test(const void *data) +{ + const TestState *ts = data; + + tpm_test_swtpm_migration_test(ts->src_tpm_path, ts->dst_tpm_path, ts->uri, + tpm_util_crb_transfer, "tpm-crb-device", + MACHINE_OPTIONS); +} + +int main(int argc, char **argv) +{ + int ret; + TestState ts = { 0 }; + + ts.src_tpm_path = g_dir_make_tmp("qemu-tpm-crb-swtpm-test.XXXXXX", NULL); + ts.dst_tpm_path = g_dir_make_tmp("qemu-tpm-crb-swtpm-test.XXXXXX", NULL); + ts.uri = g_strdup_printf("unix:%s/migsocket", ts.src_tpm_path); + + module_call_init(MODULE_INIT_QOM); + g_test_init(&argc, &argv, NULL); + + qtest_add_data_func("/tpm/crb-swtpm/test", &ts, tpm_crb_swtpm_test); + qtest_add_data_func("/tpm/crb-swtpm-migration/test", &ts, + tpm_crb_swtpm_migration_test); + ret = g_test_run(); + + tpm_util_rmdir(ts.dst_tpm_path); + g_free(ts.dst_tpm_path); + tpm_util_rmdir(ts.src_tpm_path); + g_free(ts.src_tpm_path); + g_free(ts.uri); + + return ret; +} diff --git a/tests/qtest/tpm-crb-device-test.c b/tests/qtest/tpm-crb-device-test.c new file mode 100644 index 0000000000..17d09a57fd --- /dev/null +++ b/tests/qtest/tpm-crb-device-test.c @@ -0,0 +1,71 @@ +/* + * QTest testcase for TPM CRB + * + * Copyright (c) 2018 Red Hat, Inc. + * + * Authors: + * Marc-André Lureau + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include + +#include "hw/acpi/tpm.h" +#include "io/channel-socket.h" +#include "libqtest-single.h" +#include "qemu/module.h" +#include "tpm-emu.h" +#include "tpm-tests.h" + +/* + * As the Sysbus tpm-crb-device is instantiated on the ARM virt + * platform bus and it is the only sysbus device dynamically + * instantiated, it gets plugged at its base address + */ +uint64_t tpm_device_base_addr = 0xc000000; + +int main(int argc, char **argv) +{ + int ret; + char *args, *tmp_path = g_dir_make_tmp("qemu-tpm-crb-test.XXXXXX", NULL); + GThread *thread; + TPMTestState test; + + module_call_init(MODULE_INIT_QOM); + g_test_init(&argc, &argv, NULL); + + test.addr = g_new0(SocketAddress, 1); + test.addr->type = SOCKET_ADDRESS_TYPE_UNIX; + test.addr->u.q_unix.path = g_build_filename(tmp_path, "sock", NULL); + g_mutex_init(&test.data_mutex); + g_cond_init(&test.data_cond); + test.data_cond_signal = false; + test.tpm_version = TPM_VERSION_2_0; + + thread = g_thread_new(NULL, tpm_emu_ctrl_thread, &test); + tpm_emu_test_wait_cond(&test); + + args = g_strdup_printf( + "-machine virt,gic-version=max -accel tcg " + "-chardev socket,id=chr,path=%s " + "-tpmdev emulator,id=dev,chardev=chr " + "-device tpm-crb-device,tpmdev=dev", + test.addr->u.q_unix.path); + qtest_start(args); + + qtest_add_data_func("/tpm-crb/test", &test, tpm_test_crb); + ret = g_test_run(); + + qtest_end(); + + g_thread_join(thread); + g_unlink(test.addr->u.q_unix.path); + qapi_free_SocketAddress(test.addr); + g_rmdir(tmp_path); + g_free(tmp_path); + g_free(args); + return ret; +} diff --git a/tests/qtest/tpm-crb-swtpm-test.c b/tests/qtest/tpm-crb-swtpm-test.c index ffeb1c396b..08862210a4 100644 --- a/tests/qtest/tpm-crb-swtpm-test.c +++ b/tests/qtest/tpm-crb-swtpm-test.c @@ -19,6 +19,8 @@ #include "tpm-tests.h" #include "hw/acpi/tpm.h" +uint64_t tpm_device_base_addr = TPM_CRB_ADDR_BASE; + typedef struct TestState { char *src_tpm_path; char *dst_tpm_path; diff --git a/tests/qtest/tpm-crb-test.c b/tests/qtest/tpm-crb-test.c index 9d30fe8293..51614abc70 100644 --- a/tests/qtest/tpm-crb-test.c +++ b/tests/qtest/tpm-crb-test.c @@ -18,124 +18,9 @@ #include "libqtest-single.h" #include "qemu/module.h" #include "tpm-emu.h" +#include "tpm-tests.h" -#define TPM_CMD "\x80\x01\x00\x00\x00\x0c\x00\x00\x01\x44\x00\x00" - -static void tpm_crb_test(const void *data) -{ - const TPMTestState *s = data; - uint32_t intfid = readl(TPM_CRB_ADDR_BASE + A_CRB_INTF_ID); - uint32_t csize = readl(TPM_CRB_ADDR_BASE + A_CRB_CTRL_CMD_SIZE); - uint64_t caddr = readq(TPM_CRB_ADDR_BASE + A_CRB_CTRL_CMD_LADDR); - uint32_t rsize = readl(TPM_CRB_ADDR_BASE + A_CRB_CTRL_RSP_SIZE); - uint64_t raddr = readq(TPM_CRB_ADDR_BASE + A_CRB_CTRL_RSP_LADDR); - uint8_t locstate = readb(TPM_CRB_ADDR_BASE + A_CRB_LOC_STATE); - uint32_t locctrl = readl(TPM_CRB_ADDR_BASE + A_CRB_LOC_CTRL); - uint32_t locsts = readl(TPM_CRB_ADDR_BASE + A_CRB_LOC_STS); - uint32_t sts = readl(TPM_CRB_ADDR_BASE + A_CRB_CTRL_STS); - - g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, InterfaceType), ==, 1); - g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, InterfaceVersion), ==, 1); - g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapLocality), ==, 0); - g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapCRBIdleBypass), ==, 0); - g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapDataXferSizeSupport), - ==, 3); - g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapFIFO), ==, 0); - g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapCRB), ==, 1); - g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, InterfaceSelector), ==, 1); - g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, RID), ==, 0); - - g_assert_cmpint(csize, >=, 128); - g_assert_cmpint(rsize, >=, 128); - g_assert_cmpint(caddr, >, TPM_CRB_ADDR_BASE); - g_assert_cmpint(raddr, >, TPM_CRB_ADDR_BASE); - - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmEstablished), ==, 1); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, locAssigned), ==, 0); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, activeLocality), ==, 0); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, reserved), ==, 0); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmRegValidSts), ==, 1); - - g_assert_cmpint(locctrl, ==, 0); - - g_assert_cmpint(FIELD_EX32(locsts, CRB_LOC_STS, Granted), ==, 0); - g_assert_cmpint(FIELD_EX32(locsts, CRB_LOC_STS, beenSeized), ==, 0); - - g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmIdle), ==, 1); - g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmSts), ==, 0); - - /* request access to locality 0 */ - writeb(TPM_CRB_ADDR_BASE + A_CRB_LOC_CTRL, 1); - - /* granted bit must be set now */ - locsts = readl(TPM_CRB_ADDR_BASE + A_CRB_LOC_STS); - g_assert_cmpint(FIELD_EX32(locsts, CRB_LOC_STS, Granted), ==, 1); - g_assert_cmpint(FIELD_EX32(locsts, CRB_LOC_STS, beenSeized), ==, 0); - - /* we must have an assigned locality */ - locstate = readb(TPM_CRB_ADDR_BASE + A_CRB_LOC_STATE); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmEstablished), ==, 1); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, locAssigned), ==, 1); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, activeLocality), ==, 0); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, reserved), ==, 0); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmRegValidSts), ==, 1); - - /* set into ready state */ - writel(TPM_CRB_ADDR_BASE + A_CRB_CTRL_REQ, 1); - - /* TPM must not be in the idle state */ - sts = readl(TPM_CRB_ADDR_BASE + A_CRB_CTRL_STS); - g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmIdle), ==, 0); - g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmSts), ==, 0); - - memwrite(caddr, TPM_CMD, sizeof(TPM_CMD)); - - uint32_t start = 1; - uint64_t end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND; - writel(TPM_CRB_ADDR_BASE + A_CRB_CTRL_START, start); - do { - start = readl(TPM_CRB_ADDR_BASE + A_CRB_CTRL_START); - if ((start & 1) == 0) { - break; - } - } while (g_get_monotonic_time() < end_time); - start = readl(TPM_CRB_ADDR_BASE + A_CRB_CTRL_START); - g_assert_cmpint(start & 1, ==, 0); - - /* TPM must still not be in the idle state */ - sts = readl(TPM_CRB_ADDR_BASE + A_CRB_CTRL_STS); - g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmIdle), ==, 0); - g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmSts), ==, 0); - - struct tpm_hdr tpm_msg; - memread(raddr, &tpm_msg, sizeof(tpm_msg)); - g_assert_cmpmem(&tpm_msg, sizeof(tpm_msg), s->tpm_msg, sizeof(*s->tpm_msg)); - - /* set TPM into idle state */ - writel(TPM_CRB_ADDR_BASE + A_CRB_CTRL_REQ, 2); - - /* idle state must be indicated now */ - sts = readl(TPM_CRB_ADDR_BASE + A_CRB_CTRL_STS); - g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmIdle), ==, 1); - g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmSts), ==, 0); - - /* relinquish locality */ - writel(TPM_CRB_ADDR_BASE + A_CRB_LOC_CTRL, 2); - - /* Granted flag must be cleared */ - sts = readl(TPM_CRB_ADDR_BASE + A_CRB_LOC_STS); - g_assert_cmpint(FIELD_EX32(sts, CRB_LOC_STS, Granted), ==, 0); - g_assert_cmpint(FIELD_EX32(sts, CRB_LOC_STS, beenSeized), ==, 0); - - /* no locality may be assigned */ - locstate = readb(TPM_CRB_ADDR_BASE + A_CRB_LOC_STATE); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmEstablished), ==, 1); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, locAssigned), ==, 0); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, activeLocality), ==, 0); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, reserved), ==, 0); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmRegValidSts), ==, 1); - -} +uint64_t tpm_device_base_addr = TPM_CRB_ADDR_BASE; int main(int argc, char **argv) { @@ -165,7 +50,7 @@ int main(int argc, char **argv) test.addr->u.q_unix.path); qtest_start(args); - qtest_add_data_func("/tpm-crb/test", &test, tpm_crb_test); + qtest_add_data_func("/tpm-crb/test", &test, tpm_test_crb); ret = g_test_run(); qtest_end(); diff --git a/tests/qtest/tpm-tests.c b/tests/qtest/tpm-tests.c index fb94496bbd..83c5536136 100644 --- a/tests/qtest/tpm-tests.c +++ b/tests/qtest/tpm-tests.c @@ -15,7 +15,10 @@ #include "qemu/osdep.h" #include +#include "hw/registerfields.h" +#include "hw/acpi/tpm.h" #include "libqtest-single.h" +#include "tpm-emu.h" #include "tpm-tests.h" static bool @@ -130,3 +133,121 @@ void tpm_test_swtpm_migration_test(const char *src_tpm_path, g_unlink(src_tpm_addr->u.q_unix.path); qapi_free_SocketAddress(src_tpm_addr); } + +#define TPM_CMD "\x80\x01\x00\x00\x00\x0c\x00\x00\x01\x44\x00\x00" + +void tpm_test_crb(const void *data) +{ + const TPMTestState *s = data; + uint32_t intfid = readl(tpm_device_base_addr + A_CRB_INTF_ID); + uint32_t csize = readl(tpm_device_base_addr + A_CRB_CTRL_CMD_SIZE); + uint64_t caddr = readq(tpm_device_base_addr + A_CRB_CTRL_CMD_LADDR); + uint32_t rsize = readl(tpm_device_base_addr + A_CRB_CTRL_RSP_SIZE); + uint64_t raddr = readq(tpm_device_base_addr + A_CRB_CTRL_RSP_LADDR); + uint8_t locstate = readb(tpm_device_base_addr + A_CRB_LOC_STATE); + uint32_t locctrl = readl(tpm_device_base_addr + A_CRB_LOC_CTRL); + uint32_t locsts = readl(tpm_device_base_addr + A_CRB_LOC_STS); + uint32_t sts = readl(tpm_device_base_addr + A_CRB_CTRL_STS); + + g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, InterfaceType), ==, 1); + g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, InterfaceVersion), ==, 1); + g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapLocality), ==, 0); + g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapCRBIdleBypass), ==, 0); + g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapDataXferSizeSupport), + ==, 3); + g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapFIFO), ==, 0); + g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapCRB), ==, 1); + g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, InterfaceSelector), ==, 1); + g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, RID), ==, 0); + + g_assert_cmpint(csize, >=, 128); + g_assert_cmpint(rsize, >=, 128); + g_assert_cmpint(caddr, >, tpm_device_base_addr); + g_assert_cmpint(raddr, >, tpm_device_base_addr); + + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmEstablished), ==, 1); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, locAssigned), ==, 0); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, activeLocality), ==, 0); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, reserved), ==, 0); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmRegValidSts), ==, 1); + + g_assert_cmpint(locctrl, ==, 0); + + g_assert_cmpint(FIELD_EX32(locsts, CRB_LOC_STS, Granted), ==, 0); + g_assert_cmpint(FIELD_EX32(locsts, CRB_LOC_STS, beenSeized), ==, 0); + + g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmIdle), ==, 1); + g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmSts), ==, 0); + + /* request access to locality 0 */ + writeb(tpm_device_base_addr + A_CRB_LOC_CTRL, 1); + + /* granted bit must be set now */ + locsts = readl(tpm_device_base_addr + A_CRB_LOC_STS); + g_assert_cmpint(FIELD_EX32(locsts, CRB_LOC_STS, Granted), ==, 1); + g_assert_cmpint(FIELD_EX32(locsts, CRB_LOC_STS, beenSeized), ==, 0); + + /* we must have an assigned locality */ + locstate = readb(tpm_device_base_addr + A_CRB_LOC_STATE); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmEstablished), ==, 1); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, locAssigned), ==, 1); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, activeLocality), ==, 0); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, reserved), ==, 0); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmRegValidSts), ==, 1); + + /* set into ready state */ + writel(tpm_device_base_addr + A_CRB_CTRL_REQ, 1); + + /* TPM must not be in the idle state */ + sts = readl(tpm_device_base_addr + A_CRB_CTRL_STS); + g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmIdle), ==, 0); + g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmSts), ==, 0); + + memwrite(caddr, TPM_CMD, sizeof(TPM_CMD)); + + uint32_t start = 1; + uint64_t end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND; + writel(tpm_device_base_addr + A_CRB_CTRL_START, start); + do { + start = readl(tpm_device_base_addr + A_CRB_CTRL_START); + if ((start & 1) == 0) { + break; + } + } while (g_get_monotonic_time() < end_time); + start = readl(tpm_device_base_addr + A_CRB_CTRL_START); + g_assert_cmpint(start & 1, ==, 0); + + /* TPM must still not be in the idle state */ + sts = readl(tpm_device_base_addr + A_CRB_CTRL_STS); + g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmIdle), ==, 0); + g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmSts), ==, 0); + + struct tpm_hdr tpm_msg; + memread(raddr, &tpm_msg, sizeof(tpm_msg)); + g_assert_cmpmem(&tpm_msg, sizeof(tpm_msg), s->tpm_msg, sizeof(*s->tpm_msg)); + + /* set TPM into idle state */ + writel(tpm_device_base_addr + A_CRB_CTRL_REQ, 2); + + /* idle state must be indicated now */ + sts = readl(tpm_device_base_addr + A_CRB_CTRL_STS); + g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmIdle), ==, 1); + g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmSts), ==, 0); + + /* relinquish locality */ + writel(tpm_device_base_addr + A_CRB_LOC_CTRL, 2); + + /* Granted flag must be cleared */ + sts = readl(tpm_device_base_addr + A_CRB_LOC_STS); + g_assert_cmpint(FIELD_EX32(sts, CRB_LOC_STS, Granted), ==, 0); + g_assert_cmpint(FIELD_EX32(sts, CRB_LOC_STS, beenSeized), ==, 0); + + /* no locality may be assigned */ + locstate = readb(tpm_device_base_addr + A_CRB_LOC_STATE); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmEstablished), ==, 1); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, locAssigned), ==, 0); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, activeLocality), ==, 0); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, reserved), ==, 0); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmRegValidSts), ==, 1); + +} diff --git a/tests/qtest/tpm-tis-device-swtpm-test.c b/tests/qtest/tpm-tis-device-swtpm-test.c index 517a077005..54d1cedc6f 100644 --- a/tests/qtest/tpm-tis-device-swtpm-test.c +++ b/tests/qtest/tpm-tis-device-swtpm-test.c @@ -21,7 +21,7 @@ #include "tpm-tis-util.h" #include "hw/acpi/tpm.h" -uint64_t tpm_tis_base_addr = 0xc000000; +uint64_t tpm_device_base_addr = 0xc000000; #define MACHINE_OPTIONS "-machine virt,gic-version=max -accel tcg" typedef struct TestState { diff --git a/tests/qtest/tpm-tis-device-test.c b/tests/qtest/tpm-tis-device-test.c index 3ddefb51ec..4f6609ae98 100644 --- a/tests/qtest/tpm-tis-device-test.c +++ b/tests/qtest/tpm-tis-device-test.c @@ -27,7 +27,7 @@ * platform bus and it is the only sysbus device dynamically * instantiated, it gets plugged at its base address */ -uint64_t tpm_tis_base_addr = 0xc000000; +uint64_t tpm_device_base_addr = 0xc000000; int main(int argc, char **argv) { diff --git a/tests/qtest/tpm-tis-i2c-test.c b/tests/qtest/tpm-tis-i2c-test.c index 3a1af026f2..9495cc1739 100644 --- a/tests/qtest/tpm-tis-i2c-test.c +++ b/tests/qtest/tpm-tis-i2c-test.c @@ -39,6 +39,9 @@ #define I2C_SLAVE_ADDR 0x2e #define I2C_DEV_BUS_NUM 10 +/* unused but needed for tpm-util.c to link */ +uint64_t tpm_device_base_addr; + static const uint8_t TPM_CMD[12] = "\x80\x01\x00\x00\x00\x0c\x00\x00\x01\x44\x00\x00"; diff --git a/tests/qtest/tpm-tis-swtpm-test.c b/tests/qtest/tpm-tis-swtpm-test.c index 105e42e21d..5bfbbc0a67 100644 --- a/tests/qtest/tpm-tis-swtpm-test.c +++ b/tests/qtest/tpm-tis-swtpm-test.c @@ -20,7 +20,7 @@ #include "tpm-tis-util.h" #include "hw/acpi/tpm.h" -uint64_t tpm_tis_base_addr = TPM_TIS_ADDR_BASE; +uint64_t tpm_device_base_addr = TPM_TIS_ADDR_BASE; typedef struct TestState { char *src_tpm_path; diff --git a/tests/qtest/tpm-tis-test.c b/tests/qtest/tpm-tis-test.c index a4a25ba745..7661568aa8 100644 --- a/tests/qtest/tpm-tis-test.c +++ b/tests/qtest/tpm-tis-test.c @@ -22,7 +22,7 @@ #include "tpm-emu.h" #include "tpm-tis-util.h" -uint64_t tpm_tis_base_addr = TPM_TIS_ADDR_BASE; +uint64_t tpm_device_base_addr = TPM_TIS_ADDR_BASE; int main(int argc, char **argv) { diff --git a/tests/qtest/tpm-util.c b/tests/qtest/tpm-util.c index dd02057fc0..1608901a76 100644 --- a/tests/qtest/tpm-util.c +++ b/tests/qtest/tpm-util.c @@ -24,18 +24,20 @@ void tpm_util_crb_transfer(QTestState *s, const unsigned char *req, size_t req_size, unsigned char *rsp, size_t rsp_size) { - uint64_t caddr = qtest_readq(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_CMD_LADDR); - uint64_t raddr = qtest_readq(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_RSP_LADDR); + uint64_t caddr = qtest_readq(s, tpm_device_base_addr + + A_CRB_CTRL_CMD_LADDR); + uint64_t raddr = qtest_readq(s, tpm_device_base_addr + + A_CRB_CTRL_RSP_LADDR); - qtest_writeb(s, TPM_CRB_ADDR_BASE + A_CRB_LOC_CTRL, 1); + qtest_writeb(s, tpm_device_base_addr + A_CRB_LOC_CTRL, 1); qtest_memwrite(s, caddr, req, req_size); uint32_t sts, start = 1; uint64_t end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND; - qtest_writel(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_START, start); + qtest_writel(s, tpm_device_base_addr + A_CRB_CTRL_START, start); while (true) { - start = qtest_readl(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_START); + start = qtest_readl(s, tpm_device_base_addr + A_CRB_CTRL_START); if ((start & 1) == 0) { break; } @@ -43,9 +45,9 @@ void tpm_util_crb_transfer(QTestState *s, break; } }; - start = qtest_readl(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_START); + start = qtest_readl(s, tpm_device_base_addr + A_CRB_CTRL_START); g_assert_cmpint(start & 1, ==, 0); - sts = qtest_readl(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_STS); + sts = qtest_readl(s, tpm_device_base_addr + A_CRB_CTRL_STS); g_assert_cmpint(sts & 1, ==, 0); qtest_memread(s, raddr, rsp, rsp_size); diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index d6022ebd64..0e6ef6aebf 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -215,6 +215,8 @@ qtests_aarch64 = \ (cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) + \ (config_all.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? \ ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) + \ + (config_all.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_CRB_SYSBUS') ? \ + ['tpm-crb-device-test', 'tpm-crb-device-swtpm-test'] : []) + \ (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \ (config_all_devices.has_key('CONFIG_XLNX_VERSAL') ? ['xlnx-canfd-test'] : []) + \ (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \ @@ -312,6 +314,8 @@ qtests = { 'qos-test': [chardev, io, qos_test_ss.apply(config_targetos, strict: false).sources()], 'tpm-crb-swtpm-test': [io, tpmemu_files], 'tpm-crb-test': [io, tpmemu_files], + 'tpm-crb-device-swtpm-test': [io, tpmemu_files], + 'tpm-crb-device-test': [io, tpmemu_files], 'tpm-tis-swtpm-test': [io, tpmemu_files, 'tpm-tis-util.c'], 'tpm-tis-test': [io, tpmemu_files, 'tpm-tis-util.c'], 'tpm-tis-i2c-test': [io, tpmemu_files, 'qtest_aspeed.c'],