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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li Subject: [PATCH V10 1/7] x86: Drop CPU_SUP_INTEL from SCHED_MC_PRIO for the expansion. Date: Mon, 30 Oct 2023 14:33:57 +0800 Message-ID: <20231030063403.3502816-2-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231030063403.3502816-1-li.meng@amd.com> References: <20231030063403.3502816-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB73:EE_|CYYPR12MB9015:EE_ X-MS-Office365-Filtering-Correlation-Id: a8448bc7-4d65-4927-9a65-08dbd9125431 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: kAlCGr2AV/ABos/mx0ShWk9gK37uAm96BjgS8cky+XuJ5HJ1PTThRJNXQ+rbe+JOHFQqO7/st1R59GZGi+llv4K6AnO3RCjaTIno9skt+RygSRceu+B4CeYJ2w1/ZaCmx62qFI8v5MxYmWHSRMGy99rtkYNkso7y/Euz7kTrLjYxhBfQRHrpl1cS7W2wQ2coJfpCfMDXzGZkPpHg90SKsz3XTjXvKSNRc9Ea8pY4bxjMfAB/aQ/OoI/JJDihKAcHjY3tESx4R1tTqRILGIj2DTgXfWdjCJtn2h380/ZuqIKn+MwyxkkmLaZvgvCpanZ2L2w1O3YLgsjWilJxmaGxLOkIzw4aVk0t9E+9BHUzN7RKRjswLQGpf+ZuFRPUqGxWnTbM4DSPnhMyOMz20ZaLbkxnHmX/me5IbPzNfDEjgNJK7vR0nBsYfUSF1z7nqQFbilsasexABD/oQCchB5EVF4fSiwGVYrsrV8LhZHmOjgmynUW/XUF3uK7SWhjohIFjhvq09TOTlKonfJbZEpiaGyPc7REVZZipimhhlXPq2TuI2TqpJRCP3au4LL/kuMpNV/ix2QIni01AU5CC566pAb9jl7YhB+iB/odza8ECUM5rv6kr0qODqraVXjrK7VC1yr3TnlgCRum4JOdsBPMFg1Et2/UO6rz0wld6RuzH86S7wvJjhE+CRclDgEBx0tg5GrbdQz999mj9EA9MFp0ZEFjbibDR40cgMZEcmC/UKpZefv2SDuzbYgd+QxLkmWpgX3zVffn7NwPotN/2plt6og== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(136003)(396003)(376002)(346002)(230922051799003)(64100799003)(1800799009)(82310400011)(186009)(451199024)(40470700004)(46966006)(36840700001)(478600001)(7696005)(6666004)(110136005)(70206006)(70586007)(426003)(16526019)(336012)(26005)(1076003)(2616005)(41300700001)(2906002)(54906003)(4744005)(316002)(8936002)(8676002)(6636002)(5660300002)(7416002)(4326008)(86362001)(36756003)(36860700001)(83380400001)(47076005)(81166007)(82740400003)(356005)(40480700001)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2023 06:34:54.7920 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a8448bc7-4d65-4927-9a65-08dbd9125431 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB73.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB9015 Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org amd-pstate driver also uses SCHED_MC_PRIO, so decouple the requirement of CPU_SUP_INTEL from the dependencies to allow compilation in kernels without Intel CPU support. Tested-by: Oleksandr Natalenko Reviewed-by: Mario Limonciello Reviewed-by: Huang Rui Signed-off-by: Meng Li --- arch/x86/Kconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 66bfabae8814..a2e163acf623 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1054,8 +1054,9 @@ config SCHED_MC config SCHED_MC_PRIO bool "CPU core priorities scheduler support" - depends on SCHED_MC && CPU_SUP_INTEL - select X86_INTEL_PSTATE + depends on SCHED_MC + select X86_INTEL_PSTATE if CPU_SUP_INTEL + select X86_AMD_PSTATE if CPU_SUP_AMD && ACPI select CPU_FREQ default y help From patchwork Mon Oct 30 06:33:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Meng, Li (Jassmine)" X-Patchwork-Id: 13440037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3C30C4167D for ; Mon, 30 Oct 2023 06:35:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231638AbjJ3Gfb (ORCPT ); Mon, 30 Oct 2023 02:35:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231671AbjJ3GfY (ORCPT ); Mon, 30 Oct 2023 02:35:24 -0400 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2046.outbound.protection.outlook.com [40.107.101.46]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 664EBE9; Sun, 29 Oct 2023 23:35:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=nShVtEPaAZIMostyrO6fKlG58LQfbFpnHtN8kG38gechT0fJGj5LJ5XH68ZwoKLB3ayZEcRwJGorAXPMFkwRt+cN9qzDBSxCsaaG1cIm96WLKJjuCgKhB+brnlQKUiLT49zHwDzyV6tDSR+91bX9lX4GsfsFG5emta9NR0x74rBbzOchdIKDzzBp6gbcJ7xnZX06tKekY1RYD1W9gpGxybTy1c63bIrjbhGI5AmM9gvBgbJhYiVkomwERmtvPmsWxNzhb7DLc584xKMhBM6RDmcmopR1E/0bQz74VzFbiw0ZT9EvS9OpTegXPpghbm30cHY1Ib42gYxpsrTjMMvIdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=AlF2WKiSUPyODRJ7ueMUccEPh7maCKY1Dj6+XRqyp7A=; b=J/w0Cz8nXQK8JZQZ+HnmVGK1zxxVYYjHYJOuMwQN8FdCYOKdd8W4PelGz4xncdZq2M7hryAfy/sgSQxqdlUddq6LGi8jzxdpyiUD8bf3iNrMgDUSNsuk7MVATIG4Tl/CEoTcfN5jVU750/NaHegq9Soz3DHxHpF9z48hDFihZMoN64Tw0neboiuxgsKlEtz7AyyUiC4lkUJR6YJuieqh0qPgik+pt6yXZwHTr8ek5Vh5e+xoXSLvrJPIkQhyRiXIg/Xa1IRLGtEc5jB1Li0FkC3m7LdW/3B47nilVJl/5QWoZkOvQuPdw243143KnYrOPhIv2EQ3is31CJljFJQTdw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=intel.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=AlF2WKiSUPyODRJ7ueMUccEPh7maCKY1Dj6+XRqyp7A=; b=FD00Zt0dyEP7j1x667PjY8bPuFxL4DBs/+4wlYMCX0ipQgf/ZUosNCSXpqLDS7jxJrhV12FSLl4WsubR3MMIh9O+t1VIg+08VrD7X6qO07I+9d7mfAJDSS0Rnfk91INs0fx9v2b/CsLrSNXc14DjQbod0bHxxcFVIBlroQJbH6w= Received: from DM6PR06CA0025.namprd06.prod.outlook.com (2603:10b6:5:120::38) by CH3PR12MB8548.namprd12.prod.outlook.com (2603:10b6:610:165::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6933.26; Mon, 30 Oct 2023 06:35:18 +0000 Received: from CY4PEPF0000EE32.namprd05.prod.outlook.com (2603:10b6:5:120:cafe::57) by DM6PR06CA0025.outlook.office365.com (2603:10b6:5:120::38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6933.26 via Frontend Transport; Mon, 30 Oct 2023 06:35:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000EE32.mail.protection.outlook.com (10.167.242.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6933.15 via Frontend Transport; Mon, 30 Oct 2023 06:35:18 +0000 Received: from jasmine-meng.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Mon, 30 Oct 2023 01:34:54 -0500 From: Meng Li To: "Rafael J . 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This enables downstream drivers such as amd-pstate to discover and use these values. Please refer to the ACPI_Spec for details on continuous performance control of CPPC. Tested-by: Oleksandr Natalenko Reviewed-by: Mario Limonciello Reviewed-by: Wyes Karny Acked-by: Huang Rui Signed-off-by: Meng Li Link: https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html?highlight=cppc#highest-performance --- drivers/acpi/cppc_acpi.c | 13 +++++++++++++ include/acpi/cppc_acpi.h | 5 +++++ 2 files changed, 18 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 7ff269a78c20..ad388a0e8484 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1154,6 +1154,19 @@ int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf) return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf); } +/** + * cppc_get_highest_perf - Get the highest performance register value. + * @cpunum: CPU from which to get highest performance. + * @highest_perf: Return address. + * + * Return: 0 for success, -EIO otherwise. + */ +int cppc_get_highest_perf(int cpunum, u64 *highest_perf) +{ + return cppc_get_perf(cpunum, HIGHEST_PERF, highest_perf); +} +EXPORT_SYMBOL_GPL(cppc_get_highest_perf); + /** * cppc_get_epp_perf - Get the epp register value. * @cpunum: CPU from which to get epp preference value. diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 6126c977ece0..c0b69ffe7bdb 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -139,6 +139,7 @@ struct cppc_cpudata { #ifdef CONFIG_ACPI_CPPC_LIB extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf); extern int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf); +extern int cppc_get_highest_perf(int cpunum, u64 *highest_perf); extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); extern int cppc_set_enable(int cpu, bool enable); @@ -165,6 +166,10 @@ static inline int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf) { return -ENOTSUPP; } +static inline int cppc_get_highest_perf(int cpunum, u64 *highest_perf) +{ + return -ENOTSUPP; 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li , Wyes Karny Subject: [PATCH V10 3/7] cpufreq: amd-pstate: Enable amd-pstate preferred core supporting. Date: Mon, 30 Oct 2023 14:33:59 +0800 Message-ID: <20231030063403.3502816-4-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231030063403.3502816-1-li.meng@amd.com> References: <20231030063403.3502816-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB73:EE_|SJ1PR12MB6076:EE_ X-MS-Office365-Filtering-Correlation-Id: e6a4bf4b-b69d-4689-23a9-08dbd9126533 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: cSMI9yMQGL9gV37ZS8foFeFc8yLPHR6mvvxGLLnzmUYhuRcDOEC8/g1EbROwRAVLCA1QeKKkB7kCoTeSbUumK7HtrR58VOHx3uBsmqIS/hDcr69yG2TwivIOb56j0dXM/uDT4taP0vlT5QqqPmHI/H8P7b+HftLxmeaMI1mLGY6rxS8FigI8gn12lt+rXDeSylY2zpxvTqiw/dgcUXLqv3Pgq7pLD3iDviIGBivAu9tFUQQt3f8zaQXINWPYzNs9BQWpdSZmT9IYqAU7+yDQjYBQSMLZll6qMXyKtiSFUzpcSQtRAYs35jxZ0ThEBz8aNrkdxiYUPN71UdEG4I1tlgDMr8c9E4QZRnL/PS66t+BDID+vEwonxI8qLZXzuaffXNFy9VBVNy/182UTmvjlSKKdaFvfIIWdCBpLTR7j499Bnl8oJ/yIkdKcGIznUBn94VpKFy+GrnBc1LegfIJA+rtyM7ZMageV2d6calDjb6K5B5hufA14DL+jEoBj9lxQoq5cH3LKRFtaWkT18pTayX/Kmwt5jlnKHM/+CYexc/bD44w69b0pRl1KpS0cXbJW8OiIj3jcdkYDPiUDEa6NimVExqoCHA6njHZkA8tCPrTuHmR4pYca+W3qjjwnwe6ibBONHzB1YmB/x9ABX7QpEzWKZAYyMecw+6NmqjukQ5CSzKDRsGhROimPUYdgdv46iADRdm4AeUpv2O8vpvGzv9uP6wyojzCb+sqwVwaetluj4vENZxW4NsiYeOMRijkfuSinzw8hyW537HwrHgQiVw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(396003)(136003)(39860400002)(346002)(230922051799003)(186009)(451199024)(1800799009)(64100799003)(82310400011)(36840700001)(40470700004)(46966006)(5660300002)(41300700001)(7416002)(2906002)(110136005)(70586007)(54906003)(70206006)(40460700003)(8936002)(8676002)(4326008)(40480700001)(316002)(478600001)(6636002)(83380400001)(356005)(81166007)(36860700001)(47076005)(86362001)(36756003)(7696005)(6666004)(26005)(426003)(336012)(1076003)(82740400003)(2616005)(16526019)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2023 06:35:23.3077 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e6a4bf4b-b69d-4689-23a9-08dbd9126533 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB73.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6076 Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org amd-pstate driver utilizes the functions and data structures provided by the ITMT architecture to enable the scheduler to favor scheduling on cores which can be get a higher frequency with lower voltage. We call it amd-pstate preferrred core. Here sched_set_itmt_core_prio() is called to set priorities and sched_set_itmt_support() is called to enable ITMT feature. amd-pstate driver uses the highest performance value to indicate the priority of CPU. The higher value has a higher priority. The initial core rankings are set up by amd-pstate when the system boots. Add a variable hw_prefcore in cpudata structure. It will check if the processor and power firmware support preferred core feature. Add one new early parameter `disable` to allow user to disable the preferred core. Only when hardware supports preferred core and user set `enabled` in early parameter, amd pstate driver supports preferred core featue. Tested-by: Oleksandr Natalenko Reviewed-by: Huang Rui Reviewed-by: Wyes Karny Reviewed-by: Mario Limonciello Co-developed-by: Perry Yuan Signed-off-by: Perry Yuan Signed-off-by: Meng Li --- drivers/cpufreq/amd-pstate.c | 141 +++++++++++++++++++++++++++++++---- include/linux/amd-pstate.h | 4 + 2 files changed, 129 insertions(+), 16 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 9a1e194d5cf8..2033e5e70017 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include @@ -49,6 +50,7 @@ #define AMD_PSTATE_TRANSITION_LATENCY 20000 #define AMD_PSTATE_TRANSITION_DELAY 1000 +#define AMD_PSTATE_PREFCORE_THRESHOLD 166 /* * TODO: We need more time to fine tune processors with shared memory solution @@ -64,6 +66,7 @@ static struct cpufreq_driver amd_pstate_driver; static struct cpufreq_driver amd_pstate_epp_driver; static int cppc_state = AMD_PSTATE_UNDEFINED; static bool cppc_enabled; +static bool amd_pstate_prefcore = true; /* * AMD Energy Preference Performance (EPP) @@ -290,23 +293,21 @@ static inline int amd_pstate_enable(bool enable) static int pstate_init_perf(struct amd_cpudata *cpudata) { u64 cap1; - u32 highest_perf; int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &cap1); if (ret) return ret; - /* - * TODO: Introduce AMD specific power feature. - * - * CPPC entry doesn't indicate the highest performance in some ASICs. + /* For platforms that do not support the preferred core feature, the + * highest_pef may be configured with 166 or 255, to avoid max frequency + * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as + * the default max perf. */ - highest_perf = amd_get_highest_perf(); - if (highest_perf > AMD_CPPC_HIGHEST_PERF(cap1)) - highest_perf = AMD_CPPC_HIGHEST_PERF(cap1); - - WRITE_ONCE(cpudata->highest_perf, highest_perf); + if (cpudata->hw_prefcore) + WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD); + else + WRITE_ONCE(cpudata->highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1)); WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1)); @@ -318,17 +319,15 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) static int cppc_init_perf(struct amd_cpudata *cpudata) { struct cppc_perf_caps cppc_perf; - u32 highest_perf; int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); if (ret) return ret; - highest_perf = amd_get_highest_perf(); - if (highest_perf > cppc_perf.highest_perf) - highest_perf = cppc_perf.highest_perf; - - WRITE_ONCE(cpudata->highest_perf, highest_perf); + if (cpudata->hw_prefcore) + WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD); + else + WRITE_ONCE(cpudata->highest_perf, cppc_perf.highest_perf); WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf); WRITE_ONCE(cpudata->lowest_nonlinear_perf, @@ -676,6 +675,80 @@ static void amd_perf_ctl_reset(unsigned int cpu) wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0); } +/* + * Set amd-pstate preferred core enable can't be done directly from cpufreq callbacks + * due to locking, so queue the work for later. + */ +static void amd_pstste_sched_prefcore_workfn(struct work_struct *work) +{ + sched_set_itmt_support(); +} +static DECLARE_WORK(sched_prefcore_work, amd_pstste_sched_prefcore_workfn); + +/* + * Get the highest performance register value. + * @cpu: CPU from which to get highest performance. + * @highest_perf: Return address. + * + * Return: 0 for success, -EIO otherwise. + */ +static int amd_pstate_get_highest_perf(int cpu, u32 *highest_perf) +{ + int ret; + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + u64 cap1; + + ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1); + if (ret) + return ret; + WRITE_ONCE(*highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); + } else { + u64 cppc_highest_perf; + + ret = cppc_get_highest_perf(cpu, &cppc_highest_perf); + if (ret) + return ret; + WRITE_ONCE(*highest_perf, cppc_highest_perf); + } + + return (ret); +} + +#define CPPC_MAX_PERF U8_MAX + +static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata) +{ + int ret, prio; + u32 highest_perf; + + ret = amd_pstate_get_highest_perf(cpudata->cpu, &highest_perf); + if (ret) + return; + + cpudata->hw_prefcore = true; + /* check if CPPC preferred core feature is enabled*/ + if (highest_perf < CPPC_MAX_PERF) + prio = (int)highest_perf; + else { + pr_debug("AMD CPPC preferred core is unsupported!\n"); + cpudata->hw_prefcore = false; + return; + } + + if (!amd_pstate_prefcore) + return; + + /* + * The priorities can be set regardless of whether or not + * sched_set_itmt_support(true) has been called and it is valid to + * update them at any time after it has been called. + */ + sched_set_itmt_core_prio(prio, cpudata->cpu); + + schedule_work(&sched_prefcore_work); +} + static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; @@ -697,6 +770,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) cpudata->cpu = policy->cpu; + amd_pstate_init_prefcore(cpudata); + ret = amd_pstate_init_perf(cpudata); if (ret) goto free_cpudata1; @@ -845,6 +920,17 @@ static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy, return sysfs_emit(buf, "%u\n", perf); } +static ssize_t show_amd_pstate_hw_prefcore(struct cpufreq_policy *policy, + char *buf) +{ + bool hw_prefcore; + struct amd_cpudata *cpudata = policy->driver_data; + + hw_prefcore = READ_ONCE(cpudata->hw_prefcore); + + return sysfs_emit(buf, "%s\n", hw_prefcore ? "supported" : "unsupported"); +} + static ssize_t show_energy_performance_available_preferences( struct cpufreq_policy *policy, char *buf) { @@ -1037,18 +1123,27 @@ static ssize_t status_store(struct device *a, struct device_attribute *b, return ret < 0 ? ret : count; } +static ssize_t prefcore_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sysfs_emit(buf, "%s\n", amd_pstate_prefcore ? "enabled" : "disabled"); +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); cpufreq_freq_attr_ro(amd_pstate_highest_perf); +cpufreq_freq_attr_ro(amd_pstate_hw_prefcore); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); static DEVICE_ATTR_RW(status); +static DEVICE_ATTR_RO(prefcore); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, &amd_pstate_lowest_nonlinear_freq, &amd_pstate_highest_perf, + &amd_pstate_hw_prefcore, NULL, }; @@ -1056,6 +1151,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { &amd_pstate_max_freq, &amd_pstate_lowest_nonlinear_freq, &amd_pstate_highest_perf, + &amd_pstate_hw_prefcore, &energy_performance_preference, &energy_performance_available_preferences, NULL, @@ -1063,6 +1159,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { static struct attribute *pstate_global_attributes[] = { &dev_attr_status.attr, + &dev_attr_prefcore.attr, NULL }; @@ -1114,6 +1211,8 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) cpudata->cpu = policy->cpu; cpudata->epp_policy = 0; + amd_pstate_init_prefcore(cpudata); + ret = amd_pstate_init_perf(cpudata); if (ret) goto free_cpudata1; @@ -1527,7 +1626,17 @@ static int __init amd_pstate_param(char *str) return amd_pstate_set_driver(mode_idx); } + +static int __init amd_prefcore_param(char *str) +{ + if (!strcmp(str, "disable")) + amd_pstate_prefcore = false; + + return 0; +} + early_param("amd_pstate", amd_pstate_param); +early_param("amd_prefcore", amd_prefcore_param); MODULE_AUTHOR("Huang Rui "); MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver"); diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 446394f84606..87e140e9e6db 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -52,6 +52,9 @@ struct amd_aperf_mperf { * @prev: Last Aperf/Mperf/tsc count value read from register * @freq: current cpu frequency value * @boost_supported: check whether the Processor or SBIOS supports boost mode + * @hw_prefcore: check whether HW supports preferred core featue. + * Only when hw_prefcore and early prefcore param are true, + * AMD P-State driver supports preferred core featue. * @epp_policy: Last saved policy used to set energy-performance preference * @epp_cached: Cached CPPC energy-performance preference value * @policy: Cpufreq policy value @@ -81,6 +84,7 @@ struct amd_cpudata { u64 freq; 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li Subject: [PATCH V10 4/7] cpufreq: Add a notification message that the highest perf has changed Date: Mon, 30 Oct 2023 14:34:00 +0800 Message-ID: <20231030063403.3502816-5-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231030063403.3502816-1-li.meng@amd.com> References: <20231030063403.3502816-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB74:EE_|SJ2PR12MB8941:EE_ X-MS-Office365-Filtering-Correlation-Id: 49dc4ece-0bd9-4d46-ab80-08dbd912685a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: s4CynvEVHF0RBX6m6nX7fjpdUDEQGGPlPSblLnk/mQBORzo17Yy4HSQPBz5bzV3OZzo0AZ10OAss+6TTRAGxvQQfBGeTrRP32rHt3t/Ehi1dXKCq7sfqO812IGl2j9py7T5zRJjnI7x8cI1so2e3dbKII6r5Xh8xWpB0q+IstdHMiQPVoWatzQiHu7sXc9OF/Aq/zELYEVBqyy59UpElE8630a34jgcKoeBXvHW7FZwYjUrbVBNGRLDNqhKTpWkxNnhVTsz+5XgiQcqSoiUQdN2no7W6s/KYlb6vdwIbSMPTaMap4A3V7f6z9kOwdT3kAMn9RjQaQIlJMDEhbGoyIjmg7CaaMblAgMRxZJHcSr1OiAeAVpyVLRysF+U9GLPlcvyY7eTk6M3UhTrj7erFzk1JEfCOVd1++FamCY9CQmUwPrpn+58Dqcs8F+YXWPl9rMF+u6Enxy4HC61x65+xCXoFnDsmXMBxGhoCtF0qoNYqXu5r/SgvmKB+tWTtbiJHa1zd1Tv4RsQ9JhW1RZzB+dby8rYv/zj2hJWJjzNAsD6qjjFGd4iwsiyuyUlN7LR2dtEK1kSbUKWuYJClOg2Oo+HtZvgO9xEXhOmcYbyME4B3Qc71iYs5t0m7i+Tvh8LBCypFYj5wItSuFsW2IPulQr9QKQinuSTeK1kBtlLWrnEzsY3l8Psj4OD5exE+HnI06UNm6JgAUaFzAm2dmQL5Otvx+cIrUdwGH2iYnRIiw0QecGWzL5y8CFCn5D6o4WfWSZ0zGJoxIyA3qLzlGgk5OK1jEFdSB8rTv/C0ABUiwLU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(376002)(346002)(396003)(39860400002)(230922051799003)(82310400011)(186009)(1800799009)(64100799003)(451199024)(36840700001)(40470700004)(46966006)(40460700003)(2906002)(15650500001)(7416002)(5660300002)(41300700001)(4326008)(8936002)(8676002)(36756003)(40480700001)(86362001)(82740400003)(316002)(110136005)(54906003)(6636002)(36860700001)(47076005)(356005)(81166007)(70206006)(70586007)(83380400001)(426003)(1076003)(16526019)(336012)(2616005)(7696005)(966005)(478600001)(26005)(6666004)(226483002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2023 06:35:28.5999 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 49dc4ece-0bd9-4d46-ab80-08dbd912685a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB74.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8941 Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org ACPI 6.5 section 8.4.6.1.1.1 specifies that Notify event 0x85 can be emmitted to cause the the OSPM to re-evaluate the highest performance register. Add support for this event. Tested-by: Oleksandr Natalenko Reviewed-by: Mario Limonciello Reviewed-by: Huang Rui Signed-off-by: Meng Li Link: https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#processor-device-notification-values --- drivers/acpi/processor_driver.c | 6 ++++++ drivers/cpufreq/cpufreq.c | 13 +++++++++++++ include/linux/cpufreq.h | 5 +++++ 3 files changed, 24 insertions(+) diff --git a/drivers/acpi/processor_driver.c b/drivers/acpi/processor_driver.c index 4bd16b3f0781..29b2fb68a35d 100644 --- a/drivers/acpi/processor_driver.c +++ b/drivers/acpi/processor_driver.c @@ -27,6 +27,7 @@ #define ACPI_PROCESSOR_NOTIFY_PERFORMANCE 0x80 #define ACPI_PROCESSOR_NOTIFY_POWER 0x81 #define ACPI_PROCESSOR_NOTIFY_THROTTLING 0x82 +#define ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED 0x85 MODULE_AUTHOR("Paul Diefenbaugh"); MODULE_DESCRIPTION("ACPI Processor Driver"); @@ -83,6 +84,11 @@ static void acpi_processor_notify(acpi_handle handle, u32 event, void *data) acpi_bus_generate_netlink_event(device->pnp.device_class, dev_name(&device->dev), event, 0); break; + case ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED: + cpufreq_update_highest_perf(pr->id); + acpi_bus_generate_netlink_event(device->pnp.device_class, + dev_name(&device->dev), event, 0); + break; default: acpi_handle_debug(handle, "Unsupported event [0x%x]\n", event); break; diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index 4bc15634d49c..e66b040b0c61 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -2717,6 +2717,19 @@ void cpufreq_update_limits(unsigned int cpu) } EXPORT_SYMBOL_GPL(cpufreq_update_limits); +/** + * cpufreq_update_highest_perf - Update highest performance for a given CPU. + * @cpu: CPU to update the highest performance for. + * + * Invoke the driver's ->update_highest_perf callback if present + */ +void cpufreq_update_highest_perf(unsigned int cpu) +{ + if (cpufreq_driver->update_highest_perf) + cpufreq_driver->update_highest_perf(cpu); +} +EXPORT_SYMBOL_GPL(cpufreq_update_highest_perf); + /********************************************************************* * BOOST * *********************************************************************/ diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index 1c5ca92a0555..f62257b2a42f 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -235,6 +235,7 @@ int cpufreq_get_policy(struct cpufreq_policy *policy, unsigned int cpu); void refresh_frequency_limits(struct cpufreq_policy *policy); void cpufreq_update_policy(unsigned int cpu); void cpufreq_update_limits(unsigned int cpu); +void cpufreq_update_highest_perf(unsigned int cpu); bool have_governor_per_policy(void); bool cpufreq_supports_freq_invariance(void); struct kobject *get_governor_parent_kobj(struct cpufreq_policy *policy); @@ -263,6 +264,7 @@ static inline bool cpufreq_supports_freq_invariance(void) return false; } static inline void disable_cpufreq(void) { } +static inline void cpufreq_update_highest_perf(unsigned int cpu) { } #endif #ifdef CONFIG_CPU_FREQ_STAT @@ -380,6 +382,9 @@ struct cpufreq_driver { /* Called to update policy limits on firmware notifications. */ void (*update_limits)(unsigned int cpu); + /* Called to update highest performance on firmware notifications. */ + void (*update_highest_perf)(unsigned int cpu); + /* optional */ int (*bios_limit)(int cpu, unsigned int *limit); From patchwork Mon Oct 30 06:34:01 2023 Content-Type: text/plain; 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li , Wyes Karny Subject: [PATCH V10 5/7] cpufreq: amd-pstate: Update amd-pstate preferred core ranking dynamically Date: Mon, 30 Oct 2023 14:34:01 +0800 Message-ID: <20231030063403.3502816-6-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231030063403.3502816-1-li.meng@amd.com> References: <20231030063403.3502816-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB78:EE_|IA1PR12MB8079:EE_ X-MS-Office365-Filtering-Correlation-Id: 83848946-3249-4772-2799-08dbd9126b61 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0mRw208Z0nxomr0ZMyYtSBUdTQyLqvFUEuJBCTXsSt52dmeH6EN4dqb5WgVPrVKkVS7B/jfxwDemMJ5Q3oK4SHnnTx1/ZaAN0Wkle1aSSob20BOY3Txtnc1GjTsWlNSWjCFVsGq+rDzq1k9fpv4i3rYOajD6ehE9e7R7gB5E3FtVq1RsbSAKwC6CAPHUlmjvB5GJrrFw6hb5cRA3KCVRamgIU4xozNiLvaZQwMJvX9Y1Q+CXsV1vSyHc1+5knauCslIkY7qrUiiymMwZhF0knFtEz/Q4Xvh27fFd+Hdel0jX81g/LiretjG89t1vnf481jTGmsvEKJ4C2XCbfvrkzctq74rolLbFIQwafmz9M7QA3vrd4n4/YAiwrheLlkDs2KeLRGB6Q2SoRdoi39k8XwjgMs8oR3zdqwUtas/clUuxFjHTvFtQlSLz15eLgXmiqLi3DD8XdU3keZ6ZUdvJeQOCQ8RCXZKLTKOPvhOPjjNtksJUCWT1mZQX9YRQk9zWhceSO9IGBrIKklItpNTP4fOjV2Dbaltl/3wdldlc0h/i4XIf5mFqFGY5fjRXtL0LLmHqHlj2EEv67kuM+inpdOemjT9kR6tUAzWpltNGGBke9vQgj2VzmKAZUas0iBhX5mH4RnsnaPR3HbtbNL1G0s7Mh1soA4klxqNP0WSl2r7q84M/OcWAq/lByHMNOBi1vQXIMbtv2Lis8b52+ZEC+y/feHDa/8L1E1wBCZ/Lx36H5e76PDyjBzs2Tlkuk4NcGMogfeEEnuV1WhH7sizLcQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(396003)(376002)(136003)(346002)(230922051799003)(64100799003)(451199024)(1800799009)(186009)(82310400011)(36840700001)(40470700004)(46966006)(2906002)(86362001)(66899024)(41300700001)(8676002)(4326008)(8936002)(7416002)(5660300002)(15650500001)(40460700003)(36756003)(478600001)(40480700001)(47076005)(7696005)(6666004)(1076003)(81166007)(6636002)(316002)(54906003)(16526019)(110136005)(26005)(70206006)(426003)(336012)(70586007)(82740400003)(83380400001)(36860700001)(2616005)(356005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2023 06:35:33.6756 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83848946-3249-4772-2799-08dbd9126b61 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB78.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8079 Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org Preferred core rankings can be changed dynamically by the platform based on the workload and platform conditions and accounting for thermals and aging. When this occurs, cpu priority need to be set. Tested-by: Oleksandr Natalenko Reviewed-by: Mario Limonciello Reviewed-by: Wyes Karny Reviewed-by: Huang Rui Signed-off-by: Meng Li --- drivers/cpufreq/amd-pstate.c | 46 ++++++++++++++++++++++++++++++++++++ include/linux/amd-pstate.h | 6 +++++ 2 files changed, 52 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 2033e5e70017..1be33f926678 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -312,6 +312,7 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1)); WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1)); WRITE_ONCE(cpudata->lowest_perf, AMD_CPPC_LOWEST_PERF(cap1)); + WRITE_ONCE(cpudata->prefcore_ranking, AMD_CPPC_HIGHEST_PERF(cap1)); return 0; } @@ -333,6 +334,7 @@ static int cppc_init_perf(struct amd_cpudata *cpudata) WRITE_ONCE(cpudata->lowest_nonlinear_perf, cppc_perf.lowest_nonlinear_perf); WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf); + WRITE_ONCE(cpudata->prefcore_ranking, cppc_perf.highest_perf); if (cppc_state == AMD_PSTATE_ACTIVE) return 0; @@ -749,6 +751,34 @@ static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata) schedule_work(&sched_prefcore_work); } +static void amd_pstate_update_highest_perf(unsigned int cpu) +{ + struct cpufreq_policy *policy; + struct amd_cpudata *cpudata; + u32 prev_high = 0, cur_high = 0; + int ret; + + if ((!amd_pstate_prefcore) || (!cpudata->hw_prefcore)) + return; + + ret = amd_pstate_get_highest_perf(cpu, &cur_high); + if (ret) + return; + + policy = cpufreq_cpu_get(cpu); + cpudata = policy->driver_data; + prev_high = READ_ONCE(cpudata->prefcore_ranking); + + if (prev_high != cur_high) { + WRITE_ONCE(cpudata->prefcore_ranking, cur_high); + + if (cur_high < CPPC_MAX_PERF) + sched_set_itmt_core_prio((int)cur_high, cpu); + } + + cpufreq_cpu_put(policy); +} + static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; @@ -920,6 +950,17 @@ static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy, return sysfs_emit(buf, "%u\n", perf); } +static ssize_t show_amd_pstate_prefcore_ranking(struct cpufreq_policy *policy, + char *buf) +{ + u32 perf; + struct amd_cpudata *cpudata = policy->driver_data; + + perf = READ_ONCE(cpudata->prefcore_ranking); + + return sysfs_emit(buf, "%u\n", perf); +} + static ssize_t show_amd_pstate_hw_prefcore(struct cpufreq_policy *policy, char *buf) { @@ -1133,6 +1174,7 @@ cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); cpufreq_freq_attr_ro(amd_pstate_highest_perf); +cpufreq_freq_attr_ro(amd_pstate_prefcore_ranking); cpufreq_freq_attr_ro(amd_pstate_hw_prefcore); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); @@ -1143,6 +1185,7 @@ static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, &amd_pstate_lowest_nonlinear_freq, &amd_pstate_highest_perf, + &amd_pstate_prefcore_ranking, &amd_pstate_hw_prefcore, NULL, }; @@ -1151,6 +1194,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { &amd_pstate_max_freq, &amd_pstate_lowest_nonlinear_freq, &amd_pstate_highest_perf, + &amd_pstate_prefcore_ranking, &amd_pstate_hw_prefcore, &energy_performance_preference, &energy_performance_available_preferences, @@ -1491,6 +1535,7 @@ static struct cpufreq_driver amd_pstate_driver = { .suspend = amd_pstate_cpu_suspend, .resume = amd_pstate_cpu_resume, .set_boost = amd_pstate_set_boost, + .update_highest_perf = amd_pstate_update_highest_perf, .name = "amd-pstate", .attr = amd_pstate_attr, }; @@ -1505,6 +1550,7 @@ static struct cpufreq_driver amd_pstate_epp_driver = { .online = amd_pstate_epp_cpu_online, .suspend = amd_pstate_epp_suspend, .resume = amd_pstate_epp_resume, + .update_highest_perf = amd_pstate_update_highest_perf, .name = "amd-pstate-epp", .attr = amd_pstate_epp_attr, }; diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 87e140e9e6db..426822612373 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -39,11 +39,16 @@ struct amd_aperf_mperf { * @cppc_req_cached: cached performance request hints * @highest_perf: the maximum performance an individual processor may reach, * assuming ideal conditions + * For platforms that do not support the preferred core feature, the + * highest_pef may be configured with 166 or 255, to avoid max frequency + * calculated wrongly. we take the fixed value as the highest_perf. * @nominal_perf: the maximum sustained performance level of the processor, * assuming ideal operating conditions * @lowest_nonlinear_perf: the lowest performance level at which nonlinear power * savings are achieved * @lowest_perf: the absolute lowest performance level of the processor + * @prefcore_ranking: the preferred core ranking, the higher value indicates a higher + * priority. * @max_freq: the frequency that mapped to highest_perf * @min_freq: the frequency that mapped to lowest_perf * @nominal_freq: the frequency that mapped to nominal_perf @@ -73,6 +78,7 @@ struct amd_cpudata { u32 nominal_perf; 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li , Wyes Karny Subject: [PATCH V10 6/7] Documentation: amd-pstate: introduce amd-pstate preferred core Date: Mon, 30 Oct 2023 14:34:02 +0800 Message-ID: <20231030063403.3502816-7-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231030063403.3502816-1-li.meng@amd.com> References: <20231030063403.3502816-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB73:EE_|SA1PR12MB6680:EE_ X-MS-Office365-Filtering-Correlation-Id: 867c4433-cc14-4a81-8da1-08dbd9126ebc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: x1BrHWTNp5VXafcUwA/Ap9qFpFWgpRFG8YHT4bdFBMVMHzZqMP7+g7HqsDqGNiP9ifvM07R+3CGrQsH0YrS0clGLcymLZpel9v9yaOrKwJJXiXzdI+yChl9To7JgypsTAvgtK1IeL7JtRqoPz3GrCpDOMPt+pR3KiZaQktX8ly4Rv0iiupbH1w3BWkvBTNZbuBvb1VUAWhzRyE5lB2ezciwcCFJPN7XyO1u0RJKnCOsLOKEYfisg05vQZoSPajR2rUc4LmIMIZc4rSGiQyDCNbVg2p2FsceeqwlodXhANENVHgt8BS3k+jm5cWziTg5BVHW/1n8sWZCvIhN8V68H5NBsk9FNIlEJPwj87L83pqWe2teBTZkD7k/PaDZjuxndBL9q2+gGDxV6Qy7WklQibWzXDs1X5poh2L/b0c+emnyAEq+Cia9tiCEeCCojLTHu2GQWvA3bnPgZyKKJJ1aRVGKpPS+2fYQUHnECz0eV5W6TyoZ5gE4LmhUEm+QJp3ve3RIkGIrvArZGRxxjHqN87tEFTj+hiEa2UDgv7JjtnenJilVniEFF845NgtWySCCwUERe0WJUxPoY4oFsJzZD791PyTWVzhbpoL8kQfsrfso179H58PKCCnoU/yVZxOXtf0SlOR5rRSScpsmLv+3mH+nx2bETgzTdO0UlYNzsiAvKJ+TUu9pbEFlFLLNiI2KR5wF5WTFGnYhh+/axDl++ViWX75nIz//x8Cu3aHmzGu/4UGfB36jANjLin9i+l2TDpU11gy0LMPei3zfDS/MAZA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(136003)(376002)(39860400002)(396003)(230922051799003)(82310400011)(186009)(1800799009)(451199024)(64100799003)(40470700004)(46966006)(36840700001)(5660300002)(40460700003)(7416002)(81166007)(356005)(86362001)(47076005)(82740400003)(336012)(426003)(1076003)(16526019)(26005)(83380400001)(7696005)(36756003)(478600001)(6666004)(2616005)(36860700001)(40480700001)(2906002)(70586007)(70206006)(110136005)(41300700001)(8676002)(6636002)(316002)(54906003)(8936002)(4326008)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2023 06:35:39.3077 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 867c4433-cc14-4a81-8da1-08dbd9126ebc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB73.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6680 Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org Introduce amd-pstate preferred core. check preferred core state set by the kernel parameter: $ cat /sys/devices/system/cpu/amd-pstate/prefcore Tested-by: Oleksandr Natalenko Reviewed-by: Wyes Karny Reviewed-by: Mario Limonciello Reviewed-by: Huang Rui Signed-off-by: Meng Li --- Documentation/admin-guide/pm/amd-pstate.rst | 59 ++++++++++++++++++++- 1 file changed, 57 insertions(+), 2 deletions(-) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 1cf40f69278c..0b832ff529db 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -300,8 +300,8 @@ platforms. The AMD P-States mechanism is the more performance and energy efficiency frequency management method on AMD processors. -AMD Pstate Driver Operation Modes -================================= +``amd-pstate`` Driver Operation Modes +====================================== ``amd_pstate`` CPPC has 3 operation modes: autonomous (active) mode, non-autonomous (passive) mode and guided autonomous (guided) mode. @@ -353,6 +353,48 @@ is activated. In this mode, driver requests minimum and maximum performance level and the platform autonomously selects a performance level in this range and appropriate to the current workload. +``amd-pstate`` Preferred Core +================================= + +The core frequency is subjected to the process variation in semiconductors. +Not all cores are able to reach the maximum frequency respecting the +infrastructure limits. Consequently, AMD has redefined the concept of +maximum frequency of a part. This means that a fraction of cores can reach +maximum frequency. To find the best process scheduling policy for a given +scenario, OS needs to know the core ordering informed by the platform through +highest performance capability register of the CPPC interface. + +``amd-pstate`` preferred core enables the scheduler to prefer scheduling on +cores that can achieve a higher frequency with lower voltage. The preferred +core rankings can dynamically change based on the workload, platform conditions, +thermals and ageing. + +The priority metric will be initialized by the ``amd-pstate`` driver. The ``amd-pstate`` +driver will also determine whether or not ``amd-pstate`` preferred core is +supported by the platform. + +``amd-pstate`` driver will provide an initial core ordering when the system boots. +The platform uses the CPPC interfaces to communicate the core ranking to the +operating system and scheduler to make sure that OS is choosing the cores +with highest performance firstly for scheduling the process. When ``amd-pstate`` +driver receives a message with the highest performance change, it will +update the core ranking and set the cpu's priority. + +``amd-pstate`` Preferred Core Switch +================================= +Kernel Parameters +----------------- + +``amd-pstate`` peferred core`` has two states: enable and disable. +Enable/disable states can be chosen by different kernel parameters. +Default enable ``amd-pstate`` preferred core. + +``amd_prefcore=disable`` + +For systems that support ``amd-pstate`` preferred core, the core rankings will +always be advertised by the platform. But OS can choose to ignore that via the +kernel parameter ``amd_prefcore=disable``. + User Space Interface in ``sysfs`` - General =========================================== @@ -385,6 +427,19 @@ control its functionality at the system level. They are located in the to the operation mode represented by that string - or to be unregistered in the "disable" case. +``prefcore`` + Preferred core state of the driver: "enabled" or "disabled". + + "enabled" + Enable the ``amd-pstate`` preferred core. + + "disabled" + Disable the ``amd-pstate`` preferred core + + + This attribute is read-only to check the state of preferred core set + by the kernel parameter. + ``cpupower`` tool support for ``amd-pstate`` =============================================== From patchwork Mon Oct 30 06:34:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Meng, Li (Jassmine)" X-Patchwork-Id: 13440042 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B089C4167D for ; Mon, 30 Oct 2023 06:36:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231741AbjJ3GgN (ORCPT ); Mon, 30 Oct 2023 02:36:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231814AbjJ3Gf6 (ORCPT ); Mon, 30 Oct 2023 02:35:58 -0400 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2081.outbound.protection.outlook.com [40.107.223.81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 002F9D3; Sun, 29 Oct 2023 23:35:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=bjCR0SzIphwvaDz6GBy7vLI7H/VQUCWRuDi05Vk0J1ETUyWiGRbeImXEY8AkVTxo0nRKmeE++cMttQV1dLNOw7kwTfgpMRCH3kPhf9x6+8N76eoTdAPKqEBiNdO7W7aW1APytgmCPXPBfRF0jPH2AdFFzE245Y7YbqXMYIfCW3YOYwl6jIoIrhttdI80aEttvriCQwhcrL5YGwtTUcZnQ1NAvjZeffI4f+i+iSmn7ShS8trXtmJyFep0ZIWZLGjxV8jo5/YG7LhJsVSKe8YkG9sgdVPWp2ZxzqjeSdZOk+HqjeLx4xGRUIf9SAfwK2gEaSff/nW26gOZrUSDE9+D+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3BATVT8xDKQmxK5ddKWQeikq5vTddHGyEfuh2meRohc=; b=kc3BiW0Yqw379D2H0icN73tcK5tMJzcSozElFwNznsRvVgMKYaqpIkXa6PKni6wO/cbmYxQJuMTNOe4rmdhjoGJ9fLyUL4rhHYIEccSVc8QlsyzZ/VCuJe5HuH70HLFbZafV7b2NTBe+YSIArQSPvlpU/O4pAlKwJ3/+UxGDWTDUY7REOzhVKD7lhB12zM0fHjsywsN/LbnNSFRn8YAJWNbua0TEltt6uRa6QJxWwuL7XT7vll0eQ6/RJHMM07qZI4181/1vfZ/k/mz+7pghmEdm7Jc5QEdWUGSIJMUQDtB/5mxp57KppCKHhQoUO7PX/fhbJbV833wd09Tjq0A5GQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=intel.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3BATVT8xDKQmxK5ddKWQeikq5vTddHGyEfuh2meRohc=; b=S/yCjRB3v+MHvOZrsc20vzKm8dgusK0roVvW3xce75qfCUUc6KfKzKV7JKQ7LBirsRHE3TJqGcohELPIvmrKnwWZZy03ZlK7uZj2XDVW2W0Z3noag8txS611b52eDmpANm6NTduTdXmMrhpqbjP5k1+hJoA0InZ6GWG4xFvd7D0= Received: from BL1PR13CA0087.namprd13.prod.outlook.com (2603:10b6:208:2b8::32) by PH0PR12MB7790.namprd12.prod.outlook.com (2603:10b6:510:289::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6933.25; Mon, 30 Oct 2023 06:35:44 +0000 Received: from BL6PEPF0001AB78.namprd02.prod.outlook.com (2603:10b6:208:2b8:cafe::e6) by BL1PR13CA0087.outlook.office365.com (2603:10b6:208:2b8::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6954.15 via Frontend Transport; Mon, 30 Oct 2023 06:35:43 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB78.mail.protection.outlook.com (10.167.242.171) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6933.15 via Frontend Transport; Mon, 30 Oct 2023 06:35:43 +0000 Received: from jasmine-meng.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Mon, 30 Oct 2023 01:35:38 -0500 From: Meng Li To: "Rafael J . Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li , Wyes Karny Subject: [PATCH V10 7/7] Documentation: introduce amd-pstate preferrd core mode kernel command line options Date: Mon, 30 Oct 2023 14:34:03 +0800 Message-ID: <20231030063403.3502816-8-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231030063403.3502816-1-li.meng@amd.com> References: <20231030063403.3502816-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB78:EE_|PH0PR12MB7790:EE_ X-MS-Office365-Filtering-Correlation-Id: d2ffeb8c-0822-4f34-eba1-08dbd912714f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: o3PXIWQaIP6cw1g/cWry3rmRTyho5edsRoQ3A+jFzuC9CEJ8FGpAmZRRsl62qJEtoZq2rWYABXEfwj2jrCVF1XTEjkfCwQp9mtRAA+LpG1kQ2AINWrgtJN/p2E1V22nKfdy7Ka5W4zlwGA1FzByjU2qbBZmpEIDnr4y9hX5R03SySipbPXsrKRHOYOln1im6s0EyvS6pC1eJ2ZJtp7+7riVpFLkF9j1+zZk4OzgW2E4ir7Kph2a0hVfGazP+UF7um9XWZ9nRywKiNE5YLba3KCECdu3hnO/4SLEX5pk/XgUc2gs3vl9rzEYlV1uwU/3Z5EzzNGwlr8+pBUV65Cvsg53oMGLIQ77tYnF3hubj2Dlo0X8oYW9QcNNdoM7TBsuduidlGAbglVdLnsyInQfGg1MPD3+AwRfAuNoqnb7HS622/9NCNP6mrIP0qoYkhScF9Nig+HMyDujgfcQaPK/XlJacEKBHTsXGEOh9dRSPNER/Mdwn4owCf1ZV1PZDoqQ9Ctj4UStkvhcDi7XzTjHL3ZKt3RniSVk9ylrgEBSknw53eYNBVWuFEgHkmG6Z7oep5Blo/Sa5pv/96jTetfH76NyBCy8/Ot/+vqLy5sJfRKJ44PHUUD/c0whQKjDfqixziReODehJF/H77/Vi1HueLF21Sx2OFnzpt/Il4Xntu8daVQEMF7Qfs1aIjPZeFHDwNE2SzvO7heSTmxtbXWaA4i/2o1oqeFAJCUeR7LZE6XAxWHsg30WSNwoszSY52V909gqVeOOj77+KY+b9OjZUYaPFv6Tz4YnhXo/VMV3Kxw/HYXOWJs+VqFU1rRq0j8nw X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(39860400002)(376002)(396003)(136003)(230922051799003)(82310400011)(451199024)(186009)(64100799003)(1800799009)(36840700001)(40470700004)(46966006)(1076003)(26005)(16526019)(2616005)(336012)(83380400001)(478600001)(6666004)(47076005)(7696005)(36860700001)(426003)(7416002)(5660300002)(2906002)(41300700001)(110136005)(70206006)(70586007)(8936002)(8676002)(6636002)(4326008)(316002)(54906003)(40460700003)(356005)(82740400003)(81166007)(36756003)(86362001)(40480700001)(36900700001)(14943795004);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2023 06:35:43.6290 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d2ffeb8c-0822-4f34-eba1-08dbd912714f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB78.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7790 Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org amd-pstate driver support enable/disable preferred core. Default enabled on platforms supporting amd-pstate preferred core. Disable amd-pstate preferred core with "amd_prefcore=disable" added to the kernel command line. Signed-off-by: Meng Li Reviewed-by: Mario Limonciello Reviewed-by: Wyes Karny Reviewed-by: Huang Rui Tested-by: Oleksandr Natalenko --- Documentation/admin-guide/kernel-parameters.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 0a1731a0f0ef..e35b795aa8aa 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -363,6 +363,11 @@ selects a performance level in this range and appropriate to the current workload. + amd_prefcore= + [X86] + disable + Disable amd-pstate preferred core. + amijoy.map= [HW,JOY] Amiga joystick support Map of devices attached to JOY0DAT and JOY1DAT Format: ,