From patchwork Tue Oct 31 09:29:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13441331 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DA9213AF0 for ; Tue, 31 Oct 2023 09:21:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="B8h1ZqJ5" Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FD9CDA; Tue, 31 Oct 2023 02:21:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698744110; x=1730280110; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=y4GdVfvr4r3TS2jPrXzPuftPnG1qKJX1nHclPM7uF4Y=; b=B8h1ZqJ5LJ0kXzUMbyieDxzE9uMPKbngWyyUyqaj7szBaKtFugZH9mWO GemQSRSQ+SeK+sIunqhrZdDfZboNE+D8NWuY1cMzyFu0AWA3P++XJ3Vem 53rVh1A8d0fo57ASxEFGTg8G/+5X6MRfH+jWsQr9TsdiFuu7EznvyuSUb IyWwjruBB615rYVFCWqk+DIXDrayEqYIT3K1GJJOMrlSVfDQ3fh/MHgXZ loOY7HHRT3qZCAFeFd7ZKSHqjY/aTqd3u/QaUH9Aea67ZtA7NZ2J1aDkU MG78U9iNpoHej9IT3hzbuHdu2qOWO+0zY7YeGj+H6fHQAJGps3+q7wpTm g==; X-IronPort-AV: E=McAfee;i="6600,9927,10879"; a="385435956" X-IronPort-AV: E=Sophos;i="6.03,265,1694761200"; d="scan'208";a="385435956" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Oct 2023 02:21:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10879"; a="877445519" X-IronPort-AV: E=Sophos;i="6.03,265,1694761200"; d="scan'208";a="877445519" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by fmsmga002.fm.intel.com with ESMTP; 31 Oct 2023 02:21:47 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Jim Mattson , Mingwei Zhang , Like Xu , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v2 1/5] x86: pmu: Remove duplicate code in pmu_init() Date: Tue, 31 Oct 2023 17:29:17 +0800 Message-Id: <20231031092921.2885109-2-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231031092921.2885109-1-dapeng1.mi@linux.intel.com> References: <20231031092921.2885109-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Xiong Zhang There are totally same code in pmu_init() helper, remove the duplicate code. Signed-off-by: Xiong Zhang Signed-off-by: Dapeng Mi Reviewed-by: Jim Mattson --- lib/x86/pmu.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/lib/x86/pmu.c b/lib/x86/pmu.c index 0f2afd650bc9..d06e94553024 100644 --- a/lib/x86/pmu.c +++ b/lib/x86/pmu.c @@ -16,11 +16,6 @@ void pmu_init(void) pmu.fixed_counter_width = (cpuid_10.d >> 5) & 0xff; } - if (pmu.version > 1) { - pmu.nr_fixed_counters = cpuid_10.d & 0x1f; - pmu.fixed_counter_width = (cpuid_10.d >> 5) & 0xff; - } - pmu.nr_gp_counters = (cpuid_10.a >> 8) & 0xff; pmu.gp_counter_width = (cpuid_10.a >> 16) & 0xff; pmu.gp_counter_mask_length = (cpuid_10.a >> 24) & 0xff; From patchwork Tue Oct 31 09:29:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13441332 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 686B815EB6 for ; Tue, 31 Oct 2023 09:21:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="VFYiVkBm" Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78978B7; Tue, 31 Oct 2023 02:21:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698744113; x=1730280113; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JgrwofphKXeC1nxCQjenJBStSCQKow/wnGaMmvGi9t4=; b=VFYiVkBmBGD8kRqe+DrujLEQl94s4282pp2UDRfP6B+mCP3LPo4tEcEV LW5hdXni+qVAErm3OdSN23R2sk5rMjNhHsuYjAktL4i2G5Kk/Gs3S4Vuq ZzOjPX5QCUDdHQTj2/8dD8Nx0BgwdZZXFCLbMoZyz//YBH8dsrWa3rzDI rKwO/vt4e7nz8LdJ8wzyVZ76dG+PICJrJiAEcHHkVieSknL/7vMPJLU1t 32JCw1K3H0cDiVxXy52XguuwVxMzhIHfjogyQr2fMoQNr9f9WzDkJx0AT +z5rzr3FuZjECeNXboDWwZ0ZODTX86w5iwb+k4fu2g3W+z/g6RXPk5oGg A==; X-IronPort-AV: E=McAfee;i="6600,9927,10879"; a="385435968" X-IronPort-AV: E=Sophos;i="6.03,265,1694761200"; d="scan'208";a="385435968" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Oct 2023 02:21:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10879"; a="877445524" X-IronPort-AV: E=Sophos;i="6.03,265,1694761200"; d="scan'208";a="877445524" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by fmsmga002.fm.intel.com with ESMTP; 31 Oct 2023 02:21:50 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Jim Mattson , Mingwei Zhang , Like Xu , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v2 2/5] x86: pmu: Improve loop() to force to generate llc/branch misses Date: Tue, 31 Oct 2023 17:29:18 +0800 Message-Id: <20231031092921.2885109-3-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231031092921.2885109-1-dapeng1.mi@linux.intel.com> References: <20231031092921.2885109-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Current loop() helper is a very simple adding loop function, it can't garantee that LLC misses and branch misses would be always triggered in the loop() running, especailly along with the larger and larger LLC size and better and better branch predictor in new CPUs. In this situation 0 LLC/branch misses count would be seen more and more easily just like what we see on Sapphire Rapids. It's ambiguous to take 0 as a valid result in tests since we can't confirm if the PMU function works correctly or it's just disabled. So this patch improves current loop() function and introduces random jump and clflush instructions to force to generate LLC and branch misses. Since random jump and clflush instructions are involved, all pre-defined valid count ranges are also update accordingly. Signed-off-by: Dapeng Mi --- x86/pmu.c | 41 +++++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 0def28695c70..1df5794b7ef8 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -11,7 +11,7 @@ #include "libcflat.h" #include -#define N 1000000 +#define N 1000000ULL // These values match the number of instructions and branches in the // assembly block in check_emulated_instr(). @@ -28,25 +28,25 @@ typedef struct { struct pmu_event { const char *name; uint32_t unit_sel; - int min; - int max; + uint64_t min; + uint64_t max; } intel_gp_events[] = { - {"core cycles", 0x003c, 1*N, 50*N}, + {"core cycles", 0x003c, 1*N, 500*N}, {"instructions", 0x00c0, 10*N, 10.2*N}, - {"ref cycles", 0x013c, 1*N, 30*N}, - {"llc references", 0x4f2e, 1, 2*N}, - {"llc misses", 0x412e, 1, 1*N}, - {"branches", 0x00c4, 1*N, 1.1*N}, - {"branch misses", 0x00c5, 0, 0.1*N}, + {"ref cycles", 0x013c, 1*N, 300*N}, + {"llc references", 0x4f2e, 0.1*N, 2*N}, + {"llc misses", 0x412e, 0.1*N, 1*N}, + {"branches", 0x00c4, 3*N, 3.3*N}, + {"branch misses", 0x00c5, 0.1*N, 0.3*N}, }, amd_gp_events[] = { - {"core cycles", 0x0076, 1*N, 50*N}, + {"core cycles", 0x0076, 1*N, 500*N}, {"instructions", 0x00c0, 10*N, 10.2*N}, - {"branches", 0x00c2, 1*N, 1.1*N}, - {"branch misses", 0x00c3, 0, 0.1*N}, + {"branches", 0x00c2, 3*N, 3.3*N}, + {"branch misses", 0x00c3, 0.1*N, 0.3*N}, }, fixed_events[] = { {"fixed 1", MSR_CORE_PERF_FIXED_CTR0, 10*N, 10.2*N}, - {"fixed 2", MSR_CORE_PERF_FIXED_CTR0 + 1, 1*N, 30*N}, - {"fixed 3", MSR_CORE_PERF_FIXED_CTR0 + 2, 0.1*N, 30*N} + {"fixed 2", MSR_CORE_PERF_FIXED_CTR0 + 1, 1*N, 500*N}, + {"fixed 3", MSR_CORE_PERF_FIXED_CTR0 + 2, 0.1*N, 300*N}, }; char *buf; @@ -56,10 +56,15 @@ static unsigned int gp_events_size; static inline void loop(void) { - unsigned long tmp, tmp2, tmp3; + unsigned long tmp, tmp2, tmp3, tmp4; - asm volatile("1: mov (%1), %2; add $64, %1; nop; nop; nop; nop; nop; nop; nop; loop 1b" - : "=c"(tmp), "=r"(tmp2), "=r"(tmp3): "0"(N), "1"(buf)); + asm volatile("1: dec %0; jz 3f; mov (%1), %2; add $64, %1; nop; \n" + " rdrand %3; and $7, %3; jnz 2f; clflush (%1); jmp 1b\n" + "2: nop; jmp 1b;" + "3: nop" + : "=c"(tmp), "=r"(tmp2), "=r"(tmp3), "=r"(tmp4) + : "0"(N), "1"(buf) + : "memory"); } @@ -202,7 +207,7 @@ static noinline void __measure(pmu_counter_t *evt, uint64_t count) static bool verify_event(uint64_t count, struct pmu_event *e) { - // printf("%d <= %ld <= %d\n", e->min, count, e->max); + // printf("%ld <= %ld <= %ld\n", e->min, count, e->max); return count >= e->min && count <= e->max; } From patchwork Tue Oct 31 09:29:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13441333 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8813D182A4 for ; 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a="385435973" X-IronPort-AV: E=Sophos;i="6.03,265,1694761200"; d="scan'208";a="385435973" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Oct 2023 02:21:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10879"; a="877445527" X-IronPort-AV: E=Sophos;i="6.03,265,1694761200"; d="scan'208";a="877445527" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by fmsmga002.fm.intel.com with ESMTP; 31 Oct 2023 02:21:53 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Jim Mattson , Mingwei Zhang , Like Xu , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v2 3/5] x86: pmu: Enlarge cnt array length to 64 in check_counters_many() Date: Tue, 31 Oct 2023 17:29:19 +0800 Message-Id: <20231031092921.2885109-4-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231031092921.2885109-1-dapeng1.mi@linux.intel.com> References: <20231031092921.2885109-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Considering there are already 8 GP counters and 4 fixed counters on latest Intel CPUs, like Sapphire Rapids. The original cnt array length 10 is definitely not enough to cover all supported PMU counters on these new CPUs and it would cause PMU counter validation failures. It's probably more and more GP and fixed counters are introduced in the future and then directly extends the cnt array length to 64. Signed-off-by: Dapeng Mi --- x86/pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/x86/pmu.c b/x86/pmu.c index 1df5794b7ef8..6bd8f6d53f55 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -259,7 +259,7 @@ static void check_fixed_counters(void) static void check_counters_many(void) { - pmu_counter_t cnt[10]; + pmu_counter_t cnt[64]; int i, n; for (i = 0, n = 0; n < pmu.nr_gp_counters; i++) { From patchwork Tue Oct 31 09:29:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13441334 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00BAB18C29 for ; Tue, 31 Oct 2023 09:22:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Ng6mG7EJ" Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D77E110; Tue, 31 Oct 2023 02:21:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698744119; x=1730280119; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hGJvfX2hIKMvWkOHT5amNhhbAWNGgZop9FcOLKuXuaA=; b=Ng6mG7EJ4znXJ+IDS1nfquItUA+grbWRFMielJRLsPj/K6+x8rm9Ztw2 rVvi50cEyUfdVcEtkLmuBBfzg/eoXZvZl+9DZlrKKU/JpwPar892mWq3U B4Rmh4AN2B1FA1xhSAqqqM3kmcacUmNCSymaIDoFx7ZG28S9gV/csx60d 4sx9Ro62HOJY7kRXBGLtrMg4uI2hO9cFMmGTC51DXf7CqIl9qPDyo9/po I1EXWRMCoK/huf1HnABjbvw+Ke7kakRBqee9IKth9vaBjXYp5UIJTWgo3 ZOsVdRl4V5ZE042yd67F5C3FW1BE9FuzKb1NhBB1wgG7pvgRyO+BleGF8 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10879"; a="385435983" X-IronPort-AV: E=Sophos;i="6.03,265,1694761200"; d="scan'208";a="385435983" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Oct 2023 02:21:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10879"; a="877445531" X-IronPort-AV: E=Sophos;i="6.03,265,1694761200"; d="scan'208";a="877445531" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by fmsmga002.fm.intel.com with ESMTP; 31 Oct 2023 02:21:55 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Jim Mattson , Mingwei Zhang , Like Xu , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v2 4/5] x86: pmu: Support validation for Intel PMU fixed counter 3 Date: Tue, 31 Oct 2023 17:29:20 +0800 Message-Id: <20231031092921.2885109-5-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231031092921.2885109-1-dapeng1.mi@linux.intel.com> References: <20231031092921.2885109-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Intel CPUs, like Sapphire Rapids, introduces a new fixed counter (fixed counter 3) to counter/sample topdown.slots event, but current code still doesn't cover this new fixed counter. So this patch adds code to validate this new fixed counter can count slots event correctly. Signed-off-by: Dapeng Mi --- x86/pmu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/x86/pmu.c b/x86/pmu.c index 6bd8f6d53f55..404dc7b62ac2 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -47,6 +47,7 @@ struct pmu_event { {"fixed 1", MSR_CORE_PERF_FIXED_CTR0, 10*N, 10.2*N}, {"fixed 2", MSR_CORE_PERF_FIXED_CTR0 + 1, 1*N, 500*N}, {"fixed 3", MSR_CORE_PERF_FIXED_CTR0 + 2, 0.1*N, 300*N}, + {"fixed 4", MSR_CORE_PERF_FIXED_CTR0 + 3, 1*N, 5000*N}, }; char *buf; From patchwork Tue Oct 31 09:29:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13441335 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04438199A9 for ; Tue, 31 Oct 2023 09:22:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="KNM+3pQn" Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E16ACB7; Tue, 31 Oct 2023 02:22:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698744121; x=1730280121; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PuCRcyvXo/0paorC4geEOaVKWI0b7CqKhedXiIXoy0A=; b=KNM+3pQnGpmUUNQuHOdJcxhEJDaYVJgfWRz9AWWnmosWzV4A0ehXWcI/ lTcQ7n0+M5pnMKJBkf7mAKGCvzPElMZkNpf5A9oZyhQsxywtri3MP8CXR k+90mWDkWu3TC4irj/W8bzCV+I2k/DHt5GPwcdHwI79hTSZAfusPp/HyN PW/VWy8IGJjj6uj0A3mLEhTsllOP8qkA/F5oCa4zIVLB4aeMhtaNtTJMv ER38hCNC5tuW4J9Vl35gLh/DUYqMexeTcluHlsSHkjBrOuOgz7f7D9ZQX u5wKjKuiKo+1MBhBytx85ub/awqH/MP194ZIgD+flMns1Ibf4ouBRS9Rl Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10879"; a="385435997" X-IronPort-AV: E=Sophos;i="6.03,265,1694761200"; d="scan'208";a="385435997" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Oct 2023 02:22:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10879"; a="877445536" X-IronPort-AV: E=Sophos;i="6.03,265,1694761200"; d="scan'208";a="877445536" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by fmsmga002.fm.intel.com with ESMTP; 31 Oct 2023 02:21:58 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Jim Mattson , Mingwei Zhang , Like Xu , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v2 5/5] x86: pmu: Add asserts to warn inconsistent fixed events and counters Date: Tue, 31 Oct 2023 17:29:21 +0800 Message-Id: <20231031092921.2885109-6-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231031092921.2885109-1-dapeng1.mi@linux.intel.com> References: <20231031092921.2885109-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Current PMU code doesn't check whether the number of fixed counters is larger than pre-defined fixed events. If so, it would cause out of range memory access. So add asserts to warn this invalid case. Signed-off-by: Dapeng Mi --- x86/pmu.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 404dc7b62ac2..3ce05f0a1d38 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -117,8 +117,12 @@ static struct pmu_event* get_counter_event(pmu_counter_t *cnt) for (i = 0; i < gp_events_size; i++) if (gp_events[i].unit_sel == (cnt->config & 0xffff)) return &gp_events[i]; - } else - return &fixed_events[cnt->ctr - MSR_CORE_PERF_FIXED_CTR0]; + } else { + int idx = cnt->ctr - MSR_CORE_PERF_FIXED_CTR0; + + assert(idx < ARRAY_SIZE(fixed_events)); + return &fixed_events[idx]; + } return (void*)0; } @@ -251,6 +255,7 @@ static void check_fixed_counters(void) }; int i; + assert(pmu.nr_fixed_counters <= ARRAY_SIZE(fixed_events)); for (i = 0; i < pmu.nr_fixed_counters; i++) { cnt.ctr = fixed_events[i].unit_sel; measure_one(&cnt); @@ -272,6 +277,7 @@ static void check_counters_many(void) gp_events[i % gp_events_size].unit_sel; n++; } + assert(pmu.nr_fixed_counters <= ARRAY_SIZE(fixed_events)); for (i = 0; i < pmu.nr_fixed_counters; i++) { cnt[n].ctr = fixed_events[i].unit_sel; cnt[n].config = EVNTSEL_OS | EVNTSEL_USR;