From patchwork Mon Nov 13 00:55:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13453426 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 351E0C4167B for ; Mon, 13 Nov 2023 01:07:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=wRx5b9fjhhBngv41WFFoV0AeFQaNiCI8W0y7c4mg0o0=; b=ljgPxzrM3S6K6+ Feqch0DPZJlMJiPuqDcYchWRYJFX4ZnzCHNxaGc3zHhBnD9KT9uvw6uiKEJ5nq2fUahC/QuQn9rM3 nD2VzqextlUfwxTZfY2efnsCqip51UwvejlGn0zTmoMjyxtPgzpJeUCcChyzy77UQUKBZVXUEcC0l qUHznpY5hgEawyDUgLNiUkwF6fytosWX9w8gSQYzRXk+Y13zHqZy2Rq4qbu01utXRX8BJf8SpXlnn woljdjDOk8GMiXrqVTlBRCjCID16tW+xie4qcwPxGmlqcrfbOzYtiZOviIJPoTyP+lz8VYMlLTJWF EYHYLWyvnGAozXHk5PzQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r2LQV-00Cxmw-04; Mon, 13 Nov 2023 01:07:43 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r2LQR-00Cxlr-38 for linux-riscv@lists.infradead.org; Mon, 13 Nov 2023 01:07:41 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by ams.source.kernel.org (Postfix) with ESMTP id D159AB80B25; Mon, 13 Nov 2023 01:07:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id ECE9BC433CA; Mon, 13 Nov 2023 01:07:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699837656; bh=H7qZuoiU0EG1cjpw3AoWWtXlkPPaLWyV/VdLiSuYwKQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WEGavzlSqYp4rVqws4gzgtTZWf+llaZy8xr/W+HFUIYhnXD0SSrllI+QfYOTUB0RZ hcRiO061sNLZCYXunsxINP6D/gtTOzeO8baaokilbp6XR+BmovWyoQaVfyIjDSCZc0 0yUMwvN7Ci201OFB61kN6zl3J+bBtr6jamxWQJRpT7WI7dWKbZWSd4UM5e5j7NfUoi 5HlgkvZDIG6GdbWVHTNVGl0/JGTmxSyBAg5OAL5X5j5VrOpsZDoMDH1Vk2imUflUKe wAnjFx6kMMfHN9kBTmRPRq2aRggxr6Hrdx4+C6cGKQ32+Yt0rFTGjH6UHIvq9spPYb +LhSwHdFw6KsQ== From: Jisheng Zhang To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Chao Wei , Chen Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 1/4] dt-bindings: reset: Add binding for Sophgo CV1800B reset controller Date: Mon, 13 Nov 2023 08:55:00 +0800 Message-Id: <20231113005503.2423-2-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20231113005503.2423-1-jszhang@kernel.org> References: <20231113005503.2423-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231112_170740_322858_63E29268 X-CRM114-Status: GOOD ( 12.83 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add devicetree binding for Sophgo CV1800B SoC reset controller. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley --- .../bindings/reset/sophgo,cv1800b-reset.yaml | 38 ++++++++ .../dt-bindings/reset/sophgo,cv1800b-reset.h | 96 +++++++++++++++++++ 2 files changed, 134 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/sophgo,cv1800b-reset.yaml create mode 100644 include/dt-bindings/reset/sophgo,cv1800b-reset.h +#endif /* _DT_BINDINGS_CV1800B_RESET_H */ diff --git a/Documentation/devicetree/bindings/reset/sophgo,cv1800b-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,cv1800b-reset.yaml new file mode 100644 index 000000000000..20a525147490 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/sophgo,cv1800b-reset.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/sophgo,cv1800b-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo CV1800B SoC Reset Controller + +maintainers: + - Jisheng Zhang + +properties: + compatible: + enum: + - sophgo,cv1800b-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + reset-controller@3003000 { + compatible = "sophgo,cv1800b-reset"; + reg = <0x03003000 0x1000>; + #reset-cells = <1>; + }; + +... diff --git a/include/dt-bindings/reset/sophgo,cv1800b-reset.h b/include/dt-bindings/reset/sophgo,cv1800b-reset.h new file mode 100644 index 000000000000..28dda71369b4 --- /dev/null +++ b/include/dt-bindings/reset/sophgo,cv1800b-reset.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved. + * Copyright (C) 2023 Jisheng Zhang + */ + +#ifndef _DT_BINDINGS_CV1800B_RESET_H +#define _DT_BINDINGS_CV1800B_RESET_H + +/* 0-1 */ +#define RST_DDR 2 +#define RST_H264C 3 +#define RST_JPEG 4 +#define RST_H265C 5 +#define RST_VIPSYS 6 +#define RST_TDMA 7 +#define RST_TPU 8 +#define RST_TPUSYS 9 +/* 10 */ +#define RST_USB 11 +#define RST_ETH0 12 +/* 13 */ +#define RST_NAND 14 +/* 15 */ +#define RST_SD0 16 +/* 17 */ +#define RST_SDMA 18 +#define RST_I2S0 19 +#define RST_I2S1 20 +#define RST_I2S2 21 +#define RST_I2S3 22 +#define RST_UART0 23 +#define RST_UART1 24 +#define RST_UART2 25 +#define RST_UART3 26 +#define RST_I2C0 27 +#define RST_I2C1 28 +#define RST_I2C2 29 +#define RST_I2C3 30 +#define RST_I2C4 31 +#define RST_PWM0 32 +#define RST_PWM1 33 +#define RST_PWM2 34 +#define RST_PWM3 35 +/* 36-39 */ +#define RST_SPI0 40 +#define RST_SPI1 41 +#define RST_SPI2 42 +#define RST_SPI3 43 +#define RST_GPIO0 44 +#define RST_GPIO1 45 +#define RST_GPIO2 46 +#define RST_EFUSE 47 +#define RST_WDT 48 +#define RST_AHBRST_ROM 49 +#define RST_SPIC 50 +#define RST_TEMPSEN 51 +#define RST_SARADC 52 +/* 53-57 */ +#define RST_COMBORST_PHY0 58 +/* 59-60 */ +#define RST_SPIRST_NAND 61 +#define RST_SE 62 +/* 63-73 */ +#define RST_UART4 74 +#define RST_GPIO3 75 +#define RST_SYSTEM 76 +#define RST_TIMER 77 +#define RST_TIMER0 78 +#define RST_TIMER1 79 +#define RST_TIMER2 80 +#define RST_TIMER3 81 +#define RST_TIMER4 82 +#define RST_TIMER5 83 +#define RST_TIMER6 84 +#define RST_TIMER7 85 +#define RST_WGN0 86 +#define RST_WGN1 87 +#define RST_WGN2 88 +#define RST_KEYSCAN 89 +/* 90 */ +#define RST_AUDDAC 91 +#define RST_AUDDACRST_APB 92 +#define RST_AUDADC 93 +/* 94 */ +#define RST_VCSYS 95 +#define RST_ETHPHY 96 +#define RST_ETHPHYRST_APB 97 +#define RST_AUDSRC 98 +#define RST_VIP_CAM0 99 +#define RST_WDT1 100 +#define RST_WDT2 101 +/* 102-292 */ +#define RST_CPUSYS1 293 +#define RST_CPUSYS2 294 + From patchwork Mon Nov 13 00:55:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13453427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4EFFAC4332F for ; Mon, 13 Nov 2023 01:07:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=05TlOHy08/3hWFGhB6xlJ9agsgPgwLXr3/3+vdDipME=; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699837658; bh=ytHfU7p/l8yTC1DRGaIhHXhYJOUHNecTRODoCvWVCbg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=T2ujH9Nf9K0O6y6t0TvBjTkOQrqUTOcw+oSVWtmflT4R6Yf1nfHbRgvuSMKt9woxV ZtEzkWP9sXbzNiljmyleWSsO4+Jis9umphWZCLTLgRbKy/ufJFB9wpPwN60jSLhtlE WK9BRPEIX8Pc8h63mY9JP/ncinldTpLpx/IR+IQsWl274EjyJAdQ7h5lrCL8BLGIHc 0C92Kl18OKu0nH5jmIhBZAkQAw+E4iy5TAjIVNO19IYbPwXyJJTCxvpamXOWvom5XI R5b+VNh1rOyraFprRjtekyQ/ZjWB7iGMPEqOMaWswyNgf0D/7RfiWyJ4PpDliaKmdJ Xws60KmLzdCKA== From: Jisheng Zhang To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Chao Wei , Chen Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 2/4] reset: Add reset controller support for Sophgo CV1800B SoC Date: Mon, 13 Nov 2023 08:55:01 +0800 Message-Id: <20231113005503.2423-3-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20231113005503.2423-1-jszhang@kernel.org> References: <20231113005503.2423-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231112_170744_918266_6829B258 X-CRM114-Status: GOOD ( 12.19 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add reset controller support for Sophgo CV1800B SoC reusing the reset-simple driver. Signed-off-by: Jisheng Zhang --- drivers/reset/Kconfig | 3 ++- drivers/reset/reset-simple.c | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index ccd59ddd7610..2034f69d5953 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -213,7 +213,7 @@ config RESET_SCMI config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT - default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC + default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC depends on HAS_IOMEM help This enables a simple reset controller driver for reset lines that @@ -228,6 +228,7 @@ config RESET_SIMPLE - RCC reset controller in STM32 MCUs - Allwinner SoCs - SiFive FU740 SoCs + - Sophgo SoCs config RESET_SOCFPGA bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c index 7ea5adbf2097..573753ae3e08 100644 --- a/drivers/reset/reset-simple.c +++ b/drivers/reset/reset-simple.c @@ -151,6 +151,8 @@ static const struct of_device_id reset_simple_dt_ids[] = { { .compatible = "snps,dw-high-reset" }, { .compatible = "snps,dw-low-reset", .data = &reset_simple_active_low }, + { .compatible = "sophgo,cv1800b-reset", + .data = &reset_simple_active_low }, { /* sentinel */ }, }; From patchwork Mon Nov 13 00:55:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13453425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39CEEC41535 for ; Mon, 13 Nov 2023 01:07:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=OoAG5I2L2waC+VX0bLMSgNazTUl5xdobdaApMvPhqlE=; b=Z/EvOn2woJADB+ 20QD9+U0dzyFT4kC7r6tJMMb0t789rr7jzgu28zurzAUXo2bjVkFVQ26CRbpHgpMVU21QJt07GBBD KJLFnStfgo4WMRLlM3PrqTlHIWigTyHgMhABcQ9IN0mZJUbdSwgzs/Qw322zrJFkm0BSqBJM5JxzO AcAV2rmj52zkAf1VGAGC2Dj8OQJMrQagakWS7/3c+Q7mmPmAn2dDo039uIXY5d+Cccja9hkMSPLzF OC2TtYP3AC7vluEAbq4oag/4orZOS5te4S0JD6yG6sliwzgOXX0qsAAcWd9uYHC+PTEOrs/GxG8GU FRgc0kQQ9dMjPETbf4nw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r2LQY-00Cxp3-2N; Mon, 13 Nov 2023 01:07:46 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r2LQV-00Cxmt-2C for linux-riscv@lists.infradead.org; Mon, 13 Nov 2023 01:07:44 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by ams.source.kernel.org (Postfix) with ESMTP id 3046FB80B41; Mon, 13 Nov 2023 01:07:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 41267C433CB; Mon, 13 Nov 2023 01:07:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699837661; bh=FU5cMxpykFA89J/z1Xx5vbxIOEU9bDayGjmJTED/4UY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uQezJXBfixXFEnDr2uPowPMWRFtaZ5r1q34O5kMOfhXgqt6xRQJok/YdVKhr753Sc U3brf0s5laXn8qH+WlE5rwINpOTqG7YY5Gf+KvG7ZuE5RAyC4QMGnW7qPhkbtsI73i LOgFM2tUGynRSL8KRffQbgT3N+4ali7B0V4blEFMYQcYw6R2gfBJbjiQcU+4vHywGL rSuLw91jQFndlfabvrHICBhGjhAOdvNpgyWQC1JDvxgIBBNYQI/6GODycyIxNxpJWx hRWvuIIn2U2/HUSuhFuaw5nsb+TkehY43Oq1390yw7oCoKg0AiXMDqcPh15OhD3Sg/ 6E0laeQm1YkTw== From: Jisheng Zhang To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Chao Wei , Chen Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 3/4] riscv: dts: sophgo: add reset dt node for cv1800b Date: Mon, 13 Nov 2023 08:55:02 +0800 Message-Id: <20231113005503.2423-4-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20231113005503.2423-1-jszhang@kernel.org> References: <20231113005503.2423-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231112_170743_852412_5FE489D5 X-CRM114-Status: UNSURE ( 8.71 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add the reset device tree node to cv1800b SoC. Signed-off-by: Jisheng Zhang --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi index df40e87ee063..4032419486be 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -54,6 +54,12 @@ soc { dma-noncoherent; ranges; + rst: reset-controller@3003000 { + compatible = "sophgo,cv1800b-reset"; + reg = <0x03003000 0x1000>; + #reset-cells = <1>; + }; + uart0: serial@4140000 { compatible = "snps,dw-apb-uart"; reg = <0x04140000 0x100>; From patchwork Mon Nov 13 00:55:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13453428 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3BA63C072AB for ; Mon, 13 Nov 2023 01:07:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TK7/0TVq8hdcigm7andQvxKTB8jdD5Nri+8d2CPG5d8=; b=IHpMiKrU1qSTBX HI6SC7LOMb2MZkVuho7nZeb5t7h+BA0094NKAfWcFhPVp/btUCwbNZmRGl9GlIWniSN+wProS3Vkz SNEokGNwTDxwxFOT3FtwzMVcVJUGLFGYirUh/9OvY464552mDFg6Y2ejy6u9kENpJz765ahUPF/+B W/cMYaHGJrcvj2E5IcPJkbVV1QkyYGp3cGJ5m0fCf9ezIlo6C31ULYGn3wJMMNzemAzqgThcTGztC F1to1idrpu3C4GEvKQu797WaWdzjFhNbXbn5TgggZDp/oR8ugPI+nwF0AVfo+2ufGOJ6tdqVI0uzz 5vOy908VKE+zu6vOOXMw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r2LQc-00CxqI-1m; Mon, 13 Nov 2023 01:07:50 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r2LQX-00Cxnq-0I for linux-riscv@lists.infradead.org; Mon, 13 Nov 2023 01:07:46 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 5DDCD60C7B; Mon, 13 Nov 2023 01:07:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E6946C433CC; Mon, 13 Nov 2023 01:07:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699837664; bh=UhAD3REvQmN6OP/l2BKhCL7Kmd6UirEftGJf0TofIdk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y6uMoOfYrKHbDT9xNVOIrXAwjAY43Ti2zC6vtPyKcRWafuAZjfKl6WmszSJQYykgw 2e0Yzh5UwKRsaPVpDNNdaMWZyYD2zNAb2kQycdaM6oNPdpuu/GHIoM3ZDJVWneYJ6p jZjB1fFrmEFRN2OTgxnpZ9jb39mUe2a69KzqXquh4iXUBEIUDAjvZMsJVgPabVhmjH PqpjoutGlz4Xi9No7OQtLnlD5h0F0SKVX3XyF/S3pPXA7jdIEF7xXRm+sI89cinVJG fTXhBwwvfs4kZwxhkfl5XUpCSW63h91O82PyDqEVqzYID1bCs6/wLY/Rk1YOW+OLcf rSD4k41qZCW0A== From: Jisheng Zhang To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Chao Wei , Chen Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 4/4] riscv: dts: sophgo: add reset phandle to all uart nodes Date: Mon, 13 Nov 2023 08:55:03 +0800 Message-Id: <20231113005503.2423-5-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20231113005503.2423-1-jszhang@kernel.org> References: <20231113005503.2423-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231112_170745_173805_DAFD67EF X-CRM114-Status: UNSURE ( 9.01 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Although, the resets are deasserted by default. Add them for completeness. Signed-off-by: Jisheng Zhang --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi index 4032419486be..e04df04a91c0 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -4,6 +4,7 @@ */ #include +#include / { compatible = "sophgo,cv1800b"; @@ -65,6 +66,7 @@ uart0: serial@4140000 { reg = <0x04140000 0x100>; interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; clocks = <&osc>; + resets = <&rst RST_UART0>; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -75,6 +77,7 @@ uart1: serial@4150000 { reg = <0x04150000 0x100>; interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&osc>; + resets = <&rst RST_UART1>; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -85,6 +88,7 @@ uart2: serial@4160000 { reg = <0x04160000 0x100>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; clocks = <&osc>; + resets = <&rst RST_UART2>; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -95,6 +99,7 @@ uart3: serial@4170000 { reg = <0x04170000 0x100>; interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; clocks = <&osc>; + resets = <&rst RST_UART3>; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -105,6 +110,7 @@ uart4: serial@41c0000 { reg = <0x041c0000 0x100>; interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; clocks = <&osc>; + resets = <&rst RST_UART4>; reg-shift = <2>; reg-io-width = <4>; status = "disabled";