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[46.102.197.194]) by smtp.gmail.com with ESMTPSA id v9-20020a5d43c9000000b0032da022855fsm5805800wrr.111.2023.11.13.09.06.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Nov 2023 09:06:20 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: f7d490ba-8246-11ee-9b0e-b553b5be7939 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1699895181; x=1700499981; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=RMT7c/uiWiQZVRU+b+wZHF6Grzvo4YDAcSgfc5P5jVA=; b=a/tkkyxf1zD7/nmQyn6AI2Tx+NuRRWX1MLJ7TnNGOECNoguRQHnIeojqHUi60ijzRI mCK1OJAYPNdB79AxN7v8VzuVyZ0De8IiwgWInYri+jHP84BBuZhMHfDI3wbq8pAkbIbx UPJEffc5BaFTMpxZjhLHOQS5FesOmDiBFDKNc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699895181; x=1700499981; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=RMT7c/uiWiQZVRU+b+wZHF6Grzvo4YDAcSgfc5P5jVA=; b=VPPQk7VlTL6aCbyhQPt9mCE44JffQ6QP3WqhVSX5zlnXXEAVHsS06h1HnG4NjMqSuh tW9FJzIPHGpG9lv05A4qASX6Idj4eZ2Iuj0cO+u1bdpwJOLvF77dysJ964Vly+Fwyy8J jYK3uxHvWYLXq6iL9T1Z5Hv+m1jjC2pG0M3Fbp/oZRCNPQx0AZPUh6rHC2dmUR5+JA38 Gq3n27bJY8CjhyLtzagqff1NgHaTA4mCn6KJ90sHv5nz6mtO5WxKV6hjF9hg/a5gMIPI ZtRJU65tComF0Ofcz67SSg3lqfi56csXV9XZoIENHBfNAYYgmGmK6oDqeG91/wKNRZnx KhXA== X-Gm-Message-State: AOJu0YyEenpGu7wqgrq6IqnKIZI7DhkgzT0LtLZ716PzPnrubMFeBqim PwDupbunjafZxkMvBTfyCQUmRaC6O5/h0BUKkYY= X-Google-Smtp-Source: AGHT+IEUIFDEjZ8xQCJ/lIc+4at+vBm1KT5Dn4H7fIPW60l+G2YIYq35bQOe1UO53pimBlWDq1pbow== X-Received: by 2002:a05:6000:186a:b0:32f:811f:5046 with SMTP id d10-20020a056000186a00b0032f811f5046mr4992740wri.11.1699895180712; Mon, 13 Nov 2023 09:06:20 -0800 (PST) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH] xen/x86: On x2APIC mode, derive LDR from APIC_ID Date: Mon, 13 Nov 2023 16:50:23 +0000 Message-Id: <20231113165023.5824-1-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Both Intel and AMD manuals agree that on x2APIC mode, the APIC LDR and ID registers are derivable from each other through a fixed formula. Xen uses that formula, but applies it to vCPU IDs (which are sequential) rather than x2APIC_IDs (which are not, at the moment). As I understand it, this is an attempt to tightly pack vCPUs into clusters so each cluster has 16 vCPUs rather than 8, but this is problematic for OSs that might read the x2APIC_ID and internally derive LDR (or the other way around) This patch fixes the implementation so we follow the rules in the x2APIC spec(s). While in the neighborhood, replace the u32 type with the standard uint32_t Signed-off-by: Alejandro Vallejo --- xen/arch/x86/hvm/vlapic.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c index c7ce82d064..5a74e84445 100644 --- a/xen/arch/x86/hvm/vlapic.c +++ b/xen/arch/x86/hvm/vlapic.c @@ -1063,10 +1063,10 @@ static const struct hvm_mmio_ops vlapic_mmio_ops = { static void set_x2apic_id(struct vlapic *vlapic) { - u32 id = vlapic_vcpu(vlapic)->vcpu_id; - u32 ldr = ((id & ~0xf) << 12) | (1 << (id & 0xf)); + uint32_t id = vlapic_vcpu(vlapic)->vcpu_id * 2; + uint32_t ldr = ((id & ~0xf) << 12) | (1 << (id & 0xf)); - vlapic_set_reg(vlapic, APIC_ID, id * 2); + vlapic_set_reg(vlapic, APIC_ID, id); vlapic_set_reg(vlapic, APIC_LDR, ldr); }