From patchwork Mon Nov 13 20:11:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13454404 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 29B4DC4332F for ; Mon, 13 Nov 2023 20:11:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D89110E410; Mon, 13 Nov 2023 20:11:16 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 24D8110E27F for ; Mon, 13 Nov 2023 20:11:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699906273; x=1731442273; h=from:to:subject:date:message-id:mime-version: content-transfer-encoding; bh=yYvLHxVzbf96nFlGo6x2u4ah7wKWhAElL43TC0+Wp/0=; b=g8sTncbWlUTIH4d7bTtS5D3Dpjze6K7Uv09MM6KZyMKvWfQyafHm0Ewk IDt6n8mJrKLSh/MNlYoXiH9UTBU8i3wIpRd4j4FN4v1FIwTZEK6nOU4uC hy/VjkcvyMnxLd/InVWfbL8PYn93z5DAO49AaWpBNZ6A3etb8CgMiBjpp /FJnEcRL6i8UvqPQfG+ntutlb5tJvbOycWvE7yGMDaWHZVq3tRmypbyau KX9hk23mPIuaKlYY0yWpdG6LcnDZpd8Voh7Qx5vNCobvAdMNpRkHMwPDS RLIKHFQpnHwY9qQBDNftjEkpCVYxmRo9n1o88eaJPdG+AJp+U7qmu0Wif Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10893"; a="3553661" X-IronPort-AV: E=Sophos;i="6.03,299,1694761200"; d="scan'208";a="3553661" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2023 12:11:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10893"; a="937829885" X-IronPort-AV: E=Sophos;i="6.03,299,1694761200"; d="scan'208";a="937829885" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2023 12:11:10 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Mon, 13 Nov 2023 22:11:07 +0200 Message-Id: <20231113201110.510724-1-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/4] drm/i915/dp: Account for channel coding efficiency on UHBR links X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Apply the correct BW allocation overhead and channel coding efficiency on UHBR link rates, similarly to DP1.4 link rates. Signed-off-by: Imre Deak Reviewed-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_display.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 3effafcbb411a..24aebdb715e7d 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2398,16 +2398,6 @@ add_bw_alloc_overhead(int link_clock, int bw_overhead, int ch_coding_efficiency = drm_dp_bw_channel_coding_efficiency(is_uhbr); - /* - * TODO: adjust for actual UHBR channel coding efficiency and BW - * overhead. - */ - if (is_uhbr) { - *data_m = pixel_data_rate; - *data_n = link_data_rate * 8 / 10; - return; - } - *data_m = DIV_ROUND_UP_ULL(mul_u32_u32(pixel_data_rate, bw_overhead), 1000000); *data_n = DIV_ROUND_DOWN_ULL(mul_u32_u32(link_data_rate, ch_coding_efficiency), From patchwork Mon Nov 13 20:11:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13454403 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6635C4167B for ; Mon, 13 Nov 2023 20:11:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1CEDD10E27F; Mon, 13 Nov 2023 20:11:15 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4D8B010E410 for ; Mon, 13 Nov 2023 20:11:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699906273; x=1731442273; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=3uQVpk2WC20P79bu2oF+B66lV3AJDeozSuLJ8utX8a4=; b=Wv+25sIaF6IUe9DdQVoIfhVBPBMCzw6nx9/TZxl/O1WNDVEu5fyXbHYZ NwUqPaBRb1OIk0aNJyZy8wxbgbOZKSiAkKFT7exox8dLxHO4OsAZA+mQi HIJC/XT6swjtRyAt7MzBtXF91xif4UM37hOBPzDIGVPC7qsyYIOvoS96U IAEsUbseJjAvGS4z3PVNo1RcMC0SyJLAPsiW+aB/TwMeS+r5Oqo3bfh/f UmiRxWRtVNBNfx5zBrtnRlJ7CwO7Ccvzz4kuiyF1SSxS1czi9XTrigYBd wcR7C3w4SamkaxG7ngC6LH8X3V1vmHcLMMWW2MeS09ZeqWAYL4y9Q6hs+ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10893"; a="3553662" X-IronPort-AV: E=Sophos;i="6.03,299,1694761200"; d="scan'208";a="3553662" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2023 12:11:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10893"; a="937829888" X-IronPort-AV: E=Sophos;i="6.03,299,1694761200"; d="scan'208";a="937829888" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2023 12:11:11 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Mon, 13 Nov 2023 22:11:08 +0200 Message-Id: <20231113201110.510724-2-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231113201110.510724-1-imre.deak@intel.com> References: <20231113201110.510724-1-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/4] drm/i915/dp: Fix UHBR link M/N values X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The link M/N ratio is the data rate / link symbol clock rate, fix things up accordingly. On DP 1.4 this ratio was correct as the link symbol clock rate in that case matched the link data rate (in bytes/sec units, the symbol size being 8 bits), however it wasn't correct for UHBR rates where the symbol size is 32 bits. Signed-off-by: Imre Deak Reviewed-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_display.c | 16 ++++++++----- drivers/gpu/drm/i915/display/intel_dp.c | 24 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ 3 files changed, 36 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 24aebdb715e7d..c059eb0170a5b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2411,6 +2411,7 @@ intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, struct intel_link_m_n *m_n) { u32 data_clock = bits_per_pixel * pixel_clock; + u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock); u32 data_m; u32 data_n; @@ -2431,7 +2432,7 @@ intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 0x8000000); compute_m_n(&m_n->link_m, &m_n->link_n, - pixel_clock, link_clock, + pixel_clock, link_symbol_clock, 0x80000); } @@ -3943,20 +3944,23 @@ int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n) { /* - * The calculation for the data clock is: + * The calculation for the data clock -> pixel clock is: * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp * But we want to avoid losing precison if possible, so: * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) * - * and the link clock is simpler: - * link_clock = (m * link_clock) / n + * and for link freq (10kbs units) -> pixel clock it is: + * link_symbol_clock = link_freq * 10 / link_symbol_size + * pixel_clock = (m * link_symbol_clock) / n + * or for more precision: + * pixel_clock = (m * link_freq * 10) / (n * link_symbol_size) */ if (!m_n->link_n) return 0; - return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq), - m_n->link_n); + return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10), + m_n->link_n * intel_dp_link_symbol_size(link_freq)); } int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index f662d1ce5f72c..80e1e887432fa 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -132,6 +132,30 @@ bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) return intel_dp_is_uhbr_rate(crtc_state->port_clock); } +/** + * intel_dp_link_symbol_size - get the link symbol size for a given link rate + * @rate: link rate in 10kbit/s units + * + * Returns the link symbol size in bits/symbol units depending on the link + * rate -> channel coding. + */ +int intel_dp_link_symbol_size(int rate) +{ + return intel_dp_is_uhbr_rate(rate) ? 32 : 10; +} + +/** + * intel_dp_link_symbol_clock - convert link rate to link symbol clock + * @rate: link rate in 10kbit/s units + * + * Returns the link symbol clock frequency in kHz units depending on the + * link rate and channel coding. + */ +int intel_dp_link_symbol_clock(int rate) +{ + return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate)); +} + static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp) { intel_dp->sink_rates[0] = 162000; diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index e80da67554196..64dbf8f192708 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -82,6 +82,8 @@ bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp); bool intel_dp_is_edp(struct intel_dp *intel_dp); bool intel_dp_is_uhbr_rate(int rate); bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); +int intel_dp_link_symbol_size(int rate); +int intel_dp_link_symbol_clock(int rate); bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd); From patchwork Mon Nov 13 20:11:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13454406 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C8969C4167D for ; Mon, 13 Nov 2023 20:11:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B2B0D10E415; Mon, 13 Nov 2023 20:11:19 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1B83D10E27F for ; Mon, 13 Nov 2023 20:11:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699906274; x=1731442274; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=mv9l/FlFzwU4bcR2/KBDLfQT1PcdZqPzTXpUqCbLtdk=; b=izBKW0Ou8nV4DElYIS/eu+GZtKWrCGKdE0MqWs7BrBUElT4a9lcNJPM6 oiGrjJbDuQkSxpgH//HhfIpg1o1JcVNB5Y4UUQ9hZupHlPhWBt7rRGGJp SqpeXKfji1YJd24OxiS8sAEiAr86HnNMMCseeHV+7tyCtXmiuGVsXCuhr hyyrmp56IDpuMhzjbVmDzZJ+lrrzxRBR675Qdbeux1sPkkgMXuztuO2Zs GzElLUW0jUwo+lAFSpNOl57c0Fn62dQly/ZeW4SyX6A2z8wqkrEv0g/16 YKESKLMJQIg9UPn0QyLj4FTd71YrzFUhZtkBwVFNrhP55YsyyubV6P/op w==; X-IronPort-AV: E=McAfee;i="6600,9927,10893"; a="3553664" X-IronPort-AV: E=Sophos;i="6.03,299,1694761200"; d="scan'208";a="3553664" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2023 12:11:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10893"; a="937829889" X-IronPort-AV: E=Sophos;i="6.03,299,1694761200"; d="scan'208";a="937829889" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2023 12:11:12 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Mon, 13 Nov 2023 22:11:09 +0200 Message-Id: <20231113201110.510724-3-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231113201110.510724-1-imre.deak@intel.com> References: <20231113201110.510724-1-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/4] drm/i915/dp_mst: Fix PBN / MTP_TU size calculation for UHBR rates X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Atm the allocated MST PBN value is calculated from the TU size (number of allocated MTP slots) as PBN = TU * pbn_div pbn_div being the link BW for each MTP slot. For DP 1.4 link rates this worked, as pbn_div there is guraranteed to be an integer number, however on UHBR this isn't the case. To get a PBN, TU pair where TU is a properly rounded-up value covering all the BW corresponding to PBN, calculate first PBN and from PBN the TU value. Signed-off-by: Imre Deak Reviewed-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index b943dbf394a22..a32ab0b4fc9d7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -170,6 +170,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) { struct intel_link_m_n remote_m_n; + int alloc_tu; int link_bpp; drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp); @@ -200,9 +201,14 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, * crtc_state->dp_m_n.tu), provided that the driver doesn't * enable SSC on the corresponding link. */ + crtc_state->pbn = DIV_ROUND_UP_ULL(mul_u32_u32(mst_state->pbn_div * 64, + remote_m_n.data_m), + remote_m_n.data_n); + + alloc_tu = DIV_ROUND_UP_ULL(crtc_state->pbn, mst_state->pbn_div); + drm_WARN_ON(&i915->drm, alloc_tu < remote_m_n.tu); drm_WARN_ON(&i915->drm, remote_m_n.tu < crtc_state->dp_m_n.tu); - crtc_state->dp_m_n.tu = remote_m_n.tu; - crtc_state->pbn = remote_m_n.tu * mst_state->pbn_div; + crtc_state->dp_m_n.tu = alloc_tu; slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr, connector->port, From patchwork Mon Nov 13 20:11:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13454405 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8704CC4332F for ; Mon, 13 Nov 2023 20:11:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 784C310E416; Mon, 13 Nov 2023 20:11:18 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9941C10E410; Mon, 13 Nov 2023 20:11:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699906275; x=1731442275; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3JRsCBbkvD1Y84ofNkeetVXUr8bjqrGeMKeJ8ALre8Y=; b=R7CwpoH4djwJYtoOsr0UQUDvg4mKkdE6kmYAcMbqyFIRJSAEsQNTBTCa DlZoDVG1ugxUTjuUS5S9Uu/V6M0tlMv+/17myIvLTh13gEHRVG21Oz9Ih mezqx1SkdnDS7L3ij+h7udY0+NfcSp4unOhwfNB4tUVSYKgwpPSzjvcPT WhMKitlKFDEUMiwVAnZywfuSBTjZsmUWUf4CYAg4aFMMxawS7kLvVV48K jOFXyhnY2JhUjD8YkBzq5nw2XszTyd6x/89HLLtyYmWrqYzfWaJgU3EA5 GL14leofCMRuporFBZJtjf3Vwtkz/HW05yKu4ZAeY/jdix9DWVilIccAe Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10893"; a="3553666" X-IronPort-AV: E=Sophos;i="6.03,299,1694761200"; d="scan'208";a="3553666" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2023 12:11:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10893"; a="937829890" X-IronPort-AV: E=Sophos;i="6.03,299,1694761200"; d="scan'208";a="937829890" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2023 12:11:13 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Mon, 13 Nov 2023 22:11:10 +0200 Message-Id: <20231113201110.510724-4-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231113201110.510724-1-imre.deak@intel.com> References: <20231113201110.510724-1-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/4] drm/dp_mst: Fix PBN divider calculation for UHBR rates X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The current way of calculating the pbn_div value, the link BW per each MTP slot, worked only for DP 1.4 link rates. Fix things up for UHBR rates calculating with the correct channel coding efficiency based on the link rate. On UHBR the resulting pbn_div value is not an integer (vs. DP 1.4 where the value is always an integer), so ideally a scaled value containing the fractional part should be returned, so that the PBN -> MTP slot count (aka TU size) conversion can be done with less error. For now return a rounded-down value - which can result in +1 excess MTP slot getting allocated on UHBR links. Cc: Lyude Paul Cc: dri-devel@lists.freedesktop.org Signed-off-by: Imre Deak --- drivers/gpu/drm/display/drm_dp_mst_topology.c | 15 +++++++++++++-- include/drm/display/drm_dp_helper.h | 13 +++++++++++++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c index 4d72c9a32026e..940a9fc0d0244 100644 --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@ -3582,12 +3582,23 @@ static int drm_dp_send_up_ack_reply(struct drm_dp_mst_topology_mgr *mgr, int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr, int link_rate, int link_lane_count) { + int ret; + if (link_rate == 0 || link_lane_count == 0) drm_dbg_kms(mgr->dev, "invalid link rate/lane count: (%d / %d)\n", link_rate, link_lane_count); - /* See DP v2.0 2.6.4.2, VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */ - return link_rate * link_lane_count / 54000; + /* See DP v2.0 2.6.4.2, 2.7.6.3 VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */ + /* + * TODO: Return the value with a higher precision, allowing a better + * slots per MTP allocation granularity. With the current returned + * value +1 slot/MTP can get allocated on UHBR links. + */ + ret = mul_u32_u32(link_rate * link_lane_count, + drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(link_rate))) / + (1000000ULL * 8 * 5400); + + return ret; } EXPORT_SYMBOL(drm_dp_get_vc_payload_bw); diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h index caee29d28463c..18ff6af0b5a31 100644 --- a/include/drm/display/drm_dp_helper.h +++ b/include/drm/display/drm_dp_helper.h @@ -251,6 +251,19 @@ drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP); } +/** + * drm_dp_is_uhbr_rate - Determine if a link rate is UHBR + * @link_rate: link rate in 10kbits/s units + * + * Determine if the provided link rate is an UHBR rate. + * + * Returns: %True if @link_rate is an UHBR rate. + */ +static inline bool drm_dp_is_uhbr_rate(int link_rate) +{ + return link_rate >= 1000000; +} + /* * DisplayPort AUX channel */