From patchwork Tue Nov 14 02:09:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13454732 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E2116C4167B for ; Tue, 14 Nov 2023 02:11:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r2iry-0001FT-GR; Mon, 13 Nov 2023 21:09:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r2irx-0001FF-2k for qemu-devel@nongnu.org; Mon, 13 Nov 2023 21:09:37 -0500 Received: from mail-pg1-f175.google.com ([209.85.215.175]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r2iru-0007Yu-FY for qemu-devel@nongnu.org; Mon, 13 Nov 2023 21:09:36 -0500 Received: by mail-pg1-f175.google.com with SMTP id 41be03b00d2f7-5b99bfca064so3313656a12.3 for ; Mon, 13 Nov 2023 18:09:34 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699927773; x=1700532573; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uly2GlWW76uVdEBogdnvfJFvgrZfN8PqNdxFiox0Dc0=; b=VvRb4Bv9ODHaLgDfg96d2BgKdMJcXYtkn10eDOj8D6kyKKsYb07aCuFWOKA7JeqJjf CFZ/9JiTAER3znVET1LIRuRfi2+jf3ElNh9hRR+K8WnbXJjSa1tFFdoRfhW770pVNbZU xFGVwflDLkA7kNohhAGW1a/sDyItp7duOFPDNK3q/ub8zve/eruxnEkcSpCH8zYF9Ddd HS30vRKmK9eSNUtIoxtsyNlLPzLy1l5zlRlkOXxl9YIBzxDZ3o2hSUI0xfZCR3Jf9H9L tE1nxiAJWVW1S/hiX8YgXxlGDcr+gH80k1GlUTThM2V52s8B1PcHvFaB/Y9mcQO748/i sViA== X-Gm-Message-State: AOJu0YzHfowTKF7PaDoLuVs7dWpv1KWlk+D4fPxkmJDtaBhxkOgQDmdg uQRmmVKOT1x3iDd0OjFsqxJLASoPlRk= X-Google-Smtp-Source: AGHT+IHSrQHEyjU4xp9tpnffoAqh10LEBuab51YPih1jZYM5ZsdQhQT2qpoJRxow7f9uSi8zTU17yg== X-Received: by 2002:a17:90b:3883:b0:280:2652:d4e with SMTP id mu3-20020a17090b388300b0028026520d4emr5751791pjb.29.1699927772763; Mon, 13 Nov 2023 18:09:32 -0800 (PST) Received: from localhost.localdomain ([2601:642:4c01:2f7:5d09:c219:9099:a639]) by smtp.gmail.com with ESMTPSA id g13-20020a17090ae58d00b0027d12b1e29dsm6175362pjz.25.2023.11.13.18.09.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Nov 2023 18:09:32 -0800 (PST) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Stefan Berger , Stefan Berger Subject: [PATCH v5 01/14] tpm_crb: refactor common code Date: Mon, 13 Nov 2023 18:09:11 -0800 Message-ID: <20231114020927.62315-2-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231114020927.62315-1-j@getutm.app> References: <20231114020927.62315-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.175; envelope-from=osy86dev@gmail.com; helo=mail-pg1-f175.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In preparation for the SysBus variant, we move common code styled after the TPM TIS devices. To maintain compatibility, we do not rename the existing tpm-crb device. Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- docs/specs/tpm.rst | 1 + hw/tpm/tpm_crb.h | 76 +++++++++++ hw/tpm/tpm_crb.c | 270 ++++++---------------------------------- hw/tpm/tpm_crb_common.c | 216 ++++++++++++++++++++++++++++++++ hw/tpm/meson.build | 1 + hw/tpm/trace-events | 2 +- 6 files changed, 331 insertions(+), 235 deletions(-) create mode 100644 hw/tpm/tpm_crb.h create mode 100644 hw/tpm/tpm_crb_common.c diff --git a/docs/specs/tpm.rst b/docs/specs/tpm.rst index efe124a148..2bc29c9804 100644 --- a/docs/specs/tpm.rst +++ b/docs/specs/tpm.rst @@ -45,6 +45,7 @@ operating system. QEMU files related to TPM CRB interface: - ``hw/tpm/tpm_crb.c`` + - ``hw/tpm/tpm_crb_common.c`` SPAPR interface --------------- diff --git a/hw/tpm/tpm_crb.h b/hw/tpm/tpm_crb.h new file mode 100644 index 0000000000..da3a0cf256 --- /dev/null +++ b/hw/tpm/tpm_crb.h @@ -0,0 +1,76 @@ +/* + * tpm_crb.h - QEMU's TPM CRB interface emulator + * + * Copyright (c) 2018 Red Hat, Inc. + * + * Authors: + * Marc-André Lureau + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + * tpm_crb is a device for TPM 2.0 Command Response Buffer (CRB) Interface + * as defined in TCG PC Client Platform TPM Profile (PTP) Specification + * Family “2.0” Level 00 Revision 01.03 v22 + */ +#ifndef TPM_TPM_CRB_H +#define TPM_TPM_CRB_H + +#include "exec/memory.h" +#include "hw/acpi/tpm.h" +#include "sysemu/tpm_backend.h" +#include "tpm_ppi.h" + +#define CRB_CTRL_CMD_SIZE (TPM_CRB_ADDR_SIZE - A_CRB_DATA_BUFFER) + +typedef struct TPMCRBState { + TPMBackend *tpmbe; + TPMBackendCmd cmd; + uint32_t regs[TPM_CRB_R_MAX]; + MemoryRegion mmio; + MemoryRegion cmdmem; + + size_t be_buffer_size; + + bool ppi_enabled; + TPMPPI ppi; +} TPMCRBState; + +#define CRB_INTF_TYPE_CRB_ACTIVE 0b1 +#define CRB_INTF_VERSION_CRB 0b1 +#define CRB_INTF_CAP_LOCALITY_0_ONLY 0b0 +#define CRB_INTF_CAP_IDLE_FAST 0b0 +#define CRB_INTF_CAP_XFER_SIZE_64 0b11 +#define CRB_INTF_CAP_FIFO_NOT_SUPPORTED 0b0 +#define CRB_INTF_CAP_CRB_SUPPORTED 0b1 +#define CRB_INTF_IF_SELECTOR_CRB 0b1 + +enum crb_loc_ctrl { + CRB_LOC_CTRL_REQUEST_ACCESS = BIT(0), + CRB_LOC_CTRL_RELINQUISH = BIT(1), + CRB_LOC_CTRL_SEIZE = BIT(2), + CRB_LOC_CTRL_RESET_ESTABLISHMENT_BIT = BIT(3), +}; + +enum crb_ctrl_req { + CRB_CTRL_REQ_CMD_READY = BIT(0), + CRB_CTRL_REQ_GO_IDLE = BIT(1), +}; + +enum crb_start { + CRB_START_INVOKE = BIT(0), +}; + +enum crb_cancel { + CRB_CANCEL_INVOKE = BIT(0), +}; + +#define TPM_CRB_NO_LOCALITY 0xff + +void tpm_crb_request_completed(TPMCRBState *s, int ret); +enum TPMVersion tpm_crb_get_version(TPMCRBState *s); +int tpm_crb_pre_save(TPMCRBState *s); +void tpm_crb_reset(TPMCRBState *s, uint64_t baseaddr); +void tpm_crb_init_memory(Object *obj, TPMCRBState *s, Error **errp); + +#endif /* TPM_TPM_CRB_H */ diff --git a/hw/tpm/tpm_crb.c b/hw/tpm/tpm_crb.c index ea930da545..3ef4977fb5 100644 --- a/hw/tpm/tpm_crb.c +++ b/hw/tpm/tpm_crb.c @@ -31,257 +31,62 @@ #include "tpm_ppi.h" #include "trace.h" #include "qom/object.h" +#include "tpm_crb.h" struct CRBState { DeviceState parent_obj; - TPMBackend *tpmbe; - TPMBackendCmd cmd; - uint32_t regs[TPM_CRB_R_MAX]; - MemoryRegion mmio; - MemoryRegion cmdmem; - - size_t be_buffer_size; - - bool ppi_enabled; - TPMPPI ppi; + TPMCRBState state; }; typedef struct CRBState CRBState; DECLARE_INSTANCE_CHECKER(CRBState, CRB, TYPE_TPM_CRB) -#define CRB_INTF_TYPE_CRB_ACTIVE 0b1 -#define CRB_INTF_VERSION_CRB 0b1 -#define CRB_INTF_CAP_LOCALITY_0_ONLY 0b0 -#define CRB_INTF_CAP_IDLE_FAST 0b0 -#define CRB_INTF_CAP_XFER_SIZE_64 0b11 -#define CRB_INTF_CAP_FIFO_NOT_SUPPORTED 0b0 -#define CRB_INTF_CAP_CRB_SUPPORTED 0b1 -#define CRB_INTF_IF_SELECTOR_CRB 0b1 - -#define CRB_CTRL_CMD_SIZE (TPM_CRB_ADDR_SIZE - A_CRB_DATA_BUFFER) - -enum crb_loc_ctrl { - CRB_LOC_CTRL_REQUEST_ACCESS = BIT(0), - CRB_LOC_CTRL_RELINQUISH = BIT(1), - CRB_LOC_CTRL_SEIZE = BIT(2), - CRB_LOC_CTRL_RESET_ESTABLISHMENT_BIT = BIT(3), -}; - -enum crb_ctrl_req { - CRB_CTRL_REQ_CMD_READY = BIT(0), - CRB_CTRL_REQ_GO_IDLE = BIT(1), -}; - -enum crb_start { - CRB_START_INVOKE = BIT(0), -}; - -enum crb_cancel { - CRB_CANCEL_INVOKE = BIT(0), -}; - -#define TPM_CRB_NO_LOCALITY 0xff - -static uint64_t tpm_crb_mmio_read(void *opaque, hwaddr addr, - unsigned size) -{ - CRBState *s = CRB(opaque); - void *regs = (void *)&s->regs + (addr & ~3); - unsigned offset = addr & 3; - uint32_t val = *(uint32_t *)regs >> (8 * offset); - - switch (addr) { - case A_CRB_LOC_STATE: - val |= !tpm_backend_get_tpm_established_flag(s->tpmbe); - break; - } - - trace_tpm_crb_mmio_read(addr, size, val); - - return val; -} - -static uint8_t tpm_crb_get_active_locty(CRBState *s) -{ - if (!ARRAY_FIELD_EX32(s->regs, CRB_LOC_STATE, locAssigned)) { - return TPM_CRB_NO_LOCALITY; - } - return ARRAY_FIELD_EX32(s->regs, CRB_LOC_STATE, activeLocality); -} - -static void tpm_crb_mmio_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - CRBState *s = CRB(opaque); - uint8_t locty = addr >> 12; - - trace_tpm_crb_mmio_write(addr, size, val); - - switch (addr) { - case A_CRB_CTRL_REQ: - switch (val) { - case CRB_CTRL_REQ_CMD_READY: - ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, - tpmIdle, 0); - break; - case CRB_CTRL_REQ_GO_IDLE: - ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, - tpmIdle, 1); - break; - } - break; - case A_CRB_CTRL_CANCEL: - if (val == CRB_CANCEL_INVOKE && - s->regs[R_CRB_CTRL_START] & CRB_START_INVOKE) { - tpm_backend_cancel_cmd(s->tpmbe); - } - break; - case A_CRB_CTRL_START: - if (val == CRB_START_INVOKE && - !(s->regs[R_CRB_CTRL_START] & CRB_START_INVOKE) && - tpm_crb_get_active_locty(s) == locty) { - void *mem = memory_region_get_ram_ptr(&s->cmdmem); - - s->regs[R_CRB_CTRL_START] |= CRB_START_INVOKE; - s->cmd = (TPMBackendCmd) { - .in = mem, - .in_len = MIN(tpm_cmd_get_size(mem), s->be_buffer_size), - .out = mem, - .out_len = s->be_buffer_size, - }; - - tpm_backend_deliver_request(s->tpmbe, &s->cmd); - } - break; - case A_CRB_LOC_CTRL: - switch (val) { - case CRB_LOC_CTRL_RESET_ESTABLISHMENT_BIT: - /* not loc 3 or 4 */ - break; - case CRB_LOC_CTRL_RELINQUISH: - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, - locAssigned, 0); - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, - Granted, 0); - break; - case CRB_LOC_CTRL_REQUEST_ACCESS: - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, - Granted, 1); - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, - beenSeized, 0); - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, - locAssigned, 1); - break; - } - break; - } -} - -static const MemoryRegionOps tpm_crb_memory_ops = { - .read = tpm_crb_mmio_read, - .write = tpm_crb_mmio_write, - .endianness = DEVICE_LITTLE_ENDIAN, - .valid = { - .min_access_size = 1, - .max_access_size = 4, - }, -}; - -static void tpm_crb_request_completed(TPMIf *ti, int ret) +static void tpm_crb_none_request_completed(TPMIf *ti, int ret) { CRBState *s = CRB(ti); - s->regs[R_CRB_CTRL_START] &= ~CRB_START_INVOKE; - if (ret != 0) { - ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, - tpmSts, 1); /* fatal error */ - } - memory_region_set_dirty(&s->cmdmem, 0, CRB_CTRL_CMD_SIZE); + tpm_crb_request_completed(&s->state, ret); } -static enum TPMVersion tpm_crb_get_version(TPMIf *ti) +static enum TPMVersion tpm_crb_none_get_version(TPMIf *ti) { CRBState *s = CRB(ti); - return tpm_backend_get_tpm_version(s->tpmbe); + return tpm_crb_get_version(&s->state); } -static int tpm_crb_pre_save(void *opaque) +static int tpm_crb_none_pre_save(void *opaque) { CRBState *s = opaque; - tpm_backend_finish_sync(s->tpmbe); - - return 0; + return tpm_crb_pre_save(&s->state); } -static const VMStateDescription vmstate_tpm_crb = { +static const VMStateDescription vmstate_tpm_crb_none = { .name = "tpm-crb", - .pre_save = tpm_crb_pre_save, + .pre_save = tpm_crb_none_pre_save, .fields = (VMStateField[]) { - VMSTATE_UINT32_ARRAY(regs, CRBState, TPM_CRB_R_MAX), + VMSTATE_UINT32_ARRAY(state.regs, CRBState, TPM_CRB_R_MAX), VMSTATE_END_OF_LIST(), } }; -static Property tpm_crb_properties[] = { - DEFINE_PROP_TPMBE("tpmdev", CRBState, tpmbe), - DEFINE_PROP_BOOL("ppi", CRBState, ppi_enabled, true), +static Property tpm_crb_none_properties[] = { + DEFINE_PROP_TPMBE("tpmdev", CRBState, state.tpmbe), + DEFINE_PROP_BOOL("ppi", CRBState, state.ppi_enabled, true), DEFINE_PROP_END_OF_LIST(), }; -static void tpm_crb_reset(void *dev) +static void tpm_crb_none_reset(void *dev) { CRBState *s = CRB(dev); - if (s->ppi_enabled) { - tpm_ppi_reset(&s->ppi); - } - tpm_backend_reset(s->tpmbe); - - memset(s->regs, 0, sizeof(s->regs)); - - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, - tpmRegValidSts, 1); - ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, - tpmIdle, 1); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, - InterfaceType, CRB_INTF_TYPE_CRB_ACTIVE); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, - InterfaceVersion, CRB_INTF_VERSION_CRB); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, - CapLocality, CRB_INTF_CAP_LOCALITY_0_ONLY); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, - CapCRBIdleBypass, CRB_INTF_CAP_IDLE_FAST); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, - CapDataXferSizeSupport, CRB_INTF_CAP_XFER_SIZE_64); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, - CapFIFO, CRB_INTF_CAP_FIFO_NOT_SUPPORTED); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, - CapCRB, CRB_INTF_CAP_CRB_SUPPORTED); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, - InterfaceSelector, CRB_INTF_IF_SELECTOR_CRB); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, - RID, 0b0000); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID2, - VID, PCI_VENDOR_ID_IBM); - - s->regs[R_CRB_CTRL_CMD_SIZE] = CRB_CTRL_CMD_SIZE; - s->regs[R_CRB_CTRL_CMD_LADDR] = TPM_CRB_ADDR_BASE + A_CRB_DATA_BUFFER; - s->regs[R_CRB_CTRL_RSP_SIZE] = CRB_CTRL_CMD_SIZE; - s->regs[R_CRB_CTRL_RSP_ADDR] = TPM_CRB_ADDR_BASE + A_CRB_DATA_BUFFER; - - s->be_buffer_size = MIN(tpm_backend_get_buffer_size(s->tpmbe), - CRB_CTRL_CMD_SIZE); - - if (tpm_backend_startup_tpm(s->tpmbe, s->be_buffer_size) < 0) { - exit(1); - } + return tpm_crb_reset(&s->state, TPM_CRB_ADDR_BASE); } -static void tpm_crb_realize(DeviceState *dev, Error **errp) +static void tpm_crb_none_realize(DeviceState *dev, Error **errp) { CRBState *s = CRB(dev); @@ -289,64 +94,61 @@ static void tpm_crb_realize(DeviceState *dev, Error **errp) error_setg(errp, "at most one TPM device is permitted"); return; } - if (!s->tpmbe) { + if (!s->state.tpmbe) { error_setg(errp, "'tpmdev' property is required"); return; } - memory_region_init_io(&s->mmio, OBJECT(s), &tpm_crb_memory_ops, s, - "tpm-crb-mmio", sizeof(s->regs)); - memory_region_init_ram(&s->cmdmem, OBJECT(s), - "tpm-crb-cmd", CRB_CTRL_CMD_SIZE, errp); + tpm_crb_init_memory(OBJECT(s), &s->state, errp); memory_region_add_subregion(get_system_memory(), - TPM_CRB_ADDR_BASE, &s->mmio); + TPM_CRB_ADDR_BASE, &s->state.mmio); memory_region_add_subregion(get_system_memory(), - TPM_CRB_ADDR_BASE + sizeof(s->regs), &s->cmdmem); + TPM_CRB_ADDR_BASE + sizeof(s->state.regs), &s->state.cmdmem); - if (s->ppi_enabled) { - tpm_ppi_init(&s->ppi, get_system_memory(), + if (s->state.ppi_enabled) { + tpm_ppi_init(&s->state.ppi, get_system_memory(), TPM_PPI_ADDR_BASE, OBJECT(s)); } if (xen_enabled()) { - tpm_crb_reset(dev); + tpm_crb_none_reset(dev); } else { - qemu_register_reset(tpm_crb_reset, dev); + qemu_register_reset(tpm_crb_none_reset, dev); } } -static void tpm_crb_class_init(ObjectClass *klass, void *data) +static void tpm_crb_none_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); TPMIfClass *tc = TPM_IF_CLASS(klass); - dc->realize = tpm_crb_realize; - device_class_set_props(dc, tpm_crb_properties); - dc->vmsd = &vmstate_tpm_crb; + dc->realize = tpm_crb_none_realize; + device_class_set_props(dc, tpm_crb_none_properties); + dc->vmsd = &vmstate_tpm_crb_none; dc->user_creatable = true; tc->model = TPM_MODEL_TPM_CRB; - tc->get_version = tpm_crb_get_version; - tc->request_completed = tpm_crb_request_completed; + tc->get_version = tpm_crb_none_get_version; + tc->request_completed = tpm_crb_none_request_completed; set_bit(DEVICE_CATEGORY_MISC, dc->categories); } -static const TypeInfo tpm_crb_info = { +static const TypeInfo tpm_crb_none_info = { .name = TYPE_TPM_CRB, /* could be TYPE_SYS_BUS_DEVICE (or LPC etc) */ .parent = TYPE_DEVICE, .instance_size = sizeof(CRBState), - .class_init = tpm_crb_class_init, + .class_init = tpm_crb_none_class_init, .interfaces = (InterfaceInfo[]) { { TYPE_TPM_IF }, { } } }; -static void tpm_crb_register(void) +static void tpm_crb_none_register(void) { - type_register_static(&tpm_crb_info); + type_register_static(&tpm_crb_none_info); } -type_init(tpm_crb_register) +type_init(tpm_crb_none_register) diff --git a/hw/tpm/tpm_crb_common.c b/hw/tpm/tpm_crb_common.c new file mode 100644 index 0000000000..fa463f295f --- /dev/null +++ b/hw/tpm/tpm_crb_common.c @@ -0,0 +1,216 @@ +/* + * tpm_crb.c - QEMU's TPM CRB interface emulator + * + * Copyright (c) 2018 Red Hat, Inc. + * + * Authors: + * Marc-André Lureau + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + * tpm_crb is a device for TPM 2.0 Command Response Buffer (CRB) Interface + * as defined in TCG PC Client Platform TPM Profile (PTP) Specification + * Family “2.0” Level 00 Revision 01.03 v22 + */ + +#include "qemu/osdep.h" + +#include "qemu/module.h" +#include "qapi/error.h" +#include "exec/address-spaces.h" +#include "hw/qdev-properties.h" +#include "hw/pci/pci_ids.h" +#include "hw/acpi/tpm.h" +#include "migration/vmstate.h" +#include "sysemu/tpm_backend.h" +#include "sysemu/tpm_util.h" +#include "tpm_prop.h" +#include "tpm_ppi.h" +#include "trace.h" +#include "qom/object.h" +#include "tpm_crb.h" + +static uint64_t tpm_crb_mmio_read(void *opaque, hwaddr addr, + unsigned size) +{ + TPMCRBState *s = opaque; + void *regs = (void *)&s->regs + (addr & ~3); + unsigned offset = addr & 3; + uint32_t val = *(uint32_t *)regs >> (8 * offset); + + switch (addr) { + case A_CRB_LOC_STATE: + val |= !tpm_backend_get_tpm_established_flag(s->tpmbe); + break; + } + + trace_tpm_crb_mmio_read(addr, size, val); + + return val; +} + +static uint8_t tpm_crb_get_active_locty(TPMCRBState *s) +{ + if (!ARRAY_FIELD_EX32(s->regs, CRB_LOC_STATE, locAssigned)) { + return TPM_CRB_NO_LOCALITY; + } + return ARRAY_FIELD_EX32(s->regs, CRB_LOC_STATE, activeLocality); +} + +static void tpm_crb_mmio_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + TPMCRBState *s = opaque; + uint8_t locty = addr >> 12; + + trace_tpm_crb_mmio_write(addr, size, val); + + switch (addr) { + case A_CRB_CTRL_REQ: + switch (val) { + case CRB_CTRL_REQ_CMD_READY: + ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, + tpmIdle, 0); + break; + case CRB_CTRL_REQ_GO_IDLE: + ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, + tpmIdle, 1); + break; + } + break; + case A_CRB_CTRL_CANCEL: + if (val == CRB_CANCEL_INVOKE && + s->regs[R_CRB_CTRL_START] & CRB_START_INVOKE) { + tpm_backend_cancel_cmd(s->tpmbe); + } + break; + case A_CRB_CTRL_START: + if (val == CRB_START_INVOKE && + !(s->regs[R_CRB_CTRL_START] & CRB_START_INVOKE) && + tpm_crb_get_active_locty(s) == locty) { + void *mem = memory_region_get_ram_ptr(&s->cmdmem); + + s->regs[R_CRB_CTRL_START] |= CRB_START_INVOKE; + s->cmd = (TPMBackendCmd) { + .in = mem, + .in_len = MIN(tpm_cmd_get_size(mem), s->be_buffer_size), + .out = mem, + .out_len = s->be_buffer_size, + }; + + tpm_backend_deliver_request(s->tpmbe, &s->cmd); + } + break; + case A_CRB_LOC_CTRL: + switch (val) { + case CRB_LOC_CTRL_RESET_ESTABLISHMENT_BIT: + /* not loc 3 or 4 */ + break; + case CRB_LOC_CTRL_RELINQUISH: + ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, + locAssigned, 0); + ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, + Granted, 0); + break; + case CRB_LOC_CTRL_REQUEST_ACCESS: + ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, + Granted, 1); + ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, + beenSeized, 0); + ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, + locAssigned, 1); + break; + } + break; + } +} + +const MemoryRegionOps tpm_crb_memory_ops = { + .read = tpm_crb_mmio_read, + .write = tpm_crb_mmio_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 4, + }, +}; + +void tpm_crb_request_completed(TPMCRBState *s, int ret) +{ + s->regs[R_CRB_CTRL_START] &= ~CRB_START_INVOKE; + if (ret != 0) { + ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, + tpmSts, 1); /* fatal error */ + } + memory_region_set_dirty(&s->cmdmem, 0, CRB_CTRL_CMD_SIZE); +} + +enum TPMVersion tpm_crb_get_version(TPMCRBState *s) +{ + return tpm_backend_get_tpm_version(s->tpmbe); +} + +int tpm_crb_pre_save(TPMCRBState *s) +{ + tpm_backend_finish_sync(s->tpmbe); + + return 0; +} + +void tpm_crb_reset(TPMCRBState *s, uint64_t baseaddr) +{ + if (s->ppi_enabled) { + tpm_ppi_reset(&s->ppi); + } + tpm_backend_reset(s->tpmbe); + + memset(s->regs, 0, sizeof(s->regs)); + + ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, + tpmRegValidSts, 1); + ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, + tpmIdle, 1); + ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + InterfaceType, CRB_INTF_TYPE_CRB_ACTIVE); + ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + InterfaceVersion, CRB_INTF_VERSION_CRB); + ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + CapLocality, CRB_INTF_CAP_LOCALITY_0_ONLY); + ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + CapCRBIdleBypass, CRB_INTF_CAP_IDLE_FAST); + ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + CapDataXferSizeSupport, CRB_INTF_CAP_XFER_SIZE_64); + ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + CapFIFO, CRB_INTF_CAP_FIFO_NOT_SUPPORTED); + ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + CapCRB, CRB_INTF_CAP_CRB_SUPPORTED); + ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + InterfaceSelector, CRB_INTF_IF_SELECTOR_CRB); + ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + RID, 0b0000); + ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID2, + VID, PCI_VENDOR_ID_IBM); + + baseaddr += A_CRB_DATA_BUFFER; + s->regs[R_CRB_CTRL_CMD_SIZE] = CRB_CTRL_CMD_SIZE; + s->regs[R_CRB_CTRL_CMD_LADDR] = (uint32_t)baseaddr; + s->regs[R_CRB_CTRL_CMD_HADDR] = (uint32_t)(baseaddr >> 32); + s->regs[R_CRB_CTRL_RSP_SIZE] = CRB_CTRL_CMD_SIZE; + s->regs[R_CRB_CTRL_RSP_ADDR] = (uint32_t)baseaddr; + + s->be_buffer_size = MIN(tpm_backend_get_buffer_size(s->tpmbe), + CRB_CTRL_CMD_SIZE); + + if (tpm_backend_startup_tpm(s->tpmbe, s->be_buffer_size) < 0) { + exit(1); + } +} + +void tpm_crb_init_memory(Object *obj, TPMCRBState *s, Error **errp) +{ + memory_region_init_io(&s->mmio, obj, &tpm_crb_memory_ops, s, + "tpm-crb-mmio", sizeof(s->regs)); + memory_region_init_ram(&s->cmdmem, obj, + "tpm-crb-cmd", CRB_CTRL_CMD_SIZE, errp); +} diff --git a/hw/tpm/meson.build b/hw/tpm/meson.build index 6968e60b3f..cb8204d5bc 100644 --- a/hw/tpm/meson.build +++ b/hw/tpm/meson.build @@ -3,6 +3,7 @@ system_ss.add(when: 'CONFIG_TPM_TIS_ISA', if_true: files('tpm_tis_isa.c')) system_ss.add(when: 'CONFIG_TPM_TIS_SYSBUS', if_true: files('tpm_tis_sysbus.c')) system_ss.add(when: 'CONFIG_TPM_TIS_I2C', if_true: files('tpm_tis_i2c.c')) system_ss.add(when: 'CONFIG_TPM_CRB', if_true: files('tpm_crb.c')) +system_ss.add(when: 'CONFIG_TPM_CRB', if_true: files('tpm_crb_common.c')) system_ss.add(when: 'CONFIG_TPM_TIS', if_true: files('tpm_ppi.c')) system_ss.add(when: 'CONFIG_TPM_CRB', if_true: files('tpm_ppi.c')) diff --git a/hw/tpm/trace-events b/hw/tpm/trace-events index fa882dfefe..3ab1bdb97b 100644 --- a/hw/tpm/trace-events +++ b/hw/tpm/trace-events @@ -1,6 +1,6 @@ # See docs/devel/tracing.rst for syntax documentation. -# tpm_crb.c +# tpm_crb_common.c tpm_crb_mmio_read(uint64_t addr, unsigned size, uint32_t val) "CRB read 0x%016" PRIx64 " len:%u val: 0x%" PRIx32 tpm_crb_mmio_write(uint64_t addr, unsigned size, uint32_t val) "CRB write 0x%016" PRIx64 " len:%u val: 0x%" PRIx32 From patchwork Tue Nov 14 02:09:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13454725 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E8B9DC4332F for ; Tue, 14 Nov 2023 02:11:13 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r2is0-0001G8-TT; Mon, 13 Nov 2023 21:09:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r2irz-0001Fj-2k for qemu-devel@nongnu.org; Mon, 13 Nov 2023 21:09:39 -0500 Received: from mail-pg1-f176.google.com ([209.85.215.176]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r2irx-0007ZM-G1 for qemu-devel@nongnu.org; Mon, 13 Nov 2023 21:09:38 -0500 Received: by mail-pg1-f176.google.com with SMTP id 41be03b00d2f7-5c18a3387f5so1018349a12.1 for ; Mon, 13 Nov 2023 18:09:37 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699927776; x=1700532576; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NYf3Mp/7wpNrEOrqYg1zrC2cEXg6lKB+hhoqy9GgIhw=; b=ZiIbb6+GjrbLwRlNoBtQuSmfZc9kWPL2CF1GfqlIqN7dEhte0rFHz2SuMq+0hbO6Bf 5nv4buGeZLIK0oJ+KXmRAGP2F6Fo1wu2hOtwq6c76WARIV81YoMzaRkngOe6J/8XfAge oQK6r77ufoeO945MRfV56PelSyG/LTXuNvLgfid65hNebggiPCQ6SQE3RBVsyZN5Be/r UR63eTdE1n6kOnHS+B1P/gzH1gVYZTV7OcmVxp26/7fw74hZtyL1WRmTx1zQ/AY9Sdr3 xfW6GSEHuD8GdP8Dm4PfgXenivw3UjqmZWof/2rwb61BXb1Ie2jyf3uoLZ7EIWflIWvT RFpQ== X-Gm-Message-State: AOJu0YzS6MvisuLkgrfTdb72HQtcPflkF7rpU7xxqFjgZUB1N6JNH8gC FcgU439chlMvSzZ2Dzj5/gv47xpoJ2xVcA== X-Google-Smtp-Source: AGHT+IE2HiFsrm0XSh7nZv097dnZL3mwIdNea176u/c0VjmS2NSpCQZTy1wEVtOMWxBoj6ToqdDIXQ== X-Received: by 2002:a17:90b:3b43:b0:27d:6b5:9e07 with SMTP id ot3-20020a17090b3b4300b0027d06b59e07mr6318423pjb.1.1699927776039; Mon, 13 Nov 2023 18:09:36 -0800 (PST) Received: from localhost.localdomain ([2601:642:4c01:2f7:5d09:c219:9099:a639]) by smtp.gmail.com with ESMTPSA id g13-20020a17090ae58d00b0027d12b1e29dsm6175362pjz.25.2023.11.13.18.09.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Nov 2023 18:09:34 -0800 (PST) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Stefan Berger , Stefan Berger , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha , Thomas Huth , Laurent Vivier , Paolo Bonzini Subject: [PATCH v5 02/14] tpm_crb: CTRL_RSP_ADDR is 64-bits wide Date: Mon, 13 Nov 2023 18:09:12 -0800 Message-ID: <20231114020927.62315-3-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231114020927.62315-1-j@getutm.app> References: <20231114020927.62315-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.176; envelope-from=osy86dev@gmail.com; helo=mail-pg1-f176.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The register is actually 64-bits but in order to make this more clear than the specification, we define two 32-bit registers: CTRL_RSP_LADDR and CTRL_RSP_HADDR to match the CTRL_CMD_* naming. This deviates from the specs but is way more clear. Previously, the only CRB device uses a fixed system address so this was not an issue. However, once we support SysBus CRB device, the address can be anywhere in 64-bit space. Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- include/hw/acpi/tpm.h | 3 ++- hw/tpm/tpm_crb_common.c | 3 ++- tests/qtest/tpm-crb-test.c | 2 +- tests/qtest/tpm-util.c | 2 +- 4 files changed, 6 insertions(+), 4 deletions(-) diff --git a/include/hw/acpi/tpm.h b/include/hw/acpi/tpm.h index 579c45f5ba..f60bfe2789 100644 --- a/include/hw/acpi/tpm.h +++ b/include/hw/acpi/tpm.h @@ -174,7 +174,8 @@ REG32(CRB_CTRL_CMD_SIZE, 0x58) REG32(CRB_CTRL_CMD_LADDR, 0x5C) REG32(CRB_CTRL_CMD_HADDR, 0x60) REG32(CRB_CTRL_RSP_SIZE, 0x64) -REG32(CRB_CTRL_RSP_ADDR, 0x68) +REG32(CRB_CTRL_RSP_LADDR, 0x68) +REG32(CRB_CTRL_RSP_HADDR, 0x6C) REG32(CRB_DATA_BUFFER, 0x80) #define TPM_CRB_ADDR_BASE 0xFED40000 diff --git a/hw/tpm/tpm_crb_common.c b/hw/tpm/tpm_crb_common.c index fa463f295f..01b35808f6 100644 --- a/hw/tpm/tpm_crb_common.c +++ b/hw/tpm/tpm_crb_common.c @@ -197,7 +197,8 @@ void tpm_crb_reset(TPMCRBState *s, uint64_t baseaddr) s->regs[R_CRB_CTRL_CMD_LADDR] = (uint32_t)baseaddr; s->regs[R_CRB_CTRL_CMD_HADDR] = (uint32_t)(baseaddr >> 32); s->regs[R_CRB_CTRL_RSP_SIZE] = CRB_CTRL_CMD_SIZE; - s->regs[R_CRB_CTRL_RSP_ADDR] = (uint32_t)baseaddr; + s->regs[R_CRB_CTRL_RSP_LADDR] = (uint32_t)baseaddr; + s->regs[R_CRB_CTRL_RSP_HADDR] = (uint32_t)(baseaddr >> 32); s->be_buffer_size = MIN(tpm_backend_get_buffer_size(s->tpmbe), CRB_CTRL_CMD_SIZE); diff --git a/tests/qtest/tpm-crb-test.c b/tests/qtest/tpm-crb-test.c index 396ae3f91c..9d30fe8293 100644 --- a/tests/qtest/tpm-crb-test.c +++ b/tests/qtest/tpm-crb-test.c @@ -28,7 +28,7 @@ static void tpm_crb_test(const void *data) uint32_t csize = readl(TPM_CRB_ADDR_BASE + A_CRB_CTRL_CMD_SIZE); uint64_t caddr = readq(TPM_CRB_ADDR_BASE + A_CRB_CTRL_CMD_LADDR); uint32_t rsize = readl(TPM_CRB_ADDR_BASE + A_CRB_CTRL_RSP_SIZE); - uint64_t raddr = readq(TPM_CRB_ADDR_BASE + A_CRB_CTRL_RSP_ADDR); + uint64_t raddr = readq(TPM_CRB_ADDR_BASE + A_CRB_CTRL_RSP_LADDR); uint8_t locstate = readb(TPM_CRB_ADDR_BASE + A_CRB_LOC_STATE); uint32_t locctrl = readl(TPM_CRB_ADDR_BASE + A_CRB_LOC_CTRL); uint32_t locsts = readl(TPM_CRB_ADDR_BASE + A_CRB_LOC_STS); diff --git a/tests/qtest/tpm-util.c b/tests/qtest/tpm-util.c index 1c0319e6e7..dd02057fc0 100644 --- a/tests/qtest/tpm-util.c +++ b/tests/qtest/tpm-util.c @@ -25,7 +25,7 @@ void tpm_util_crb_transfer(QTestState *s, unsigned char *rsp, size_t rsp_size) { uint64_t caddr = qtest_readq(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_CMD_LADDR); - uint64_t raddr = qtest_readq(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_RSP_ADDR); + uint64_t raddr = qtest_readq(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_RSP_LADDR); qtest_writeb(s, TPM_CRB_ADDR_BASE + A_CRB_LOC_CTRL, 1); From patchwork Tue Nov 14 02:09:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13454734 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 62029C4167B for ; Tue, 14 Nov 2023 02:12:26 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r2is2-0001Gl-48; Mon, 13 Nov 2023 21:09:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r2is0-0001Fy-CC for qemu-devel@nongnu.org; Mon, 13 Nov 2023 21:09:40 -0500 Received: from mail-pg1-f176.google.com ([209.85.215.176]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r2iry-0007ZV-QU for qemu-devel@nongnu.org; Mon, 13 Nov 2023 21:09:40 -0500 Received: by mail-pg1-f176.google.com with SMTP id 41be03b00d2f7-5bda105206fso3541585a12.3 for ; Mon, 13 Nov 2023 18:09:38 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699927777; x=1700532577; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CnroBZ0wk45t3A1wwABp8NCUEpsFnTDAcOrQjgGFhUQ=; b=o10T4ZkUFLF0nF1PE1RnjmV2s+sHjkbSjeDsR9/9/uNJWjEdIY/6F/kAaYd4j+GQ9U LxhU0UbC1yRLvpnsD6GlQKw61WbEVrPK19yePNiAhde0KSE5O90XfWY6kp9ET3qVQzMs u5ZwVUeoxE4psNCf/O7XUSjTBWej+tajIDlOP/9U1eJ+IGC4GWIYgu4X7sYDKlCnscJh h+sSH1mUryT7aGmM9u/lUywwKRDKakG9QdBmH08G2HiCqoz6ecByeOoBZ9m43qHI+yg6 9qcZJ74G5qGN5iaGw5aIdaIq86G+/XdRCaRlp4DL8BseKYCV/GKrwWyv3zkneFhIEx5O 1liA== X-Gm-Message-State: AOJu0YzOw8mFm0J/ObSvbFvWPzTNQK//x+C+5dZXsoO/Wl1RvFhyraVX Bs8LH+nI4dqt6mzmRub66gmXgnLhpGrgBg== X-Google-Smtp-Source: AGHT+IFpRUUcItGcC4QvPuybbErAnVk+qouZvZ2hE4h73sJHfR4G3TOTH3uifD9fIbxVfTQzUZOLlA== X-Received: by 2002:a05:6a20:daa9:b0:172:83b8:67f8 with SMTP id iy41-20020a056a20daa900b0017283b867f8mr6962118pzb.29.1699927777310; Mon, 13 Nov 2023 18:09:37 -0800 (PST) Received: from localhost.localdomain ([2601:642:4c01:2f7:5d09:c219:9099:a639]) by smtp.gmail.com with ESMTPSA id g13-20020a17090ae58d00b0027d12b1e29dsm6175362pjz.25.2023.11.13.18.09.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Nov 2023 18:09:36 -0800 (PST) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Stefan Berger , Stefan Berger Subject: [PATCH v5 03/14] tpm_ppi: refactor memory space initialization Date: Mon, 13 Nov 2023 18:09:13 -0800 Message-ID: <20231114020927.62315-4-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231114020927.62315-1-j@getutm.app> References: <20231114020927.62315-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.176; envelope-from=osy86dev@gmail.com; helo=mail-pg1-f176.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Instead of calling `memory_region_add_subregion` directly, we defer to the caller to do it. This allows us to re-use the code for a SysBus device. Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- hw/tpm/tpm_ppi.h | 10 +++------- hw/tpm/tpm_crb.c | 4 ++-- hw/tpm/tpm_crb_common.c | 3 +++ hw/tpm/tpm_ppi.c | 5 +---- hw/tpm/tpm_tis_isa.c | 5 +++-- 5 files changed, 12 insertions(+), 15 deletions(-) diff --git a/hw/tpm/tpm_ppi.h b/hw/tpm/tpm_ppi.h index bf5d4a300f..30863c6438 100644 --- a/hw/tpm/tpm_ppi.h +++ b/hw/tpm/tpm_ppi.h @@ -20,17 +20,13 @@ typedef struct TPMPPI { } TPMPPI; /** - * tpm_ppi_init: + * tpm_ppi_init_memory: * @tpmppi: a TPMPPI - * @m: the address-space / MemoryRegion to use - * @addr: the address of the PPI region * @obj: the owner object * - * Register the TPM PPI memory region at @addr on the given address - * space for the object @obj. + * Creates the TPM PPI memory region. **/ -void tpm_ppi_init(TPMPPI *tpmppi, MemoryRegion *m, - hwaddr addr, Object *obj); +void tpm_ppi_init_memory(TPMPPI *tpmppi, Object *obj); /** * tpm_ppi_reset: diff --git a/hw/tpm/tpm_crb.c b/hw/tpm/tpm_crb.c index 3ef4977fb5..598c3e0161 100644 --- a/hw/tpm/tpm_crb.c +++ b/hw/tpm/tpm_crb.c @@ -107,8 +107,8 @@ static void tpm_crb_none_realize(DeviceState *dev, Error **errp) TPM_CRB_ADDR_BASE + sizeof(s->state.regs), &s->state.cmdmem); if (s->state.ppi_enabled) { - tpm_ppi_init(&s->state.ppi, get_system_memory(), - TPM_PPI_ADDR_BASE, OBJECT(s)); + memory_region_add_subregion(get_system_memory(), + TPM_PPI_ADDR_BASE, &s->state.ppi.ram); } if (xen_enabled()) { diff --git a/hw/tpm/tpm_crb_common.c b/hw/tpm/tpm_crb_common.c index 01b35808f6..bee0b71fee 100644 --- a/hw/tpm/tpm_crb_common.c +++ b/hw/tpm/tpm_crb_common.c @@ -214,4 +214,7 @@ void tpm_crb_init_memory(Object *obj, TPMCRBState *s, Error **errp) "tpm-crb-mmio", sizeof(s->regs)); memory_region_init_ram(&s->cmdmem, obj, "tpm-crb-cmd", CRB_CTRL_CMD_SIZE, errp); + if (s->ppi_enabled) { + tpm_ppi_init_memory(&s->ppi, obj); + } } diff --git a/hw/tpm/tpm_ppi.c b/hw/tpm/tpm_ppi.c index 7f74e26ec6..40cab59afa 100644 --- a/hw/tpm/tpm_ppi.c +++ b/hw/tpm/tpm_ppi.c @@ -44,14 +44,11 @@ void tpm_ppi_reset(TPMPPI *tpmppi) } } -void tpm_ppi_init(TPMPPI *tpmppi, MemoryRegion *m, - hwaddr addr, Object *obj) +void tpm_ppi_init_memory(TPMPPI *tpmppi, Object *obj) { tpmppi->buf = qemu_memalign(qemu_real_host_page_size(), HOST_PAGE_ALIGN(TPM_PPI_ADDR_SIZE)); memory_region_init_ram_device_ptr(&tpmppi->ram, obj, "tpm-ppi", TPM_PPI_ADDR_SIZE, tpmppi->buf); vmstate_register_ram(&tpmppi->ram, DEVICE(obj)); - - memory_region_add_subregion(m, addr, &tpmppi->ram); } diff --git a/hw/tpm/tpm_tis_isa.c b/hw/tpm/tpm_tis_isa.c index 0367401586..d596f38c0f 100644 --- a/hw/tpm/tpm_tis_isa.c +++ b/hw/tpm/tpm_tis_isa.c @@ -134,8 +134,9 @@ static void tpm_tis_isa_realizefn(DeviceState *dev, Error **errp) TPM_TIS_ADDR_BASE, &s->mmio); if (s->ppi_enabled) { - tpm_ppi_init(&s->ppi, isa_address_space(ISA_DEVICE(dev)), - TPM_PPI_ADDR_BASE, OBJECT(dev)); + tpm_ppi_init_memory(&s->ppi, OBJECT(dev)); + memory_region_add_subregion(isa_address_space(ISA_DEVICE(dev)), + TPM_PPI_ADDR_BASE, &s->ppi.ram); } } From patchwork Tue Nov 14 02:09:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13454736 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8A1B7C4332F for ; Tue, 14 Nov 2023 02:13:11 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r2is3-0001HJ-VP; Mon, 13 Nov 2023 21:09:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r2is2-0001Gp-Hq for qemu-devel@nongnu.org; Mon, 13 Nov 2023 21:09:42 -0500 Received: from mail-pf1-f172.google.com ([209.85.210.172]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r2is0-0007Zm-CU for qemu-devel@nongnu.org; Mon, 13 Nov 2023 21:09:42 -0500 Received: by mail-pf1-f172.google.com with SMTP id d2e1a72fcca58-6b20577ef7bso4368055b3a.3 for ; Mon, 13 Nov 2023 18:09:40 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699927779; x=1700532579; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=O077A+OJgWAErBfe2ZVGhyw2GZF8WV+Cs7nZbHI73FU=; b=Y4LFcoeURt1YszBkJAKQDzs5xEiqrio3+dZrBAdInXZKDnPJxZ7TcRJ0S3FZg4yBe5 OpEIDzUL/mXnbByzaBLPfL8UjFuobs+1oLC5sKi7Sn6wD3+mYWOiOM3Eh0vRhxFmpvN2 lJgC3b0ufczFv6PiC+polrqsnfSCpwsjNxj2NFzjBQoSd3BOaVvUjzxh8rXeoET0wreR Bzz3HXwFVt0UtPAxBREF6n/SZgAzBENivVjF30j8TpSbsQLgKXOIQEJlD2G9KMggxvH+ n5orL4EzWZtHxHFGutcH8dmzvxWXN4YbzGYwxHaFIZajyNFSBNHO1nzBwZFWLRba1y5t J2nA== X-Gm-Message-State: AOJu0Yx4I/vWzrTerLR0ryn+o6EDRkG9kd4TprhV8Lk7lNQNmyESxSDQ die/f/aH01rzCWcVj4qip6BZagq2i2pAFQ== X-Google-Smtp-Source: AGHT+IHO2MPBGIIkY/Lkj3J8uGOqB0Gvgf3mYsy9Y4C8kxKJUlBNAFMY0Y+JAwKeXM4GO1todONmFw== X-Received: by 2002:a05:6a20:3d01:b0:159:dccb:8bb4 with SMTP id y1-20020a056a203d0100b00159dccb8bb4mr7118068pzi.23.1699927778900; Mon, 13 Nov 2023 18:09:38 -0800 (PST) Received: from localhost.localdomain ([2601:642:4c01:2f7:5d09:c219:9099:a639]) by smtp.gmail.com with ESMTPSA id g13-20020a17090ae58d00b0027d12b1e29dsm6175362pjz.25.2023.11.13.18.09.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Nov 2023 18:09:38 -0800 (PST) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Stefan Berger Subject: [PATCH v5 04/14] tpm_crb: use a single read-as-mem/write-as-mmio mapping Date: Mon, 13 Nov 2023 18:09:14 -0800 Message-ID: <20231114020927.62315-5-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231114020927.62315-1-j@getutm.app> References: <20231114020927.62315-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.210.172; envelope-from=osy86dev@gmail.com; helo=mail-pf1-f172.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Apple Silicon, when Windows performs a LDP on the CRB MMIO space, the exception is not decoded by hardware and we cannot trap the MMIO read. This led to the idea from @agraf to use the same mapping type as ROM devices: namely that reads should be seen as memory type and writes should trap as MMIO. Once that was done, the second memory mapping of the command buffer region was redundent and was removed. A note about the removal of the read trap for `CRB_LOC_STATE`: The only usage was to return the most up-to-date value for `tpmEstablished`. However, `tpmEstablished` is only cleared when a TPM2_HashStart operation is called which only exists for locality 4. We do not handle locality 4. Indeed, the comment for the write handler of `CRB_LOC_CTRL` makes the same argument for why it is not calling the backend to reset the `tpmEstablished` bit (to 1). As this bit is unused, we do not need to worry about updating it for reads. In order to maintain migration compatibility with older versions of QEMU, we store a copy of the register data and command data which is used only during save/restore. Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- hw/tpm/tpm_crb.h | 5 +- hw/tpm/tpm_crb.c | 30 ++++++++- hw/tpm/tpm_crb_common.c | 145 +++++++++++++++++++++++----------------- 3 files changed, 114 insertions(+), 66 deletions(-) diff --git a/hw/tpm/tpm_crb.h b/hw/tpm/tpm_crb.h index da3a0cf256..36863e1664 100644 --- a/hw/tpm/tpm_crb.h +++ b/hw/tpm/tpm_crb.h @@ -26,9 +26,7 @@ typedef struct TPMCRBState { TPMBackend *tpmbe; TPMBackendCmd cmd; - uint32_t regs[TPM_CRB_R_MAX]; MemoryRegion mmio; - MemoryRegion cmdmem; size_t be_buffer_size; @@ -72,5 +70,8 @@ enum TPMVersion tpm_crb_get_version(TPMCRBState *s); int tpm_crb_pre_save(TPMCRBState *s); void tpm_crb_reset(TPMCRBState *s, uint64_t baseaddr); void tpm_crb_init_memory(Object *obj, TPMCRBState *s, Error **errp); +void tpm_crb_mem_save(TPMCRBState *s, uint32_t *saved_regs, void *saved_cmdmem); +void tpm_crb_mem_load(TPMCRBState *s, const uint32_t *saved_regs, + const void *saved_cmdmem); #endif /* TPM_TPM_CRB_H */ diff --git a/hw/tpm/tpm_crb.c b/hw/tpm/tpm_crb.c index 598c3e0161..99c64dd72a 100644 --- a/hw/tpm/tpm_crb.c +++ b/hw/tpm/tpm_crb.c @@ -37,6 +37,10 @@ struct CRBState { DeviceState parent_obj; TPMCRBState state; + + /* These states are only for migration */ + uint32_t saved_regs[TPM_CRB_R_MAX]; + MemoryRegion saved_cmdmem; }; typedef struct CRBState CRBState; @@ -57,18 +61,36 @@ static enum TPMVersion tpm_crb_none_get_version(TPMIf *ti) return tpm_crb_get_version(&s->state); } +/** + * For migrating to an older version of QEMU + */ static int tpm_crb_none_pre_save(void *opaque) { CRBState *s = opaque; + void *saved_cmdmem = memory_region_get_ram_ptr(&s->saved_cmdmem); + tpm_crb_mem_save(&s->state, s->saved_regs, saved_cmdmem); return tpm_crb_pre_save(&s->state); } +/** + * For migrating from an older version of QEMU + */ +static int tpm_crb_none_post_load(void *opaque, int version_id) +{ + CRBState *s = opaque; + void *saved_cmdmem = memory_region_get_ram_ptr(&s->saved_cmdmem); + + tpm_crb_mem_load(&s->state, s->saved_regs, saved_cmdmem); + return 0; +} + static const VMStateDescription vmstate_tpm_crb_none = { .name = "tpm-crb", .pre_save = tpm_crb_none_pre_save, + .post_load = tpm_crb_none_post_load, .fields = (VMStateField[]) { - VMSTATE_UINT32_ARRAY(state.regs, CRBState, TPM_CRB_R_MAX), + VMSTATE_UINT32_ARRAY(saved_regs, CRBState, TPM_CRB_R_MAX), VMSTATE_END_OF_LIST(), } }; @@ -101,10 +123,12 @@ static void tpm_crb_none_realize(DeviceState *dev, Error **errp) tpm_crb_init_memory(OBJECT(s), &s->state, errp); + /* only used for migration */ + memory_region_init_ram(&s->saved_cmdmem, OBJECT(s), + "tpm-crb-cmd", CRB_CTRL_CMD_SIZE, errp); + memory_region_add_subregion(get_system_memory(), TPM_CRB_ADDR_BASE, &s->state.mmio); - memory_region_add_subregion(get_system_memory(), - TPM_CRB_ADDR_BASE + sizeof(s->state.regs), &s->state.cmdmem); if (s->state.ppi_enabled) { memory_region_add_subregion(get_system_memory(), diff --git a/hw/tpm/tpm_crb_common.c b/hw/tpm/tpm_crb_common.c index bee0b71fee..f96a8cf299 100644 --- a/hw/tpm/tpm_crb_common.c +++ b/hw/tpm/tpm_crb_common.c @@ -31,31 +31,12 @@ #include "qom/object.h" #include "tpm_crb.h" -static uint64_t tpm_crb_mmio_read(void *opaque, hwaddr addr, - unsigned size) +static uint8_t tpm_crb_get_active_locty(TPMCRBState *s, uint32_t *regs) { - TPMCRBState *s = opaque; - void *regs = (void *)&s->regs + (addr & ~3); - unsigned offset = addr & 3; - uint32_t val = *(uint32_t *)regs >> (8 * offset); - - switch (addr) { - case A_CRB_LOC_STATE: - val |= !tpm_backend_get_tpm_established_flag(s->tpmbe); - break; - } - - trace_tpm_crb_mmio_read(addr, size, val); - - return val; -} - -static uint8_t tpm_crb_get_active_locty(TPMCRBState *s) -{ - if (!ARRAY_FIELD_EX32(s->regs, CRB_LOC_STATE, locAssigned)) { + if (!ARRAY_FIELD_EX32(regs, CRB_LOC_STATE, locAssigned)) { return TPM_CRB_NO_LOCALITY; } - return ARRAY_FIELD_EX32(s->regs, CRB_LOC_STATE, activeLocality); + return ARRAY_FIELD_EX32(regs, CRB_LOC_STATE, activeLocality); } static void tpm_crb_mmio_write(void *opaque, hwaddr addr, @@ -63,35 +44,49 @@ static void tpm_crb_mmio_write(void *opaque, hwaddr addr, { TPMCRBState *s = opaque; uint8_t locty = addr >> 12; + uint32_t *regs; + void *mem; trace_tpm_crb_mmio_write(addr, size, val); + regs = memory_region_get_ram_ptr(&s->mmio); + mem = ®s[R_CRB_DATA_BUFFER]; + assert(regs); + + /* receive TPM command bytes in DATA_BUFFER */ + if (addr >= A_CRB_DATA_BUFFER) { + assert(addr + size <= TPM_CRB_ADDR_SIZE); + assert(size <= sizeof(val)); + memcpy(mem + addr - A_CRB_DATA_BUFFER, &val, size); + memory_region_set_dirty(&s->mmio, addr, size); + return; + } + /* otherwise we are doing MMIO writes */ switch (addr) { case A_CRB_CTRL_REQ: switch (val) { case CRB_CTRL_REQ_CMD_READY: - ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, + ARRAY_FIELD_DP32(regs, CRB_CTRL_STS, tpmIdle, 0); break; case CRB_CTRL_REQ_GO_IDLE: - ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, + ARRAY_FIELD_DP32(regs, CRB_CTRL_STS, tpmIdle, 1); break; } break; case A_CRB_CTRL_CANCEL: if (val == CRB_CANCEL_INVOKE && - s->regs[R_CRB_CTRL_START] & CRB_START_INVOKE) { + regs[R_CRB_CTRL_START] & CRB_START_INVOKE) { tpm_backend_cancel_cmd(s->tpmbe); } break; case A_CRB_CTRL_START: if (val == CRB_START_INVOKE && - !(s->regs[R_CRB_CTRL_START] & CRB_START_INVOKE) && - tpm_crb_get_active_locty(s) == locty) { - void *mem = memory_region_get_ram_ptr(&s->cmdmem); + !(regs[R_CRB_CTRL_START] & CRB_START_INVOKE) && + tpm_crb_get_active_locty(s, regs) == locty) { - s->regs[R_CRB_CTRL_START] |= CRB_START_INVOKE; + regs[R_CRB_CTRL_START] |= CRB_START_INVOKE; s->cmd = (TPMBackendCmd) { .in = mem, .in_len = MIN(tpm_cmd_get_size(mem), s->be_buffer_size), @@ -108,26 +103,27 @@ static void tpm_crb_mmio_write(void *opaque, hwaddr addr, /* not loc 3 or 4 */ break; case CRB_LOC_CTRL_RELINQUISH: - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, + ARRAY_FIELD_DP32(regs, CRB_LOC_STATE, locAssigned, 0); - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, + ARRAY_FIELD_DP32(regs, CRB_LOC_STS, Granted, 0); break; case CRB_LOC_CTRL_REQUEST_ACCESS: - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, + ARRAY_FIELD_DP32(regs, CRB_LOC_STS, Granted, 1); - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, + ARRAY_FIELD_DP32(regs, CRB_LOC_STS, beenSeized, 0); - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, + ARRAY_FIELD_DP32(regs, CRB_LOC_STATE, locAssigned, 1); break; } break; } + + memory_region_set_dirty(&s->mmio, 0, A_CRB_DATA_BUFFER); } const MemoryRegionOps tpm_crb_memory_ops = { - .read = tpm_crb_mmio_read, .write = tpm_crb_mmio_write, .endianness = DEVICE_LITTLE_ENDIAN, .valid = { @@ -138,12 +134,16 @@ const MemoryRegionOps tpm_crb_memory_ops = { void tpm_crb_request_completed(TPMCRBState *s, int ret) { - s->regs[R_CRB_CTRL_START] &= ~CRB_START_INVOKE; + uint32_t *regs = memory_region_get_ram_ptr(&s->mmio); + + assert(regs); + regs[R_CRB_CTRL_START] &= ~CRB_START_INVOKE; if (ret != 0) { - ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, + ARRAY_FIELD_DP32(regs, CRB_CTRL_STS, tpmSts, 1); /* fatal error */ } - memory_region_set_dirty(&s->cmdmem, 0, CRB_CTRL_CMD_SIZE); + + memory_region_set_dirty(&s->mmio, 0, TPM_CRB_ADDR_SIZE); } enum TPMVersion tpm_crb_get_version(TPMCRBState *s) @@ -160,45 +160,50 @@ int tpm_crb_pre_save(TPMCRBState *s) void tpm_crb_reset(TPMCRBState *s, uint64_t baseaddr) { + uint32_t *regs = memory_region_get_ram_ptr(&s->mmio); + + assert(regs); if (s->ppi_enabled) { tpm_ppi_reset(&s->ppi); } tpm_backend_reset(s->tpmbe); - memset(s->regs, 0, sizeof(s->regs)); + memset(regs, 0, TPM_CRB_ADDR_SIZE); - ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, + ARRAY_FIELD_DP32(regs, CRB_LOC_STATE, tpmRegValidSts, 1); - ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, + ARRAY_FIELD_DP32(regs, CRB_LOC_STATE, + tpmEstablished, 1); + ARRAY_FIELD_DP32(regs, CRB_CTRL_STS, tpmIdle, 1); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + ARRAY_FIELD_DP32(regs, CRB_INTF_ID, InterfaceType, CRB_INTF_TYPE_CRB_ACTIVE); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + ARRAY_FIELD_DP32(regs, CRB_INTF_ID, InterfaceVersion, CRB_INTF_VERSION_CRB); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + ARRAY_FIELD_DP32(regs, CRB_INTF_ID, CapLocality, CRB_INTF_CAP_LOCALITY_0_ONLY); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + ARRAY_FIELD_DP32(regs, CRB_INTF_ID, CapCRBIdleBypass, CRB_INTF_CAP_IDLE_FAST); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + ARRAY_FIELD_DP32(regs, CRB_INTF_ID, CapDataXferSizeSupport, CRB_INTF_CAP_XFER_SIZE_64); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + ARRAY_FIELD_DP32(regs, CRB_INTF_ID, CapFIFO, CRB_INTF_CAP_FIFO_NOT_SUPPORTED); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + ARRAY_FIELD_DP32(regs, CRB_INTF_ID, CapCRB, CRB_INTF_CAP_CRB_SUPPORTED); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + ARRAY_FIELD_DP32(regs, CRB_INTF_ID, InterfaceSelector, CRB_INTF_IF_SELECTOR_CRB); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, + ARRAY_FIELD_DP32(regs, CRB_INTF_ID, RID, 0b0000); - ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID2, + ARRAY_FIELD_DP32(regs, CRB_INTF_ID2, VID, PCI_VENDOR_ID_IBM); baseaddr += A_CRB_DATA_BUFFER; - s->regs[R_CRB_CTRL_CMD_SIZE] = CRB_CTRL_CMD_SIZE; - s->regs[R_CRB_CTRL_CMD_LADDR] = (uint32_t)baseaddr; - s->regs[R_CRB_CTRL_CMD_HADDR] = (uint32_t)(baseaddr >> 32); - s->regs[R_CRB_CTRL_RSP_SIZE] = CRB_CTRL_CMD_SIZE; - s->regs[R_CRB_CTRL_RSP_LADDR] = (uint32_t)baseaddr; - s->regs[R_CRB_CTRL_RSP_HADDR] = (uint32_t)(baseaddr >> 32); + regs[R_CRB_CTRL_CMD_SIZE] = CRB_CTRL_CMD_SIZE; + regs[R_CRB_CTRL_CMD_LADDR] = (uint32_t)baseaddr; + regs[R_CRB_CTRL_CMD_HADDR] = (uint32_t)(baseaddr >> 32); + regs[R_CRB_CTRL_RSP_SIZE] = CRB_CTRL_CMD_SIZE; + regs[R_CRB_CTRL_RSP_LADDR] = (uint32_t)baseaddr; + regs[R_CRB_CTRL_RSP_HADDR] = (uint32_t)(baseaddr >> 32); s->be_buffer_size = MIN(tpm_backend_get_buffer_size(s->tpmbe), CRB_CTRL_CMD_SIZE); @@ -206,15 +211,33 @@ void tpm_crb_reset(TPMCRBState *s, uint64_t baseaddr) if (tpm_backend_startup_tpm(s->tpmbe, s->be_buffer_size) < 0) { exit(1); } + + memory_region_rom_device_set_romd(&s->mmio, true); + memory_region_set_dirty(&s->mmio, 0, TPM_CRB_ADDR_SIZE); } void tpm_crb_init_memory(Object *obj, TPMCRBState *s, Error **errp) { - memory_region_init_io(&s->mmio, obj, &tpm_crb_memory_ops, s, - "tpm-crb-mmio", sizeof(s->regs)); - memory_region_init_ram(&s->cmdmem, obj, - "tpm-crb-cmd", CRB_CTRL_CMD_SIZE, errp); + memory_region_init_rom_device_nomigrate(&s->mmio, obj, &tpm_crb_memory_ops, + s, "tpm-crb-mem", TPM_CRB_ADDR_SIZE, errp); if (s->ppi_enabled) { tpm_ppi_init_memory(&s->ppi, obj); } } + +void tpm_crb_mem_save(TPMCRBState *s, uint32_t *saved_regs, void *saved_cmdmem) +{ + uint32_t *regs = memory_region_get_ram_ptr(&s->mmio); + + memcpy(saved_regs, regs, A_CRB_DATA_BUFFER); + memcpy(saved_cmdmem, ®s[R_CRB_DATA_BUFFER], CRB_CTRL_CMD_SIZE); +} + +void tpm_crb_mem_load(TPMCRBState *s, const uint32_t *saved_regs, + const void *saved_cmdmem) +{ + uint32_t *regs = memory_region_get_ram_ptr(&s->mmio); + + memcpy(regs, saved_regs, A_CRB_DATA_BUFFER); + memcpy(®s[R_CRB_DATA_BUFFER], saved_cmdmem, CRB_CTRL_CMD_SIZE); +} From patchwork Tue Nov 14 02:09:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13454723 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BB578C4332F for ; Tue, 14 Nov 2023 02:10:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r2is6-0001Ja-MC; Mon, 13 Nov 2023 21:09:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r2is4-0001Hf-Ig for qemu-devel@nongnu.org; Mon, 13 Nov 2023 21:09:44 -0500 Received: from mail-pj1-f54.google.com ([209.85.216.54]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r2is2-0007aH-U1 for qemu-devel@nongnu.org; Mon, 13 Nov 2023 21:09:44 -0500 Received: by mail-pj1-f54.google.com with SMTP id 98e67ed59e1d1-282ff1a97dcso3283471a91.1 for ; Mon, 13 Nov 2023 18:09:42 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699927781; x=1700532581; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SFCjYhKVZnE2YpkIUkqgvjnf/2XFMF0OVXQFbD0oMKo=; b=c3/OdmPrV8zaDwv7olOsrH8/YDdSV0wPXbBJ3LMmpEdSxNgj7MrHNE5iQIzIjz60Bt Cew9e0L0Is0v7DXQA1W5QY77vmrfvPhJHxeKY1EEna8iSjGGWaPUbejEhMIIKCUOdprD 3QeA2EAhlxoQjJ1xfumbhxvn4VYuZGn7z/NHXjPkPZTWEzTN+JapnwC5SKzELQuvJO7x kpI9n4443SnzRphJrLRrojXNl2ShjdrqGTNby764M/WUk24LdyZZ0Vi/F6EoPZoJoHZ9 jIYG3ycyLtQXjp5dZebLHLl4peftb6YixOb5dAMpOcocZEELC3pLVtBCExox5oQ0yRzd MLJQ== X-Gm-Message-State: AOJu0YwNsA9EiU3KP/geNgI8E34zqkNJguacsIJqL4bSogSh35oSJEBD HEZNopW23CsqKY+SBVM98voNRdQRTPO+eA== X-Google-Smtp-Source: AGHT+IGcoiMj+cWOnxGxOijbZAYVGKi/+aacwULKuHlE9CCdTNSef4WOJNSFQFX5SUZOH3/GyvDxIg== X-Received: by 2002:a17:90b:4c89:b0:27e:3342:5c1f with SMTP id my9-20020a17090b4c8900b0027e33425c1fmr6172234pjb.43.1699927781397; Mon, 13 Nov 2023 18:09:41 -0800 (PST) Received: from localhost.localdomain ([2601:642:4c01:2f7:5d09:c219:9099:a639]) by smtp.gmail.com with ESMTPSA id g13-20020a17090ae58d00b0027d12b1e29dsm6175362pjz.25.2023.11.13.18.09.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Nov 2023 18:09:40 -0800 (PST) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum , Stefan Berger Subject: [PATCH v5 05/14] tpm_crb: move ACPI table building to device interface Date: Mon, 13 Nov 2023 18:09:15 -0800 Message-ID: <20231114020927.62315-6-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231114020927.62315-1-j@getutm.app> References: <20231114020927.62315-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.216.54; envelope-from=osy86dev@gmail.com; helo=mail-pj1-f54.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This logic is similar to TPM TIS ISA device. Since TPM CRB can only support TPM 2.0 backends, we check for this in realize. Signed-off-by: Joelle van Dyne --- hw/tpm/tpm_crb.h | 2 ++ hw/i386/acpi-build.c | 16 +--------------- hw/tpm/tpm_crb.c | 16 ++++++++++++++++ hw/tpm/tpm_crb_common.c | 19 +++++++++++++++++++ 4 files changed, 38 insertions(+), 15 deletions(-) diff --git a/hw/tpm/tpm_crb.h b/hw/tpm/tpm_crb.h index 36863e1664..e6a86e3fd1 100644 --- a/hw/tpm/tpm_crb.h +++ b/hw/tpm/tpm_crb.h @@ -73,5 +73,7 @@ void tpm_crb_init_memory(Object *obj, TPMCRBState *s, Error **errp); void tpm_crb_mem_save(TPMCRBState *s, uint32_t *saved_regs, void *saved_cmdmem); void tpm_crb_mem_load(TPMCRBState *s, const uint32_t *saved_regs, const void *saved_cmdmem); +void tpm_crb_build_aml(TPMIf *ti, Aml *scope, uint32_t baseaddr, uint32_t size, + bool build_ppi); #endif /* TPM_TPM_CRB_H */ diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 80db183b78..7491cee2af 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1792,21 +1792,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, #ifdef CONFIG_TPM if (TPM_IS_CRB(tpm)) { - dev = aml_device("TPM"); - aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); - aml_append(dev, aml_name_decl("_STR", - aml_string("TPM 2.0 Device"))); - crs = aml_resource_template(); - aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, - TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); - aml_append(dev, aml_name_decl("_CRS", crs)); - - aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); - aml_append(dev, aml_name_decl("_UID", aml_int(1))); - - tpm_build_ppi_acpi(tpm, dev); - - aml_append(sb_scope, dev); + call_dev_aml_func(DEVICE(tpm), scope); } #endif diff --git a/hw/tpm/tpm_crb.c b/hw/tpm/tpm_crb.c index 99c64dd72a..8d57295b15 100644 --- a/hw/tpm/tpm_crb.c +++ b/hw/tpm/tpm_crb.c @@ -19,6 +19,8 @@ #include "qemu/module.h" #include "qapi/error.h" #include "exec/address-spaces.h" +#include "hw/acpi/acpi_aml_interface.h" +#include "hw/acpi/tpm.h" #include "hw/qdev-properties.h" #include "hw/pci/pci_ids.h" #include "hw/acpi/tpm.h" @@ -121,6 +123,11 @@ static void tpm_crb_none_realize(DeviceState *dev, Error **errp) return; } + if (tpm_crb_none_get_version(TPM_IF(s)) != TPM_VERSION_2_0) { + error_setg(errp, "TPM CRB only supports TPM 2.0 backends"); + return; + } + tpm_crb_init_memory(OBJECT(s), &s->state, errp); /* only used for migration */ @@ -142,10 +149,17 @@ static void tpm_crb_none_realize(DeviceState *dev, Error **errp) } } +static void build_tpm_crb_none_aml(AcpiDevAmlIf *adev, Aml *scope) +{ + tpm_crb_build_aml(TPM_IF(adev), scope, TPM_CRB_ADDR_BASE, TPM_CRB_ADDR_SIZE, + true); +} + static void tpm_crb_none_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); TPMIfClass *tc = TPM_IF_CLASS(klass); + AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); dc->realize = tpm_crb_none_realize; device_class_set_props(dc, tpm_crb_none_properties); @@ -154,6 +168,7 @@ static void tpm_crb_none_class_init(ObjectClass *klass, void *data) tc->model = TPM_MODEL_TPM_CRB; tc->get_version = tpm_crb_none_get_version; tc->request_completed = tpm_crb_none_request_completed; + adevc->build_dev_aml = build_tpm_crb_none_aml; set_bit(DEVICE_CATEGORY_MISC, dc->categories); } @@ -166,6 +181,7 @@ static const TypeInfo tpm_crb_none_info = { .class_init = tpm_crb_none_class_init, .interfaces = (InterfaceInfo[]) { { TYPE_TPM_IF }, + { TYPE_ACPI_DEV_AML_IF }, { } } }; diff --git a/hw/tpm/tpm_crb_common.c b/hw/tpm/tpm_crb_common.c index f96a8cf299..09ca55eece 100644 --- a/hw/tpm/tpm_crb_common.c +++ b/hw/tpm/tpm_crb_common.c @@ -241,3 +241,22 @@ void tpm_crb_mem_load(TPMCRBState *s, const uint32_t *saved_regs, memcpy(regs, saved_regs, A_CRB_DATA_BUFFER); memcpy(®s[R_CRB_DATA_BUFFER], saved_cmdmem, CRB_CTRL_CMD_SIZE); } + +void tpm_crb_build_aml(TPMIf *ti, Aml *scope, uint32_t baseaddr, uint32_t size, + bool build_ppi) +{ + Aml *dev, *crs; + + dev = aml_device("TPM"); + aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); + aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device"))); + aml_append(dev, aml_name_decl("_UID", aml_int(1))); + aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); + crs = aml_resource_template(); + aml_append(crs, aml_memory32_fixed(baseaddr, size, AML_READ_WRITE)); + aml_append(dev, aml_name_decl("_CRS", crs)); + if (build_ppi) { + tpm_build_ppi_acpi(ti, dev); + } + aml_append(scope, dev); +} From patchwork Tue Nov 14 02:09:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13454727 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8F99FC4167B for ; Tue, 14 Nov 2023 02:11:26 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r2is7-0001LI-Jw; Mon, 13 Nov 2023 21:09:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r2is6-0001JD-9S for qemu-devel@nongnu.org; Mon, 13 Nov 2023 21:09:46 -0500 Received: from mail-pj1-f44.google.com ([209.85.216.44]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r2is4-0007ae-Mj for qemu-devel@nongnu.org; Mon, 13 Nov 2023 21:09:46 -0500 Received: by mail-pj1-f44.google.com with SMTP id 98e67ed59e1d1-2809b4d648bso4289364a91.2 for ; Mon, 13 Nov 2023 18:09:44 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699927783; x=1700532583; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=thzx3xuZnRgtiRpHIay8GaaQihSYfRbbl9Vnnhg5FOU=; b=Gw6yOoEq55lPcsowylXso0RCpprtGJ59TDOf9tsw06vZ4njs1Qcy/sabrFaQAWz/kG WzKxpCPl0qIxpw6q3cMZv6zZvxdaNw7nFWDgnRm/NbZmu0he4qLj7ztZ2HNvYXRPAQg/ 1tix4OqvzxPO9CZVh0DAFCnvMP1GOWFJj6Jv73KGchHIgB4YagnhtVnBTtFAs6XVJYcS sRoNgg9gxVAx0jcsjloncShga/2JgzL/Kw6N04XKkgKVa68F9aNkEM5LwGkUyPdTBsxv PtrsEB8sO7tds1ISY143sYlnWQKka5QOSRdzz5GitQYwcqVAKuPzwcloKI7sNyNsUApu Uspw== X-Gm-Message-State: AOJu0YzIZGpeJZLIQrdoTvVe6Nz2eniMTdLkJPFag9K96FqtOItGJZzh bC0D9Uf1AN3Gxn982CZw8NIpk8MZETsMkg== X-Google-Smtp-Source: AGHT+IHNfi332UN67iCwIQQU2iK6wS2HMJmTdwGw4/4QX5e7cTyYIjALrgAtLpnRgPVqhsgb9bMZzQ== X-Received: by 2002:a17:90b:3b8b:b0:283:27e0:652c with SMTP id pc11-20020a17090b3b8b00b0028327e0652cmr5564057pjb.43.1699927783084; Mon, 13 Nov 2023 18:09:43 -0800 (PST) Received: from localhost.localdomain ([2601:642:4c01:2f7:5d09:c219:9099:a639]) by smtp.gmail.com with ESMTPSA id g13-20020a17090ae58d00b0027d12b1e29dsm6175362pjz.25.2023.11.13.18.09.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Nov 2023 18:09:42 -0800 (PST) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Stefan Berger , Stefan Berger Subject: [PATCH v5 06/14] tpm-sysbus: add plug handler for TPM on SysBus Date: Mon, 13 Nov 2023 18:09:16 -0800 Message-ID: <20231114020927.62315-7-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231114020927.62315-1-j@getutm.app> References: <20231114020927.62315-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.216.44; envelope-from=osy86dev@gmail.com; helo=mail-pj1-f44.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org TPM needs to know its own base address in order to generate its DSDT device entry. Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- include/sysemu/tpm.h | 4 ++++ hw/tpm/tpm-sysbus.c | 47 ++++++++++++++++++++++++++++++++++++++++++++ hw/tpm/meson.build | 1 + 3 files changed, 52 insertions(+) create mode 100644 hw/tpm/tpm-sysbus.c diff --git a/include/sysemu/tpm.h b/include/sysemu/tpm.h index 1ee568b3b6..ffd300e607 100644 --- a/include/sysemu/tpm.h +++ b/include/sysemu/tpm.h @@ -12,6 +12,8 @@ #ifndef QEMU_TPM_H #define QEMU_TPM_H +#include "qemu/osdep.h" +#include "exec/hwaddr.h" #include "qapi/qapi-types-tpm.h" #include "qom/object.h" @@ -78,6 +80,8 @@ static inline TPMVersion tpm_get_version(TPMIf *ti) return TPM_IF_GET_CLASS(ti)->get_version(ti); } +void tpm_sysbus_plug(TPMIf *tpmif, Object *pbus, hwaddr pbus_base); + #else /* CONFIG_TPM */ #define tpm_init() (0) diff --git a/hw/tpm/tpm-sysbus.c b/hw/tpm/tpm-sysbus.c new file mode 100644 index 0000000000..732ce34c73 --- /dev/null +++ b/hw/tpm/tpm-sysbus.c @@ -0,0 +1,47 @@ +/* + * tpm-sysbus.c - Support functions for SysBus TPM devices + * + * Copyright (c) 2023 QEMU contributors + * + * Authors: + * Joelle van Dyne + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ +#include "sysemu/tpm.h" +#include "hw/platform-bus.h" +#include "hw/sysbus.h" +#include "qapi/error.h" + +/** + * Called from a machine's pre_plug handler to set the device's physical addr. + */ +void tpm_sysbus_plug(TPMIf *tpmif, Object *pbus, hwaddr pbus_base) +{ + PlatformBusDevice *pbusdev = PLATFORM_BUS_DEVICE(pbus); + SysBusDevice *sbdev = SYS_BUS_DEVICE(tpmif); + MemoryRegion *sbdev_mr; + hwaddr tpm_base; + uint64_t tpm_size; + + /* exit early if TPM is not a sysbus device */ + if (!object_dynamic_cast(OBJECT(tpmif), TYPE_SYS_BUS_DEVICE)) { + return; + } + + assert(object_dynamic_cast(pbus, TYPE_PLATFORM_BUS_DEVICE)); + + tpm_base = platform_bus_get_mmio_addr(pbusdev, sbdev, 0); + assert(tpm_base != -1); + + tpm_base += pbus_base; + + sbdev_mr = sysbus_mmio_get_region(sbdev, 0); + tpm_size = memory_region_size(sbdev_mr); + + object_property_set_uint(OBJECT(sbdev), "x-baseaddr", + tpm_base, &error_abort); + object_property_set_uint(OBJECT(sbdev), "x-size", + tpm_size, &error_abort); +} diff --git a/hw/tpm/meson.build b/hw/tpm/meson.build index cb8204d5bc..3060ac05e8 100644 --- a/hw/tpm/meson.build +++ b/hw/tpm/meson.build @@ -1,6 +1,7 @@ system_ss.add(when: 'CONFIG_TPM_TIS', if_true: files('tpm_tis_common.c')) system_ss.add(when: 'CONFIG_TPM_TIS_ISA', if_true: files('tpm_tis_isa.c')) system_ss.add(when: 'CONFIG_TPM_TIS_SYSBUS', if_true: files('tpm_tis_sysbus.c')) +system_ss.add(when: 'CONFIG_TPM_TIS_SYSBUS', if_true: files('tpm-sysbus.c')) system_ss.add(when: 'CONFIG_TPM_TIS_I2C', if_true: files('tpm_tis_i2c.c')) system_ss.add(when: 'CONFIG_TPM_CRB', if_true: files('tpm_crb.c')) system_ss.add(when: 'CONFIG_TPM_CRB', if_true: files('tpm_crb_common.c')) From patchwork Tue Nov 14 02:09:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13454724 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9FCD6C4332F for ; Tue, 14 Nov 2023 02:11:06 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r2is9-0001MQ-8K; Mon, 13 Nov 2023 21:09:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r2is8-0001LM-2t; Mon, 13 Nov 2023 21:09:48 -0500 Received: from mail-pj1-f53.google.com ([209.85.216.53]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r2is6-0007aq-NT; Mon, 13 Nov 2023 21:09:47 -0500 Received: by mail-pj1-f53.google.com with SMTP id 98e67ed59e1d1-2801d7f46f9so4411143a91.3; Mon, 13 Nov 2023 18:09:46 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699927785; x=1700532585; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pnXe1Tp9eRoBQn7pI22tFabU1RSpPOFV8giEL0/CmJw=; b=ErrnDCyGYQZMKXDQLfZquRIOJjhQ5tMipzslhwgi25v7u2MxBs6n0BOxFchDGvBvtq 4j4LMa4YuRcnnw86FBKdosw1otLeNVpeSzx8YiGYf6IprcoCHjLdQuGq28wjdT7VrbDP aU2Luuwn5q3hfiGQlhyd2vBnigQoq1h0tTmzoSwxKdlVdiJJBLmxV/tGuY9nxAxY38Xl Tw+eLe5T7r4fV+TOtTHWCt8xuc4MCXNYKYwZflT7+zRZxdyaiDXxuDHsyw07hyPTtlCu WQH8qiEF438AHCvpcUzCLckommXrzl27NxlPinzwSvnJ3cghLFcmFQ2Onnc9GtyElKYn cxmA== X-Gm-Message-State: AOJu0Yz1HOOlRbVeQLVwUC0WY2rOvzZZBM0FM1l5YFvJltIgUp8xZh+z C5kun1G3HVbgC+j8CuxP52eAFPdfeijggw== X-Google-Smtp-Source: AGHT+IFbxGDzVfu1z5Rm23aY3D+RQF2Lz+Uuq5Qv1x57LJuNnhsZ/iP6Yb9Rh4msR/HtpJvyVkF7lQ== X-Received: by 2002:a17:90b:3783:b0:280:9074:eb3d with SMTP id mz3-20020a17090b378300b002809074eb3dmr6106221pjb.22.1699927784791; Mon, 13 Nov 2023 18:09:44 -0800 (PST) Received: from localhost.localdomain ([2601:642:4c01:2f7:5d09:c219:9099:a639]) by smtp.gmail.com with ESMTPSA id g13-20020a17090ae58d00b0027d12b1e29dsm6175362pjz.25.2023.11.13.18.09.43 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Nov 2023 18:09:44 -0800 (PST) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Stefan Berger , Peter Maydell , qemu-arm@nongnu.org (open list:Virt) Subject: [PATCH v5 07/14] hw/arm/virt: connect TPM to platform bus Date: Mon, 13 Nov 2023 18:09:17 -0800 Message-ID: <20231114020927.62315-8-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231114020927.62315-1-j@getutm.app> References: <20231114020927.62315-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.216.53; envelope-from=osy86dev@gmail.com; helo=mail-pj1-f53.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- hw/arm/virt.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 85e3c5ba9d..36e2506420 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2811,6 +2811,13 @@ static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, vms->virtio_iommu_bdf = pci_get_bdf(pdev); create_virtio_iommu_dt_bindings(vms); } + +#ifdef CONFIG_TPM + if (object_dynamic_cast(OBJECT(dev), TYPE_TPM_IF)) { + tpm_sysbus_plug(TPM_IF(dev), OBJECT(vms->platform_bus_dev), + vms->memmap[VIRT_PLATFORM_BUS].base); + } +#endif } static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, From patchwork Tue Nov 14 02:09:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13454728 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0CC68C4332F for ; Tue, 14 Nov 2023 02:11:52 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r2isF-0001O7-4l; Mon, 13 Nov 2023 21:09:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r2isD-0001NL-Fx for qemu-devel@nongnu.org; Mon, 13 Nov 2023 21:09:53 -0500 Received: from mail-pj1-f43.google.com ([209.85.216.43]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r2is8-0007b5-QZ for qemu-devel@nongnu.org; Mon, 13 Nov 2023 21:09:53 -0500 Received: by mail-pj1-f43.google.com with SMTP id 98e67ed59e1d1-2800f7c8125so4722111a91.1 for ; Mon, 13 Nov 2023 18:09:48 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699927787; x=1700532587; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7QEdUJS68W5mzt9ORxKLrBXJOs881kVxhlYUSB2HGuY=; b=udeWgC8a86w6o3ZJFgdESGXrpU5h00G5fNiDoRgGdCZyzD9BSQNcD8Izoq60XuEQFR 3KqpMsktOEp+aQNis6PF1UCAhVHQ8kCSJALmfOyRw0fLQwJ3np44QVzjLsJ88u19cHd6 Fqb5LYd+WUdt9VU+hj1QQRDL8tyNVZD033mkgtqFeRUSWJaTNjSfbCszW5lervFzc7dQ SeqCAd6fTtTrqhxYL0QtLajsX1GUccTXOcDFS1i08AUnRv9FKhLY/Dd7XlXaIhQ5itMg Ub2DiXEzXkA7N3ALNZLMAh2slSfh1rJ+QC1kcn4qGyfucWpY8e4V4XIrqx1P3sQi0D9s yRIg== X-Gm-Message-State: AOJu0YxrhQ8/Ql8x3yfQiCjljJAsH9unvuD8oUMEKP1aGCGNxXcsh6CP +nc8L9aDEFVk6WKGZpTVOS+l/vSM0YgufQ== X-Google-Smtp-Source: AGHT+IHS9p2OTvHSwXPNuconknEWB68F/vMI0Q/NASN2Elph/BwpKCBzajSi+wtw8GPiQ1jCgc/00Q== X-Received: by 2002:a17:90a:9282:b0:280:74e7:9284 with SMTP id n2-20020a17090a928200b0028074e79284mr1894675pjo.21.1699927787091; Mon, 13 Nov 2023 18:09:47 -0800 (PST) Received: from localhost.localdomain ([2601:642:4c01:2f7:5d09:c219:9099:a639]) by smtp.gmail.com with ESMTPSA id g13-20020a17090ae58d00b0027d12b1e29dsm6175362pjz.25.2023.11.13.18.09.45 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Nov 2023 18:09:46 -0800 (PST) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Stefan Berger , Paolo Bonzini , Song Gao Subject: [PATCH v5 08/14] hw/loongarch/virt: connect TPM to platform bus Date: Mon, 13 Nov 2023 18:09:18 -0800 Message-ID: <20231114020927.62315-9-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231114020927.62315-1-j@getutm.app> References: <20231114020927.62315-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.216.43; envelope-from=osy86dev@gmail.com; helo=mail-pj1-f43.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- hw/loongarch/virt.c | 7 +++++++ hw/loongarch/Kconfig | 1 + 2 files changed, 8 insertions(+) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 4b7dc67a2d..feed0f8bbf 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -1004,6 +1004,13 @@ static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev, } else if (memhp_type_supported(dev)) { virt_mem_plug(hotplug_dev, dev, errp); } + +#ifdef CONFIG_TPM + if (object_dynamic_cast(OBJECT(dev), TYPE_TPM_IF)) { + tpm_sysbus_plug(TPM_IF(dev), OBJECT(lams->platform_bus_dev), + VIRT_PLATFORM_BUS_BASEADDRESS); + } +#endif } static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index 5727efed6d..25da190ffc 100644 --- a/hw/loongarch/Kconfig +++ b/hw/loongarch/Kconfig @@ -5,6 +5,7 @@ config LOONGARCH_VIRT imply VIRTIO_VGA imply PCI_DEVICES imply NVDIMM + imply TPM_TIS_SYSBUS select SERIAL select VIRTIO_PCI select PLATFORM_BUS From patchwork Tue Nov 14 02:09:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13454731 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6A71EC072A2 for ; Tue, 14 Nov 2023 02:11:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r2isF-0001OI-BZ; Mon, 13 Nov 2023 21:09:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r2isE-0001NZ-2k; Mon, 13 Nov 2023 21:09:54 -0500 Received: from mail-pj1-f47.google.com ([209.85.216.47]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r2isB-0007bI-4q; Mon, 13 Nov 2023 21:09:53 -0500 Received: by mail-pj1-f47.google.com with SMTP id 98e67ed59e1d1-2809a824bbbso4036562a91.3; Mon, 13 Nov 2023 18:09:50 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699927789; x=1700532589; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=er+wGHhNJaRHONgLNEvt2ueAmajPNkBV9dZrECb5Yzw=; b=m7g9nrV9LOaEky8JvEkr8TRix45TvSHaGlqBpnljNmfzQnQgfo2tVfZDtWPYtJtcTJ b2tHwP94t7f997qV6Util4lrCCceHLvSaUfprV6AYi0aCaZEwV6n/phdro8KDQJb+FpL kCG5Ea49vZhjw5o7P8GzxDjAn+Lwv0qVE62yvNdu95C1GllUMD8gr9NhgcXg1OMIohyV J8OxoCKX+cUUUB/GWTEbw7VfwJHovJ1XQf2qBamCURDfv8Wn2VnmS/TWm+h/1rIPVw24 y6wa/VyyWSQX62TmqBIl9fo3hzedLqg/KG4EbdQHAkGIQdEXH7u6POG02Tav3VMYRKSy dRbw== X-Gm-Message-State: AOJu0YxXrtbdCfGAVxyIU9dtzMGj/8qdN4EbWf/qBjG/5yGMOf92/vpK +btP281ikUBeXY05vq4v/qqWSJBIROCeTw== X-Google-Smtp-Source: AGHT+IEHEXmbyxCYng6ZGfKgnnRe6PUewCu3xSLxObG0XaACO3bYIOvzCWaaKF13x+RFytgeM+kDow== X-Received: by 2002:a17:90b:4d06:b0:283:23d9:2bcf with SMTP id mw6-20020a17090b4d0600b0028323d92bcfmr5517185pjb.0.1699927789220; Mon, 13 Nov 2023 18:09:49 -0800 (PST) Received: from localhost.localdomain ([2601:642:4c01:2f7:5d09:c219:9099:a639]) by smtp.gmail.com with ESMTPSA id g13-20020a17090ae58d00b0027d12b1e29dsm6175362pjz.25.2023.11.13.18.09.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Nov 2023 18:09:48 -0800 (PST) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Stefan Berger , Shannon Zhao , Peter Maydell , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha , Song Gao , Stefan Berger , qemu-arm@nongnu.org (open list:ARM ACPI Subsystem) Subject: [PATCH v5 09/14] tpm_tis_sysbus: move DSDT AML generation to device Date: Mon, 13 Nov 2023 18:09:19 -0800 Message-ID: <20231114020927.62315-10-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231114020927.62315-1-j@getutm.app> References: <20231114020927.62315-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.216.47; envelope-from=osy86dev@gmail.com; helo=mail-pj1-f47.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This reduces redundant code in different machine types with ACPI table generation. Additionally, this will allow us to support different TPM interfaces with the same AML logic. Finally, this matches up with the TPM TIS ISA implementation. Ideally, we would be able to call `qbus_build_aml` and avoid any TPM specific code in the ACPI table generation. However, currently we still have to call `build_tpm2` anyways and it does not look like most other ACPI devices support the `ACPI_DEV_AML_IF` interface. Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- hw/arm/virt-acpi-build.c | 38 ++------------------------------------ hw/loongarch/acpi-build.c | 38 ++------------------------------------ hw/tpm/tpm_tis_sysbus.c | 37 +++++++++++++++++++++++++++++++++++++ 3 files changed, 41 insertions(+), 72 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 8bc35a483c..499d30eb5d 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -35,6 +35,7 @@ #include "target/arm/cpu.h" #include "hw/acpi/acpi-defs.h" #include "hw/acpi/acpi.h" +#include "hw/acpi/acpi_aml_interface.h" #include "hw/nvram/fw_cfg.h" #include "hw/acpi/bios-linker-loader.h" #include "hw/acpi/aml-build.h" @@ -208,41 +209,6 @@ static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, aml_append(scope, dev); } -#ifdef CONFIG_TPM -static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms) -{ - PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); - hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base; - SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find()); - MemoryRegion *sbdev_mr; - hwaddr tpm_base; - - if (!sbdev) { - return; - } - - tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); - assert(tpm_base != -1); - - tpm_base += pbus_base; - - sbdev_mr = sysbus_mmio_get_region(sbdev, 0); - - Aml *dev = aml_device("TPM0"); - aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); - aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device"))); - aml_append(dev, aml_name_decl("_UID", aml_int(0))); - - Aml *crs = aml_resource_template(); - aml_append(crs, - aml_memory32_fixed(tpm_base, - (uint32_t)memory_region_size(sbdev_mr), - AML_READ_WRITE)); - aml_append(dev, aml_name_decl("_CRS", crs)); - aml_append(scope, dev); -} -#endif - #define ID_MAPPING_ENTRY_SIZE 20 #define SMMU_V3_ENTRY_SIZE 68 #define ROOT_COMPLEX_ENTRY_SIZE 36 @@ -891,7 +857,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) acpi_dsdt_add_power_button(scope); #ifdef CONFIG_TPM - acpi_dsdt_add_tpm(scope, vms); + call_dev_aml_func(DEVICE(tpm_find()), scope); #endif aml_append(dsdt, scope); diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c index ae292fc543..1969bfc8f9 100644 --- a/hw/loongarch/acpi-build.c +++ b/hw/loongarch/acpi-build.c @@ -14,6 +14,7 @@ #include "target/loongarch/cpu.h" #include "hw/acpi/acpi-defs.h" #include "hw/acpi/acpi.h" +#include "hw/acpi/acpi_aml_interface.h" #include "hw/nvram/fw_cfg.h" #include "hw/acpi/bios-linker-loader.h" #include "migration/vmstate.h" @@ -328,41 +329,6 @@ static void build_flash_aml(Aml *scope, LoongArchMachineState *lams) aml_append(scope, dev); } -#ifdef CONFIG_TPM -static void acpi_dsdt_add_tpm(Aml *scope, LoongArchMachineState *vms) -{ - PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); - hwaddr pbus_base = VIRT_PLATFORM_BUS_BASEADDRESS; - SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find()); - MemoryRegion *sbdev_mr; - hwaddr tpm_base; - - if (!sbdev) { - return; - } - - tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); - assert(tpm_base != -1); - - tpm_base += pbus_base; - - sbdev_mr = sysbus_mmio_get_region(sbdev, 0); - - Aml *dev = aml_device("TPM0"); - aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); - aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device"))); - aml_append(dev, aml_name_decl("_UID", aml_int(0))); - - Aml *crs = aml_resource_template(); - aml_append(crs, - aml_memory32_fixed(tpm_base, - (uint32_t)memory_region_size(sbdev_mr), - AML_READ_WRITE)); - aml_append(dev, aml_name_decl("_CRS", crs)); - aml_append(scope, dev); -} -#endif - /* build DSDT */ static void build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine) @@ -379,7 +345,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine) build_la_ged_aml(dsdt, machine); build_flash_aml(dsdt, lams); #ifdef CONFIG_TPM - acpi_dsdt_add_tpm(dsdt, lams); + call_dev_aml_func(DEVICE(tpm_find()), dsdt); #endif /* System State Package */ scope = aml_scope("\\"); diff --git a/hw/tpm/tpm_tis_sysbus.c b/hw/tpm/tpm_tis_sysbus.c index 2fc550f119..462b0e1571 100644 --- a/hw/tpm/tpm_tis_sysbus.c +++ b/hw/tpm/tpm_tis_sysbus.c @@ -30,6 +30,7 @@ #include "hw/sysbus.h" #include "tpm_tis.h" #include "qom/object.h" +#include "hw/acpi/acpi_aml_interface.h" struct TPMStateSysBus { /*< private >*/ @@ -37,6 +38,8 @@ struct TPMStateSysBus { /*< public >*/ TPMState state; /* not a QOM object */ + uint64_t baseaddr; + uint64_t size; }; OBJECT_DECLARE_SIMPLE_TYPE(TPMStateSysBus, TPM_TIS_SYSBUS) @@ -93,6 +96,10 @@ static void tpm_tis_sysbus_reset(DeviceState *dev) static Property tpm_tis_sysbus_properties[] = { DEFINE_PROP_UINT32("irq", TPMStateSysBus, state.irq_num, TPM_TIS_IRQ), DEFINE_PROP_TPMBE("tpmdev", TPMStateSysBus, state.be_driver), + DEFINE_PROP_UINT64("x-baseaddr", TPMStateSysBus, baseaddr, + TPM_TIS_ADDR_BASE), + DEFINE_PROP_UINT64("x-size", TPMStateSysBus, size, + TPM_TIS_ADDR_SIZE), DEFINE_PROP_END_OF_LIST(), }; @@ -125,10 +132,38 @@ static void tpm_tis_sysbus_realizefn(DeviceState *dev, Error **errp) } } +static void build_tpm_tis_sysbus_aml(AcpiDevAmlIf *adev, Aml *scope) +{ + Aml *dev, *crs; + TPMStateSysBus *sbdev = TPM_TIS_SYSBUS(adev); + TPMIf *ti = TPM_IF(sbdev); + + dev = aml_device("TPM"); + if (tpm_tis_sysbus_get_tpm_version(ti) == TPM_VERSION_2_0) { + aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); + aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device"))); + } else { + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31"))); + } + aml_append(dev, aml_name_decl("_UID", aml_int(0))); + aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); + crs = aml_resource_template(); + aml_append(crs, aml_memory32_fixed(sbdev->baseaddr, sbdev->size, + AML_READ_WRITE)); + /* + * FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, + * fix default TPM_TIS_IRQ value there to use some unused IRQ + */ + /* aml_append(crs, aml_irq_no_flags(sbdev->state.irq_num)); */ + aml_append(dev, aml_name_decl("_CRS", crs)); + aml_append(scope, dev); +} + static void tpm_tis_sysbus_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); TPMIfClass *tc = TPM_IF_CLASS(klass); + AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); device_class_set_props(dc, tpm_tis_sysbus_properties); dc->vmsd = &vmstate_tpm_tis_sysbus; @@ -139,6 +174,7 @@ static void tpm_tis_sysbus_class_init(ObjectClass *klass, void *data) tc->request_completed = tpm_tis_sysbus_request_completed; tc->get_version = tpm_tis_sysbus_get_tpm_version; set_bit(DEVICE_CATEGORY_MISC, dc->categories); + adevc->build_dev_aml = build_tpm_tis_sysbus_aml; } static const TypeInfo tpm_tis_sysbus_info = { @@ -149,6 +185,7 @@ static const TypeInfo tpm_tis_sysbus_info = { .class_init = tpm_tis_sysbus_class_init, .interfaces = (InterfaceInfo[]) { { TYPE_TPM_IF }, + { TYPE_ACPI_DEV_AML_IF }, { } } }; From patchwork Tue Nov 14 02:09:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13454730 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A382C4332F for ; Tue, 14 Nov 2023 02:11:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r2isJ-0001PB-3d; Mon, 13 Nov 2023 21:09:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r2isH-0001Oz-Sm for qemu-devel@nongnu.org; Mon, 13 Nov 2023 21:09:57 -0500 Received: from mail-pg1-f179.google.com ([209.85.215.179]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r2isD-0007bV-8W for qemu-devel@nongnu.org; Mon, 13 Nov 2023 21:09:57 -0500 Received: by mail-pg1-f179.google.com with SMTP id 41be03b00d2f7-5b8f68ba4e5so3549478a12.1 for ; Mon, 13 Nov 2023 18:09:52 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699927791; x=1700532591; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=145VN8wvl1zAFaa1Qd5kwCb0udgJKqihEQq8C5UE0Po=; b=ajx7LVlgnvRxmpid3kLAVEevD0U+PJyZWV0qDY0Gk9dUqHqpbvAmt70F/eBLgm9JnF T6HFSHjZ0i16xEqVz8wmD6M0IcghDSJunBeLxrasa42Hsp/bOdQU/37he4GNMZ2mljwV SJiDM/RAzWuo+HBeDOXlQc3MVHLXdiPOS63opVkvDtlQZzUETKnzXNbjAEQb3hzq3d9P Xt1CI17ZIlKTZRWLBWz9EbG69oujNu7DvzZMuhV1eqvJ6bktKLq4WEYKwC72Mjavhb7d x3bOa83HM5Zj/8y8BiPjcO7xv8fcxjnwruVdFFBOizk53HKVzJmtdWNG2Xys9223ppts yJXA== X-Gm-Message-State: AOJu0YxG6GzA+tValxTfVzXp8hhussDFCBi7+30RAOyA9xr8JQGeYRLM vWd80QHqfmlDknLoXN6N+uRfsupAPXY1hQ== X-Google-Smtp-Source: AGHT+IHCeFSGVIU1bDa4P3JL9KftRpbpeHscZGhIWX26DRQHGn/lgxqeH04oUn+5VnktFkZWWH2waw== X-Received: by 2002:a05:6a20:3c90:b0:186:6dd1:b334 with SMTP id b16-20020a056a203c9000b001866dd1b334mr4322385pzj.27.1699927791598; Mon, 13 Nov 2023 18:09:51 -0800 (PST) Received: from localhost.localdomain ([2601:642:4c01:2f7:5d09:c219:9099:a639]) by smtp.gmail.com with ESMTPSA id g13-20020a17090ae58d00b0027d12b1e29dsm6175362pjz.25.2023.11.13.18.09.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Nov 2023 18:09:50 -0800 (PST) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Stefan Berger , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha Subject: [PATCH v5 10/14] tests: acpi: prepare for TPM CRB tests Date: Mon, 13 Nov 2023 18:09:20 -0800 Message-ID: <20231114020927.62315-11-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231114020927.62315-1-j@getutm.app> References: <20231114020927.62315-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.179; envelope-from=osy86dev@gmail.com; helo=mail-pg1-f179.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- tests/qtest/bios-tables-test-allowed-diff.h | 4 ++++ tests/data/acpi/q35/DSDT.crb.tpm2 | 0 tests/data/acpi/q35/TPM2.crb.tpm2 | 0 tests/data/acpi/virt/DSDT.crb-device.tpm2 | 0 tests/data/acpi/virt/TPM2.crb-device.tpm2 | 0 5 files changed, 4 insertions(+) create mode 100644 tests/data/acpi/q35/DSDT.crb.tpm2 create mode 100644 tests/data/acpi/q35/TPM2.crb.tpm2 create mode 100644 tests/data/acpi/virt/DSDT.crb-device.tpm2 create mode 100644 tests/data/acpi/virt/TPM2.crb-device.tpm2 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..c2d1924c2f 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,5 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/q35/DSDT.crb.tpm2", +"tests/data/acpi/q35/TPM2.crb.tpm2", +"tests/data/acpi/virt/DSDT.crb.tpm2", +"tests/data/acpi/virt/TPM2.crb.tpm2", diff --git a/tests/data/acpi/q35/DSDT.crb.tpm2 b/tests/data/acpi/q35/DSDT.crb.tpm2 new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/q35/TPM2.crb.tpm2 b/tests/data/acpi/q35/TPM2.crb.tpm2 new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/virt/DSDT.crb-device.tpm2 b/tests/data/acpi/virt/DSDT.crb-device.tpm2 new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/virt/TPM2.crb-device.tpm2 b/tests/data/acpi/virt/TPM2.crb-device.tpm2 new file mode 100644 index 0000000000..e69de29bb2 From patchwork Tue Nov 14 02:09:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13454722 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 53D11C4167D for ; Tue, 14 Nov 2023 02:10:17 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r2isL-0001Q2-M6; Mon, 13 Nov 2023 21:10:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r2isJ-0001PO-Sx; Mon, 13 Nov 2023 21:09:59 -0500 Received: from mail-pj1-f47.google.com ([209.85.216.47]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r2isH-0007c0-Kr; Mon, 13 Nov 2023 21:09:59 -0500 Received: by mail-pj1-f47.google.com with SMTP id 98e67ed59e1d1-280137f1a1bso4036895a91.1; Mon, 13 Nov 2023 18:09:56 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699927795; x=1700532595; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vbiTVookckMidOOPTQoozqrFKatQNEIrxbgSipaZNzQ=; b=YIb/U7QRIuSOxEy8XAJ1oVMHU29J8IgXXHNvd0f8m9TgjOluxCp12pUZ/wnuz/iRWy gA7eq2qtJzJ1B3GIPJfF6fk7AP1Dhkv8MAgF58yqq9ISEQPqT/yyM++Mgdj0aqulXAw3 pxBMCDMfTtQwHtiu1zbCOSkQRFYPmbB+05/62K5A3TazDNBoRgPOjZfxTuR7iszcvb9W IYHlmITrGmFQsvdfXIU4fhQiov+vCjfnM6bNsalODUb+0ZMP9whx3c44MO//xxCifMEq lU/gvRfkVTMjRHI1AXVtEoj8oaDjRV8tVuhVyqIFTzkOoOwo+h+e6By88RIaVaydnmJR lG4g== X-Gm-Message-State: AOJu0YzlM+PyaNA8MZy0j5i7sy1inI3KdJNqLNdDBbDHQfeOGf18jA4E RCBzxlATfS1DqnkXGU7XDdhL0QXw9HGfWA== X-Google-Smtp-Source: AGHT+IFdTtkzpsoKW3Fe1LOu/M7OSElelByuspKsf3YdFVCzYwaqTQsWxRKZ3ZOAejve9K8boy936w== X-Received: by 2002:a17:90b:3b88:b0:27d:1051:83c4 with SMTP id pc8-20020a17090b3b8800b0027d105183c4mr6314581pjb.12.1699927795268; Mon, 13 Nov 2023 18:09:55 -0800 (PST) Received: from localhost.localdomain ([2601:642:4c01:2f7:5d09:c219:9099:a639]) by smtp.gmail.com with ESMTPSA id g13-20020a17090ae58d00b0027d12b1e29dsm6175362pjz.25.2023.11.13.18.09.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Nov 2023 18:09:54 -0800 (PST) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Stefan Berger , Stefan Berger , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha , Paolo Bonzini , Peter Maydell , Song Gao , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-arm@nongnu.org (open list:ARM TCG CPUs), qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Subject: [PATCH v5 11/14] tpm_crb_sysbus: introduce TPM CRB SysBus device Date: Mon, 13 Nov 2023 18:09:21 -0800 Message-ID: <20231114020927.62315-12-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231114020927.62315-1-j@getutm.app> References: <20231114020927.62315-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.216.47; envelope-from=osy86dev@gmail.com; helo=mail-pj1-f47.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This SysBus variant of the CRB interface supports dynamically locating the MMIO interface so that Virt machines can use it. This interface is currently the only one supported by QEMU that works on Windows 11 ARM64 as 'tpm-tis-device' does not work with current Windows drivers. We largely follow that device as a template. To try out this device with Windows 11 before OVMF is updated, you will need to modify `sysbus-fdt.c` and change the added line from: ```c TYPE_BINDING(TYPE_TPM_CRB_SYSBUS, no_fdt_node), ``` to ```c TYPE_BINDING(TYPE_TPM_CRB_SYSBUS, add_tpm_tis_fdt_node), ``` This change was not included because it can confuse Linux (although from testing, it seems like Linux is able to properly ignore the device from the TPM TIS driver and recognize it from the ACPI device in the TPM CRB driver). A proper fix would require OVMF to recognize the ACPI device and not depend on the FDT node for recognizing TPM. The command line to try out this device with SWTPM is: ``` $ qemu-system-aarch64 \ -chardev socket,id=chrtpm0,path=tpm.sock \ -tpmdev emulator,id=tpm0,chardev=chrtpm0 \ -device tpm-crb-device,tpmdev=tpm0 ``` along with SWTPM: ``` $ swtpm \ --ctrl type=unixio,path=tpm.sock,terminate \ --tpmstate backend-uri=file://tpm.data \ --tpm2 ``` Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- docs/specs/tpm.rst | 1 + include/sysemu/tpm.h | 3 + hw/acpi/aml-build.c | 7 +- hw/arm/virt.c | 1 + hw/core/sysbus-fdt.c | 1 + hw/loongarch/virt.c | 1 + hw/riscv/virt.c | 1 + hw/tpm/tpm_crb_sysbus.c | 162 ++++++++++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + hw/loongarch/Kconfig | 1 + hw/riscv/Kconfig | 1 + hw/tpm/Kconfig | 5 ++ hw/tpm/meson.build | 3 + 13 files changed, 187 insertions(+), 1 deletion(-) create mode 100644 hw/tpm/tpm_crb_sysbus.c diff --git a/docs/specs/tpm.rst b/docs/specs/tpm.rst index 2bc29c9804..95aeb49220 100644 --- a/docs/specs/tpm.rst +++ b/docs/specs/tpm.rst @@ -46,6 +46,7 @@ operating system. QEMU files related to TPM CRB interface: - ``hw/tpm/tpm_crb.c`` - ``hw/tpm/tpm_crb_common.c`` + - ``hw/tpm/tpm_crb_sysbus.c`` SPAPR interface --------------- diff --git a/include/sysemu/tpm.h b/include/sysemu/tpm.h index ffd300e607..bab30fa546 100644 --- a/include/sysemu/tpm.h +++ b/include/sysemu/tpm.h @@ -49,6 +49,7 @@ struct TPMIfClass { #define TYPE_TPM_TIS_ISA "tpm-tis" #define TYPE_TPM_TIS_SYSBUS "tpm-tis-device" #define TYPE_TPM_CRB "tpm-crb" +#define TYPE_TPM_CRB_SYSBUS "tpm-crb-device" #define TYPE_TPM_SPAPR "tpm-spapr" #define TYPE_TPM_TIS_I2C "tpm-tis-i2c" @@ -58,6 +59,8 @@ struct TPMIfClass { object_dynamic_cast(OBJECT(chr), TYPE_TPM_TIS_SYSBUS) #define TPM_IS_CRB(chr) \ object_dynamic_cast(OBJECT(chr), TYPE_TPM_CRB) +#define TPM_IS_CRB_SYSBUS(chr) \ + object_dynamic_cast(OBJECT(chr), TYPE_TPM_CRB_SYSBUS) #define TPM_IS_SPAPR(chr) \ object_dynamic_cast(OBJECT(chr), TYPE_TPM_SPAPR) #define TPM_IS_TIS_I2C(chr) \ diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index af66bde0f5..acc654382e 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -31,6 +31,7 @@ #include "hw/pci/pci_bus.h" #include "hw/pci/pci_bridge.h" #include "qemu/cutils.h" +#include "qom/object.h" static GArray *build_alloc_array(void) { @@ -2218,7 +2219,7 @@ void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, { uint8_t start_method_params[12] = {}; unsigned log_addr_offset; - uint64_t control_area_start_address; + uint64_t baseaddr, control_area_start_address; TPMIf *tpmif = tpm_find(); uint32_t start_method; AcpiTable table = { .sig = "TPM2", .rev = 4, @@ -2236,6 +2237,10 @@ void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, } else if (TPM_IS_CRB(tpmif)) { control_area_start_address = TPM_CRB_ADDR_CTRL; start_method = TPM2_START_METHOD_CRB; + } else if (TPM_IS_CRB_SYSBUS(tpmif)) { + baseaddr = object_property_get_uint(OBJECT(tpmif), "x-baseaddr", NULL); + control_area_start_address = baseaddr + A_CRB_CTRL_REQ; + start_method = TPM2_START_METHOD_CRB; } else { g_assert_not_reached(); } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 36e2506420..e6152a2f51 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2955,6 +2955,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); #ifdef CONFIG_TPM machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_CRB_SYSBUS); #endif mc->block_default_type = IF_VIRTIO; mc->no_cdrom = 1; diff --git a/hw/core/sysbus-fdt.c b/hw/core/sysbus-fdt.c index eebcd28f9a..9c783f88eb 100644 --- a/hw/core/sysbus-fdt.c +++ b/hw/core/sysbus-fdt.c @@ -493,6 +493,7 @@ static const BindingEntry bindings[] = { #endif #ifdef CONFIG_TPM TYPE_BINDING(TYPE_TPM_TIS_SYSBUS, add_tpm_tis_fdt_node), + TYPE_BINDING(TYPE_TPM_CRB_SYSBUS, no_fdt_node), #endif TYPE_BINDING(TYPE_RAMFB_DEVICE, no_fdt_node), TYPE_BINDING("", NULL), /* last element */ diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index feed0f8bbf..9d5ad2bc8e 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -1114,6 +1114,7 @@ static void loongarch_class_init(ObjectClass *oc, void *data) machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); #ifdef CONFIG_TPM machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_CRB_SYSBUS); #endif } diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c7fc97e273..4cce0b14ab 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1702,6 +1702,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); #ifdef CONFIG_TPM machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_CRB_SYSBUS); #endif diff --git a/hw/tpm/tpm_crb_sysbus.c b/hw/tpm/tpm_crb_sysbus.c new file mode 100644 index 0000000000..7edeae3665 --- /dev/null +++ b/hw/tpm/tpm_crb_sysbus.c @@ -0,0 +1,162 @@ +/* + * tpm_crb_sysbus.c - QEMU's TPM CRB interface emulator + * + * Copyright (c) 2018 Red Hat, Inc. + * + * Authors: + * Marc-André Lureau + * Joelle van Dyne + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + * tpm_crb is a device for TPM 2.0 Command Response Buffer (CRB) Interface + * as defined in TCG PC Client Platform TPM Profile (PTP) Specification + * Family “2.0” Level 00 Revision 01.03 v22 + */ + +#include "qemu/osdep.h" +#include "hw/acpi/acpi_aml_interface.h" +#include "hw/acpi/tpm.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" +#include "tpm_prop.h" +#include "hw/sysbus.h" +#include "qapi/visitor.h" +#include "qom/object.h" +#include "sysemu/tpm_util.h" +#include "trace.h" +#include "tpm_crb.h" + +struct TPMCRBStateSysBus { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + TPMCRBState state; + uint64_t baseaddr; + uint64_t size; +}; + +OBJECT_DECLARE_SIMPLE_TYPE(TPMCRBStateSysBus, TPM_CRB_SYSBUS) + +static void tpm_crb_sysbus_request_completed(TPMIf *ti, int ret) +{ + TPMCRBStateSysBus *s = TPM_CRB_SYSBUS(ti); + + return tpm_crb_request_completed(&s->state, ret); +} + +static enum TPMVersion tpm_crb_sysbus_get_tpm_version(TPMIf *ti) +{ + TPMCRBStateSysBus *s = TPM_CRB_SYSBUS(ti); + + return tpm_crb_get_version(&s->state); +} + +static int tpm_crb_sysbus_pre_save(void *opaque) +{ + TPMCRBStateSysBus *s = opaque; + + return tpm_crb_pre_save(&s->state); +} + +static const VMStateDescription vmstate_tpm_crb_sysbus = { + .name = "tpm-crb-sysbus", + .pre_save = tpm_crb_sysbus_pre_save, + .fields = (VMStateField[]) { + VMSTATE_END_OF_LIST(), + } +}; + +static Property tpm_crb_sysbus_properties[] = { + DEFINE_PROP_TPMBE("tpmdev", TPMCRBStateSysBus, state.tpmbe), + DEFINE_PROP_UINT64("x-baseaddr", TPMCRBStateSysBus, + baseaddr, TPM_CRB_ADDR_BASE), + DEFINE_PROP_UINT64("x-size", TPMCRBStateSysBus, + size, TPM_CRB_ADDR_SIZE), + DEFINE_PROP_END_OF_LIST(), +}; + +static void tpm_crb_sysbus_initfn(Object *obj) +{ + TPMCRBStateSysBus *s = TPM_CRB_SYSBUS(obj); + + tpm_crb_init_memory(obj, &s->state, NULL); + + vmstate_register_ram(&s->state.mmio, DEVICE(obj)); + + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->state.mmio); +} + +static void tpm_crb_sysbus_reset(DeviceState *dev) +{ + TPMCRBStateSysBus *s = TPM_CRB_SYSBUS(dev); + + return tpm_crb_reset(&s->state, s->baseaddr); +} + +static void tpm_crb_sysbus_realizefn(DeviceState *dev, Error **errp) +{ + TPMCRBStateSysBus *s = TPM_CRB_SYSBUS(dev); + + if (!tpm_find()) { + error_setg(errp, "at most one TPM device is permitted"); + return; + } + + if (!s->state.tpmbe) { + error_setg(errp, "'tpmdev' property is required"); + return; + } + + if (tpm_crb_sysbus_get_tpm_version(TPM_IF(s)) != TPM_VERSION_2_0) { + error_setg(errp, "TPM CRB only supports TPM 2.0 backends"); + return; + } +} + +static void build_tpm_crb_sysbus_aml(AcpiDevAmlIf *adev, Aml *scope) +{ + TPMCRBStateSysBus *s = TPM_CRB_SYSBUS(adev); + + tpm_crb_build_aml(TPM_IF(adev), scope, s->baseaddr, s->size, false); +} + +static void tpm_crb_sysbus_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + TPMIfClass *tc = TPM_IF_CLASS(klass); + AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); + + device_class_set_props(dc, tpm_crb_sysbus_properties); + dc->vmsd = &vmstate_tpm_crb_sysbus; + tc->model = TPM_MODEL_TPM_CRB; + dc->realize = tpm_crb_sysbus_realizefn; + dc->user_creatable = true; + dc->reset = tpm_crb_sysbus_reset; + tc->request_completed = tpm_crb_sysbus_request_completed; + tc->get_version = tpm_crb_sysbus_get_tpm_version; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + adevc->build_dev_aml = build_tpm_crb_sysbus_aml; +} + +static const TypeInfo tpm_crb_sysbus_info = { + .name = TYPE_TPM_CRB_SYSBUS, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(TPMCRBStateSysBus), + .instance_init = tpm_crb_sysbus_initfn, + .class_init = tpm_crb_sysbus_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TPM_IF }, + { TYPE_ACPI_DEV_AML_IF }, + { } + } +}; + +static void tpm_crb_sysbus_register(void) +{ + type_register_static(&tpm_crb_sysbus_info); +} + +type_init(tpm_crb_sysbus_register) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 3ada335a24..f524994fd3 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -5,6 +5,7 @@ config ARM_VIRT imply VFIO_AMD_XGBE imply VFIO_PLATFORM imply VFIO_XGMAC + imply TPM_CRB_SYSBUS imply TPM_TIS_SYSBUS imply TPM_TIS_I2C imply NVDIMM diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index 25da190ffc..70544f3ce5 100644 --- a/hw/loongarch/Kconfig +++ b/hw/loongarch/Kconfig @@ -6,6 +6,7 @@ config LOONGARCH_VIRT imply PCI_DEVICES imply NVDIMM imply TPM_TIS_SYSBUS + imply TPM_CRB_SYSBUS select SERIAL select VIRTIO_PCI select PLATFORM_BUS diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index b6a5eb4452..d824cb58f9 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -29,6 +29,7 @@ config RISCV_VIRT imply PCI_DEVICES imply VIRTIO_VGA imply TEST_DEVICES + imply TPM_CRB_SYSBUS imply TPM_TIS_SYSBUS select RISCV_NUMA select GOLDFISH_RTC diff --git a/hw/tpm/Kconfig b/hw/tpm/Kconfig index a46663288c..28139c456a 100644 --- a/hw/tpm/Kconfig +++ b/hw/tpm/Kconfig @@ -25,6 +25,11 @@ config TPM_CRB depends on TPM && PC select TPM_BACKEND +config TPM_CRB_SYSBUS + bool + depends on TPM + select TPM_BACKEND + config TPM_SPAPR bool default y diff --git a/hw/tpm/meson.build b/hw/tpm/meson.build index 3060ac05e8..f2536c99e3 100644 --- a/hw/tpm/meson.build +++ b/hw/tpm/meson.build @@ -5,6 +5,9 @@ system_ss.add(when: 'CONFIG_TPM_TIS_SYSBUS', if_true: files('tpm-sysbus.c')) system_ss.add(when: 'CONFIG_TPM_TIS_I2C', if_true: files('tpm_tis_i2c.c')) system_ss.add(when: 'CONFIG_TPM_CRB', if_true: files('tpm_crb.c')) system_ss.add(when: 'CONFIG_TPM_CRB', if_true: files('tpm_crb_common.c')) +system_ss.add(when: 'CONFIG_TPM_CRB_SYSBUS', if_true: files('tpm_crb_sysbus.c')) +system_ss.add(when: 'CONFIG_TPM_CRB_SYSBUS', if_true: files('tpm_crb_common.c')) +system_ss.add(when: 'CONFIG_TPM_CRB_SYSBUS', if_true: files('tpm-sysbus.c')) system_ss.add(when: 'CONFIG_TPM_TIS', if_true: files('tpm_ppi.c')) system_ss.add(when: 'CONFIG_TPM_CRB', if_true: files('tpm_ppi.c')) From patchwork Tue Nov 14 02:09:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13454726 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70123C4332F for ; Tue, 14 Nov 2023 02:11:26 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r2isN-0001Qy-DJ; Mon, 13 Nov 2023 21:10:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r2isL-0001Q3-PX for qemu-devel@nongnu.org; Mon, 13 Nov 2023 21:10:01 -0500 Received: from mail-pg1-f172.google.com ([209.85.215.172]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r2isJ-0007cN-2o for qemu-devel@nongnu.org; Mon, 13 Nov 2023 21:10:01 -0500 Received: by mail-pg1-f172.google.com with SMTP id 41be03b00d2f7-5c184b3bbc4so1507277a12.1 for ; Mon, 13 Nov 2023 18:09:58 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699927797; x=1700532597; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LKng5jW02pfTHM8qdP5SDtXR0Tx7XEwnbKFIYpevwgw=; b=ZJD+Q0HHzibOc4tshZvlKF5ng6NfpWZOokXfELxfBV5oWXdMGGfq98CO0WyRk/DiEH Q+zdT5+xJv43ml12zogbE+k7sORorbUa1dUSQlRFr3Idpx2GSXe9f20mLG7G8mkC98tW 6AvtNIi/hQR9PlrfehO8Kl8p01yqphBN8vBhViTi2jJjxrYfCCaXayMU4T7YIM0jclZ0 MsEI2AS2Eowh1HmsVsm/5bbhaQh2jZC+1QhvXxwCGAu8ZiXc2YsvgI+s7GFVWFD/sIvG 35At6nMR8YcKxWBSVibfwXW+8yWfXAmF1f+vDva3Wrc6Lx+EWt6tB0bVzrtjNZqikDBl SUzA== X-Gm-Message-State: AOJu0Yww3w/4VCeHrJY4UFSY2ivz+PkmeBjb3ovXJgXMpodn0igWWEhI JIXcwBxb3PK5i1aXQprSRRrCfAsl/wF9Jw== X-Google-Smtp-Source: AGHT+IFPHKYXRxig3YZ6/NdufQnSjhVrgOplFvuUcwq4isRvQy5PasPdMmVh0UStoRrmeaJw2yH3jw== X-Received: by 2002:a05:6a20:4424:b0:169:7d6f:9f22 with SMTP id ce36-20020a056a20442400b001697d6f9f22mr10622495pzb.54.1699927797673; Mon, 13 Nov 2023 18:09:57 -0800 (PST) Received: from localhost.localdomain ([2601:642:4c01:2f7:5d09:c219:9099:a639]) by smtp.gmail.com with ESMTPSA id g13-20020a17090ae58d00b0027d12b1e29dsm6175362pjz.25.2023.11.13.18.09.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Nov 2023 18:09:56 -0800 (PST) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Stefan Berger , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha Subject: [PATCH v5 12/14] tests: acpi: implement TPM CRB tests for ARM virt Date: Mon, 13 Nov 2023 18:09:22 -0800 Message-ID: <20231114020927.62315-13-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231114020927.62315-1-j@getutm.app> References: <20231114020927.62315-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.172; envelope-from=osy86dev@gmail.com; helo=mail-pg1-f172.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- tests/qtest/bios-tables-test.c | 43 ++++++++++++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 2 deletions(-) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 71af5cf69f..bb4ebf00c1 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1447,6 +1447,28 @@ static void test_acpi_piix4_tcg_numamem(void) uint64_t tpm_tis_base_addr; +static test_data tcg_tpm_test_data(const char *machine) +{ + if (g_strcmp0(machine, "virt") == 0) { + test_data data = { + .machine = "virt", + .tcg_only = true, + .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 = "pc-bios/edk2-arm-vars.fd", + .cd = + "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2", + .ram_start = 0x40000000ULL, + .scan_len = 128ULL * 1024 * 1024, + }; + return data; + } else { + test_data data = { + .machine = machine, + }; + return data; + } +} + static void test_acpi_tcg_tpm(const char *machine, const char *tpm_if, uint64_t base, enum TPMVersion tpm_version) { @@ -1454,7 +1476,7 @@ static void test_acpi_tcg_tpm(const char *machine, const char *tpm_if, machine, tpm_if); char *tmp_path = g_dir_make_tmp(tmp_dir_name, NULL); TPMTestState test; - test_data data = {}; + test_data data = tcg_tpm_test_data(machine); GThread *thread; const char *suffix = tpm_version == TPM_VERSION_2_0 ? "tpm2" : "tpm12"; char *args, *variant = g_strdup_printf(".%s.%s", tpm_if, suffix); @@ -1474,13 +1496,14 @@ static void test_acpi_tcg_tpm(const char *machine, const char *tpm_if, thread = g_thread_new(NULL, tpm_emu_ctrl_thread, &test); tpm_emu_test_wait_cond(&test); - data.machine = machine; data.variant = variant; args = g_strdup_printf( + " %s" " -chardev socket,id=chr,path=%s" " -tpmdev emulator,id=dev,chardev=chr" " -device tpm-%s,tpmdev=dev", + g_strcmp0(machine, "virt") == 0 ? "-cpu cortex-a57" : "", test.addr->u.q_unix.path, tpm_if); test_acpi_one(args, &data); @@ -1506,6 +1529,16 @@ static void test_acpi_q35_tcg_tpm12_tis(void) test_acpi_tcg_tpm("q35", "tis", 0xFED40000, TPM_VERSION_1_2); } +static void test_acpi_q35_tcg_tpm2_crb(void) +{ + test_acpi_tcg_tpm("q35", "crb", 0xFED40000, TPM_VERSION_2_0); +} + +static void test_acpi_virt_tcg_tpm2_crb(void) +{ + test_acpi_tcg_tpm("virt", "crb-device", 0xFED40000, TPM_VERSION_2_0); +} + static void test_acpi_tcg_dimm_pxm(const char *machine) { test_data data = {}; @@ -2212,6 +2245,9 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/q35/tpm12-tis", test_acpi_q35_tcg_tpm12_tis); } + if (tpm_model_is_available("-machine q35", "tpm-crb")) { + qtest_add_func("acpi/q35/tpm2-crb", test_acpi_q35_tcg_tpm2_crb); + } qtest_add_func("acpi/q35/bridge", test_acpi_q35_tcg_bridge); qtest_add_func("acpi/q35/no-acpi-hotplug", test_acpi_q35_tcg_no_acpi_hotplug); @@ -2301,6 +2337,9 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/virt/viot", test_acpi_virt_viot); } } + if (tpm_model_is_available("-machine virt", "tpm-crb")) { + qtest_add_func("acpi/virt/tpm2-crb", test_acpi_virt_tcg_tpm2_crb); + } } ret = g_test_run(); boot_sector_cleanup(disk); From patchwork Tue Nov 14 02:09:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13454737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 593B7C4332F for ; Tue, 14 Nov 2023 02:15:10 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r2isQ-0001Rp-O8; Mon, 13 Nov 2023 21:10:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r2isO-0001RE-Ed for qemu-devel@nongnu.org; Mon, 13 Nov 2023 21:10:04 -0500 Received: from mail-pf1-f170.google.com ([209.85.210.170]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r2isL-0007eD-9H for qemu-devel@nongnu.org; Mon, 13 Nov 2023 21:10:04 -0500 Received: by mail-pf1-f170.google.com with SMTP id d2e1a72fcca58-6bb4abb8100so4252981b3a.2 for ; Mon, 13 Nov 2023 18:10:00 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699927800; x=1700532600; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OBfH51c4RFRkGG5vljBK2ptO3oyO8WStfwjKun2xG4g=; b=pAx/fOxkBfZbUJzAAEAu2RG7KrxDhO/UDgruK5/6oXKSXs0o6NKmQ/KfPcfkfpQ9vV 52vII4Qt9OEVB3NCm73E4wCl0pUB+SOyVAO3uuXzye4VU98VDRAyxRW4b192ZTtHRc7g sZEY8M0cflEN5HABMLwMhDUe6IIgt2N6x7R/zZDAhXzwAgGa/Jt/gWT8NY+44okD/M9+ GSwQabglvmv5o3lQvemWNJfAOoYuR2cWjfrbuIbJWmTnoApHXnAxNdW1Bs3c1mXHYnNh rg4xbm5zVXdtyBcLI/CKVCCFDLYX4DMSf8CWN2jmp6k5G3cRhPLZJwSzbodjxVjhJQqL wNgQ== X-Gm-Message-State: AOJu0YyYPlBdSE+F5gZf1H9v1JltaGnhjcq4RE+0vguIpKt+9otn2NB7 SILouu6UXsX0+ZFJzGxakQ1sm4u/5GiAXg== X-Google-Smtp-Source: AGHT+IGRrfqp+rvSBTPP6sKmw3fKfiwehALNv5H8Ztm80QwED/NX5jE5Xbi4yEdHwbJSKTnjts/ZjA== X-Received: by 2002:a05:6a20:8f25:b0:186:8a9b:2e1 with SMTP id b37-20020a056a208f2500b001868a9b02e1mr4156221pzk.44.1699927799800; Mon, 13 Nov 2023 18:09:59 -0800 (PST) Received: from localhost.localdomain ([2601:642:4c01:2f7:5d09:c219:9099:a639]) by smtp.gmail.com with ESMTPSA id g13-20020a17090ae58d00b0027d12b1e29dsm6175362pjz.25.2023.11.13.18.09.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Nov 2023 18:09:58 -0800 (PST) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Stefan Berger , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha Subject: [PATCH v5 13/14] tests: acpi: updated expected blobs for TPM CRB Date: Mon, 13 Nov 2023 18:09:23 -0800 Message-ID: <20231114020927.62315-14-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231114020927.62315-1-j@getutm.app> References: <20231114020927.62315-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.210.170; envelope-from=osy86dev@gmail.com; helo=mail-pf1-f170.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Joelle van Dyne Tested-by: Stefan Berger --- tests/qtest/bios-tables-test-allowed-diff.h | 4 ---- tests/data/acpi/q35/DSDT.crb.tpm2 | Bin 0 -> 8355 bytes tests/data/acpi/q35/TPM2.crb.tpm2 | Bin 0 -> 76 bytes tests/data/acpi/virt/DSDT.crb-device.tpm2 | Bin 0 -> 5276 bytes tests/data/acpi/virt/TPM2.crb-device.tpm2 | Bin 0 -> 76 bytes 5 files changed, 4 deletions(-) diff --git a/tests/data/acpi/q35/DSDT.crb.tpm2 b/tests/data/acpi/q35/DSDT.crb.tpm2 index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..fb89ae0ac6d4346e33156e9e4d3718698a0a1a8e 100644 GIT binary patch literal 8355 zcmb7JOKcm*8J^`sS}m8-l3H7S#U`8>eWXYzJ1?|oP;!?qOOz=tWv8G4E+waxod8)R zF%Ty(AS*!P_|$}T&?B8HKyU4-*Ba=hz4_JvJ@wE_u0;`_qJIC(jyR z|M_Nj=UdMBf#3Umi815V>Lsrkl&WuZyb?YJV~mdJ*J)+0vi^==Z48WDDr5BTC~XclT0V1EX9t%8FLUoL=J{8a$7|Wqc45(S`t5&S`0mW9UwnDx z{mR3i|KnHp-m)?PoX4+;-wP3ag&&31>2U0PF}iNtCOSX2JYM`_#7~Phht5PHwLGvz z6Qx?-d&^zP*8HHIAHOoX!J`}kkI_Fg!iy?@uC#YS- zrTUv~WpJ%1@T%q7MVzRvwYx^{k)ToFRo6D!rB2I#qtrL5tKJH8&vm@o#Z>=UiuU)T zZ9+u1jO&bY^nXCjd(3^l0?srP<%;MljIp6xo$K)N^k)t=pcpkO!Uqsv2HV7CxINlr zqfHxQv(Ii1jp6O#EyJ39I>6&|+UO?|M4RF=n4OkaXRbZKuMuri#S%~yOl!FkU<(jlNIwB^beO&;Npl_0M3hZoCl~3 ziHZCio8nAh*I0HosF6cTDsyZD_r=#g~be#xQodr#2LDN~#bs|)C z7B!tkO=nTpiBQ$KsOenPbS~;T5vn>}O{c5rbakBwRh>sPokujCM|7PCRh>sQokumD zM|GVDRh_UgF=z2vX-U($r0Ybe>O7|DJf`V9rt3tg>O9Vwm3SsR&Y9JCvO6xA-qVnn zevCb#F;8gB6FL*2$~>ttPioAQIuoJFJf$&DY0OhP6QRm{Mq@ssF`vFwO=K`)$^IEADxgmc6rq#`0~J_lpbC@>R6w5?C_?l`8mPd=5!FOi>6pZnBSr>_ z5Iy2p7^uL;QLK?O$v_2EhN?~&s7TA1Fi-_b28vL+A{i(`sS^e&u$&14RiI>`0?KQW zfg+STVW0xbnJ`cVN(L&RoJj_XQ0jz%3M^;BKouw%sDN@N87M+|Jz<~%%b74x1xf}g zpqxnticso=feI{V!ax-$8K{7ACK)I~sS^e&u$&14RiI>`0?L_Wpa`W-7^uKf}LawZulLa7r5DzKah z16818paRO7WS|J8P8g`bawZH^fs%m=C})y^B9uB|paRR8Fi-_b1}dPONd}5g>V$y` zEN8+%6(|{~fN~}oC_Az;Y%GRDqI#3Mglifg+ST zVW0xbnJ`cVN(L&RoJj_XQ0jz%3M^;BKouw%sDN@N87M-j69y`}VUmF=OcK^?eeK12m6?d_< zj{pDTxsR-!ZMJ94?O8eZrPjLForCRm%Y}I>_t^}a<4Xy**ga~qviNRAA8lI;jE<0~ zTkh|!&cf#_awW!I5bG}{N(Y6b*5YULY%UFlVwi&&W>a>HxeJ4!S7Ce9g-&<9;uZ#e zD`2c%0eSC#5jUcHL`snx6Q^y=0A zZkx1=wHT~I#oDdZA>|dr0>%4qDQNDga`FdQwkt{!Ri1H1ke1n&7 zB+54qDBp<7H6%l<>Y}^13d0xaZ+z{XZRzJ zA9}9ibjioqD(LC(zA%wav`tMn@mv=5ba;uFNGIB+rki-q7WH&^vzSOH+NP$Pcy3%h z9bPvk(uuaI=_a0oBYHZ#gG{6oZBx@t+}B6-ba*kDNGIB+rkl7=m-KXaTbW2F+Vpfz z+Z4B9w`6y(g5bLpfY&`$@Xvls$wAsJ@o85ys!qRAYy?VG&^FA-|#xCEAc~m7dzp*X5f9Ho3R9MOD)Yc5IwH6p& zw|&{b%6pl<>IO@DUfaj&evy!AFQ~1S0QW1s5|*u7Yb`Tk)QE@g!d1R8fDVaH#%h+! z)D5w%l64DSul~!_*cxrKPdrGy?lxzzZBUu(KYR7Xj4G4_(7J!J8O0*n2^l3%kc7xu zzIL4Kd4LSlTdQ3uruHMY6&csQ@{6NuM#Qc~ zMi{Z-SF84KMxk+k3r%6Pl`P2xCmV55#!L5;t+*^(UytWTLu(&pzK*7yA3rxSa&+CJ zt-I96A-g$5uO7TQet81M?+jeNEh`;O3=B?!cXNxj-D(-J??wqX*%n=LXxr*9PZu|l z3;nsdIenPhbKa$(XCE-k)9;pv{209G`joMWtW>gwo+j-P81RGuqX` zeQoa1-Hj)pUFj8amdUViL9fH^JT?}4ITFLRuitP_;^DzGFsPN!v-pXp2Z`<}r+q{` zS$sc;Pa+p{)}Qa@SqgI$KKt}#G>pggW7{y%ZrIp?VeC7cer!L9^VmLO>_2>SkDsTv z>HU3ro2E~SY1@7#cDDW~&agjdXC7id@OyFQ;p_LF$5vsSO|+3Z+7^RQ?L#r9pIt8l zonp_G?>ts8-HEA;+LbvBlXS0Q<;1kf=djXDX~w`FWPkT!rqk?n`COPtfpHcQS7~x{+9&8L_IGnZxjZlj6~7BLKMu;Ti2zs3VDRu@*=N|@ z#KC!aaDfh>+zska!DnbbZ*|vGR%qFdm*GYFcYgX}n#vH8&KmSD2mi>{tMuj3mv1td z*?NtR>-5#2ucq1GeQBlYqcdVlJPl7IO|f|$vyL>3kcG^^?RJe_!|&M?zpBr*FKs+w zE#Rd_VVPF;ENvb4ch9eOddo6*2IB<>!{00g>sa}Q@j?27v}vB*;hE2Sm)cJ_S)iwL z9;Y9tnR(XXoO9it_oO#D)FJ2PsUsFK!#v9j>drz?uf*e?Vi-zlsKyOxG&nXrlX!Wk HVR!t0z{JvO literal 0 HcmV?d00001 diff --git a/tests/data/acpi/q35/TPM2.crb.tpm2 b/tests/data/acpi/q35/TPM2.crb.tpm2 index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..9d89c5becc0fc4558a0556daf46e152181f2eb51 100644 GIT binary patch literal 76 zcmWFu@HO&bU|?Wja`Jcf2v%^42yj*a0!E-1hz+7az=7e)KM>6hB2WNG#ec9c0JCKY A0RR91 literal 0 HcmV?d00001 diff --git a/tests/data/acpi/virt/DSDT.crb-device.tpm2 b/tests/data/acpi/virt/DSDT.crb-device.tpm2 index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..1b3a8ef4cb3ab093402f4bdb2a349b3d0d015ad5 100644 GIT binary patch literal 5276 zcmZvg%WoT16o>D`lh__VVmr?JVHZlpGaB1Xla{u`9y^IkoEVSWAf=KkRYjC+Dp6G` z6;jBeh3;r1RxE-P3H}TuR_xfZV9kbqfF0&{=guVOsAr^%=gi#m&Hcv5@$qf?&Hj%? zrAB^f?0Q>%x$$Y&D`T^iQu8F~^Y@MZ&m7 z8Dg384@p$&Q-tv$Wyp1!mgX@-7}qI7uG5Ufm?MlElp)t?R$?p=#!bqQ>vUXVED^>> zlp)t?PGXb^W1TYOI?YRrHwdFn8FHN#B*sO;Xi$b+rxOz65@C3RQI+eoC^6n9j3#Bs zbvh|A-X)9{Wyp0pB{AM7j19_=>vURTEEC2iWyp0pBQadU*rE)%PG==Xl`z_rA=l}g z#JEftwWPqgrkH1nd8W80Lh6}jo@wTZmXCTOq@Ee(nPHw8?un3kW|?P}d7?$6o(QSuIP)B5 zp5xpTA@#)18B^my73Y{IT1x7Pkb35sXP$ZHxhF#ESzw+8=7|=RdLpEr6U=jhc}{Ro zgwzv16p3e%d7@>do(QSuB=ekPo|D`YA@!VMo>R;dEiUy$NIj>S=QQ)2=AH4mY8}Xq@J_PbC!9|a!-WRbB=k=F;BG6)Dt1~oM)c%%yXW5BBY)R%yWTxqUENZ z2&v~H^IT+}i`)|-^;}|}OUx53I`u?IJxk29#5_yf6QS|kKWf|htu#O1^p~>dZk&A) zcd;yybyC4n#GAoaI=**bJ69YV_&whWQDMixP*^9RsEY#1oI69^(z6O1T!zx?1(fxc zz%u7JD{OQ*3+o1ybxB~Eb0Mpk8+eVnI>rA`m0QQoJdUln^Z4708o|GFY(u@XUf|P} zMt2cxx#93X{j&_)a2Z#uG+vPM?3O68`OOS0%iD zZ(9{Nl7n5}vtJ%4uenz_*@_>3o}X}X`<=gP|CSckf7p9m|MkY7pS?VAYz(O4HG$XK zBOPdtKB#HbGre<4dVi98b^Or!8doa8=*r2|tK(>#Ii1rNAL+sR{OQ3@S#w_Bq;h&t z{9w@ZJNC&1Gn+qFfB)NG`Kt5%^go^1-@MLA^7spNnvYqQ-eIAuWA|DtZM4G{fq1{ccJWw+dX@Z{nB2POj_8@q4~S+55hwtp;-oW32mq=x B2mt^9 literal 0 HcmV?d00001 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index c2d1924c2f..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,5 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/q35/DSDT.crb.tpm2", -"tests/data/acpi/q35/TPM2.crb.tpm2", -"tests/data/acpi/virt/DSDT.crb.tpm2", -"tests/data/acpi/virt/TPM2.crb.tpm2", From patchwork Tue Nov 14 02:09:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13454735 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3810BC4332F for ; Tue, 14 Nov 2023 02:12:26 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r2isa-0001Sc-Fx; Mon, 13 Nov 2023 21:10:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r2isT-0001SB-EE for qemu-devel@nongnu.org; Mon, 13 Nov 2023 21:10:09 -0500 Received: from mail-pf1-f176.google.com ([209.85.210.176]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r2isQ-0007qe-FZ for qemu-devel@nongnu.org; Mon, 13 Nov 2023 21:10:09 -0500 Received: by mail-pf1-f176.google.com with SMTP id d2e1a72fcca58-6b5af4662b7so4420441b3a.3 for ; Mon, 13 Nov 2023 18:10:06 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699927804; x=1700532604; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0HzVGYAwG45YmMVBphKqNzgqtvt9RPSnTc9N48TOsN4=; b=aeM0yjbJfcPpWC5RDRjoZcCBQ4xciQODw1IBIj1XDUqLufSoiPmFX4y6vB5WgMUQNH RV/aQXYfR6SBrm1fi0nnQGi91RAro6PrkSWxBOZ4TF+tcEM8q4PlByJ2TziySVJoUydK YXUEj/OYHp8ka9DYLiwmllJBXAtmV8mOt0C9uKYJr4lWkJkRS7sJqenCb8Y+iQiUqykL RYo+sqBWO66tdb7TUmGhhqQ0OXrkEp7Ll5p8rm0fgIn/tzdGWykGZUh35A3jCfLluhKT BoJSfuWjorFoLmkrWOVXeS5KVD0BcNUWQYhZwA/Vdv1zCT4Jv2LbSnt2CtGnnMR9rDJH Wlkg== X-Gm-Message-State: AOJu0YyQsnnnRLTCm0MjeYb0GemK2Jj4br1ZhLjrs//OydM0rwA4zoW6 iAvttiSar8/otYUXziSGizL36V+kLQwzGA== X-Google-Smtp-Source: AGHT+IHoU4lSx7lPqVre9T0vHZY/6AvkiNs3cvPtwMHV+A1+6T0aGKYAhvB9awOEVvvWiSy/uv2P/A== X-Received: by 2002:a05:6a21:7182:b0:181:82f0:6f77 with SMTP id wq2-20020a056a21718200b0018182f06f77mr7480637pzb.61.1699927802769; Mon, 13 Nov 2023 18:10:02 -0800 (PST) Received: from localhost.localdomain ([2601:642:4c01:2f7:5d09:c219:9099:a639]) by smtp.gmail.com with ESMTPSA id g13-20020a17090ae58d00b0027d12b1e29dsm6175362pjz.25.2023.11.13.18.10.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Nov 2023 18:10:01 -0800 (PST) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Stefan Berger , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha , Thomas Huth , Laurent Vivier , Paolo Bonzini , Stefan Berger Subject: [PATCH v5 14/14] tests: add TPM-CRB sysbus tests for aarch64 Date: Mon, 13 Nov 2023 18:09:24 -0800 Message-ID: <20231114020927.62315-15-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231114020927.62315-1-j@getutm.app> References: <20231114020927.62315-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.210.176; envelope-from=osy86dev@gmail.com; helo=mail-pf1-f176.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org - Factor out common test code from tpm-crb-test.c -> tpm-tests.c - Store device addr in `tpm_device_base_addr` (unify with TIS tests) - Add new tests for aarch64 Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- tests/qtest/tpm-tests.h | 2 + tests/qtest/tpm-util.h | 4 +- tests/qtest/bios-tables-test.c | 4 +- tests/qtest/tpm-crb-device-swtpm-test.c | 72 ++++++++++++++ tests/qtest/tpm-crb-device-test.c | 71 ++++++++++++++ tests/qtest/tpm-crb-swtpm-test.c | 2 + tests/qtest/tpm-crb-test.c | 121 +----------------------- tests/qtest/tpm-tests.c | 121 ++++++++++++++++++++++++ tests/qtest/tpm-tis-device-swtpm-test.c | 2 +- tests/qtest/tpm-tis-device-test.c | 2 +- tests/qtest/tpm-tis-i2c-test.c | 3 + tests/qtest/tpm-tis-swtpm-test.c | 2 +- tests/qtest/tpm-tis-test.c | 2 +- tests/qtest/tpm-util.c | 16 ++-- tests/qtest/meson.build | 4 + 15 files changed, 295 insertions(+), 133 deletions(-) create mode 100644 tests/qtest/tpm-crb-device-swtpm-test.c create mode 100644 tests/qtest/tpm-crb-device-test.c diff --git a/tests/qtest/tpm-tests.h b/tests/qtest/tpm-tests.h index 07ba60d26e..c1bfb2f914 100644 --- a/tests/qtest/tpm-tests.h +++ b/tests/qtest/tpm-tests.h @@ -24,4 +24,6 @@ void tpm_test_swtpm_migration_test(const char *src_tpm_path, const char *ifmodel, const char *machine_options); +void tpm_test_crb(const void *data); + #endif /* TESTS_TPM_TESTS_H */ diff --git a/tests/qtest/tpm-util.h b/tests/qtest/tpm-util.h index 0cb28dd6e5..c99380684e 100644 --- a/tests/qtest/tpm-util.h +++ b/tests/qtest/tpm-util.h @@ -15,10 +15,10 @@ #include "io/channel-socket.h" -extern uint64_t tpm_tis_base_addr; +extern uint64_t tpm_device_base_addr; #define TIS_REG(LOCTY, REG) \ - (tpm_tis_base_addr + ((LOCTY) << 12) + REG) + (tpm_device_base_addr + ((LOCTY) << 12) + REG) typedef void (tx_func)(QTestState *s, const unsigned char *req, size_t req_size, diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index bb4ebf00c1..01e0a4aa00 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1445,7 +1445,7 @@ static void test_acpi_piix4_tcg_numamem(void) free_test_data(&data); } -uint64_t tpm_tis_base_addr; +uint64_t tpm_device_base_addr; static test_data tcg_tpm_test_data(const char *machine) { @@ -1481,7 +1481,7 @@ static void test_acpi_tcg_tpm(const char *machine, const char *tpm_if, const char *suffix = tpm_version == TPM_VERSION_2_0 ? "tpm2" : "tpm12"; char *args, *variant = g_strdup_printf(".%s.%s", tpm_if, suffix); - tpm_tis_base_addr = base; + tpm_device_base_addr = base; module_call_init(MODULE_INIT_QOM); diff --git a/tests/qtest/tpm-crb-device-swtpm-test.c b/tests/qtest/tpm-crb-device-swtpm-test.c new file mode 100644 index 0000000000..332add5ca6 --- /dev/null +++ b/tests/qtest/tpm-crb-device-swtpm-test.c @@ -0,0 +1,72 @@ +/* + * QTest testcase for TPM CRB talking to external swtpm and swtpm migration + * + * Copyright (c) 2018 IBM Corporation + * with parts borrowed from migration-test.c that is: + * Copyright (c) 2016-2018 Red Hat, Inc. and/or its affiliates + * + * Authors: + * Stefan Berger + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" + +#include "libqtest.h" +#include "qemu/module.h" +#include "tpm-tests.h" +#include "hw/acpi/tpm.h" + +uint64_t tpm_device_base_addr = 0xc000000; +#define MACHINE_OPTIONS "-machine virt,gic-version=max -accel tcg" + +typedef struct TestState { + char *src_tpm_path; + char *dst_tpm_path; + char *uri; +} TestState; + +static void tpm_crb_swtpm_test(const void *data) +{ + const TestState *ts = data; + + tpm_test_swtpm_test(ts->src_tpm_path, tpm_util_crb_transfer, + "tpm-crb-device", MACHINE_OPTIONS); +} + +static void tpm_crb_swtpm_migration_test(const void *data) +{ + const TestState *ts = data; + + tpm_test_swtpm_migration_test(ts->src_tpm_path, ts->dst_tpm_path, ts->uri, + tpm_util_crb_transfer, "tpm-crb-device", + MACHINE_OPTIONS); +} + +int main(int argc, char **argv) +{ + int ret; + TestState ts = { 0 }; + + ts.src_tpm_path = g_dir_make_tmp("qemu-tpm-crb-swtpm-test.XXXXXX", NULL); + ts.dst_tpm_path = g_dir_make_tmp("qemu-tpm-crb-swtpm-test.XXXXXX", NULL); + ts.uri = g_strdup_printf("unix:%s/migsocket", ts.src_tpm_path); + + module_call_init(MODULE_INIT_QOM); + g_test_init(&argc, &argv, NULL); + + qtest_add_data_func("/tpm/crb-swtpm/test", &ts, tpm_crb_swtpm_test); + qtest_add_data_func("/tpm/crb-swtpm-migration/test", &ts, + tpm_crb_swtpm_migration_test); + ret = g_test_run(); + + tpm_util_rmdir(ts.dst_tpm_path); + g_free(ts.dst_tpm_path); + tpm_util_rmdir(ts.src_tpm_path); + g_free(ts.src_tpm_path); + g_free(ts.uri); + + return ret; +} diff --git a/tests/qtest/tpm-crb-device-test.c b/tests/qtest/tpm-crb-device-test.c new file mode 100644 index 0000000000..17d09a57fd --- /dev/null +++ b/tests/qtest/tpm-crb-device-test.c @@ -0,0 +1,71 @@ +/* + * QTest testcase for TPM CRB + * + * Copyright (c) 2018 Red Hat, Inc. + * + * Authors: + * Marc-André Lureau + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include + +#include "hw/acpi/tpm.h" +#include "io/channel-socket.h" +#include "libqtest-single.h" +#include "qemu/module.h" +#include "tpm-emu.h" +#include "tpm-tests.h" + +/* + * As the Sysbus tpm-crb-device is instantiated on the ARM virt + * platform bus and it is the only sysbus device dynamically + * instantiated, it gets plugged at its base address + */ +uint64_t tpm_device_base_addr = 0xc000000; + +int main(int argc, char **argv) +{ + int ret; + char *args, *tmp_path = g_dir_make_tmp("qemu-tpm-crb-test.XXXXXX", NULL); + GThread *thread; + TPMTestState test; + + module_call_init(MODULE_INIT_QOM); + g_test_init(&argc, &argv, NULL); + + test.addr = g_new0(SocketAddress, 1); + test.addr->type = SOCKET_ADDRESS_TYPE_UNIX; + test.addr->u.q_unix.path = g_build_filename(tmp_path, "sock", NULL); + g_mutex_init(&test.data_mutex); + g_cond_init(&test.data_cond); + test.data_cond_signal = false; + test.tpm_version = TPM_VERSION_2_0; + + thread = g_thread_new(NULL, tpm_emu_ctrl_thread, &test); + tpm_emu_test_wait_cond(&test); + + args = g_strdup_printf( + "-machine virt,gic-version=max -accel tcg " + "-chardev socket,id=chr,path=%s " + "-tpmdev emulator,id=dev,chardev=chr " + "-device tpm-crb-device,tpmdev=dev", + test.addr->u.q_unix.path); + qtest_start(args); + + qtest_add_data_func("/tpm-crb/test", &test, tpm_test_crb); + ret = g_test_run(); + + qtest_end(); + + g_thread_join(thread); + g_unlink(test.addr->u.q_unix.path); + qapi_free_SocketAddress(test.addr); + g_rmdir(tmp_path); + g_free(tmp_path); + g_free(args); + return ret; +} diff --git a/tests/qtest/tpm-crb-swtpm-test.c b/tests/qtest/tpm-crb-swtpm-test.c index ffeb1c396b..08862210a4 100644 --- a/tests/qtest/tpm-crb-swtpm-test.c +++ b/tests/qtest/tpm-crb-swtpm-test.c @@ -19,6 +19,8 @@ #include "tpm-tests.h" #include "hw/acpi/tpm.h" +uint64_t tpm_device_base_addr = TPM_CRB_ADDR_BASE; + typedef struct TestState { char *src_tpm_path; char *dst_tpm_path; diff --git a/tests/qtest/tpm-crb-test.c b/tests/qtest/tpm-crb-test.c index 9d30fe8293..51614abc70 100644 --- a/tests/qtest/tpm-crb-test.c +++ b/tests/qtest/tpm-crb-test.c @@ -18,124 +18,9 @@ #include "libqtest-single.h" #include "qemu/module.h" #include "tpm-emu.h" +#include "tpm-tests.h" -#define TPM_CMD "\x80\x01\x00\x00\x00\x0c\x00\x00\x01\x44\x00\x00" - -static void tpm_crb_test(const void *data) -{ - const TPMTestState *s = data; - uint32_t intfid = readl(TPM_CRB_ADDR_BASE + A_CRB_INTF_ID); - uint32_t csize = readl(TPM_CRB_ADDR_BASE + A_CRB_CTRL_CMD_SIZE); - uint64_t caddr = readq(TPM_CRB_ADDR_BASE + A_CRB_CTRL_CMD_LADDR); - uint32_t rsize = readl(TPM_CRB_ADDR_BASE + A_CRB_CTRL_RSP_SIZE); - uint64_t raddr = readq(TPM_CRB_ADDR_BASE + A_CRB_CTRL_RSP_LADDR); - uint8_t locstate = readb(TPM_CRB_ADDR_BASE + A_CRB_LOC_STATE); - uint32_t locctrl = readl(TPM_CRB_ADDR_BASE + A_CRB_LOC_CTRL); - uint32_t locsts = readl(TPM_CRB_ADDR_BASE + A_CRB_LOC_STS); - uint32_t sts = readl(TPM_CRB_ADDR_BASE + A_CRB_CTRL_STS); - - g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, InterfaceType), ==, 1); - g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, InterfaceVersion), ==, 1); - g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapLocality), ==, 0); - g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapCRBIdleBypass), ==, 0); - g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapDataXferSizeSupport), - ==, 3); - g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapFIFO), ==, 0); - g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapCRB), ==, 1); - g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, InterfaceSelector), ==, 1); - g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, RID), ==, 0); - - g_assert_cmpint(csize, >=, 128); - g_assert_cmpint(rsize, >=, 128); - g_assert_cmpint(caddr, >, TPM_CRB_ADDR_BASE); - g_assert_cmpint(raddr, >, TPM_CRB_ADDR_BASE); - - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmEstablished), ==, 1); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, locAssigned), ==, 0); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, activeLocality), ==, 0); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, reserved), ==, 0); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmRegValidSts), ==, 1); - - g_assert_cmpint(locctrl, ==, 0); - - g_assert_cmpint(FIELD_EX32(locsts, CRB_LOC_STS, Granted), ==, 0); - g_assert_cmpint(FIELD_EX32(locsts, CRB_LOC_STS, beenSeized), ==, 0); - - g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmIdle), ==, 1); - g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmSts), ==, 0); - - /* request access to locality 0 */ - writeb(TPM_CRB_ADDR_BASE + A_CRB_LOC_CTRL, 1); - - /* granted bit must be set now */ - locsts = readl(TPM_CRB_ADDR_BASE + A_CRB_LOC_STS); - g_assert_cmpint(FIELD_EX32(locsts, CRB_LOC_STS, Granted), ==, 1); - g_assert_cmpint(FIELD_EX32(locsts, CRB_LOC_STS, beenSeized), ==, 0); - - /* we must have an assigned locality */ - locstate = readb(TPM_CRB_ADDR_BASE + A_CRB_LOC_STATE); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmEstablished), ==, 1); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, locAssigned), ==, 1); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, activeLocality), ==, 0); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, reserved), ==, 0); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmRegValidSts), ==, 1); - - /* set into ready state */ - writel(TPM_CRB_ADDR_BASE + A_CRB_CTRL_REQ, 1); - - /* TPM must not be in the idle state */ - sts = readl(TPM_CRB_ADDR_BASE + A_CRB_CTRL_STS); - g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmIdle), ==, 0); - g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmSts), ==, 0); - - memwrite(caddr, TPM_CMD, sizeof(TPM_CMD)); - - uint32_t start = 1; - uint64_t end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND; - writel(TPM_CRB_ADDR_BASE + A_CRB_CTRL_START, start); - do { - start = readl(TPM_CRB_ADDR_BASE + A_CRB_CTRL_START); - if ((start & 1) == 0) { - break; - } - } while (g_get_monotonic_time() < end_time); - start = readl(TPM_CRB_ADDR_BASE + A_CRB_CTRL_START); - g_assert_cmpint(start & 1, ==, 0); - - /* TPM must still not be in the idle state */ - sts = readl(TPM_CRB_ADDR_BASE + A_CRB_CTRL_STS); - g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmIdle), ==, 0); - g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmSts), ==, 0); - - struct tpm_hdr tpm_msg; - memread(raddr, &tpm_msg, sizeof(tpm_msg)); - g_assert_cmpmem(&tpm_msg, sizeof(tpm_msg), s->tpm_msg, sizeof(*s->tpm_msg)); - - /* set TPM into idle state */ - writel(TPM_CRB_ADDR_BASE + A_CRB_CTRL_REQ, 2); - - /* idle state must be indicated now */ - sts = readl(TPM_CRB_ADDR_BASE + A_CRB_CTRL_STS); - g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmIdle), ==, 1); - g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmSts), ==, 0); - - /* relinquish locality */ - writel(TPM_CRB_ADDR_BASE + A_CRB_LOC_CTRL, 2); - - /* Granted flag must be cleared */ - sts = readl(TPM_CRB_ADDR_BASE + A_CRB_LOC_STS); - g_assert_cmpint(FIELD_EX32(sts, CRB_LOC_STS, Granted), ==, 0); - g_assert_cmpint(FIELD_EX32(sts, CRB_LOC_STS, beenSeized), ==, 0); - - /* no locality may be assigned */ - locstate = readb(TPM_CRB_ADDR_BASE + A_CRB_LOC_STATE); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmEstablished), ==, 1); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, locAssigned), ==, 0); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, activeLocality), ==, 0); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, reserved), ==, 0); - g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmRegValidSts), ==, 1); - -} +uint64_t tpm_device_base_addr = TPM_CRB_ADDR_BASE; int main(int argc, char **argv) { @@ -165,7 +50,7 @@ int main(int argc, char **argv) test.addr->u.q_unix.path); qtest_start(args); - qtest_add_data_func("/tpm-crb/test", &test, tpm_crb_test); + qtest_add_data_func("/tpm-crb/test", &test, tpm_test_crb); ret = g_test_run(); qtest_end(); diff --git a/tests/qtest/tpm-tests.c b/tests/qtest/tpm-tests.c index fb94496bbd..83c5536136 100644 --- a/tests/qtest/tpm-tests.c +++ b/tests/qtest/tpm-tests.c @@ -15,7 +15,10 @@ #include "qemu/osdep.h" #include +#include "hw/registerfields.h" +#include "hw/acpi/tpm.h" #include "libqtest-single.h" +#include "tpm-emu.h" #include "tpm-tests.h" static bool @@ -130,3 +133,121 @@ void tpm_test_swtpm_migration_test(const char *src_tpm_path, g_unlink(src_tpm_addr->u.q_unix.path); qapi_free_SocketAddress(src_tpm_addr); } + +#define TPM_CMD "\x80\x01\x00\x00\x00\x0c\x00\x00\x01\x44\x00\x00" + +void tpm_test_crb(const void *data) +{ + const TPMTestState *s = data; + uint32_t intfid = readl(tpm_device_base_addr + A_CRB_INTF_ID); + uint32_t csize = readl(tpm_device_base_addr + A_CRB_CTRL_CMD_SIZE); + uint64_t caddr = readq(tpm_device_base_addr + A_CRB_CTRL_CMD_LADDR); + uint32_t rsize = readl(tpm_device_base_addr + A_CRB_CTRL_RSP_SIZE); + uint64_t raddr = readq(tpm_device_base_addr + A_CRB_CTRL_RSP_LADDR); + uint8_t locstate = readb(tpm_device_base_addr + A_CRB_LOC_STATE); + uint32_t locctrl = readl(tpm_device_base_addr + A_CRB_LOC_CTRL); + uint32_t locsts = readl(tpm_device_base_addr + A_CRB_LOC_STS); + uint32_t sts = readl(tpm_device_base_addr + A_CRB_CTRL_STS); + + g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, InterfaceType), ==, 1); + g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, InterfaceVersion), ==, 1); + g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapLocality), ==, 0); + g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapCRBIdleBypass), ==, 0); + g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapDataXferSizeSupport), + ==, 3); + g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapFIFO), ==, 0); + g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapCRB), ==, 1); + g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, InterfaceSelector), ==, 1); + g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, RID), ==, 0); + + g_assert_cmpint(csize, >=, 128); + g_assert_cmpint(rsize, >=, 128); + g_assert_cmpint(caddr, >, tpm_device_base_addr); + g_assert_cmpint(raddr, >, tpm_device_base_addr); + + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmEstablished), ==, 1); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, locAssigned), ==, 0); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, activeLocality), ==, 0); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, reserved), ==, 0); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmRegValidSts), ==, 1); + + g_assert_cmpint(locctrl, ==, 0); + + g_assert_cmpint(FIELD_EX32(locsts, CRB_LOC_STS, Granted), ==, 0); + g_assert_cmpint(FIELD_EX32(locsts, CRB_LOC_STS, beenSeized), ==, 0); + + g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmIdle), ==, 1); + g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmSts), ==, 0); + + /* request access to locality 0 */ + writeb(tpm_device_base_addr + A_CRB_LOC_CTRL, 1); + + /* granted bit must be set now */ + locsts = readl(tpm_device_base_addr + A_CRB_LOC_STS); + g_assert_cmpint(FIELD_EX32(locsts, CRB_LOC_STS, Granted), ==, 1); + g_assert_cmpint(FIELD_EX32(locsts, CRB_LOC_STS, beenSeized), ==, 0); + + /* we must have an assigned locality */ + locstate = readb(tpm_device_base_addr + A_CRB_LOC_STATE); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmEstablished), ==, 1); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, locAssigned), ==, 1); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, activeLocality), ==, 0); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, reserved), ==, 0); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmRegValidSts), ==, 1); + + /* set into ready state */ + writel(tpm_device_base_addr + A_CRB_CTRL_REQ, 1); + + /* TPM must not be in the idle state */ + sts = readl(tpm_device_base_addr + A_CRB_CTRL_STS); + g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmIdle), ==, 0); + g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmSts), ==, 0); + + memwrite(caddr, TPM_CMD, sizeof(TPM_CMD)); + + uint32_t start = 1; + uint64_t end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND; + writel(tpm_device_base_addr + A_CRB_CTRL_START, start); + do { + start = readl(tpm_device_base_addr + A_CRB_CTRL_START); + if ((start & 1) == 0) { + break; + } + } while (g_get_monotonic_time() < end_time); + start = readl(tpm_device_base_addr + A_CRB_CTRL_START); + g_assert_cmpint(start & 1, ==, 0); + + /* TPM must still not be in the idle state */ + sts = readl(tpm_device_base_addr + A_CRB_CTRL_STS); + g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmIdle), ==, 0); + g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmSts), ==, 0); + + struct tpm_hdr tpm_msg; + memread(raddr, &tpm_msg, sizeof(tpm_msg)); + g_assert_cmpmem(&tpm_msg, sizeof(tpm_msg), s->tpm_msg, sizeof(*s->tpm_msg)); + + /* set TPM into idle state */ + writel(tpm_device_base_addr + A_CRB_CTRL_REQ, 2); + + /* idle state must be indicated now */ + sts = readl(tpm_device_base_addr + A_CRB_CTRL_STS); + g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmIdle), ==, 1); + g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmSts), ==, 0); + + /* relinquish locality */ + writel(tpm_device_base_addr + A_CRB_LOC_CTRL, 2); + + /* Granted flag must be cleared */ + sts = readl(tpm_device_base_addr + A_CRB_LOC_STS); + g_assert_cmpint(FIELD_EX32(sts, CRB_LOC_STS, Granted), ==, 0); + g_assert_cmpint(FIELD_EX32(sts, CRB_LOC_STS, beenSeized), ==, 0); + + /* no locality may be assigned */ + locstate = readb(tpm_device_base_addr + A_CRB_LOC_STATE); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmEstablished), ==, 1); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, locAssigned), ==, 0); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, activeLocality), ==, 0); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, reserved), ==, 0); + g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmRegValidSts), ==, 1); + +} diff --git a/tests/qtest/tpm-tis-device-swtpm-test.c b/tests/qtest/tpm-tis-device-swtpm-test.c index 517a077005..54d1cedc6f 100644 --- a/tests/qtest/tpm-tis-device-swtpm-test.c +++ b/tests/qtest/tpm-tis-device-swtpm-test.c @@ -21,7 +21,7 @@ #include "tpm-tis-util.h" #include "hw/acpi/tpm.h" -uint64_t tpm_tis_base_addr = 0xc000000; +uint64_t tpm_device_base_addr = 0xc000000; #define MACHINE_OPTIONS "-machine virt,gic-version=max -accel tcg" typedef struct TestState { diff --git a/tests/qtest/tpm-tis-device-test.c b/tests/qtest/tpm-tis-device-test.c index 3ddefb51ec..4f6609ae98 100644 --- a/tests/qtest/tpm-tis-device-test.c +++ b/tests/qtest/tpm-tis-device-test.c @@ -27,7 +27,7 @@ * platform bus and it is the only sysbus device dynamically * instantiated, it gets plugged at its base address */ -uint64_t tpm_tis_base_addr = 0xc000000; +uint64_t tpm_device_base_addr = 0xc000000; int main(int argc, char **argv) { diff --git a/tests/qtest/tpm-tis-i2c-test.c b/tests/qtest/tpm-tis-i2c-test.c index 3a1af026f2..9495cc1739 100644 --- a/tests/qtest/tpm-tis-i2c-test.c +++ b/tests/qtest/tpm-tis-i2c-test.c @@ -39,6 +39,9 @@ #define I2C_SLAVE_ADDR 0x2e #define I2C_DEV_BUS_NUM 10 +/* unused but needed for tpm-util.c to link */ +uint64_t tpm_device_base_addr; + static const uint8_t TPM_CMD[12] = "\x80\x01\x00\x00\x00\x0c\x00\x00\x01\x44\x00\x00"; diff --git a/tests/qtest/tpm-tis-swtpm-test.c b/tests/qtest/tpm-tis-swtpm-test.c index 105e42e21d..5bfbbc0a67 100644 --- a/tests/qtest/tpm-tis-swtpm-test.c +++ b/tests/qtest/tpm-tis-swtpm-test.c @@ -20,7 +20,7 @@ #include "tpm-tis-util.h" #include "hw/acpi/tpm.h" -uint64_t tpm_tis_base_addr = TPM_TIS_ADDR_BASE; +uint64_t tpm_device_base_addr = TPM_TIS_ADDR_BASE; typedef struct TestState { char *src_tpm_path; diff --git a/tests/qtest/tpm-tis-test.c b/tests/qtest/tpm-tis-test.c index a4a25ba745..7661568aa8 100644 --- a/tests/qtest/tpm-tis-test.c +++ b/tests/qtest/tpm-tis-test.c @@ -22,7 +22,7 @@ #include "tpm-emu.h" #include "tpm-tis-util.h" -uint64_t tpm_tis_base_addr = TPM_TIS_ADDR_BASE; +uint64_t tpm_device_base_addr = TPM_TIS_ADDR_BASE; int main(int argc, char **argv) { diff --git a/tests/qtest/tpm-util.c b/tests/qtest/tpm-util.c index dd02057fc0..1608901a76 100644 --- a/tests/qtest/tpm-util.c +++ b/tests/qtest/tpm-util.c @@ -24,18 +24,20 @@ void tpm_util_crb_transfer(QTestState *s, const unsigned char *req, size_t req_size, unsigned char *rsp, size_t rsp_size) { - uint64_t caddr = qtest_readq(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_CMD_LADDR); - uint64_t raddr = qtest_readq(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_RSP_LADDR); + uint64_t caddr = qtest_readq(s, tpm_device_base_addr + + A_CRB_CTRL_CMD_LADDR); + uint64_t raddr = qtest_readq(s, tpm_device_base_addr + + A_CRB_CTRL_RSP_LADDR); - qtest_writeb(s, TPM_CRB_ADDR_BASE + A_CRB_LOC_CTRL, 1); + qtest_writeb(s, tpm_device_base_addr + A_CRB_LOC_CTRL, 1); qtest_memwrite(s, caddr, req, req_size); uint32_t sts, start = 1; uint64_t end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND; - qtest_writel(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_START, start); + qtest_writel(s, tpm_device_base_addr + A_CRB_CTRL_START, start); while (true) { - start = qtest_readl(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_START); + start = qtest_readl(s, tpm_device_base_addr + A_CRB_CTRL_START); if ((start & 1) == 0) { break; } @@ -43,9 +45,9 @@ void tpm_util_crb_transfer(QTestState *s, break; } }; - start = qtest_readl(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_START); + start = qtest_readl(s, tpm_device_base_addr + A_CRB_CTRL_START); g_assert_cmpint(start & 1, ==, 0); - sts = qtest_readl(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_STS); + sts = qtest_readl(s, tpm_device_base_addr + A_CRB_CTRL_STS); g_assert_cmpint(sts & 1, ==, 0); qtest_memread(s, raddr, rsp, rsp_size); diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 47dabf91d0..386f71df4d 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -215,6 +215,8 @@ qtests_aarch64 = \ (cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) + \ (config_all.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? \ ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) + \ + (config_all.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_CRB_SYSBUS') ? \ + ['tpm-crb-device-test', 'tpm-crb-device-swtpm-test'] : []) + \ (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \ (config_all_devices.has_key('CONFIG_XLNX_VERSAL') ? ['xlnx-canfd-test', 'xlnx-versal-trng-test'] : []) + \ (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \ @@ -313,6 +315,8 @@ qtests = { 'qos-test': [chardev, io, qos_test_ss.apply(config_targetos, strict: false).sources()], 'tpm-crb-swtpm-test': [io, tpmemu_files], 'tpm-crb-test': [io, tpmemu_files], + 'tpm-crb-device-swtpm-test': [io, tpmemu_files], + 'tpm-crb-device-test': [io, tpmemu_files], 'tpm-tis-swtpm-test': [io, tpmemu_files, 'tpm-tis-util.c'], 'tpm-tis-test': [io, tpmemu_files, 'tpm-tis-util.c'], 'tpm-tis-i2c-test': [io, tpmemu_files, 'qtest_aspeed.c'],