From patchwork Tue Nov 14 07:59:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454913 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E16E8C4167B for ; Tue, 14 Nov 2023 08:00:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232283AbjKNIAk (ORCPT ); Tue, 14 Nov 2023 03:00:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229566AbjKNIAi (ORCPT ); Tue, 14 Nov 2023 03:00:38 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 621DD1A3 for ; Tue, 14 Nov 2023 00:00:34 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 6C2EC1C0305; Tue, 14 Nov 2023 17:00:33 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Rich Felker , John Paul Adrian Glaubitz Subject: [PATCH v4 01/37] sh: passing FDT address to kernel startup. Date: Tue, 14 Nov 2023 16:59:52 +0900 Message-Id: <3b24a5ce5ecd00f8d48654ee2eff8340e2827169.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org R4 is caller saved in SH ABI. Save it so it doesn't get corrupted until it's needed for initialization. Signed-off-by: Yoshinori Sato --- arch/sh/boot/compressed/head_32.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/sh/boot/compressed/head_32.S b/arch/sh/boot/compressed/head_32.S index 7bb168133dbb..b5ff297145b6 100644 --- a/arch/sh/boot/compressed/head_32.S +++ b/arch/sh/boot/compressed/head_32.S @@ -15,7 +15,8 @@ startup: /* Load initial status register */ mov.l init_sr, r1 ldc r1, sr - + /* Save FDT address */ + mov r4, r13 /* Move myself to proper location if necessary */ mova 1f, r0 mov.l 1f, r2 @@ -84,7 +85,7 @@ l1: /* Jump to the start of the decompressed kernel */ mov.l kernel_start_addr, r0 jmp @r0 - nop + mov r13,r4 .align 2 bss_start_addr: From patchwork Tue Nov 14 07:59:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454915 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBCD6C4332F for ; Tue, 14 Nov 2023 08:00:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232226AbjKNIAl (ORCPT ); Tue, 14 Nov 2023 03:00:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232235AbjKNIAi (ORCPT ); Tue, 14 Nov 2023 03:00:38 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 278871A7 for ; Tue, 14 Nov 2023 00:00:35 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 3AB2D1C0314; Tue, 14 Nov 2023 17:00:34 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Rich Felker , John Paul Adrian Glaubitz , Arnd Bergmann , Geert Uytterhoeven , Randy Dunlap Subject: [PATCH v4 02/37] sh: Kconfig unified OF supported targets. Date: Tue, 14 Nov 2023 16:59:53 +0900 Message-Id: <2e3530590d72257ac5cb657e4f4d4da3ec7d03e7.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Targets that support OF should be treated as one board. Signed-off-by: Yoshinori Sato --- arch/sh/boards/Kconfig | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig index 109bec4dad94..d95f078ff5c9 100644 --- a/arch/sh/boards/Kconfig +++ b/arch/sh/boards/Kconfig @@ -19,16 +19,10 @@ config SH_DEVICE_TREE select TIMER_OF select COMMON_CLK select GENERIC_CALIBRATE_DELAY - -config SH_JCORE_SOC - bool "J-Core SoC" - select SH_DEVICE_TREE - select CLKSRC_JCORE_PIT - select JCORE_AIC - depends on CPU_J2 - help - Select this option to include drivers core components of the - J-Core SoC, including interrupt controllers and timers. + select GENERIC_IOMAP + select GENERIC_IRQ_CHIP + select SYS_SUPPORTS_PCI + select GENERIC_PCI_IOMAP if PCI config SH_SOLUTION_ENGINE bool "SolutionEngine" @@ -293,6 +287,7 @@ config SH_LANDISK bool "LANDISK" depends on CPU_SUBTYPE_SH7751R select HAVE_PCI + select SYS_SUPPORTS_PCI help I-O DATA DEVICE, INC. "LANDISK Series" support. @@ -369,6 +364,16 @@ config SH_APSH4AD0A help Select AP-SH4AD-0A if configuring for an ALPHAPROJECT AP-SH4AD-0A. +config SH_OF_BOARD + bool "General Open Firmware boards" + select SH_DEVICE_TREE + select CLKSRC_JCORE_PIT if CPU_J2 + select JCORE_AIC if CPU_J2 + select HAVE_PCI if CPU_SUBTYPE_SH7751R + help + This board means general OF supported targets. + + source "arch/sh/boards/mach-r2d/Kconfig" source "arch/sh/boards/mach-highlander/Kconfig" source "arch/sh/boards/mach-sdk7780/Kconfig" From patchwork Tue Nov 14 07:59:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454917 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 865A3C074FE for ; Tue, 14 Nov 2023 08:00:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232235AbjKNIAm (ORCPT ); Tue, 14 Nov 2023 03:00:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232288AbjKNIAk (ORCPT ); Tue, 14 Nov 2023 03:00:40 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 19BFB1B3 for ; Tue, 14 Nov 2023 00:00:36 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 320311C03C0; Tue, 14 Nov 2023 17:00:36 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Rich Felker , John Paul Adrian Glaubitz , Arnd Bergmann Subject: [PATCH v4 03/37] sh: Enable OF support for build and configuration. Date: Tue, 14 Nov 2023 16:59:54 +0900 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org IRQ, CLK and PCI will be migrated to a common driver framework. So if OF, disable the SH specific drivers. Signed-off-by: Yoshinori Sato --- arch/sh/Kconfig | 11 ++++++----- arch/sh/drivers/Makefile | 2 ++ arch/sh/kernel/cpu/Makefile | 9 +++++++-- arch/sh/kernel/cpu/sh4/Makefile | 3 +++ 4 files changed, 18 insertions(+), 7 deletions(-) diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 7500521b2b98..63961d273af7 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -65,10 +65,10 @@ config SUPERH select MODULES_USE_ELF_RELA select NEED_SG_DMA_LENGTH select NO_DMA if !MMU && !DMA_COHERENT - select NO_GENERIC_PCI_IOPORT_MAP if PCI + select NO_GENERIC_PCI_IOPORT_MAP if !SH_DEVICE_TREE select OLD_SIGACTION select OLD_SIGSUSPEND - select PCI_DOMAINS if PCI + select PCI_DOMAINS if PCI && !SH_DEVICE_TREE select PERF_EVENTS select PERF_USE_VMALLOC select RTC_LIB @@ -152,7 +152,7 @@ menu "System type" # config CPU_SH2 bool - select SH_INTC + select SH_INTC if !SH_DEVICE_TREE config CPU_SH2A bool @@ -178,7 +178,7 @@ config CPU_SH4 select CPU_HAS_INTEVT select CPU_HAS_SR_RB select CPU_HAS_FPU if !CPU_SH4AL_DSP - select SH_INTC + select SH_INTC if !SH_DEVICE_TREE select SYS_SUPPORTS_SH_TMU config CPU_SH4A @@ -521,6 +521,7 @@ config SH_PCLK_FREQ config SH_CLK_CPG def_bool y + depends on !COMMON_CLK config SH_CLK_CPG_LEGACY depends on SH_CLK_CPG @@ -665,7 +666,7 @@ config BUILTIN_DTB_SOURCE kernel. config ZERO_PAGE_OFFSET - hex + hex "Zero page offset" default "0x00010000" if PAGE_SIZE_64KB || SH_RTS7751R2D || \ SH_7751_SOLUTION_ENGINE default "0x00004000" if PAGE_SIZE_16KB || SH_SH03 diff --git a/arch/sh/drivers/Makefile b/arch/sh/drivers/Makefile index 8bd10b904bf9..83f609ca1eb4 100644 --- a/arch/sh/drivers/Makefile +++ b/arch/sh/drivers/Makefile @@ -5,6 +5,8 @@ obj-y += dma/ platform_early.o +ifndef CONFIG_SH_DEVICE_TREE obj-$(CONFIG_PCI) += pci/ +endif obj-$(CONFIG_PUSH_SWITCH) += push-switch.o obj-$(CONFIG_HEARTBEAT) += heartbeat.o diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile index 46118236bf04..e00ebf134985 100644 --- a/arch/sh/kernel/cpu/Makefile +++ b/arch/sh/kernel/cpu/Makefile @@ -16,6 +16,11 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/ # Common interfaces. obj-$(CONFIG_SH_ADC) += adc.o +ifndef CONFIG_COMMON_CLK +obj-y += clock.o obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o - -obj-y += irq/ init.o clock.o fpu.o pfc.o proc.o +endif +ifndef CONFIG_GENERIC_IRQ_CHIP +obj-y += irq/ +endif +obj-y += init.o fpu.o pfc.o proc.o diff --git a/arch/sh/kernel/cpu/sh4/Makefile b/arch/sh/kernel/cpu/sh4/Makefile index 02e3ee16e15c..33da4c86feff 100644 --- a/arch/sh/kernel/cpu/sh4/Makefile +++ b/arch/sh/kernel/cpu/sh4/Makefile @@ -15,6 +15,7 @@ perf-$(CONFIG_CPU_SUBTYPE_SH7750) := perf_event.o perf-$(CONFIG_CPU_SUBTYPE_SH7750S) := perf_event.o perf-$(CONFIG_CPU_SUBTYPE_SH7091) := perf_event.o +ifndef CONFIG_SH_DEVICE_TREE # CPU subtype setup obj-$(CONFIG_CPU_SUBTYPE_SH7750) += setup-sh7750.o obj-$(CONFIG_CPU_SUBTYPE_SH7750R) += setup-sh7750.o @@ -29,5 +30,7 @@ ifndef CONFIG_CPU_SH4A clock-$(CONFIG_CPU_SH4) := clock-sh4.o endif +endif # CONFIG_SH_DEVICE_TREE + obj-y += $(clock-y) obj-$(CONFIG_PERF_EVENTS) += $(perf-y) From patchwork Tue Nov 14 07:59:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454916 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 230F2C4167B for ; Tue, 14 Nov 2023 08:00:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232241AbjKNIAn (ORCPT ); Tue, 14 Nov 2023 03:00:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232242AbjKNIAm (ORCPT ); Tue, 14 Nov 2023 03:00:42 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 95D6B19B for ; Tue, 14 Nov 2023 00:00:38 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id DACAA1C00A4; Tue, 14 Nov 2023 17:00:37 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v4 04/37] dt-bindings: interrupt-controller: Add header for Renesas SH3/4 INTC. Date: Tue, 14 Nov 2023 16:59:55 +0900 Message-Id: <5d796f8d8e27a1c68f4103f9a0d92c84fb0bdda8.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Renesas SH7751 Interrupt controller priority register define. Signed-off-by: Yoshinori Sato --- .../dt-bindings/interrupt-controller/sh_intc.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 include/dt-bindings/interrupt-controller/sh_intc.h diff --git a/include/dt-bindings/interrupt-controller/sh_intc.h b/include/dt-bindings/interrupt-controller/sh_intc.h new file mode 100644 index 000000000000..b399cd15e1a8 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/sh_intc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * SH3/4 INTC EVT - IRQ conversion + */ + +#define evt2irq(evt) ((evt) >> 5) + +#define IPRA 0 +#define IPRB 4 +#define IPRC 8 +#define IPRD 12 +#define INTPRI00 256 +#define IPR_B12 12 +#define IPR_B8 8 +#define IPR_B4 4 +#define IPR_B0 0 From patchwork Tue Nov 14 07:59:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454918 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78E1DC4332F for ; Tue, 14 Nov 2023 08:00:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232288AbjKNIAq (ORCPT ); Tue, 14 Nov 2023 03:00:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232242AbjKNIAp (ORCPT ); Tue, 14 Nov 2023 03:00:45 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D1150195 for ; Tue, 14 Nov 2023 00:00:41 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id C58F41C03C1; Tue, 14 Nov 2023 17:00:40 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Rich Felker , John Paul Adrian Glaubitz , Andrew Morton , Arnd Bergmann , Stephen Rothwell , Michael Karcher , Randy Dunlap , Sergey Shtylyov , Geert Uytterhoeven Subject: [PATCH v4 05/37] sh: GENERIC_IRQ_CHIP support for CONFIG_OF=y Date: Tue, 14 Nov 2023 16:59:56 +0900 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Remove unused function prototype. Add helper update_sr_imask. use for SH7751 irq driver. Add stub intc_finalize. Signed-off-by: Yoshinori Sato --- arch/sh/include/asm/irq.h | 10 ++++++++-- arch/sh/kernel/cpu/Makefile | 5 +---- arch/sh/kernel/cpu/irq/imask.c | 17 +++++++++++++++++ include/linux/sh_intc.h | 7 ++++++- 4 files changed, 32 insertions(+), 7 deletions(-) diff --git a/arch/sh/include/asm/irq.h b/arch/sh/include/asm/irq.h index 0f384b1f45ca..c3e3db793dba 100644 --- a/arch/sh/include/asm/irq.h +++ b/arch/sh/include/asm/irq.h @@ -16,8 +16,8 @@ /* * Simple Mask Register Support */ -extern void make_maskreg_irq(unsigned int irq); -extern unsigned short *irq_mask_register; + +void update_sr_imask(unsigned int irq, unsigned int enable); /* * PINT IRQs @@ -54,4 +54,10 @@ extern void irq_finish(unsigned int irq); #include +/* SH3/4 INTC stuff */ +/* IRL level 0 - 15 */ +#define NR_IRL 15 +/* IRL0 -> IRQ16 */ +#define IRL_BASE_IRQ 16 + #endif /* __ASM_SH_IRQ_H */ diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile index e00ebf134985..ad12807fae9c 100644 --- a/arch/sh/kernel/cpu/Makefile +++ b/arch/sh/kernel/cpu/Makefile @@ -20,7 +20,4 @@ ifndef CONFIG_COMMON_CLK obj-y += clock.o obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o endif -ifndef CONFIG_GENERIC_IRQ_CHIP -obj-y += irq/ -endif -obj-y += init.o fpu.o pfc.o proc.o +obj-y += init.o fpu.o pfc.o proc.o irq/ diff --git a/arch/sh/kernel/cpu/irq/imask.c b/arch/sh/kernel/cpu/irq/imask.c index 572585c3f2fd..d9a703715228 100644 --- a/arch/sh/kernel/cpu/irq/imask.c +++ b/arch/sh/kernel/cpu/irq/imask.c @@ -51,6 +51,7 @@ static inline void set_interrupt_registers(int ip) : "t"); } +#ifndef CONFIG_GENERIC_IRQ_CHIP static void mask_imask_irq(struct irq_data *data) { unsigned int irq = data->irq; @@ -83,3 +84,19 @@ void make_imask_irq(unsigned int irq) irq_set_chip_and_handler_name(irq, &imask_irq_chip, handle_level_irq, "level"); } +#else +void update_sr_imask(unsigned int irq, unsigned int enable) +{ + if (enable) { + set_bit(irq, imask_mask); + interrupt_priority = IMASK_PRIORITY - + find_first_bit(imask_mask, IMASK_PRIORITY); + } else { + clear_bit(irq, imask_mask); + if (interrupt_priority < IMASK_PRIORITY - irq) + interrupt_priority = IMASK_PRIORITY - irq; + } + set_interrupt_registers(interrupt_priority); +} +EXPORT_SYMBOL(update_sr_imask); +#endif diff --git a/include/linux/sh_intc.h b/include/linux/sh_intc.h index 27ae79191bdc..994b5b05a0d7 100644 --- a/include/linux/sh_intc.h +++ b/include/linux/sh_intc.h @@ -139,8 +139,13 @@ struct intc_desc symbol __initdata = { \ int register_intc_controller(struct intc_desc *desc); int intc_set_priority(unsigned int irq, unsigned int prio); int intc_irq_lookup(const char *chipname, intc_enum enum_id); +#ifndef CONFIG_SH_DEVICE_TREE void intc_finalize(void); - +#else +static inline void intc_finalize(void) +{ +} +#endif #ifdef CONFIG_INTC_USERIMASK int register_intc_userimask(unsigned long addr); #else From patchwork Tue Nov 14 07:59:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454919 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68042C4167D for ; Tue, 14 Nov 2023 08:00:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232242AbjKNIAr (ORCPT ); Tue, 14 Nov 2023 03:00:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232278AbjKNIAp (ORCPT ); Tue, 14 Nov 2023 03:00:45 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D11AB19E for ; Tue, 14 Nov 2023 00:00:42 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id C0C671C03F8; Tue, 14 Nov 2023 17:00:41 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Rich Felker , John Paul Adrian Glaubitz , Arnd Bergmann , Javier Martinez Canillas , Helge Deller , Azeem Shaikh , Thomas Gleixner , Randy Dunlap Subject: [PATCH v4 06/37] sh: kernel/setup Update DT support. Date: Tue, 14 Nov 2023 16:59:57 +0900 Message-Id: <65013d2dc41a9ce13bcd159d7cc5d267c6e90a67.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Fix extrnal fdt initialize and bootargs. Signed-off-by: Yoshinori Sato --- arch/sh/kernel/setup.c | 36 +++++++++++++++++++++++++----------- 1 file changed, 25 insertions(+), 11 deletions(-) diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index 3d80515298d2..62b049ce586f 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -74,7 +75,13 @@ extern int root_mountflags; #define RAMDISK_PROMPT_FLAG 0x8000 #define RAMDISK_LOAD_FLAG 0x4000 +#if defined(CONFIG_OF) && !defined(CONFIG_USE_BUILTIN_DTB) +#define CHOSEN_BOOTARGS +#endif + +#ifndef CHOSEN_BOOTARGS static char __initdata command_line[COMMAND_LINE_SIZE] = { 0, }; +#endif static struct resource code_resource = { .name = "Kernel code", @@ -99,6 +106,8 @@ unsigned long memory_limit = 0; static struct resource mem_resources[MAX_NUMNODES]; +static void *dt_virt; + int l1i_cache_shape, l1d_cache_shape, l2_cache_shape; static int __init early_parse_mem(char *p) @@ -244,7 +253,6 @@ void __init __weak plat_early_device_setup(void) void __ref sh_fdt_init(phys_addr_t dt_phys) { static int done = 0; - void *dt_virt; /* Avoid calling an __init function on secondary cpus. */ if (done) return; @@ -269,8 +277,17 @@ void __ref sh_fdt_init(phys_addr_t dt_phys) void __init setup_arch(char **cmdline_p) { +#ifdef CONFIG_OF +#ifdef CONFIG_USE_BUILTIN_DTB + unflatten_and_copy_device_tree(); +#else + memblock_reserve(__pa(dt_virt), fdt_totalsize(dt_virt)); + unflatten_device_tree(); +#endif +#endif enable_mmu(); +#ifndef CONFIG_OF ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV); printk(KERN_NOTICE "Boot params:\n" @@ -299,6 +316,9 @@ void __init setup_arch(char **cmdline_p) bss_resource.start = virt_to_phys(__bss_start); bss_resource.end = virt_to_phys(__bss_stop)-1; +#endif + +#ifndef CHOSEN_BOOTARGS #ifdef CONFIG_CMDLINE_OVERWRITE strscpy(command_line, CONFIG_CMDLINE, sizeof(command_line)); #else @@ -307,11 +327,13 @@ void __init setup_arch(char **cmdline_p) strlcat(command_line, " ", sizeof(command_line)); strlcat(command_line, CONFIG_CMDLINE, sizeof(command_line)); #endif -#endif - +#endif /* CONFIG_CMDLINE_OVERWRITE */ /* Save unparsed command line copy for /proc/cmdline */ memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); *cmdline_p = command_line; +#else + *cmdline_p = boot_command_line; +#endif parse_early_param(); @@ -322,14 +344,6 @@ void __init setup_arch(char **cmdline_p) /* Let earlyprintk output early console messages */ sh_early_platform_driver_probe("earlyprintk", 1, 1); -#ifdef CONFIG_OF_EARLY_FLATTREE -#ifdef CONFIG_USE_BUILTIN_DTB - unflatten_and_copy_device_tree(); -#else - unflatten_device_tree(); -#endif -#endif - paging_init(); /* Perform the machine specific initialisation */ From patchwork Tue Nov 14 07:59:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454920 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56F8BC4167B for ; Tue, 14 Nov 2023 08:00:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232282AbjKNIAs (ORCPT ); Tue, 14 Nov 2023 03:00:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232281AbjKNIAr (ORCPT ); Tue, 14 Nov 2023 03:00:47 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 6B8E819E for ; Tue, 14 Nov 2023 00:00:43 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 40E3F1C02FE; Tue, 14 Nov 2023 17:00:43 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Rich Felker , John Paul Adrian Glaubitz Subject: [PATCH v4 07/37] sh: Fix COMMON_CLK support in CONFIG_OF=y. Date: Tue, 14 Nov 2023 16:59:58 +0900 Message-Id: <3ca76277d7409f458fb64ea25d6c7ad3cfc38ce5.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Initialize the clock and timer using the COMMON_CLK procedure. sh's earlytimer mechanism doesn't work properly in OF, so timer initialization is delayed. If CONFIG_OF=y, perform the general timer initialization procedure. Signed-off-by: Yoshinori Sato --- arch/sh/boards/of-generic.c | 28 ++++------------------------ arch/sh/kernel/time.c | 12 ++++++++++++ 2 files changed, 16 insertions(+), 24 deletions(-) diff --git a/arch/sh/boards/of-generic.c b/arch/sh/boards/of-generic.c index f7f3e618e85b..f1ca5a914c11 100644 --- a/arch/sh/boards/of-generic.c +++ b/arch/sh/boards/of-generic.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -98,16 +99,7 @@ static void sh_of_smp_probe(void) #endif -static void noop(void) -{ -} - -static int noopi(void) -{ - return 0; -} - -static void __init sh_of_mem_reserve(void) +static void __init sh_of_mem_init(void) { early_init_fdt_reserve_self(); early_init_fdt_scan_reserved_mem(); @@ -140,25 +132,13 @@ static void __init sh_of_init_irq(void) irqchip_init(); } -static int __init sh_of_clk_init(void) -{ -#ifdef CONFIG_COMMON_CLK - /* Disabled pending move to COMMON_CLK framework. */ - pr_info("SH generic board support: scanning for clk providers\n"); - of_clk_init(NULL); -#endif - return 0; -} - static struct sh_machine_vector __initmv sh_of_generic_mv = { .mv_setup = sh_of_setup, .mv_name = "devicetree", /* replaced by DT root's model */ .mv_irq_demux = sh_of_irq_demux, .mv_init_irq = sh_of_init_irq, - .mv_clk_init = sh_of_clk_init, - .mv_mode_pins = noopi, - .mv_mem_init = noop, - .mv_mem_reserve = sh_of_mem_reserve, + .mv_mode_pins = generic_mode_pins, + .mv_mem_init = sh_of_mem_init, }; struct sh_clk_ops; diff --git a/arch/sh/kernel/time.c b/arch/sh/kernel/time.c index 821a09cbd605..ce5b7c2f8628 100644 --- a/arch/sh/kernel/time.c +++ b/arch/sh/kernel/time.c @@ -19,7 +19,9 @@ #include #include #include +#include +#ifndef CONFIG_SH_DEVICE_TREE static void __init sh_late_time_init(void) { /* @@ -43,3 +45,13 @@ void __init time_init(void) late_time_init = sh_late_time_init; } +#else +/* CONFIG_SH_DEVICE_TREE */ +void __init time_init(void) +{ + pr_info("SH generic board support: scanning for clk providers\n"); + + of_clk_init(NULL); + timer_probe(); +} +#endif From patchwork Tue Nov 14 07:59:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454922 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CBFCC072A2 for ; Tue, 14 Nov 2023 08:00:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232281AbjKNIAt (ORCPT ); Tue, 14 Nov 2023 03:00:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47020 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232278AbjKNIAs (ORCPT ); Tue, 14 Nov 2023 03:00:48 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 6BA121A7 for ; Tue, 14 Nov 2023 00:00:44 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 993AF1C0463; Tue, 14 Nov 2023 17:00:43 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Daniel Lezcano , Thomas Gleixner , Geert Uytterhoeven , Magnus Damm Subject: [PATCH v4 08/37] clocksource: sh_tmu: CLOCKSOURCE support. Date: Tue, 14 Nov 2023 16:59:59 +0900 Message-Id: <487844e4432fd9183d5879b66dc7acc95feefcf0.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Allows initialization as CLOCKSOURCE. Signed-off-by: Yoshinori Sato --- drivers/clocksource/sh_tmu.c | 161 +++++++++++++++++++++++------------ 1 file changed, 106 insertions(+), 55 deletions(-) diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c index beffff81c00f..e4ae83c9f7d4 100644 --- a/drivers/clocksource/sh_tmu.c +++ b/drivers/clocksource/sh_tmu.c @@ -17,6 +17,8 @@ #include #include #include +#include +#include #include #include #include @@ -65,6 +67,7 @@ struct sh_tmu_device { bool has_clockevent; bool has_clocksource; + const char *name; }; #define TSTR -1 /* shared register */ @@ -148,8 +151,8 @@ static int __sh_tmu_enable(struct sh_tmu_channel *ch) /* enable clock */ ret = clk_enable(ch->tmu->clk); if (ret) { - dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n", - ch->index); + pr_err("%s ch%u: cannot enable clock\n", + ch->tmu->name, ch->index); return ret; } @@ -174,9 +177,10 @@ static int sh_tmu_enable(struct sh_tmu_channel *ch) if (ch->enable_count++ > 0) return 0; - pm_runtime_get_sync(&ch->tmu->pdev->dev); - dev_pm_syscore_device(&ch->tmu->pdev->dev, true); - + if (ch->tmu->pdev) { + pm_runtime_get_sync(&ch->tmu->pdev->dev); + dev_pm_syscore_device(&ch->tmu->pdev->dev, true); + } return __sh_tmu_enable(ch); } @@ -202,8 +206,10 @@ static void sh_tmu_disable(struct sh_tmu_channel *ch) __sh_tmu_disable(ch); - dev_pm_syscore_device(&ch->tmu->pdev->dev, false); - pm_runtime_put(&ch->tmu->pdev->dev); + if (ch->tmu->pdev) { + dev_pm_syscore_device(&ch->tmu->pdev->dev, false); + pm_runtime_put(&ch->tmu->pdev->dev); + } } static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta, @@ -245,7 +251,7 @@ static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs) +static inline struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs) { return container_of(cs, struct sh_tmu_channel, cs); } @@ -292,7 +298,8 @@ static void sh_tmu_clocksource_suspend(struct clocksource *cs) if (--ch->enable_count == 0) { __sh_tmu_disable(ch); - dev_pm_genpd_suspend(&ch->tmu->pdev->dev); + if (ch->tmu->pdev) + dev_pm_genpd_suspend(&ch->tmu->pdev->dev); } } @@ -304,7 +311,8 @@ static void sh_tmu_clocksource_resume(struct clocksource *cs) return; if (ch->enable_count++ == 0) { - dev_pm_genpd_resume(&ch->tmu->pdev->dev); + if (ch->tmu->pdev) + dev_pm_genpd_resume(&ch->tmu->pdev->dev); __sh_tmu_enable(ch); } } @@ -324,14 +332,14 @@ static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch, cs->mask = CLOCKSOURCE_MASK(32); cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; - dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n", - ch->index); + pr_info("%s ch%u: used as clock source\n", + ch->tmu->name, ch->index); clocksource_register_hz(cs, ch->tmu->rate); return 0; } -static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced) +static inline struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced) { return container_of(ced, struct sh_tmu_channel, ced); } @@ -364,8 +372,8 @@ static int sh_tmu_clock_event_set_state(struct clock_event_device *ced, if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) sh_tmu_disable(ch); - dev_info(&ch->tmu->pdev->dev, "ch%u: used for %s clock events\n", - ch->index, periodic ? "periodic" : "oneshot"); + pr_info("%s ch%u: used for %s clock events\n", + ch->tmu->name, ch->index, periodic ? "periodic" : "oneshot"); sh_tmu_clock_event_start(ch, periodic); return 0; } @@ -403,7 +411,8 @@ static void sh_tmu_clock_event_resume(struct clock_event_device *ced) } static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch, - const char *name) + const char *name, + struct device_node *np) { struct clock_event_device *ced = &ch->ced; int ret; @@ -417,30 +426,32 @@ static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch, ced->set_state_shutdown = sh_tmu_clock_event_shutdown; ced->set_state_periodic = sh_tmu_clock_event_set_periodic; ced->set_state_oneshot = sh_tmu_clock_event_set_oneshot; - ced->suspend = sh_tmu_clock_event_suspend; - ced->resume = sh_tmu_clock_event_resume; - - dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n", - ch->index); + if (ch->tmu->pdev) { + ced->suspend = sh_tmu_clock_event_suspend; + ced->resume = sh_tmu_clock_event_resume; + } + pr_info("%s ch%u: used for clock events\n", + ch->tmu->name, ch->index); clockevents_config_and_register(ced, ch->tmu->rate, 0x300, 0xffffffff); ret = request_irq(ch->irq, sh_tmu_interrupt, IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, - dev_name(&ch->tmu->pdev->dev), ch); + ch->tmu->name, ch); if (ret) { - dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n", - ch->index, ch->irq); + pr_err("%s ch%u: failed to request irq %d\n", + ch->tmu->name, ch->index, ch->irq); return; } } static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name, + struct device_node *np, bool clockevent, bool clocksource) { if (clockevent) { ch->tmu->has_clockevent = true; - sh_tmu_register_clockevent(ch, name); + sh_tmu_register_clockevent(ch, name, np); } else if (clocksource) { ch->tmu->has_clocksource = true; sh_tmu_register_clocksource(ch, name); @@ -451,7 +462,8 @@ static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name, static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index, bool clockevent, bool clocksource, - struct sh_tmu_device *tmu) + struct sh_tmu_device *tmu, + struct device_node *np) { /* Skip unused channels. */ if (!clockevent && !clocksource) @@ -465,53 +477,59 @@ static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index, else ch->base = tmu->mapbase + 8 + ch->index * 12; - ch->irq = platform_get_irq(tmu->pdev, index); + if (tmu->pdev) + ch->irq = platform_get_irq(tmu->pdev, index); + else + ch->irq = of_irq_get(np, index); if (ch->irq < 0) return ch->irq; ch->cs_enabled = false; ch->enable_count = 0; - return sh_tmu_register(ch, dev_name(&tmu->pdev->dev), + return sh_tmu_register(ch, tmu->name, np, clockevent, clocksource); } -static int sh_tmu_map_memory(struct sh_tmu_device *tmu) +static int sh_tmu_map_memory(struct sh_tmu_device *tmu, struct device_node *np) { struct resource *res; - res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&tmu->pdev->dev, "failed to get I/O memory\n"); - return -ENXIO; - } + if (tmu->pdev) { + res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0); + if (!res) { + pr_err("sh_tmu failed to get I/O memory\n"); + return -ENXIO; + } + + tmu->mapbase = ioremap(res->start, resource_size(res)); + } else + tmu->mapbase = of_iomap(np, 0); - tmu->mapbase = ioremap(res->start, resource_size(res)); if (tmu->mapbase == NULL) return -ENXIO; return 0; } -static int sh_tmu_parse_dt(struct sh_tmu_device *tmu) +static int sh_tmu_parse_dt(struct sh_tmu_device *tmu, struct device_node *np) { - struct device_node *np = tmu->pdev->dev.of_node; - tmu->model = SH_TMU; tmu->num_channels = 3; of_property_read_u32(np, "#renesas,channels", &tmu->num_channels); if (tmu->num_channels != 2 && tmu->num_channels != 3) { - dev_err(&tmu->pdev->dev, "invalid number of channels %u\n", - tmu->num_channels); + pr_err("%s: invalid number of channels %u\n", + tmu->name, tmu->num_channels); return -EINVAL; } return 0; } -static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) +static int sh_tmu_setup(struct sh_tmu_device *tmu, + struct platform_device *pdev, struct device_node *np) { unsigned int i; int ret; @@ -520,8 +538,13 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) raw_spin_lock_init(&tmu->lock); - if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { - ret = sh_tmu_parse_dt(tmu); + if (pdev) + tmu->name = dev_name(&pdev->dev); + else + tmu->name = of_node_full_name(np); + + if (IS_ENABLED(CONFIG_OF) && np) { + ret = sh_tmu_parse_dt(tmu, np); if (ret < 0) return ret; } else if (pdev->dev.platform_data) { @@ -531,14 +554,17 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) tmu->model = id->driver_data; tmu->num_channels = hweight8(cfg->channels_mask); } else { - dev_err(&tmu->pdev->dev, "missing platform data\n"); + pr_err("%s missing platform data\n", tmu->name); return -ENXIO; } /* Get hold of clock. */ - tmu->clk = clk_get(&tmu->pdev->dev, "fck"); + if (pdev) + tmu->clk = clk_get(&tmu->pdev->dev, "fck"); + else + tmu->clk = of_clk_get(np, 0); if (IS_ERR(tmu->clk)) { - dev_err(&tmu->pdev->dev, "cannot get clock\n"); + pr_err("%s: cannot get clock\n", tmu->name); return PTR_ERR(tmu->clk); } @@ -555,9 +581,9 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) clk_disable(tmu->clk); /* Map the memory resource. */ - ret = sh_tmu_map_memory(tmu); + ret = sh_tmu_map_memory(tmu, np); if (ret < 0) { - dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n"); + pr_err("%s: failed to remap I/O memory\n", tmu->name); goto err_clk_unprepare; } @@ -575,12 +601,12 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) */ for (i = 0; i < tmu->num_channels; ++i) { ret = sh_tmu_channel_setup(&tmu->channels[i], i, - i == 0, i == 1, tmu); + i == 0, i == 1, tmu, np); if (ret < 0) goto err_unmap; } - - platform_set_drvdata(pdev, tmu); + if (pdev) + platform_set_drvdata(pdev, tmu); return 0; @@ -594,6 +620,7 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) return ret; } +#ifndef CONFIG_SH_DEVICE_TREE static int sh_tmu_probe(struct platform_device *pdev) { struct sh_tmu_device *tmu = platform_get_drvdata(pdev); @@ -613,7 +640,7 @@ static int sh_tmu_probe(struct platform_device *pdev) if (tmu == NULL) return -ENOMEM; - ret = sh_tmu_setup(tmu, pdev); + ret = sh_tmu_setup(tmu, pdev, pdev->dev.of_node); if (ret) { kfree(tmu); pm_runtime_idle(&pdev->dev); @@ -631,7 +658,26 @@ static int sh_tmu_probe(struct platform_device *pdev) return 0; } +#else +static int __init sh_tmu_of_register(struct device_node *np) +{ + struct sh_tmu_device *tmu; + int ret; + + tmu = kzalloc(sizeof(*tmu), GFP_KERNEL); + if (tmu == NULL) + return -ENOMEM; + + ret = sh_tmu_setup(tmu, NULL, np); + if (ret) { + kfree(tmu); + pr_warn("%pOF: Timer register failed (%d)", np, ret); + } + return ret; +} +#endif +#ifndef CONFIG_SH_DEVICE_TREE static const struct platform_device_id sh_tmu_id_table[] = { { "sh-tmu", SH_TMU }, { "sh-tmu-sh3", SH_TMU_SH3 }, @@ -665,12 +711,17 @@ static void __exit sh_tmu_exit(void) platform_driver_unregister(&sh_tmu_device_driver); } +subsys_initcall(sh_tmu_init); +module_exit(sh_tmu_exit); +#endif + #ifdef CONFIG_SUPERH +#ifdef CONFIG_SH_DEVICE_TREE +TIMER_OF_DECLARE(sh_tmu, "renesas,tmu", sh_tmu_of_register); +#else sh_early_platform_init("earlytimer", &sh_tmu_device_driver); #endif - -subsys_initcall(sh_tmu_init); -module_exit(sh_tmu_exit); +#endif MODULE_AUTHOR("Magnus Damm"); MODULE_DESCRIPTION("SuperH TMU Timer Driver"); From patchwork Tue Nov 14 08:00:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454921 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0EBF9C41535 for ; Tue, 14 Nov 2023 08:00:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232286AbjKNIAs (ORCPT ); Tue, 14 Nov 2023 03:00:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47014 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232282AbjKNIAr (ORCPT ); Tue, 14 Nov 2023 03:00:47 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 0600B1AC for ; Tue, 14 Nov 2023 00:00:44 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 0005B1C046A; Tue, 14 Nov 2023 17:00:43 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Laurent Pinchart Subject: [PATCH v4 09/37] dt-bindings: timer: renesas,tmu: add renesas,tmu-sh7750 Date: Tue, 14 Nov 2023 17:00:00 +0900 Message-Id: <31c717c18bd94839d46c4de726cc573ff563b3e1.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Add SH7750 TMU entry. Signed-off-by: Yoshinori Sato --- .../devicetree/bindings/timer/renesas,tmu.yaml | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml index a67e427a9e7e..925c2a691b25 100644 --- a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml +++ b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml @@ -21,6 +21,7 @@ properties: compatible: items: - enum: + - renesas,tmu-sh7750 # SH7750 - renesas,tmu-r8a7740 # R-Mobile A1 - renesas,tmu-r8a774a1 # RZ/G2M - renesas,tmu-r8a774b1 # RZ/G2N @@ -46,7 +47,14 @@ properties: interrupts: minItems: 2 - maxItems: 3 + maxItems: 4 + + interrupt-names: + items: + - const: tuni0 + - const: tuni1 + - const: tuni2 + - const: ticpi2 clocks: maxItems: 1 @@ -84,6 +92,7 @@ if: - renesas,tmu-r8a7740 - renesas,tmu-r8a7778 - renesas,tmu-r8a7779 + - renesas,tmu-sh7750 then: required: - resets From patchwork Tue Nov 14 08:00:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454923 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF95AC4332F for ; Tue, 14 Nov 2023 08:00:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232292AbjKNIA4 (ORCPT ); Tue, 14 Nov 2023 03:00:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232254AbjKNIAz (ORCPT ); Tue, 14 Nov 2023 03:00:55 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E6BCC19E for ; Tue, 14 Nov 2023 00:00:51 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 248191C0497; Tue, 14 Nov 2023 17:00:51 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Rich Felker , John Paul Adrian Glaubitz , Arnd Bergmann , Andrew Morton , Baoquan He , Guenter Roeck Subject: [PATCH v4 10/37] sh: Common PCI framework support Date: Tue, 14 Nov 2023 17:00:01 +0900 Message-Id: <65b5ddcbecfa05088b3889d0815588012dc816da.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org When CONFIG_OF=y, a common PCI framework is used. The new driver also needs to reference PCI headers, so move the necessary header files to a public location rather than a private one. Signed-off-by: Yoshinori Sato --- arch/sh/include/asm/io.h | 40 +++++++++++++------ .../sh/{drivers/pci => include/asm}/pci-sh4.h | 7 ++-- .../{drivers/pci => include/asm}/pci-sh7751.h | 0 .../{drivers/pci => include/asm}/pci-sh7780.h | 0 arch/sh/include/asm/pci.h | 4 ++ 5 files changed, 36 insertions(+), 15 deletions(-) rename arch/sh/{drivers/pci => include/asm}/pci-sh4.h (99%) rename arch/sh/{drivers/pci => include/asm}/pci-sh7751.h (100%) rename arch/sh/{drivers/pci => include/asm}/pci-sh7780.h (100%) diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h index ac521f287fa5..ef9b774dd4c8 100644 --- a/arch/sh/include/asm/io.h +++ b/arch/sh/include/asm/io.h @@ -150,6 +150,7 @@ __BUILD_MEMORY_STRING(__raw_, q, u64) */ #undef CONF_SLOWDOWN_IO +#ifndef CONFIG_GENERIC_IOMAP /* * On SuperH I/O ports are memory mapped, so we access them using normal * load/store instructions. sh_io_port_base is the virtual address to @@ -163,11 +164,7 @@ static inline void __set_io_port_base(unsigned long pbase) barrier(); } -#ifdef CONFIG_GENERIC_IOMAP -#define __ioport_map ioport_map -#else extern void __iomem *__ioport_map(unsigned long addr, unsigned int size); -#endif #ifdef CONF_SLOWDOWN_IO #define SLOW_DOWN_IO __raw_readw(sh_io_port_base) @@ -239,12 +236,6 @@ __BUILD_IOPORT_STRING(w, u16) __BUILD_IOPORT_STRING(l, u32) __BUILD_IOPORT_STRING(q, u64) -#else /* !CONFIG_HAS_IOPORT_MAP */ - -#include - -#endif - #define inb(addr) inb(addr) #define inw(addr) inw(addr) #define inl(addr) inl(addr) @@ -265,6 +256,21 @@ __BUILD_IOPORT_STRING(q, u64) #define outsb outsb #define outsw outsw #define outsl outsl +#else /* !CONFIG_GENERIC_IOMAP */ +#define __ioport_map ioport_map +#endif + +#else /* !CONFIG_HAS_IOPORT_MAP */ + +#define insb insb +#define insw insw +#define insl insl +#define outsb outsb +#define outsw outsw +#define outsl outsl +#include + +#endif #define IO_SPACE_LIMIT 0xffffffff @@ -311,10 +317,20 @@ unsigned long long poke_real_address_q(unsigned long long addr, #define xlate_dev_mem_ptr(p) __va(p) #define unxlate_dev_mem_ptr(p, v) do { } while (0) -#include - #define ARCH_HAS_VALID_PHYS_ADDR_RANGE int valid_phys_addr_range(phys_addr_t addr, size_t size); int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); + +#ifdef __KERNEL__ +#define PCI_IOBASE ((void __iomem *)0xfe240000UL) + +#define HAVE_ARCH_PIO_SIZE +#define PIO_OFFSET 0xfe240000UL +#define PIO_MASK 0x3ffffUL +#define PIO_RESERVED 0x40000UL +#endif /* __KERNEL__ */ + +#include + #endif /* __ASM_SH_IO_H */ diff --git a/arch/sh/drivers/pci/pci-sh4.h b/arch/sh/include/asm/pci-sh4.h similarity index 99% rename from arch/sh/drivers/pci/pci-sh4.h rename to arch/sh/include/asm/pci-sh4.h index 1543c50b6503..26a75841fbe2 100644 --- a/arch/sh/drivers/pci/pci-sh4.h +++ b/arch/sh/include/asm/pci-sh4.h @@ -5,9 +5,9 @@ #if defined(CONFIG_CPU_SUBTYPE_SH7780) || \ defined(CONFIG_CPU_SUBTYPE_SH7785) || \ defined(CONFIG_CPU_SUBTYPE_SH7763) -#include "pci-sh7780.h" +#include #else -#include "pci-sh7751.h" +#include #endif #include @@ -153,6 +153,7 @@ #define SH4_PCIPDTR_PB0 0x000000001 /* Port 0 Enable */ #define SH4_PCIPDR 0x220 /* Port IO Data Register */ +#ifndef CONFIG_PCI_HOST_COMMON /* arch/sh/kernel/drivers/pci/ops-sh4.c */ extern struct pci_ops sh4_pci_ops; int pci_fixup_pcic(struct pci_channel *chan); @@ -178,5 +179,5 @@ static inline unsigned long pci_read_reg(struct pci_channel *chan, { return __raw_readl(chan->reg_base + reg); } - +#endif #endif /* __PCI_SH4_H */ diff --git a/arch/sh/drivers/pci/pci-sh7751.h b/arch/sh/include/asm/pci-sh7751.h similarity index 100% rename from arch/sh/drivers/pci/pci-sh7751.h rename to arch/sh/include/asm/pci-sh7751.h diff --git a/arch/sh/drivers/pci/pci-sh7780.h b/arch/sh/include/asm/pci-sh7780.h similarity index 100% rename from arch/sh/drivers/pci/pci-sh7780.h rename to arch/sh/include/asm/pci-sh7780.h diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h index 54c30126ea17..92b3bd604319 100644 --- a/arch/sh/include/asm/pci.h +++ b/arch/sh/include/asm/pci.h @@ -2,6 +2,7 @@ #ifndef __ASM_SH_PCI_H #define __ASM_SH_PCI_H +#ifndef CONFIG_SH_DEVICE_TREE /* Can be used to override the logic in pci_scan_bus for skipping already-configured bus numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the loader */ @@ -88,4 +89,7 @@ static inline int pci_proc_domain(struct pci_bus *bus) return hose->need_domain_info; } +#else /* CONFIG_SH_DEVICE_TREE */ +#include +#endif #endif /* __ASM_SH_PCI_H */ From patchwork Tue Nov 14 08:00:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454924 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD3C4C4167D for ; Tue, 14 Nov 2023 08:00:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232254AbjKNIA5 (ORCPT ); Tue, 14 Nov 2023 03:00:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232278AbjKNIA4 (ORCPT ); Tue, 14 Nov 2023 03:00:56 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 7F28119B for ; Tue, 14 Nov 2023 00:00:53 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id B868C1C00A4; Tue, 14 Nov 2023 17:00:52 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Rich Felker , John Paul Adrian Glaubitz Subject: [PATCH v4 11/37] sh: Add old PCI drivers compatible stub. Date: Tue, 14 Nov 2023 17:00:02 +0900 Message-Id: <5f625f7535f51eb934a3a69318137884aca96304.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Place the stub so that the old driver can reference the moved header file. Signed-off-by: Yoshinori Sato --- arch/sh/drivers/pci/pci-sh4.h | 1 + 1 file changed, 1 insertion(+) create mode 100644 arch/sh/drivers/pci/pci-sh4.h diff --git a/arch/sh/drivers/pci/pci-sh4.h b/arch/sh/drivers/pci/pci-sh4.h new file mode 100644 index 000000000000..c051a1ffb082 --- /dev/null +++ b/arch/sh/drivers/pci/pci-sh4.h @@ -0,0 +1 @@ +#include From patchwork Tue Nov 14 08:00:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454926 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AAE6C4332F for ; Tue, 14 Nov 2023 08:00:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232300AbjKNIA7 (ORCPT ); Tue, 14 Nov 2023 03:00:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232296AbjKNIA6 (ORCPT ); Tue, 14 Nov 2023 03:00:58 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id BD1F7195 for ; Tue, 14 Nov 2023 00:00:54 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id B554C1C04D0; Tue, 14 Nov 2023 17:00:53 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Geert Uytterhoeven , Magnus Damm Subject: [PATCH v4 12/37] pci: pci-sh7751: Add SH7751 PCI driver Date: Tue, 14 Nov 2023 17:00:03 +0900 Message-Id: <90c0f0810c778e4f515bb9d8582b501d77e2bf1a.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Renesas SH7751 CPU Internal PCI Controller driver. Signed-off-by: Yoshinori Sato --- drivers/pci/controller/Kconfig | 9 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pci-sh7751.c | 293 ++++++++++++++++++++++++++++ 3 files changed, 303 insertions(+) create mode 100644 drivers/pci/controller/pci-sh7751.c diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index e534c02ee34f..a2fd917a2e03 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -353,6 +353,15 @@ config PCIE_XILINX_CPM Say 'Y' here if you want kernel support for the Xilinx Versal CPM host bridge. +config PCI_SH7751 + bool "Renesas SH7751 PCI controller" + depends on OF + depends on CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R || COMPILE_TEST + select PCI_HOST_COMMON + help + Say 'Y' here if you want kernel to support the Renesas SH7751 PCI + Host Bridge driver. + source "drivers/pci/controller/cadence/Kconfig" source "drivers/pci/controller/dwc/Kconfig" source "drivers/pci/controller/mobiveil/Kconfig" diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile index f2b19e6174af..aa97e5d74e58 100644 --- a/drivers/pci/controller/Makefile +++ b/drivers/pci/controller/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o +obj-$(CONFIG_PCI_SH7751) += pci-sh7751.o # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW obj-y += dwc/ diff --git a/drivers/pci/controller/pci-sh7751.c b/drivers/pci/controller/pci-sh7751.c new file mode 100644 index 000000000000..36b4f5e9c4a9 --- /dev/null +++ b/drivers/pci/controller/pci-sh7751.c @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SH7751 PCI driver + * Copyright (C) 2023 Yoshinori Sato + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define pcic_writel(val, base, reg) __raw_writel(val, base + (reg)) +#define pcic_readl(base, reg) __raw_readl(base + (reg)) + +/* BSC registers offset */ +#define BSC_BCR1 0x00000000 +#define BSC_BCR2 0x00000004 +#define BSC_WCR1 0x00000008 +#define BSC_WCR2 0x0000000c +#define BSC_WCR3 0x00000010 +#define BSC_MCR 0x00000014 + +/* + * PCIC fixups + */ + +static inline void pci_fixup_write_regs(struct device_node *np, + const char *prop, + void __iomem *pcic, int reg, + int nr_regs) +{ + int i; + u32 val; + + for (i = 0; i < nr_regs; i++) { + if (of_property_read_u32_index(np, prop, i, &val)) + pcic_writel(val, pcic, reg + i * 4); + } +} + +#define SH7751_NUM_CONFIG 18 +static void pcic_fixups(struct device_node *np, + void __iomem *pcic, void __iomem *bsc) +{ + unsigned long bcr1, mcr; + u32 val; + int i, r; + u32 pci_config[SH7751_NUM_CONFIG * 2]; + + const struct { + const char *name; + int reg; + int nr; + } reg_prop[] = { + /* + * The bus timing uses the bootloader settings, + * so do not change them here. + */ + { "renesas,intm", SH4_PCIINTM, 1, }, + { "renesas,aintm", SH4_PCIAINTM, 1, }, + { "renesas,lsr", SH4_PCILSR0, 2, }, + { "renesas,lar", SH4_PCILAR0, 2, }, + { "renesas,dmabt", SH4_PCIDMABT, 1, }, + { "renesas,pintm", SH4_PCIPINTM, 1, }, + }; + + if (of_property_read_u32(np, "sh7751-pci,bcr1", &val)) { + bcr1 = ioread32(bsc + BSC_BCR1); + bcr1 |= val; + pcic_writel(bcr1, pcic, SH4_PCIBCR1); + } + if (of_property_read_u32(np, "renesas,clkr", &val)) { + val = (0xa5 << 24) | (val & 0xffffff); + pcic_writel(val, pcic, SH4_PCICLKR); + } + for (i = 0; i < ARRAY_SIZE(reg_prop); i++) + pci_fixup_write_regs(np, reg_prop[i].name, pcic, + reg_prop[i].reg, reg_prop[i].nr); + + memset(pci_config, 0, sizeof(pci_config)); + if (of_property_read_u32_array(np, "renesas,config", + pci_config, SH7751_NUM_CONFIG) == 0) { + for (i = 0; i < SH7751_NUM_CONFIG; i++) { + r = pci_config[i * 2]; + /* CONFIG0 is read-only, so make it a sentinel. */ + if (r == 0) + break; + pcic_writel(pci_config[i * 2 + 1], pcic, + SH7751_PCICONF0 + r * 4); + } + } + + if (of_property_read_u32(np, "sh7751-pci,mcrmask", &val)) { + mcr = ioread32(bsc + BSC_MCR); + mcr &= ~val; + pcic_writel(mcr, pcic, SH4_PCIMCR); + } +} + +/* + * Direct access to PCI hardware... + */ +#define CONFIG_CMD(bus, devfn, where) \ + (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3)) + +/* + * We need to avoid collisions with `mirrored' VGA ports + * and other strange ISA hardware, so we always want the + * addresses to be allocated in the 0x000-0x0ff region + * modulo 0x400. + */ +#define IO_REGION_BASE 0x1000 +resource_size_t pcibios_align_resource(void *data, const struct resource *res, + resource_size_t size, resource_size_t align) +{ + resource_size_t start = res->start; + + if (res->flags & IORESOURCE_IO) { + if (start < PCIBIOS_MIN_IO + IO_REGION_BASE) + start = PCIBIOS_MIN_IO + IO_REGION_BASE; + + /* + * Put everything into 0x00-0xff region modulo 0x400. + */ + if (start & 0x300) + start = (start + 0x3ff) & ~0x3ff; + } + + return start; +} + +static int area_sdram_check(struct device *dev, void __iomem *pcic, + void __iomem *bsc, unsigned int area) +{ + unsigned long word; + + word = __raw_readl(bsc + BSC_BCR1); + /* check BCR for SDRAM in area */ + if (((word >> area) & 1) == 0) { + dev_info(dev, "PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n", + area, word); + return 0; + } + pcic_writel(word, pcic, SH4_PCIBCR1); + + word = __raw_readw(bsc + BSC_BCR2); + /* check BCR2 for 32bit SDRAM interface*/ + if (((word >> (area << 1)) & 0x3) != 0x3) { + dev_info(dev, "PCI: Area %d is not 32 bit SDRAM. BCR2=0x%lx\n", + area, word); + return 0; + } + pcic_writel(word, pcic, SH4_PCIBCR2); + + return 1; +} + +static void set_pci_window(void __iomem *pcic, int no, struct resource *res) +{ + u32 word; + + word = res->end - res->start - 1; + pcic_writel(word, pcic, SH4_PCILSR0 + no * 4); + word = P2SEGADDR(res->start); + pcic_writel(word, pcic, SH4_PCILAR0 + no * 4); + pcic_writel(word, pcic, SH7751_PCICONF5 + no * 4); +} + +static int sh7751_pci_probe(struct platform_device *pdev) +{ + struct resource *res, *w0res; + u32 id; + u32 reg, word; + void __iomem *pcic; + void __iomem *bsc; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pcic = (void __iomem *)res->start; + if (IS_ERR(pcic)) + return PTR_ERR(pcic); + + w0res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (IS_ERR(w0res)) + return PTR_ERR(w0res); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + bsc = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(bsc)) + return PTR_ERR(bsc); + + /* check for SH7751/SH7751R hardware */ + id = pcic_readl(pcic, SH7751_PCICONF0); + if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) && + id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) { + dev_warn(&pdev->dev, "PCI: This is not an SH7751(R)\n"); + return -ENODEV; + } + dev_info(&pdev->dev, "PCI core found at %pR\n", pcic); + + /* Set the BCR's to enable PCI access */ + reg = __raw_readl(bsc); + reg |= 0x80000; + __raw_writel(reg, bsc); + + /* Turn the clocks back on (not done in reset)*/ + pcic_writel(0, pcic, SH4_PCICLKR); + /* Clear Powerdown IRQ's (not done in reset) */ + word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0; + pcic_writel(word, pcic, SH4_PCIPINT); + + /* set the command/status bits to: + * Wait Cycle Control + Parity Enable + Bus Master + + * Mem space enable + */ + word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER | + SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES; + pcic_writel(word, pcic, SH7751_PCICONF1); + + /* define this host as the host bridge */ + word = PCI_BASE_CLASS_BRIDGE << 24; + pcic_writel(word, pcic, SH7751_PCICONF2); + + /* Set IO and Mem windows to local address + * Make PCI and local address the same for easy 1 to 1 mapping + */ + set_pci_window(pcic, 0, w0res); /* memory */ + + /* check BCR for SDRAM in specified area */ + area_sdram_check(&pdev->dev, pcic, bsc, (w0res->start >> 27) & 0x07); + + /* configure the wait control registers */ + word = __raw_readl(bsc + BSC_WCR1); + pcic_writel(word, pcic, SH4_PCIWCR1); + word = __raw_readl(bsc + BSC_WCR2); + pcic_writel(word, pcic, SH4_PCIWCR2); + word = __raw_readl(bsc + BSC_WCR3); + pcic_writel(word, pcic, SH4_PCIWCR3); + word = __raw_readl(bsc + BSC_MCR); + pcic_writel(word, pcic, SH4_PCIMCR); + + /* Override register setting */ + pcic_fixups(pdev->dev.of_node, pcic, bsc); + + /* SH7751 init done, set central function init complete */ + /* use round robin mode to stop a device starving/overrunning */ + word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM; + pcic_writel(word, pcic, SH4_PCICR); + + return pci_host_common_probe(pdev); +} + +static void __iomem *sh4_pci_map_bus(struct pci_bus *bus, + unsigned int devfn, int where) +{ + struct pci_config_window *cfg = bus->sysdata; + void __iomem *pcic = (void __iomem *)cfg->res.start; + + pcic_writel(CONFIG_CMD(bus, devfn, where), pcic, SH4_PCIPAR); + return pcic + SH4_PCIPDR; +} + +static const struct pci_ecam_ops pci_sh7751_bus_ops = { + .pci_ops = { + .map_bus = sh4_pci_map_bus, + .read = pci_generic_config_read32, + .write = pci_generic_config_write32, + } +}; + +static const struct of_device_id sh7751_pci_of_match[] = { + { .compatible = "renesas,sh7751-pci", + .data = &pci_sh7751_bus_ops }, + { } +}; +MODULE_DEVICE_TABLE(of, sh7751_pci_of_match); + +static struct platform_driver sh7751_pci_driver = { + .driver = { + .name = "sh7751-pci", + .of_match_table = sh7751_pci_of_match, + }, + .probe = sh7751_pci_probe, +}; +module_platform_driver(sh7751_pci_driver); + +MODULE_DESCRIPTION("SH7751 PCI driver"); From patchwork Tue Nov 14 08:00:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454925 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C032C4167B for ; Tue, 14 Nov 2023 08:00:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232296AbjKNIA7 (ORCPT ); Tue, 14 Nov 2023 03:00:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54716 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232298AbjKNIA6 (ORCPT ); Tue, 14 Nov 2023 03:00:58 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 7B7E819E for ; Tue, 14 Nov 2023 00:00:55 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id A1D8F1C03C0; Tue, 14 Nov 2023 17:00:54 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Subject: [PATCH v4 13/37] dt-bindings: pci: pci-sh7751: Add SH7751 PCI Date: Tue, 14 Nov 2023 17:00:04 +0900 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Renesas SH7751 PCI Controller json-schema. Signed-off-by: Yoshinori Sato --- .../bindings/pci/renesas,sh7751-pci.yaml | 123 ++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml diff --git a/Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml b/Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml new file mode 100644 index 000000000000..17bc7d2118a4 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/renesas,sh7751-pci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH7751 PCI Host controller + +maintainers: + - Yoshinori Sato + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + items: + - enum: + - renesas,sh7751-pci + + reg: + minItems: 3 + maxItems: 3 + + "#interrupt-cells": + const: 1 + + "#address-cells": + const: 3 + + "#size-cells": + const: 2 + + ranges: true + + interrupt-controller: true + + renesas,bcr1: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + SH7751 PCIC PCIBCR1 value. This value makes add the value of BSC's BCR1. + + renesas,mcrmask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + SH7751 PCIC PCIMCR value. This value makes clear bit in the value of BSC's MCR. + + renesas,intm: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + SH7751 PCIC PCIINTM value. + + renesas,aintm: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + SH7751 PCIC PCIIANTM value. + + renesas,lsr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + SH7751 PCIC PCILSR0 and PCILSR1 values. + First word is PCILSR0, Second word is PCILSR1. + + renesas,lar: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + SH7751 PCIC PCILSA0 and PCILAR1 values. + First word is PCILAR0, Second word is PCILAR1. + + renesas,dmabt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + SH7751 PCIC PCIDMABT value. + + renesas,pintm: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + SH7751 PCIC PCIPINTM value. + + renesas,config: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + SH7751 PCIC PCICONFIG values array. Register Number and value pair list. + +required: + - compatible + - reg + - "#interrupt-cells" + - "#address-cells" + - "#size-cells" + - ranges + - interrupt-map + - interrupt-map-mask + +unevaluatedProperties: false + +examples: + - | + pci@fe200000 { + compatible = "renesas,sh7751-pci"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>, + <0x01000000 0 0x00000000 0xfe240000 0 0x00040000>; + reg = <0xfe200000 0x0400>, + <0x0c000000 0x04000000>, + <0xff800000 0x0030>; + #interrupt-cells = <1>; + interrupt-map = <0x0000 0 0 1 &julianintc 5>, + <0x0000 0 0 2 &julianintc 6>, + <0x0000 0 0 3 &julianintc 7>, + <0x0000 0 0 4 &julianintc 8>, + <0x0800 0 0 1 &julianintc 6>, + <0x0800 0 0 2 &julianintc 7>, + <0x0800 0 0 3 &julianintc 8>, + <0x0800 0 0 4 &julianintc 5>, + <0x1000 0 0 1 &julianintc 7>, + <0x1000 0 0 2 &julianintc 8>, + <0x1000 0 0 3 &julianintc 5>, + <0x1000 0 0 4 &julianintc 6>; + interrupt-map-mask = <0x1800 0 0 7>; + }; From patchwork Tue Nov 14 08:00:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454928 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D9BEC072A2 for ; Tue, 14 Nov 2023 08:00:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229566AbjKNIBA (ORCPT ); Tue, 14 Nov 2023 03:01:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232302AbjKNIA7 (ORCPT ); Tue, 14 Nov 2023 03:00:59 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9E2A7195 for ; Tue, 14 Nov 2023 00:00:56 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id A80E01C04EC; Tue, 14 Nov 2023 17:00:55 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Subject: [PATCH v4 14/37] dt-bindings: clock: sh7750-cpg: Add renesas,sh7750-cpg header. Date: Tue, 14 Nov 2023 17:00:05 +0900 Message-Id: <65cf2917d762e2f2933dbf9e8d61735b2bc4fb7b.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org SH7750 CPG Clock output define. Signed-off-by: Yoshinori Sato --- .../bindings/clock/renesas,sh7750-cpg.yaml | 103 ++++++++++++++++++ include/dt-bindings/clock/sh7750-cpg.h | 26 +++++ 2 files changed, 129 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml create mode 100644 include/dt-bindings/clock/sh7750-cpg.h diff --git a/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml new file mode 100644 index 000000000000..da0b837c1123 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH7750/7751 Clock Pulse Generator (CPG) + +maintainers: + - Yoshinori Sato + +description: + The Clock Pulse Generator (CPG) generates core clocks for the SoC. It + includes PLLs, and variable ratio dividers. + + The CPG may also provide a Clock Domain for SoC devices, in combination with + the CPG Module Stop (MSTP) Clocks. + +properties: + compatible: + enum: + - renesas,sh7750-cpg # SH7750 + - renesas,sh7750s-cpg # SH775S + - renesas,sh7750r-cpg # SH7750R + - renesas,sh7751-cpg # SH7751 + - renesas,sh7751r-cpg # SH7751R + + reg: true + + reg-names: true + + clocks: true + + clock-names: true + + '#clock-cells': + const: 1 + + renesas,mode: + description: Board-specific settings of the MD[0-2] pins on SoC + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 6 + + '#power-domain-cells': + const: 0 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - '#clock-cells' + +allOf: + - if: + properties: + compatible: + contains: + enum: + - renesas,sh7750-cpg + - renesas,sh7750s-cpg + then: + properties: + reg: + maxItems: 1 + reg-names: + items: + - const: FRQCR + + - if: + properties: + compatible: + contains: + enum: + - renesas,sh7750r-cpg + - renesas,sh7751-cpg + - renesas,sh7751r-cpg + then: + properties: + reg: + maxItems: 2 + reg-names: + items: + - const: FRQCR + - const: CLKSTP00 + +additionalProperties: false + +examples: + - | + #include + cpg: clock-controller@ffc00000 { + #clock-cells = <1>; + #power-domain-cells = <0>; + compatible = "renesas,sh7751r-cpg"; + clocks = <&xtal>; + clock-names = "xtal"; + reg = <0xffc00000 20>, <0xfe0a0000 16>; + reg-names = "FRQCR", "CLKSTP00"; + renesas,mode = <0>; + }; diff --git a/include/dt-bindings/clock/sh7750-cpg.h b/include/dt-bindings/clock/sh7750-cpg.h new file mode 100644 index 000000000000..17d5a8076aac --- /dev/null +++ b/include/dt-bindings/clock/sh7750-cpg.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright 2023 Yoshinori Sato + */ + +#ifndef __DT_BINDINGS_CLOCK_SH7750_H__ +#define __DT_BINDINGS_CLOCK_SH7750_H__ + +#define SH7750_CPG_PLLOUT 0 + +#define SH7750_CPG_FCK 1 +#define SH7750_CPG_BCK 2 +#define SH7750_CPG_ICK 3 + +#define SH7750_MSTP_SCI 4 +#define SH7750_MSTP_RTC 5 +#define SH7750_MSTP_TMU012 6 +#define SH7750_MSTP_SCIF 7 +#define SH7750_MSTP_DMAC 8 +#define SH7750_MSTP_UBC 9 +#define SH7750_MSTP_SQ 10 +#define SH7750_CSTP_INTC 11 +#define SH7750_CSTP_TMU34 12 +#define SH7750_CSTP_PCIC 13 + +#endif From patchwork Tue Nov 14 08:00:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454927 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB450C4167D for ; Tue, 14 Nov 2023 08:01:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232301AbjKNIBB (ORCPT ); Tue, 14 Nov 2023 03:01:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232298AbjKNIBA (ORCPT ); Tue, 14 Nov 2023 03:01:00 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id CE59919B for ; Tue, 14 Nov 2023 00:00:56 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 5D2351C04FB; Tue, 14 Nov 2023 17:00:56 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Michael Turquette , Stephen Boyd Subject: [PATCH v4 15/37] clk: Compatible with narrow registers Date: Tue, 14 Nov 2023 17:00:06 +0900 Message-Id: <5fb31a1370d34bb8a3a1a881fbbb1d2f80483734.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org divider and gate only support 32-bit registers. Older hardware uses narrower registers, so I want to be able to handle 8-bit and 16-bit wide registers. Signed-off-by: Yoshinori Sato --- drivers/clk/clk-divider.c | 56 ++++++++++++++++++++++++------------ drivers/clk/clk-gate.c | 56 +++++++++++++++++++++++++++--------- include/linux/clk-provider.h | 22 ++++++++++---- 3 files changed, 97 insertions(+), 37 deletions(-) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index a2c2b5203b0a..a1b5187cd63d 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -26,20 +26,38 @@ * parent - fixed parent. No clk_set_parent support */ -static inline u32 clk_div_readl(struct clk_divider *divider) -{ - if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) - return ioread32be(divider->reg); - - return readl(divider->reg); +static inline u32 clk_div_read(struct clk_divider *divider) +{ + if (divider->flags & CLK_DIVIDER_REG_8BIT) + return readb(divider->reg); + else if (divider->flags & CLK_DIVIDER_REG_16BIT) { + if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) + return ioread16be(divider->reg); + else + return readw(divider->reg); + } else { + if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) + return ioread32be(divider->reg); + else + return readl(divider->reg); + } } -static inline void clk_div_writel(struct clk_divider *divider, u32 val) +static inline void clk_div_write(struct clk_divider *divider, u32 val) { - if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) - iowrite32be(val, divider->reg); - else - writel(val, divider->reg); + if (divider->flags & CLK_DIVIDER_REG_8BIT) + writeb(val, divider->reg); + else if (divider->flags & CLK_DIVIDER_REG_16BIT) { + if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) + iowrite16be(val, divider->reg); + else + writew(val, divider->reg); + } else { + if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) + iowrite32be(val, divider->reg); + else + writel(val, divider->reg); + } } static unsigned int _get_table_maxdiv(const struct clk_div_table *table, @@ -152,7 +170,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, struct clk_divider *divider = to_clk_divider(hw); unsigned int val; - val = clk_div_readl(divider) >> divider->shift; + val = clk_div_read(divider) >> divider->shift; val &= clk_div_mask(divider->width); return divider_recalc_rate(hw, parent_rate, val, divider->table, @@ -434,7 +452,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, if (divider->flags & CLK_DIVIDER_READ_ONLY) { u32 val; - val = clk_div_readl(divider) >> divider->shift; + val = clk_div_read(divider) >> divider->shift; val &= clk_div_mask(divider->width); return divider_ro_round_rate(hw, rate, prate, divider->table, @@ -455,7 +473,7 @@ static int clk_divider_determine_rate(struct clk_hw *hw, if (divider->flags & CLK_DIVIDER_READ_ONLY) { u32 val; - val = clk_div_readl(divider) >> divider->shift; + val = clk_div_read(divider) >> divider->shift; val &= clk_div_mask(divider->width); return divider_ro_determine_rate(hw, req, divider->table, @@ -505,11 +523,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { val = clk_div_mask(divider->width) << (divider->shift + 16); } else { - val = clk_div_readl(divider); + val = clk_div_read(divider); val &= ~(clk_div_mask(divider->width) << divider->shift); } val |= (u32)value << divider->shift; - clk_div_writel(divider, val); + clk_div_write(divider, val); if (divider->lock) spin_unlock_irqrestore(divider->lock, flags); @@ -538,7 +556,7 @@ struct clk_hw *__clk_hw_register_divider(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, const struct clk_parent_data *parent_data, unsigned long flags, - void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, + void __iomem *reg, u8 shift, u8 width, u32 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock) { struct clk_divider *div; @@ -610,7 +628,7 @@ EXPORT_SYMBOL_GPL(__clk_hw_register_divider); struct clk *clk_register_divider_table(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, - u8 clk_divider_flags, const struct clk_div_table *table, + u32 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock) { struct clk_hw *hw; @@ -664,7 +682,7 @@ struct clk_hw *__devm_clk_hw_register_divider(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, const struct clk_parent_data *parent_data, unsigned long flags, - void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, + void __iomem *reg, u8 shift, u8 width, u32 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock) { struct clk_hw **ptr, *hw; diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 68e585a02fd9..8a7e97e8dc73 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -24,20 +24,38 @@ * parent - fixed parent. No clk_set_parent support */ -static inline u32 clk_gate_readl(struct clk_gate *gate) +static inline u32 clk_gate_read(struct clk_gate *gate) { - if (gate->flags & CLK_GATE_BIG_ENDIAN) - return ioread32be(gate->reg); - - return readl(gate->reg); + if (gate->flags & CLK_GATE_REG_8BIT) + return readb(gate->reg); + else if (gate->flags & CLK_GATE_REG_16BIT) { + if (gate->flags & CLK_GATE_BIG_ENDIAN) + return ioread16be(gate->reg); + else + return readw(gate->reg); + } else { + if (gate->flags & CLK_GATE_BIG_ENDIAN) + return ioread32be(gate->reg); + else + return readl(gate->reg); + } } -static inline void clk_gate_writel(struct clk_gate *gate, u32 val) +static inline void clk_gate_write(struct clk_gate *gate, u32 val) { - if (gate->flags & CLK_GATE_BIG_ENDIAN) - iowrite32be(val, gate->reg); - else - writel(val, gate->reg); + if (gate->flags & CLK_GATE_REG_8BIT) + writeb(val, gate->reg); + else if (gate->flags & CLK_GATE_REG_16BIT) { + if (gate->flags & CLK_GATE_BIG_ENDIAN) + iowrite16be(val, gate->reg); + else + writew(val, gate->reg); + } else { + if (gate->flags & CLK_GATE_BIG_ENDIAN) + iowrite32be(val, gate->reg); + else + writel(val, gate->reg); + } } /* @@ -72,7 +90,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) if (set) reg |= BIT(gate->bit_idx); } else { - reg = clk_gate_readl(gate); + reg = clk_gate_read(gate); if (set) reg |= BIT(gate->bit_idx); @@ -80,7 +98,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) reg &= ~BIT(gate->bit_idx); } - clk_gate_writel(gate, reg); + clk_gate_write(gate, reg); if (gate->lock) spin_unlock_irqrestore(gate->lock, flags); @@ -105,7 +123,7 @@ int clk_gate_is_enabled(struct clk_hw *hw) u32 reg; struct clk_gate *gate = to_clk_gate(hw); - reg = clk_gate_readl(gate); + reg = clk_gate_read(gate); /* if a set bit disables this clk, flip it before masking */ if (gate->flags & CLK_GATE_SET_TO_DISABLE) @@ -143,6 +161,18 @@ struct clk_hw *__clk_hw_register_gate(struct device *dev, return ERR_PTR(-EINVAL); } } + if (clk_gate_flags & CLK_GATE_REG_16BIT) { + if (bit_idx > 15) { + pr_err("gate bit exceeds 16 bits\n"); + return ERR_PTR(-EINVAL); + } + } + if (clk_gate_flags & CLK_GATE_REG_8BIT) { + if (bit_idx > 7) { + pr_err("gate bit exceeds 8 bits\n"); + return ERR_PTR(-EINVAL); + } + } /* allocate the gate */ gate = kzalloc(sizeof(*gate), GFP_KERNEL); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index ace3a4ce2fc9..d9ae66caa3b7 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -508,12 +508,16 @@ void of_fixed_clk_setup(struct device_node *np); * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for * the gate register. Setting this flag makes the register accesses big * endian. + * CLK_GATE_REG_8BIT - by default 32bit register accesses are used for + * the gate register. Setting this flag makes the register accesses 8bit. + * CLK_GATE_REG_16BIT - by default 32bit register accesses are used for + * the gate register. Setting this flag makes the register accesses 16bit. */ struct clk_gate { struct clk_hw hw; void __iomem *reg; u8 bit_idx; - u8 flags; + u32 flags; spinlock_t *lock; }; @@ -522,6 +526,8 @@ struct clk_gate { #define CLK_GATE_SET_TO_DISABLE BIT(0) #define CLK_GATE_HIWORD_MASK BIT(1) #define CLK_GATE_BIG_ENDIAN BIT(2) +#define CLK_GATE_REG_8BIT BIT(3) +#define CLK_GATE_REG_16BIT BIT(4) extern const struct clk_ops clk_gate_ops; struct clk_hw *__clk_hw_register_gate(struct device *dev, @@ -675,13 +681,17 @@ struct clk_div_table { * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used * for the divider register. Setting this flag makes the register accesses * big endian. + * CLK_DIVIDER_REG_8BIT - by default 32bit register accesses are used for + * the gate register. Setting this flag makes the register accesses 8bit. + * CLK_DIVIDER_REG_16BIT - by default 32bit register accesses are used for + * the gate register. Setting this flag makes the register accesses 16bit. */ struct clk_divider { struct clk_hw hw; void __iomem *reg; u8 shift; u8 width; - u8 flags; + u32 flags; const struct clk_div_table *table; spinlock_t *lock; }; @@ -697,6 +707,8 @@ struct clk_divider { #define CLK_DIVIDER_READ_ONLY BIT(5) #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) #define CLK_DIVIDER_BIG_ENDIAN BIT(7) +#define CLK_DIVIDER_REG_8BIT BIT(8) +#define CLK_DIVIDER_REG_16BIT BIT(9) extern const struct clk_ops clk_divider_ops; extern const struct clk_ops clk_divider_ro_ops; @@ -726,18 +738,18 @@ struct clk_hw *__clk_hw_register_divider(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, const struct clk_parent_data *parent_data, unsigned long flags, - void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, + void __iomem *reg, u8 shift, u8 width, u32 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock); struct clk_hw *__devm_clk_hw_register_divider(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, const struct clk_parent_data *parent_data, unsigned long flags, - void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, + void __iomem *reg, u8 shift, u8 width, u32 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock); struct clk *clk_register_divider_table(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, - u8 clk_divider_flags, const struct clk_div_table *table, + u32 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock); /** * clk_register_divider - register a divider clock with the clock framework From patchwork Tue Nov 14 08:00:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454929 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DD54C4332F for ; Tue, 14 Nov 2023 08:01:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232303AbjKNIBD (ORCPT ); Tue, 14 Nov 2023 03:01:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232278AbjKNIBC (ORCPT ); Tue, 14 Nov 2023 03:01:02 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E1D341A3 for ; Tue, 14 Nov 2023 00:00:57 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 562DD1C04D2; Tue, 14 Nov 2023 17:00:57 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Magnus Damm Subject: [PATCH v4 16/37] clk: renesas: Add SH7750/7751 CPG Driver Date: Tue, 14 Nov 2023 17:00:07 +0900 Message-Id: <4fe9c57c6b5f67665451415f9940a933afc83f0e.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Renesas SH7750 and SH7751 series CPG driver. This driver supported frequency control and clock gating. Signed-off-by: Yoshinori Sato --- drivers/clk/renesas/Kconfig | 16 +- drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/clk-sh7750.c | 498 +++++++++++++++++++++++++++++++ 3 files changed, 513 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/renesas/clk-sh7750.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 69396e197959..b1350cda7ade 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -1,8 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 config CLK_RENESAS - bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS - default y if ARCH_RENESAS + bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS && !SUPERH + default y if ARCH_RENESAS || SUPERH select CLK_EMEV2 if ARCH_EMEV2 select CLK_RZA1 if ARCH_R7S72100 select CLK_R7S9210 if ARCH_R7S9210 @@ -40,6 +40,9 @@ config CLK_RENESAS select CLK_R9A08G045 if ARCH_R9A08G045 select CLK_R9A09G011 if ARCH_R9A09G011 select CLK_SH73A0 if ARCH_SH73A0 + select CLK_SH7750 if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \ + CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751 || \ + CPU_SUBTYPE_SH7751R if CLK_RENESAS @@ -193,6 +196,10 @@ config CLK_SH73A0 select CLK_RENESAS_CPG_MSTP select CLK_RENESAS_DIV6 +config CLK_SH7750 + bool "SH7750/7751 family clock support" if COMPILE_TEST + help + This is a driver for SH7750 / SH7751 CPG. # Family config CLK_RCAR_CPG_LIB @@ -223,6 +230,11 @@ config CLK_RZG2L bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST select RESET_CONTROLLER +config CLK_SH7750 + bool "Renesas SH7750/7751 family clock support" if COMPILE_TEST + help + This is a driver for SH7750 / SH7751 CPG. + # Generic config CLK_RENESAS_CPG_MSSR bool "CPG/MSSR clock support" if COMPILE_TEST diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 879a07d445f9..233e029fcd54 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o +obj-$(CONFIG_CLK_SH7750) += clk-sh7750.o # Family obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o diff --git a/drivers/clk/renesas/clk-sh7750.c b/drivers/clk/renesas/clk-sh7750.c new file mode 100644 index 000000000000..bd971e9a8869 --- /dev/null +++ b/drivers/clk/renesas/clk-sh7750.c @@ -0,0 +1,498 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas SH7750/51 CPG driver + * + * Copyright 2023 Yoshinori Sato + */ + +#include +#include +#include +#include +#include +#include +#include + +/* PCLK divide rate selector */ +static const struct clk_div_table pdiv_table[] = { + { .val = 0, .div = 2, }, + { .val = 1, .div = 3, }, + { .val = 2, .div = 4, }, + { .val = 3, .div = 6, }, + { .val = 4, .div = 8, }, + { } +}; + +/* ICLK and BCLK divide rate selector */ +static const struct clk_div_table div_table[] = { + { .val = 0, .div = 1, }, + { .val = 1, .div = 2, }, + { .val = 2, .div = 3, }, + { .val = 3, .div = 4, }, + { .val = 4, .div = 6, }, + { .val = 5, .div = 8, }, + { } +}; + +struct cpg_priv { + struct clk_hw hw; + spinlock_t clklock; + void __iomem *frqcr; + void __iomem *clkstp00; + u32 mode; + u32 feat; +}; + +/* CPG feature flag */ +#define CPG_DIV1 BIT(0) /* 7750, 7750S, 7751 */ +#define MSTP_CR2 BIT(1) /* 7750S, 7750R, 7751, 7751R */ +#define MSTP_CLKSTP BIT(2) /* 7750R, 7751, 7751R */ +#define MSTP_CSTP2 BIT(3) /* 7751, 7751R */ + +enum { + CPG_SH7750, + CPG_SH7750S, + CPG_SH7750R, + CPG_SH7751, + CPG_SH7751R, +}; + +static const u32 cpg_feature[] = { + [CPG_SH7750] = CPG_DIV1, + [CPG_SH7750S] = CPG_DIV1 | MSTP_CR2, + [CPG_SH7750R] = MSTP_CR2 | MSTP_CLKSTP, + [CPG_SH7751] = CPG_DIV1 | MSTP_CR2 | MSTP_CLKSTP | MSTP_CSTP2, + [CPG_SH7751R] = MSTP_CR2 | MSTP_CLKSTP | MSTP_CSTP2, +}; + +enum clk_type {CLK_DIV, CLK_STBCR, CLK_STBCR2, CLK_CLKSTP00}; + +enum { + FRQCR = 0, + STBCR = 4, + WTCNT = 8, + WTCSR = 12, + STBCR2 = 16, + CLKSTP00 = 0, + CLKSTPCLR00 = 8, +}; + +static struct cpg_priv *cpg_data; + +#define to_priv(_hw) container_of(_hw, struct cpg_priv, hw) + +#define FRQCR_PLL1EN BIT(10) +static const unsigned int pll1mult[] = { 12, 12, 6, 12, 6, 12, 1}; + +static unsigned long pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct cpg_priv *cpg = to_priv(hw); + unsigned long rate = parent_rate; + u16 frqcr; + + frqcr = ioread16(cpg->frqcr); + if (frqcr & FRQCR_PLL1EN) { + rate *= pll1mult[cpg->mode]; + if (cpg->mode < 6 && (cpg->feat & CPG_DIV1)) + rate /= 2; + } + return rate; +} + +static void get_round_rate(struct cpg_priv *cpg, + unsigned long *out, bool *pllen, + unsigned long rate, unsigned long prate) +{ + long pllout, res; + bool pll; + + if (cpg->mode < 6 && (cpg->feat & CPG_DIV1)) + prate /= 2; + + pllout = prate * pll1mult[cpg->mode]; + if (abs(pllout - rate) > abs(prate - rate)) { + res = prate; + pll = false; + } else { + res = pllout; + pll = true; + } + if (out) + *out = res; + if (pllen) + *pllen = pll; +} + +static int pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) +{ + struct cpg_priv *cpg = to_priv(hw); + + get_round_rate(cpg, &req->rate, NULL, req->rate, req->best_parent_rate); + return 0; +} + +static int pll_set_rate(struct clk_hw *hw, + unsigned long rate, unsigned long prate) +{ + struct cpg_priv *cpg = to_priv(hw); + bool oldpll, newpll; + u16 frqcr; + + frqcr = ioread16(cpg->frqcr); + get_round_rate(cpg, NULL, &newpll, rate, prate); + oldpll = frqcr & FRQCR_PLL1EN; + frqcr &= ~FRQCR_PLL1EN; + + if (newpll) { + frqcr |= FRQCR_PLL1EN; + if (!oldpll) { + /* set PLL wakeup delay time */ + iowrite16(0xa500, cpg->frqcr + WTCNT); + iowrite16(0xa507, cpg->frqcr + WTCNT); + iowrite16(0x5a00, cpg->frqcr + WTCSR); + } + } + iowrite16(frqcr, cpg->frqcr); + + /* Test for new PLL state */ + frqcr = ioread16(cpg->frqcr); + oldpll = frqcr & FRQCR_PLL1EN; + return !(oldpll == newpll); +} + +static const struct clk_ops pll_ops = { + .recalc_rate = pll_recalc_rate, + .determine_rate = pll_determine_rate, + .set_rate = pll_set_rate, +}; + +#define PLLOUT "pllout" + +static int register_pll(struct device_node *node, struct cpg_priv *cpg) +{ + const char *clk_name = node->name; + const char *parent_name; + struct clk_init_data init = { + .name = PLLOUT, + .ops = &pll_ops, + .flags = 0, + .num_parents = 1, + }; + int ret; + + parent_name = of_clk_get_parent_name(node, 0); + init.parent_names = &parent_name; + cpg->hw.init = &init; + + ret = of_clk_hw_register(node, &cpg->hw); + if (ret < 0) { + pr_err("%s: failed to register %s pll clock (%d)\n", + __func__, clk_name, ret); + return ret; + } + if (ret < 0) + pr_err("%s: failed to add provider %s (%d)\n", + __func__, clk_name, ret); + return ret; +} + +static void clkstp00_sw(struct clk_hw *hw, bool on) +{ + u32 val; + struct clk_gate *gate = to_clk_gate(hw); + + val = BIT(gate->bit_idx); + if (on) + writel(val, gate->reg + CLKSTPCLR00); + else + writel(val, gate->reg); +} + +static int clkstp00_enable(struct clk_hw *hw) +{ + clkstp00_sw(hw, true); + return 0; +} + +static void clkstp00_disable(struct clk_hw *hw) +{ + clkstp00_sw(hw, false); +} + +static int clkstp00_is_enabled(struct clk_hw *hw) +{ + u8 val; + struct clk_gate *gate = to_clk_gate(hw); + + val = readb(gate->reg); + val &= 1 << gate->bit_idx; + return val == 0; +} + +static const struct clk_ops gate_clkstp00_ops = { + .enable = clkstp00_enable, + .disable = clkstp00_disable, + .is_enabled = clkstp00_is_enabled, +}; + +static struct clk_hw *clk_hw_register_clkstp(struct device_node *node, + const char *name, + const char *parent, + void __iomem *reg, int bit, + spinlock_t *lock) +{ + struct clk_gate *gate; + struct clk_init_data init = { + .name = name, + .ops = &gate_clkstp00_ops, + .flags = 0, + .parent_names = &parent, + .num_parents = 1, + }; + struct clk_hw *hw; + int ret; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (gate == NULL) + goto error; + gate->reg = reg; + gate->bit_idx = bit; + gate->flags = 0; + gate->lock = lock; + gate->hw.init = &init; + hw = &gate->hw; + ret = of_clk_hw_register(node, hw); + if (ret < 0) + goto error; + return hw; +error: + kfree(gate); + return ERR_PTR(ret); +} + +static int register_div(struct device_node *node, struct cpg_priv *cpg) +{ + static const char * const divout[] = { + "fck", "bck", "ick", + }; + static const char * const stbcrout[] = { + "sci_clk", "rtc_clk", "tmu012_clk", /* STBCR */ + "scif_clk", "dmac_clk", /* STBCR */ + "ubc_clk", "sq_clk", /* STBCR2 */ + }; + static const char * const clkstpout[] = { + "intc_clk", "tmu34_clk", "pcic_clk", /* CLKSTP00 */ + }; + + unsigned int i; + int ret; + struct clk_hw_onecell_data *data; + struct clk_hw *reg_hw; + int num_clk = ARRAY_SIZE(divout) + ARRAY_SIZE(stbcrout) + ARRAY_SIZE(clkstpout); + + data = kzalloc(struct_size(data, hws, num_clk + 1), GFP_KERNEL); + if (!data) + return -ENOMEM; + + num_clk = 0; + for (i = 0; i < ARRAY_SIZE(divout); i++) { + reg_hw = __clk_hw_register_divider(NULL, node, divout[i], + PLLOUT, NULL, NULL, + 0, cpg->frqcr, i * 3, 3, + CLK_DIVIDER_REG_16BIT, + (i == 0) ? pdiv_table : div_table, + &cpg->clklock); + if (IS_ERR(reg_hw)) { + ret = PTR_ERR(reg_hw); + goto error; + } + data->hws[num_clk++] = reg_hw; + } + for (i = 0; i < ARRAY_SIZE(stbcrout); i++) { + u32 off = (i < 5) ? STBCR : STBCR2; + + if (i >= 5 && !(cpg->feat & MSTP_CR2)) + break; + reg_hw = __clk_hw_register_gate(NULL, node, stbcrout[i], + divout[0], NULL, NULL, + 0, cpg->frqcr + off, i % 5, + CLK_GATE_REG_8BIT | CLK_GATE_SET_TO_DISABLE, + &cpg->clklock); + if (IS_ERR(reg_hw)) { + ret = PTR_ERR(reg_hw); + goto error; + } + data->hws[num_clk++] = reg_hw; + } + if (cpg->feat & MSTP_CLKSTP) { + for (i = 0; i < ARRAY_SIZE(clkstpout); i++) { + if (i == 2 && !(cpg->feat & MSTP_CSTP2)) + continue; + reg_hw = clk_hw_register_clkstp(node, clkstpout[i], + divout[0], cpg->clkstp00, + i, &cpg->clklock); + if (IS_ERR(reg_hw)) { + ret = PTR_ERR(reg_hw); + goto error; + } + data->hws[num_clk++] = reg_hw; + } + } + data->num = num_clk; + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data); + if (ret < 0) + goto error; + return 0; + +error: + pr_err("%pOF: failed to register clock (%d)\n", + node, ret); + for (num_clk--; num_clk >= 0; num_clk--) + kfree(data->hws[num_clk]); + kfree(data); + return ret; +} + +static struct cpg_priv *sh7750_cpg_setup(struct device_node *node, u32 feat) +{ + unsigned int num_parents; + u32 mode; + struct cpg_priv *cpg; + int ret = 0; + + num_parents = of_clk_get_parent_count(node); + if (num_parents < 1) { + pr_err("%s: no parent found", node->name); + return ERR_PTR(-ENODEV); + } + + of_property_read_u32_index(node, "renesas,mode", 0, &mode); + if (mode >= 7) { + pr_err("%s: Invalid clock mode setting (%u)\n", + node->name, mode); + return ERR_PTR(-EINVAL); + } + + cpg = kzalloc(sizeof(struct cpg_priv), GFP_KERNEL); + if (!cpg) + return ERR_PTR(-ENOMEM); + + cpg->frqcr = of_iomap(node, 0); + if (cpg->frqcr == NULL) { + pr_err("%pOF: failed to map divide register", node); + ret = -ENODEV; + goto cpg_free; + } + + if (feat & MSTP_CLKSTP) { + cpg->clkstp00 = of_iomap(node, 1); + if (cpg->clkstp00 == NULL) { + pr_err("%pOF: failed to map clkstp00 register", node); + ret = -ENODEV; + goto unmap_frqcr; + } + } + cpg->feat = feat; + cpg->mode = mode; + + ret = register_pll(node, cpg); + if (ret < 0) + goto unmap_clkstp00; + + ret = register_div(node, cpg); + if (ret < 0) + goto unmap_clkstp00; + + return cpg; + +unmap_clkstp00: + iounmap(cpg->clkstp00); +unmap_frqcr: + iounmap(cpg->frqcr); +cpg_free: + kfree(cpg); + return ERR_PTR(ret); +} + +static void __init sh7750_cpg_init(struct device_node *node) +{ + cpg_data = sh7750_cpg_setup(node, cpg_feature[CPG_SH7750]); + if (IS_ERR(cpg_data)) + cpg_data = NULL; +} + +static void __init sh7750s_cpg_init(struct device_node *node) +{ + cpg_data = sh7750_cpg_setup(node, cpg_feature[CPG_SH7750S]); + if (IS_ERR(cpg_data)) + cpg_data = NULL; +} + +static void __init sh7750r_cpg_init(struct device_node *node) +{ + cpg_data = sh7750_cpg_setup(node, cpg_feature[CPG_SH7750R]); + if (IS_ERR(cpg_data)) + cpg_data = NULL; +} + +static void __init sh7751_cpg_init(struct device_node *node) +{ + cpg_data = sh7750_cpg_setup(node, cpg_feature[CPG_SH7751]); + if (IS_ERR(cpg_data)) + cpg_data = NULL; +} + +static void __init sh7751r_cpg_init(struct device_node *node) +{ + cpg_data = sh7750_cpg_setup(node, cpg_feature[CPG_SH7751R]); + if (IS_ERR(cpg_data)) + cpg_data = NULL; +} + +CLK_OF_DECLARE_DRIVER(sh7750_cpg, "renesas,sh7750-cpg", + sh7750_cpg_init); +CLK_OF_DECLARE_DRIVER(sh7750s_cpg, "renesas,sh7750s-cpg", + sh7750s_cpg_init); +CLK_OF_DECLARE_DRIVER(sh7750r_cpg, "renesas,sh7750r-cpg", + sh7750r_cpg_init); +CLK_OF_DECLARE_DRIVER(sh7751_cpg, "renesas,sh7751-cpg", + sh7751_cpg_init); +CLK_OF_DECLARE_DRIVER(sh7751r_cpg, "renesas,sh7751r-cpg", + sh7751r_cpg_init); + +static int sh7750_cpg_probe(struct platform_device *pdev) +{ + u32 feature; + + if (cpg_data) + return 0; + feature = *(u32 *)of_device_get_match_data(&pdev->dev); + cpg_data = sh7750_cpg_setup(pdev->dev.of_node, feature); + if (IS_ERR(cpg_data)) + return PTR_ERR(cpg_data); + return 0; +} + +static const struct of_device_id sh7750_cpg_of_match[] = { + { .compatible = "renesas,sh7750-cpg", + .data = &cpg_feature[CPG_SH7750] }, + { .compatible = "renesas,sh7750s-cpg", + .data = &cpg_feature[CPG_SH7750S] }, + { .compatible = "renesas,sh7750r-cpg", + .data = &cpg_feature[CPG_SH7750R] }, + { .compatible = "renesas,sh7751-cpg", + .data = &cpg_feature[CPG_SH7751] }, + { .compatible = "renesas,sh7751r-cpg", + .data = &cpg_feature[CPG_SH7751R] }, + { } +}; + +static struct platform_driver sh7750_cpg_driver = { + .probe = sh7750_cpg_probe, + .driver = { + .name = "sh7750-cpg", + .of_match_table = sh7750_cpg_of_match, + }, +}; +builtin_platform_driver(sh7750_cpg_driver); From patchwork Tue Nov 14 08:00:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454931 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7F96C074FE for ; Tue, 14 Nov 2023 08:01:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232226AbjKNIBE (ORCPT ); Tue, 14 Nov 2023 03:01:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40600 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232298AbjKNIBC (ORCPT ); Tue, 14 Nov 2023 03:01:02 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id BF46E19B for ; Tue, 14 Nov 2023 00:00:58 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 53B881C02FE; Tue, 14 Nov 2023 17:00:58 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Thomas Gleixner , Geert Uytterhoeven , Magnus Damm Subject: [PATCH v4 17/37] irqchip: Add SH7751 INTC driver Date: Tue, 14 Nov 2023 17:00:08 +0900 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Renesas SH7751 Internal interrupt controller driver. Signed-off-by: Yoshinori Sato --- drivers/irqchip/Kconfig | 8 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-renesas-sh7751.c | 290 +++++++++++++++++++++++++++ 3 files changed, 299 insertions(+) create mode 100644 drivers/irqchip/irq-renesas-sh7751.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index f7149d0f3d45..658523f65b1d 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -679,4 +679,12 @@ config SUNPLUS_SP7021_INTC chained controller, routing all interrupt source in P-Chip to the primary controller on C-Chip. +config RENESAS_SH7751_INTC + bool "Renesas SH7751 Interrupt Controller" + depends on SH_DEVICE_TREE || COMPILE_TEST + select IRQ_DOMAIN_HIERARCHY + help + Support for the Renesas SH7751 On-chip interrupt controller. + And external interrupt encoder for some targets. + endmenu diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index ffd945fe71aa..26c91d075e25 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -120,3 +120,4 @@ obj-$(CONFIG_IRQ_IDT3243X) += irq-idt3243x.o obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o +obj-$(CONFIG_RENESAS_SH7751_INTC) += irq-renesas-sh7751.o diff --git a/drivers/irqchip/irq-renesas-sh7751.c b/drivers/irqchip/irq-renesas-sh7751.c new file mode 100644 index 000000000000..f3bc150267c0 --- /dev/null +++ b/drivers/irqchip/irq-renesas-sh7751.c @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas SH7751 interrupt controller driver + * + * Copyright 2023 Yoshinori Sato + */ + +#include +#include +#include +#include +#include +#include +#include + +struct ipr { + unsigned int off; + unsigned int idx; +}; + +struct sh7751_intc_priv { + void __iomem *base; + void __iomem *intpri00; + struct ipr *iprmap[2]; + bool irlm; +}; + +enum { + R_ICR = 0x00, + R_IPR = 0x04, + R_INTPRI00 = 0x00, + R_INTREQ00 = 0x20, + R_INTMSK00 = 0x40, + R_INTMSKCLR00 = 0x60, +}; + +#define ICR_IRLM BIT(7) + +/* + * SH7751 IRQ mapping + * IRQ16 - 63: Group0 - IPRA to IPRD + * IRQ16 - 31: external IRL input (ICR.IRLM is 0) + * IRQ80 - 92: Group1 - INTPRI00 + */ +#define IRQ_START 16 +#define MAX_IRL (IRQ_START + NR_IRL) +#define GRP0_IRQ_END 63 +#define GRP1_IRQ_START 80 +#define IRQ_END 92 + +#define NR_IPRMAP0 (GRP0_IRQ_END - IRQ_START + 1) +#define NR_IPRMAP1 (IRQ_END - GRP1_IRQ_START) +#define IPR_PRI_MASK 0x000f + +/* + * IPR registers have 4bit priority x 4 entry (16bits) + * Interrupts can be masked by setting pri to 0. + */ +static void update_ipr(struct sh7751_intc_priv *priv, unsigned int irq, u16 pri) +{ + struct ipr *ipr = NULL; + void __iomem *ipr_base; + unsigned int offset; + u16 mask; + + if (irq < GRP1_IRQ_START) { + /* Group0 */ + ipr = priv->iprmap[0]; + ipr += irq - IRQ_START; + ipr_base = priv->base + R_IPR; + offset = ipr->off; + } else { + /* Group1 */ + ipr = priv->iprmap[1]; + ipr += irq - GRP1_IRQ_START; + ipr_base = priv->intpri00; + offset = ipr->off - INTPRI00; + } + if (ipr->off != ~0) { + mask = ~(IPR_PRI_MASK << ipr->idx); + pri = (pri & IPR_PRI_MASK) << ipr->idx; + mask &= __raw_readw(ipr_base + offset); + __raw_writew(mask | pri, ipr_base + offset); + } else { + pr_warn_once("%s: undefined IPR in irq %u\n", __FILE__, irq); + } +} + +static inline bool is_valid_irq(unsigned int irq) +{ + /* IRQ16 - 63 */ + if (irq >= IRQ_START && irq < IRQ_START + NR_IPRMAP0) + return true; + /* IRQ80 - 92 */ + if (irq >= GRP1_IRQ_START && irq <= IRQ_END) + return true; + return false; +} + +static inline struct sh7751_intc_priv *irq_data_to_priv(struct irq_data *data) +{ + return data->domain->host_data; +} + +static void endisable_irq(struct irq_data *data, int enable) +{ + struct sh7751_intc_priv *priv; + unsigned int irq; + + priv = irq_data_to_priv(data); + + irq = irqd_to_hwirq(data); + if (!is_valid_irq(irq)) { + /* IRQ out of range */ + pr_warn_once("%s: IRQ %u is out of range\n", __FILE__, irq); + return; + } + + if (irq <= MAX_IRL && !priv->irlm) + /* IRL encoded external interrupt */ + /* disable for SR.IMASK */ + update_sr_imask(irq - IRQ_START, enable); + else + /* Internal peripheral interrupt */ + /* mask for IPR priority 0 */ + update_ipr(priv, irq, enable); +} + +static void sh7751_mask_irq(struct irq_data *data) +{ + endisable_irq(data, 0); +} + +static void sh7751_unmask_irq(struct irq_data *data) +{ + endisable_irq(data, 1); +} + +static const struct irq_chip sh7751_irq_chip = { + .name = "SH7751-INTC", + .irq_unmask = sh7751_unmask_irq, + .irq_mask = sh7751_mask_irq, +}; + +static int irq_sh7751_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw_irq_num) +{ + irq_set_chip_and_handler(virq, &sh7751_irq_chip, handle_level_irq); + irq_get_irq_data(virq)->chip_data = h->host_data; + irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOPROBE); + return 0; +} +static const struct irq_domain_ops irq_ops = { + .map = irq_sh7751_map, + .xlate = irq_domain_xlate_onecell, +}; + +static int __init load_ipr_map(struct device_node *intc, + struct sh7751_intc_priv *priv) +{ + struct property *ipr_map; + unsigned int num_ipr, i; + struct ipr *ipr; + const __be32 *p; + u32 irq; + + ipr_map = of_find_property(intc, "renesas,ipr-map", &num_ipr); + if (IS_ERR(ipr_map)) + return PTR_ERR(ipr_map); + num_ipr /= sizeof(u32); + /* 3words per entry. */ + if (num_ipr % 3) + goto error1; + num_ipr /= 3; + if (num_ipr >= NR_IPRMAP0 + NR_IPRMAP1) + goto error1; + + /* Allocate map array and fill in unassigned */ + priv->iprmap[0] = kmalloc_array(NR_IPRMAP0, sizeof(struct ipr), GFP_KERNEL); + if (priv->iprmap[0] == NULL) + return -ENOMEM; + memset(priv->iprmap[0], ~0, NR_IPRMAP0 * sizeof(struct ipr)); + priv->iprmap[1] = kmalloc_array(NR_IPRMAP1, sizeof(struct ipr), GFP_KERNEL); + if (priv->iprmap[1] == NULL) { + kfree(priv->iprmap[0]); + return -ENOMEM; + } + memset(priv->iprmap[1], ~0, NR_IPRMAP1 * sizeof(struct ipr)); + + p = NULL; + for (; num_ipr > 0; num_ipr--) { + /* 1st word - INTEVT code */ + p = of_prop_next_u32(ipr_map, p, &irq); + if (!p) + goto error; + irq = evt2irq(irq); + if (!is_valid_irq(irq)) + goto error; + if (irq < GRP1_IRQ_START) { + ipr = priv->iprmap[0]; + irq -= IRQ_START; + } else { + ipr = priv->iprmap[1]; + irq -= GRP1_IRQ_START; + } + ipr += irq; + /* 2nd word - IPR register offset */ + p = of_prop_next_u32(ipr_map, p, &ipr->off); + /* 3rd word - IPR register bit indx */ + p = of_prop_next_u32(ipr_map, p, &ipr->idx); + + if ((ipr->off != INTPRI00 && ipr->off > IPRD) || + ipr->idx > IPR_B12) + goto error; + } + + for (ipr = priv->iprmap[0], i = 0; i < NR_IPRMAP0; ipr++, i++) { + if (ipr->off != ~0) { + pr_debug("INTEVT=%04x (%u) reg=IPR%c idx=%u\n", + irq2evt(i + IRQ_START), i + IRQ_START, + 'A' + ipr->off / 4, ipr->idx); + } + } + for (ipr = priv->iprmap[1], i = 0; i < NR_IPRMAP1; ipr++, i++) { + if (ipr->off != ~0) { + pr_debug("INTEVT=%04x (%u) reg=INTPRI00 idx=%u\n", + irq2evt(i + GRP1_IRQ_START), i + GRP1_IRQ_START, + ipr->idx); + } + } + return 0; +error: + kfree(priv->iprmap[0]); + kfree(priv->iprmap[1]); +error1: + pr_err("%pOFP: Failed to load renesas,ipr-map\n", intc); + return -EINVAL; +} + +static int __init sh7751_intc_of_init(struct device_node *intc, + struct device_node *parent) +{ + struct sh7751_intc_priv *priv; + void __iomem *base, *base2; + struct irq_domain *domain; + u16 icr; + int ret; + + base = of_iomap(intc, 0); + base2 = of_iomap(intc, 1); + if (!base || !base2) { + pr_err("%pOFP: Invalid register definition\n", intc); + return -EINVAL; + } + + priv = kzalloc(sizeof(struct sh7751_intc_priv), GFP_KERNEL); + if (priv == NULL) + return -ENOMEM; + + ret = load_ipr_map(intc, priv); + if (ret < 0) { + kfree(priv); + return ret; + } + + priv->base = base; + priv->intpri00 = base2; + + if (of_property_read_bool(intc, "renesas,irlm")) { + priv->irlm = true; + icr = __raw_readw(priv->base + R_ICR); + icr |= ICR_IRLM; + __raw_writew(icr, priv->base + R_ICR); + } + + domain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, priv); + if (domain == NULL) { + pr_err("%pOFP: cannot initialize irq domain\n", intc); + kfree(priv); + return -ENOMEM; + } + + irq_set_default_host(domain); + pr_info("%pOFP: SH7751 Interrupt controller (%s external IRQ)", + intc, priv->irlm ? "4 lines" : "15 level"); + return 0; +} + +IRQCHIP_DECLARE(sh_7751_intc, + "renesas,sh7751-intc", sh7751_intc_of_init); From patchwork Tue Nov 14 08:00:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454930 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 095D6C4167B for ; Tue, 14 Nov 2023 08:01:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232298AbjKNIBE (ORCPT ); Tue, 14 Nov 2023 03:01:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232302AbjKNIBD (ORCPT ); Tue, 14 Nov 2023 03:01:03 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B50181A7 for ; Tue, 14 Nov 2023 00:00:59 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 2DE521C04EC; Tue, 14 Nov 2023 17:00:59 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Subject: [PATCH v4 18/37] dt-bindings: interrupt-controller: renesas,sh7751-intc: Add json-schema Date: Tue, 14 Nov 2023 17:00:09 +0900 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Renesas SH7751 INTC json-schema. Signed-off-by: Yoshinori Sato --- .../renesas,sh7751-intc.yaml | 105 ++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml new file mode 100644 index 000000000000..9d05c10f5c32 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH7751 Interrupt Controller + +maintainers: + - Yoshinori Sato + +properties: + compatible: + items: + - const: renesas,sh7751-intc + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + + reg: + maxItems: 2 + + reg-names: + items: + - const: ICR + - const: INTPRI00 + + renesas,icr-irlm: + type: boolean + description: If true ICR.IRLM=1 + + renesas,ipr-map: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + IRQ to IPR mapping definition. + 1st - INTEVT + 2nd - Register + 3rd - bit index + +required: + - compatible + - '#interrupt-cells' + - interrupt-controller + - reg + - reg-names + - renesas,ipr-map + +additionalProperties: false + +examples: + - | + #include + shintc: interrupt-controller@ffd00000 { + compatible = "renesas,sh7751-intc"; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0xffd00000 14>, <0xfe080000 128>; + reg-names = "ICR", "INTPRI00"; + renesas,ipr-map = <0x240 IPRD IPR_B12>, /* IRL0 */ + <0x2a0 IPRD IPR_B8>, /* IRL1 */ + <0x300 IPRD IPR_B4>, /* IRL2 */ + <0x360 IPRD IPR_B0>, /* IRL3 */ + <0x400 IPRA IPR_B12>, /* TMU0 */ + <0x420 IPRA IPR_B8>, /* TMU1 */ + <0x440 IPRA IPR_B4>, /* TMU2 TNUI */ + <0x460 IPRA IPR_B4>, /* TMU2 TICPI */ + <0x480 IPRA IPR_B0>, /* RTC ATI */ + <0x4a0 IPRA IPR_B0>, /* RTC PRI */ + <0x4c0 IPRA IPR_B0>, /* RTC CUI */ + <0x4e0 IPRB IPR_B4>, /* SCI ERI */ + <0x500 IPRB IPR_B4>, /* SCI RXI */ + <0x520 IPRB IPR_B4>, /* SCI TXI */ + <0x540 IPRB IPR_B4>, /* SCI TEI */ + <0x560 IPRB IPR_B12>, /* WDT */ + <0x580 IPRB IPR_B8>, /* REF RCMI */ + <0x5a0 IPRB IPR_B4>, /* REF ROVI */ + <0x600 IPRC IPR_B0>, /* H-UDI */ + <0x620 IPRC IPR_B12>, /* GPIO */ + <0x640 IPRC IPR_B8>, /* DMAC DMTE0 */ + <0x660 IPRC IPR_B8>, /* DMAC DMTE1 */ + <0x680 IPRC IPR_B8>, /* DMAC DMTE2 */ + <0x6a0 IPRC IPR_B8>, /* DMAC DMTE3 */ + <0x6c0 IPRC IPR_B8>, /* DMAC DMAE */ + <0x700 IPRC IPR_B4>, /* SCIF ERI */ + <0x720 IPRC IPR_B4>, /* SCIF RXI */ + <0x740 IPRC IPR_B4>, /* SCIF BRI */ + <0x760 IPRC IPR_B4>, /* SCIF TXI */ + <0x780 IPRC IPR_B8>, /* DMAC DMTE4 */ + <0x7a0 IPRC IPR_B8>, /* DMAC DMTE5 */ + <0x7c0 IPRC IPR_B8>, /* DMAC DMTE6 */ + <0x7e0 IPRC IPR_B8>, /* DMAC DMTE7 */ + <0xa00 INTPRI00 IPR_B0>, /* PCIC PCISERR */ + <0xa20 INTPRI00 IPR_B4>, /* PCIC PCIDMA3 */ + <0xa40 INTPRI00 IPR_B4>, /* PCIC PCIDMA2 */ + <0xa60 INTPRI00 IPR_B4>, /* PCIC PCIDMA1 */ + <0xa80 INTPRI00 IPR_B4>, /* PCIC PCIDMA0 */ + <0xaa0 INTPRI00 IPR_B4>, /* PCIC PCIPWON */ + <0xac0 INTPRI00 IPR_B4>, /* PCIC PCIPWDWN */ + <0xae0 INTPRI00 IPR_B4>, /* PCIC PCIERR */ + <0xb00 INTPRI00 IPR_B8>, /* TMU3 */ + <0xb80 INTPRI00 IPR_B12>; /* TMU4 */ + }; +... From patchwork Tue Nov 14 08:00:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454932 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 214AAC41535 for ; Tue, 14 Nov 2023 08:01:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232302AbjKNIBF (ORCPT ); Tue, 14 Nov 2023 03:01:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40644 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232278AbjKNIBE (ORCPT ); Tue, 14 Nov 2023 03:01:04 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id AADAD1B3 for ; Tue, 14 Nov 2023 00:01:00 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 36D941C0463; Tue, 14 Nov 2023 17:01:00 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Thomas Gleixner , Geert Uytterhoeven , Magnus Damm Subject: [PATCH v4 19/37] irqchip: SH7751 IRL external encoder with enable gate. Date: Tue, 14 Nov 2023 17:00:10 +0900 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org SH7751 have 15 level external interrupt. It is typically connected to the CPU through a priority encoder that can suppress requests. This driver provides a way to control those hardware with irqchip. Signed-off-by: Yoshinori Sato --- drivers/irqchip/Kconfig | 7 + drivers/irqchip/Makefile | 2 + drivers/irqchip/irq-renesas-sh7751irl.c | 227 ++++++++++++++++++++++++ 3 files changed, 236 insertions(+) create mode 100644 drivers/irqchip/irq-renesas-sh7751irl.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 658523f65b1d..2a061c01f381 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -687,4 +687,11 @@ config RENESAS_SH7751_INTC Support for the Renesas SH7751 On-chip interrupt controller. And external interrupt encoder for some targets. +config RENESAS_SH7751IRL_INTC + bool "Renesas SH7751 based target IRL encoder support." + depends on RENESAS_SH7751_INTC + help + Support for External Interrupt encoder + on the some Renesas SH7751 based target. + endmenu diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 26c91d075e25..91df16726b1f 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -121,3 +121,5 @@ obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o obj-$(CONFIG_RENESAS_SH7751_INTC) += irq-renesas-sh7751.o +obj-$(CONFIG_RENESAS_SH7751IRL_INTC) += irq-renesas-sh7751irl.o + diff --git a/drivers/irqchip/irq-renesas-sh7751irl.c b/drivers/irqchip/irq-renesas-sh7751irl.c new file mode 100644 index 000000000000..99ee5bf9fb1e --- /dev/null +++ b/drivers/irqchip/irq-renesas-sh7751irl.c @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SH7751 based board IRL encoder driver + * (Renesas RTS7751R2D / IO DATA DEVICE LANDISK, USL-5P) + * + * Copyright (C) 2023 Yoshinori Sato + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct sh7751irl_intc_priv { + struct irq_domain *irq_domain; + void __iomem *base; + unsigned int width; + bool invert; + u32 enable_bit[NR_IRL]; +}; + +static inline unsigned long get_reg(void __iomem *addr, unsigned int w) +{ + switch (w) { + case 8: + return __raw_readb(addr); + case 16: + return __raw_readw(addr); + case 32: + return __raw_readl(addr); + default: + /* The size is checked when reading the properties. */ + pr_err("%s: Invalid width %d", __FILE__, w); + return 0; + } +} + +static inline void set_reg(void __iomem *addr, unsigned int w, unsigned long val) +{ + switch (w) { + case 8: + __raw_writeb(val, addr); + break; + case 16: + __raw_writew(val, addr); + break; + case 32: + __raw_writel(val, addr); + break; + default: + pr_err("%s: Invalid width %d", __FILE__, w); + } +} + +static inline struct sh7751irl_intc_priv *irq_data_to_priv(struct irq_data *data) +{ + return data->domain->host_data; +} + +static void irl_endisable(struct irq_data *data, unsigned int enable) +{ + struct sh7751irl_intc_priv *priv; + unsigned long val; + unsigned int irl; + + priv = irq_data_to_priv(data); + irl = irqd_to_hwirq(data) - IRL_BASE_IRQ; + + if (irl < NR_IRL && priv->enable_bit[irl] < priv->width) { + if (priv->invert) + enable = !enable; + + val = get_reg(priv->base, priv->width); + if (enable) + set_bit(priv->enable_bit[irl], &val); + else + clear_bit(priv->enable_bit[irl], &val); + set_reg(priv->base, priv->width, val); + } else { + pr_err("%s: Invalid register define in IRL %u", __FILE__, irl); + } +} + +static void sh7751irl_intc_disable_irq(struct irq_data *data) +{ + irl_endisable(data, 0); +} + +static void sh7751irl_intc_enable_irq(struct irq_data *data) +{ + irl_endisable(data, 1); +} + +static struct irq_chip sh7751irl_intc_chip = { + .name = "SH7751IRL-INTC", + .irq_enable = sh7751irl_intc_enable_irq, + .irq_disable = sh7751irl_intc_disable_irq, +}; + +static int sh7751irl_intc_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw_irq_num) +{ + irq_set_chip_and_handler(virq, &sh7751irl_intc_chip, handle_level_irq); + irq_get_irq_data(virq)->chip_data = h->host_data; + irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOPROBE); + return 0; +} + +static int sh7751irl_intc_translate(struct irq_domain *domain, + struct irq_fwspec *fwspec, unsigned long *hwirq, + unsigned int *type) +{ + if (fwspec->param[0] > NR_IRL) + return -EINVAL; + + switch (fwspec->param_count) { + case 2: + *type = fwspec->param[1]; + fallthrough; + case 1: + *hwirq = fwspec->param[0] + IRL_BASE_IRQ; + break; + default: + return -EINVAL; + } + return 0; +} + +static const struct irq_domain_ops sh7751irl_intc_domain_ops = { + .map = sh7751irl_intc_map, + .translate = sh7751irl_intc_translate, +}; + +static int __init load_irq_bit(struct device_node *node, struct sh7751irl_intc_priv *priv) +{ + struct property *enable_map; + const __be32 *p; + u32 nr_bits; + u32 irl; + int ret; + + /* Fill in unused */ + memset(priv->enable_bit, ~0, sizeof(priv->enable_bit)); + + enable_map = of_find_property(node, "renesas,enable-bit", &nr_bits); + if (IS_ERR(enable_map)) + return PTR_ERR(enable_map); + + nr_bits /= sizeof(u32); + /* 2words per entry. */ + if (nr_bits % 2) + return -EINVAL; + nr_bits /= 2; + if (nr_bits > NR_IRL) + return -EINVAL; + + ret = nr_bits; + p = NULL; + for (; nr_bits > 0; nr_bits--) { + /* 1st word - IRL */ + p = of_prop_next_u32(enable_map, p, &irl); + if (!p || irl > NR_IRL) + return -EINVAL; + /* 2nd word - enable bit index */ + p = of_prop_next_u32(enable_map, p, &priv->enable_bit[irl]); + if (priv->enable_bit[irl] >= priv->width) + return -EINVAL; + } + return ret; +} + +static int __init sh7751irl_init(struct device_node *node, struct device_node *parent) +{ + struct sh7751irl_intc_priv *priv; + struct irq_domain *d; + void __iomem *base; + int ret = 0; + + base = of_iomap(node, 0); + if (!base) + ret = -EINVAL; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = base; + of_property_read_u32(node, "renesas,width", &priv->width); + if (priv->width != 8 && priv->width != 16 && priv->width != 32) { + pr_err("%pOFP: Invalid register width.\n", node); + ret = -EINVAL; + goto error; + } + + priv->invert = of_property_read_bool(node, "renesas,set-to-disable"); + + ret = load_irq_bit(node, priv); + if (ret < 0) { + pr_err("%pOFP: Invalid register define.\n", node); + goto error; + } + + d = irq_domain_add_tree(node, &sh7751irl_intc_domain_ops, priv); + if (d == NULL) { + pr_err("%pOFP: cannot initialize irq domain\n", node); + ret = -ENOMEM; + goto error; + } + + priv->irq_domain = d; + irq_domain_update_bus_token(d, DOMAIN_BUS_WIRED); + pr_info("%pOFP: SH7751 External Interrupt encoder (input=%d)", node, ret); + return 0; +error: + kfree(priv); + return ret; +} + +IRQCHIP_DECLARE(renesas_sh7751_irl, "renesas,sh7751-irl-ext", sh7751irl_init); From patchwork Tue Nov 14 08:00:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1BB3C4167D for ; Tue, 14 Nov 2023 08:01:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232278AbjKNIBF (ORCPT ); Tue, 14 Nov 2023 03:01:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232304AbjKNIBE (ORCPT ); Tue, 14 Nov 2023 03:01:04 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id BD84219B for ; Tue, 14 Nov 2023 00:01:01 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 0FC9C1C04D2; Tue, 14 Nov 2023 17:01:01 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Subject: [PATCH v4 20/37] dt-bindings: interrupt-controller: renesas,sh7751-irl-ext: Add json-schema Date: Tue, 14 Nov 2023 17:00:11 +0900 Message-Id: <79f04fd1a9cda155b1fb1771832a99bee8c3e838.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Renesas SH7751 external interrupt encoder json-schema. Signed-off-by: Yoshinori Sato --- .../renesas,sh7751-irl-ext.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml new file mode 100644 index 000000000000..ba4fe2e4d749 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-irl-ext.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH7751 IRL external encoder with enable regs. + +maintainers: + - Yoshinori Sato + +description: | + This is the generally used external interrupt encoder on SH7751 based boards. + +properties: + compatible: + items: + - const: renesas,sh7751-irl-ext + + reg: + minItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + '#address-cells': + const: 0 + + '#size-cells': + const: 0 + + renesas,width: + description: Enable register width + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [8, 16, 32] + + renesas,set-to-disable: + $ref: /schemas/types.yaml#/definitions/flag + description: Setting this flag to 1 disables it. + + renesas,enable-bit: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + IRL enable register bit mapping + 1st word IRL + 2nd word bit index of enable register + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - renesas,width + - renesas,enable-bit + +additionalProperties: false + +examples: + - | + r2dintc: sh7751irl_encoder@a4000000 { + compatible = "renesas,sh7751-irl-ext"; + reg = <0xa4000000 0x02>; + interrupt-controller; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <1>; + renesas,width = <16>; + renesas,enable-bit = <0 11>, /* PCI INTD */ + <1 9>, /* CF IDE */ + <2 8>, /* CF CD */ + <3 12>, /* PCI INTC */ + <4 10>, /* SM501 */ + <5 6>, /* KEY */ + <6 5>, /* RTC ALARM */ + <7 4>, /* RTC T */ + <8 7>, /* SDCARD */ + <9 14>, /* PCI INTA */ + <10 13>, /* PCI INTB */ + <11 0>, /* EXT */ + <12 15>; /* TP */ + }; From patchwork Tue Nov 14 08:00:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454934 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98087C4332F for ; Tue, 14 Nov 2023 08:01:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232308AbjKNIBJ (ORCPT ); Tue, 14 Nov 2023 03:01:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232304AbjKNIBH (ORCPT ); Tue, 14 Nov 2023 03:01:07 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 72CEB19E for ; Tue, 14 Nov 2023 00:01:04 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 4A1091C0463; Tue, 14 Nov 2023 17:01:03 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Greg Kroah-Hartman , Jiri Slaby , Geert Uytterhoeven , Magnus Damm , Max Filippov , Palmer Dabbelt , Bin Meng , Arnd Bergmann , Jonathan Corbet , Jean Delvare , Tom Rix , Jacky Huang , Lukas Bulwahn , Conor Dooley , Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Petr Mladek , Rob Herring , John Ogness , Thomas Gleixner Subject: [PATCH v4 21/37] serial: sh-sci: fix SH4 OF support. Date: Tue, 14 Nov 2023 17:00:12 +0900 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org - fix earlycon name. - fix earlyprintk hung (NULL pointer reference). Signed-off-by: Yoshinori Sato --- drivers/tty/serial/Kconfig | 2 +- drivers/tty/serial/sh-sci.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 732c893c8d16..56d635371fd3 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -658,7 +658,7 @@ config SERIAL_SH_SCI_EARLYCON depends on SERIAL_SH_SCI=y select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON - default ARCH_RENESAS + default ARCH_RENESAS || SUPERH config SERIAL_SH_SCI_DMA bool "DMA support" if EXPERT diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 84ab434c94ba..0a33581be08b 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -2720,7 +2720,7 @@ static int sci_remap_port(struct uart_port *port) if (port->membase) return 0; - if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { + if ((port->dev && port->dev->of_node) || (port->flags & UPF_IOREMAP)) { port->membase = ioremap(port->mapbase, sport->reg_size); if (unlikely(!port->membase)) { dev_err(port->dev, "can't remap port#%d\n", port->line); @@ -3555,8 +3555,8 @@ static int __init hscif_early_console_setup(struct earlycon_device *device, OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); -OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); -OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup); +OF_EARLYCON_DECLARE(rzscifa, "renesas,scif-r7s9210", rzscifa_early_console_setup); +OF_EARLYCON_DECLARE(rzscifa, "renesas,scif-r9a07g044", rzscifa_early_console_setup); OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); From patchwork Tue Nov 14 08:00:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0ABCC4167D for ; Tue, 14 Nov 2023 08:01:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232304AbjKNIBJ (ORCPT ); Tue, 14 Nov 2023 03:01:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232305AbjKNIBI (ORCPT ); Tue, 14 Nov 2023 03:01:08 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 3DE42195 for ; Tue, 14 Nov 2023 00:01:05 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 17C9C1C00A4; Tue, 14 Nov 2023 17:01:04 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Subject: [PATCH v4 22/37] dt-bindings: serial: renesas,scif: Add scif-sh7751. Date: Tue, 14 Nov 2023 17:00:13 +0900 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Add Renesas SH7751 SCIF. Signed-off-by: Yoshinori Sato --- Documentation/devicetree/bindings/serial/renesas,scif.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml index 4610a5bd580c..a774f16400c2 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -17,6 +17,7 @@ properties: oneOf: - items: - enum: + - renesas,scif-sh7751 # SH7751 - renesas,scif-r7s72100 # RZ/A1H - const: renesas,scif # generic SCIF compatible UART From patchwork Tue Nov 14 08:00:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454936 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32999C4167B for ; Tue, 14 Nov 2023 08:01:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232305AbjKNIBL (ORCPT ); Tue, 14 Nov 2023 03:01:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232306AbjKNIBK (ORCPT ); Tue, 14 Nov 2023 03:01:10 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 2593419E for ; Tue, 14 Nov 2023 00:01:06 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 3856E1C04D0; Tue, 14 Nov 2023 17:01:06 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v4 23/37] dt-bindings: display: smi,sm501: SMI SM501 binding json-schema Date: Tue, 14 Nov 2023 17:00:14 +0900 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Define SM501 functions and modes. Signed-off-by: Yoshinori Sato --- .../bindings/display/smi,sm501.yaml | 138 ++++++++++++++++++ include/dt-bindings/display/sm501.h | 25 ++++ 2 files changed, 163 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/smi,sm501.yaml create mode 100644 include/dt-bindings/display/sm501.h diff --git a/Documentation/devicetree/bindings/display/smi,sm501.yaml b/Documentation/devicetree/bindings/display/smi,sm501.yaml new file mode 100644 index 000000000000..4861b8e14ce5 --- /dev/null +++ b/Documentation/devicetree/bindings/display/smi,sm501.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/smi,sm501.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silicon Motion SM501 Mobile Multimedia Companion Chip + +maintainers: + - Yoshinori Sato + +description: | + These DT bindings describe the SM501. + +properties: + compatible: + const: + smi,sm501 + + reg: + maxItems: 2 + description: | + First entry: System Configuration register + Second entry: IO space (Display Controller register) + + interrupts: + description: SM501 interrupt to the cpu should be described here. + + interrupt-name: true + + mode: + $ref: /schemas/types.yaml#/definitions/string + description: select a video mode + + edid: + description: | + verbatim EDID data block describing attached display. + Data from the detailed timing descriptor will be used to + program the display controller. + + little-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: available on big endian systems, to set different foreign endian. + big-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: available on little endian systems, to set different foreign endian. + + swap-fb-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: swap framebuffer byteorder. + + route-crt-panel: + $ref: /schemas/types.yaml#/definitions/flag + description: Panel output merge to CRT. + + crt: + description: CRT output control + + panel: + description: Panel output control + + bpp: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Color depth + + smi,flags: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Display control flags. + + smi,devices: + $ref: /schemas/types.yaml#/definitions/uint32 + description: SM501 device function select. + + smi,mclk: + $ref: /schemas/types.yaml#/definitions/uint32 + description: mclk frequency. + + smi,m1xclk: + $ref: /schemas/types.yaml#/definitions/uint32 + description: m1xclk frequency. + + smi,misc-timing: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Miscellaneous Timing reg value. + + smi,misc-control: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Miscellaneous Control reg value. + + smi,gpio-low: + $ref: /schemas/types.yaml#/definitions/uint32 + description: GPIO0 to 31 Control reg value. + + smi,gpio-high: + $ref: /schemas/types.yaml#/definitions/uint32 + description: GPIO32 to 63 Control reg value. + + smi,num-i2c: + $ref: /schemas/types.yaml#/definitions/uint32 + description: I2C channel number. + + smi,gpio-i2c: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 5 + description: | + GPIO I2C bus number + 1st field - I2C bus number + 2nd Field - GPIO SDA + 3rd Field - GPIO SCL + 4th Field - Timeout + 5th Field - udelay + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + + +examples: + # MPC5200 + - | + display@1,0 { + compatible = "smi,sm501"; + reg = <0x00000000 0x00800000 + 0x03e00000 0x00200000>; + interrupts = <1 1 3>; + mode = "640x480-32@60"; + edid = [00 ff ff ff ff ff ff 00 00 00 00 00 00 00 00 00 + 00 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 f0 0a 80 fb 20 e0 25 10 32 60 + 02 00 00 00 00 00 00 06 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 bd]; + }; diff --git a/include/dt-bindings/display/sm501.h b/include/dt-bindings/display/sm501.h new file mode 100644 index 000000000000..9cf6566c242e --- /dev/null +++ b/include/dt-bindings/display/sm501.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Platform data definitions */ + +#define SM501FB_FLAG_USE_INIT_MODE (1<<0) +#define SM501FB_FLAG_DISABLE_AT_EXIT (1<<1) +#define SM501FB_FLAG_USE_HWCURSOR (1<<2) +#define SM501FB_FLAG_USE_HWACCEL (1<<3) +#define SM501FB_FLAG_PANEL_NO_FPEN (1<<4) +#define SM501FB_FLAG_PANEL_NO_VBIASEN (1<<5) +#define SM501FB_FLAG_PANEL_INV_FPEN (1<<6) +#define SM501FB_FLAG_PANEL_INV_VBIASEN (1<<7) + +#define SM501_USE_USB_HOST (1<<0) +#define SM501_USE_USB_SLAVE (1<<1) +#define SM501_USE_SSP0 (1<<2) +#define SM501_USE_SSP1 (1<<3) +#define SM501_USE_UART0 (1<<4) +#define SM501_USE_UART1 (1<<5) +#define SM501_USE_FBACCEL (1<<6) +#define SM501_USE_AC97 (1<<7) +#define SM501_USE_I2S (1<<8) +#define SM501_USE_GPIO (1<<9) + +#define SM501_USE_ALL (0xffffffff) From patchwork Tue Nov 14 08:00:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454937 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CD30C4332F for ; Tue, 14 Nov 2023 08:01:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232314AbjKNIBO (ORCPT ); Tue, 14 Nov 2023 03:01:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232306AbjKNIBN (ORCPT ); Tue, 14 Nov 2023 03:01:13 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 7B4FE19B for ; Tue, 14 Nov 2023 00:01:09 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id A88EA1C0465; Tue, 14 Nov 2023 17:01:08 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Lee Jones , Helge Deller , Thomas Zimmermann , Sam Ravnborg , Javier Martinez Canillas , Rob Herring , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= Subject: [PATCH v4 24/37] mfd: sm501: Convert platform_data to OF property Date: Tue, 14 Nov 2023 17:00:15 +0900 Message-Id: <478cf6465ab23eaf00515b8d067101bec514358b.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Various parameters of SM501 can be set using platform_data, so parameters cannot be passed in the DeviceTree target. Expands the parameters set in platform_data so that they can be specified using DeviceTree properties. Signed-off-by: Yoshinori Sato --- drivers/mfd/sm501.c | 70 +++++++++++++++++++++++++++++++++++ drivers/video/fbdev/sm501fb.c | 70 +++++++++++++++++++++++++++++++++-- include/linux/sm501.h | 3 +- 3 files changed, 138 insertions(+), 5 deletions(-) diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c index 28027982cf69..4f9c9c5936ff 100644 --- a/drivers/mfd/sm501.c +++ b/drivers/mfd/sm501.c @@ -1370,6 +1370,69 @@ static int sm501_init_dev(struct sm501_devdata *sm) return 0; } +#ifdef CONFIG_OF +static void sm501_of_read_reg_init(struct device_node *np, + const char *propname, struct sm501_reg_init *val) +{ + u32 u32_val[2]; + + if (!of_property_read_u32_array(np, propname, u32_val, sizeof(u32_val))) { + val->set = u32_val[0]; + val->mask = u32_val[1]; + } +} + +static int sm501_parse_dt(struct sm501_devdata *sm, struct device_node *np) +{ + struct sm501_platdata *plat; + u32 u32_val; + + plat = devm_kzalloc(sm->dev, sizeof(*plat), GFP_KERNEL); + if (!plat) + return -ENOMEM; + + plat->init = devm_kzalloc(sm->dev, sizeof(*plat->init), GFP_KERNEL); + if (!plat->init) + return -ENOMEM; + + if (!of_property_read_u32(np, "smi,devices", &u32_val)) + plat->init->devices = u32_val; + + if (!of_property_read_u32(np, "smi,mclk", &u32_val)) + plat->init->mclk = u32_val; + + if (!of_property_read_u32(np, "smi,m1xclk", &u32_val)) + plat->init->m1xclk = u32_val; + + sm501_of_read_reg_init(np, "smi,misc-timing", &plat->init->misc_timing); + sm501_of_read_reg_init(np, "smi,misc-control", &plat->init->misc_control); + sm501_of_read_reg_init(np, "smi,gpio-low", &plat->init->gpio_low); + sm501_of_read_reg_init(np, "smi,gpio-high", &plat->init->gpio_high); + +#ifdef CONFIG_MFD_SM501_GPIO + if (plat->init->devices & SM501_USE_GPIO) { + if (!of_property_read_u32_index(np, "smi,num-i2c", 0, &u32_val)) + plat->gpio_i2c_nr = u32_val; + else + plat->gpio_i2c_nr = 0; + } + if (plat->gpio_i2c_nr > 0) { + int sz_gpio; + + sz_gpio = sizeof(struct sm501_platdata_gpio_i2c) * plat->gpio_i2c_nr; + plat->gpio_i2c = devm_kzalloc(sm->dev, sz_gpio, GFP_KERNEL); + if (plat->gpio_i2c == NULL) + return -ENOMEM; + + of_property_read_variable_u32(np, "smi,gpio-i2c", + plat->gpio_i2c, sz_gpio / sizeof(int)); + } +#endif /* CONFIG_MFD_SM501_GPIO */ + sm->platdata = plat; + return 0; +} +#endif /* CONFIG_OF */ + static int sm501_plat_probe(struct platform_device *dev) { struct sm501_devdata *sm; @@ -1406,6 +1469,13 @@ static int sm501_plat_probe(struct platform_device *dev) goto err_res; } +#ifdef CONFIG_OF + if (dev->dev.of_node) { + ret = sm501_parse_dt(sm, dev->dev.of_node); + if (ret) + goto err_res; + } +#endif platform_set_drvdata(dev, sm); sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res)); diff --git a/drivers/video/fbdev/sm501fb.c b/drivers/video/fbdev/sm501fb.c index d6fdc1737cd2..36a080dd35a1 100644 --- a/drivers/video/fbdev/sm501fb.c +++ b/drivers/video/fbdev/sm501fb.c @@ -1932,10 +1932,62 @@ static int sm501fb_start_one(struct sm501fb_info *info, return 0; } +#if defined(CONFIG_OF) +static struct sm501_platdata_fbsub *read_fbsub(struct device_node *np, const char *ch_name) +{ + struct sm501_platdata_fbsub *fbsub = NULL; + struct fb_videomode *def_mode; + struct device_node *child; + const void *prop; + u32 flags; + u32 bpp; + int len; + + child = of_get_child_by_name(np, ch_name); + if (child == NULL) + return NULL; + + prop = of_get_property(child, "edid", &len); + if (prop && len == EDID_LENGTH) { + struct fb_monspecs *specs; + u8 *edid; + + edid = kmemdup(prop, EDID_LENGTH, GFP_KERNEL); + if (edid) { + specs = kzalloc(sizeof(*specs), GFP_KERNEL); + if (specs) { + fb_edid_to_monspecs(edid, specs); + def_mode = specs->modedb; + } + kfree(specs); + } + kfree(edid); + } + + if (of_property_read_u32(child, "bpp", &bpp)) + bpp = 0; + if (of_property_read_u32(child, "smi,flags", &flags)) + flags = 0; + + if (def_mode || bpp || flags) { + fbsub = kzalloc(sizeof(*fbsub), GFP_KERNEL); + if (fbsub) { + fbsub->def_mode = def_mode; + fbsub->def_bpp = bpp; + fbsub->flags = flags; + } + } + return fbsub; +} +#endif + static int sm501fb_probe(struct platform_device *pdev) { - struct sm501fb_info *info; struct device *dev = &pdev->dev; + struct sm501fb_info *info; + const void *prop; + const char *cp; + int len; int ret; /* allocate our framebuffers */ @@ -1957,9 +2009,7 @@ static int sm501fb_probe(struct platform_device *pdev) int found = 0; #if defined(CONFIG_OF) struct device_node *np = pdev->dev.parent->of_node; - const u8 *prop; - const char *cp; - int len; + struct sm501_platdata_fbsub *sub; info->pdata = &sm501fb_def_pdata; if (np) { @@ -1974,6 +2024,18 @@ static int sm501fb_probe(struct platform_device *pdev) if (info->edid_data) found = 1; } + if (of_property_read_bool(np, "route-crt-panel")) + info->pdata->fb_route = SM501_FB_CRT_PANEL; + else + info->pdata->fb_route = SM501_FB_OWN; + if (of_property_read_bool(np, "swap-fb-endian")) + info->pdata->flags |= SM501_FBPD_SWAP_FB_ENDIAN; + sub = read_fbsub(np, "crt"); + if (sub) + info->pdata->fb_crt = sub; + sub = read_fbsub(np, "panel"); + if (sub) + info->pdata->fb_pnl = sub; } #endif if (!found) { diff --git a/include/linux/sm501.h b/include/linux/sm501.h index 2f3488b2875d..5c9a683b0615 100644 --- a/include/linux/sm501.h +++ b/include/linux/sm501.h @@ -6,6 +6,8 @@ * Vincent Sanders */ +#include + extern int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to); @@ -35,7 +37,6 @@ extern unsigned long sm501_modify_reg(struct device *dev, unsigned long clear); -/* Platform data definitions */ #define SM501FB_FLAG_USE_INIT_MODE (1<<0) #define SM501FB_FLAG_DISABLE_AT_EXIT (1<<1) From patchwork Tue Nov 14 08:00:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454938 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92A01C4167D for ; Tue, 14 Nov 2023 08:01:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232315AbjKNIBQ (ORCPT ); Tue, 14 Nov 2023 03:01:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232306AbjKNIBO (ORCPT ); Tue, 14 Nov 2023 03:01:14 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id CB1D9195 for ; Tue, 14 Nov 2023 00:01:11 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 183DC1C04DB; Tue, 14 Nov 2023 17:01:11 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Subject: [PATCH v4 25/37] dt-binding: sh: cpus: Add SH CPUs json-schema Date: Tue, 14 Nov 2023 17:00:16 +0900 Message-Id: <97773f27f0c91cd44ccf39ff07b7437c23e472fe.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Renesas SH series and compatible ISA CPUs. Signed-off-by: Yoshinori Sato --- .../devicetree/bindings/sh/cpus.yaml | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/sh/cpus.yaml diff --git a/Documentation/devicetree/bindings/sh/cpus.yaml b/Documentation/devicetree/bindings/sh/cpus.yaml new file mode 100644 index 000000000000..eb57e76e2aa2 --- /dev/null +++ b/Documentation/devicetree/bindings/sh/cpus.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sh/cpus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SuperH CPUs + +maintainers: + - Yoshinori Sato + +description: |+ + The device tree allows to describe the layout of CPUs in a system through + the "cpus" node, which in turn contains a number of subnodes (ie "cpu") + defining properties for every cpu. + + Bindings for CPU nodes follow the Devicetree Specification, available from: + + https://www.devicetree.org/specifications/ + +properties: + compatible: + items: + - enum: + - renesas,sh2a + - renesas,sh3 + - renesas,sh4 + - renesas,sh4a + - jcore,j2 + - const: renesas,sh2 + + clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + CPU core clock freqency. + + clocks: true + + clock-names: true + + reg: + $ref: /schemas/types.yaml#/definitions/uint32 + const: 0 + + device_type: true + +required: + - compatible + - reg + - device_type + +additionalProperties: true + +examples: + - | + #include + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu: cpu@0 { + compatible = "renesas,sh4", "renesas,sh2"; + device_type = "cpu"; + reg = <0>; + clocks = <&cpg SH7750_CPG_ICK>; + clock-names = "ick"; + icache-size = <16384>; + icache-line-size = <32>; + dcache-size = <32768>; + dcache-line-size = <32>; + }; + }; +... From patchwork Tue Nov 14 08:00:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454939 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A101AC4332F for ; Tue, 14 Nov 2023 08:01:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232320AbjKNIBR (ORCPT ); Tue, 14 Nov 2023 03:01:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232319AbjKNIBQ (ORCPT ); Tue, 14 Nov 2023 03:01:16 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 205F719E for ; Tue, 14 Nov 2023 00:01:13 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 423461C04EC; Tue, 14 Nov 2023 17:01:12 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Guo , Chris Morgan , Linus Walleij Subject: [PATCH v4 26/37] dt-bindings: vendor-prefix: Add new vendor iodata and smi. Date: Tue, 14 Nov 2023 17:00:17 +0900 Message-Id: <3ca881b5919a21d6d08caf48ca9287edac5baafa.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Added. - IO DATA DEVICE, Inc. - Silicon Motion Technology Corporation (Silicon Motion, Inc.) Signed-off-by: Yoshinori Sato --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 309b94c328c8..a338bdd743ab 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -671,6 +671,8 @@ patternProperties: description: Inventec "^inversepath,.*": description: Inverse Path + "^iodata,.*": + description: IO DATA DEVICE Inc. "^iom,.*": description: Iomega Corporation "^irondevice,.*": @@ -1281,6 +1283,8 @@ patternProperties: description: Skyworks Solutions, Inc. "^smartlabs,.*": description: SmartLabs LLC + "^smi,.*": + description: Silicon Motion Technology Corporation "^smsc,.*": description: Standard Microsystems Corporation "^snps,.*": From patchwork Tue Nov 14 08:00:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454940 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63EC7C072A2 for ; Tue, 14 Nov 2023 08:01:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232319AbjKNIBR (ORCPT ); Tue, 14 Nov 2023 03:01:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232306AbjKNIBQ (ORCPT ); Tue, 14 Nov 2023 03:01:16 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 73BC21A3 for ; Tue, 14 Nov 2023 00:01:13 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id AA5991C0515; Tue, 14 Nov 2023 17:01:12 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Damien Le Moal , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Linus Walleij Subject: [PATCH v4 27/37] dt-bindings: ata: ata-generic: Add new targets Date: Tue, 14 Nov 2023 17:00:18 +0900 Message-Id: <9ffa722f185f05745e62b2120f7b0dc439a712f3.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Added new ata-generic target. - iodata,usl-5p-ata - renesas,rts7751r2d-ata Each boards have simple IDE Interface. Use ATA generic driver. Signed-off-by: Yoshinori Sato --- Documentation/devicetree/bindings/ata/ata-generic.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/ata/ata-generic.yaml b/Documentation/devicetree/bindings/ata/ata-generic.yaml index 0697927f3d7e..1025b3b351d0 100644 --- a/Documentation/devicetree/bindings/ata/ata-generic.yaml +++ b/Documentation/devicetree/bindings/ata/ata-generic.yaml @@ -18,6 +18,8 @@ properties: - enum: - arm,vexpress-cf - fsl,mpc8349emitx-pata + - iodata,usl-5p-ata + - renesas,rts7751r2d-ata - const: ata-generic reg: From patchwork Tue Nov 14 08:00:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454941 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D7D6C4167B for ; Tue, 14 Nov 2023 08:01:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232322AbjKNIBS (ORCPT ); Tue, 14 Nov 2023 03:01:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232306AbjKNIBR (ORCPT ); Tue, 14 Nov 2023 03:01:17 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 838421A7 for ; Tue, 14 Nov 2023 00:01:14 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 996C91C0524; Tue, 14 Nov 2023 17:01:13 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v4 28/37] dt-bindings: soc: renesas: sh: Add SH7751 based target Date: Tue, 14 Nov 2023 17:00:19 +0900 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Signed-off-by: Yoshinori Sato --- .../devicetree/bindings/soc/renesas/sh.yaml | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/renesas/sh.yaml diff --git a/Documentation/devicetree/bindings/soc/renesas/sh.yaml b/Documentation/devicetree/bindings/soc/renesas/sh.yaml new file mode 100644 index 000000000000..3fbff2532ad3 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/sh.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/sh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SuperH Platform + +maintainers: + - Yoshinori Sato + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: RTS7751R2D Plus + items: + - enum: + - renesas,rts7751r2d # Renesas SH4 2D graphics board + - const: renesas,sh7751r + + - description: Julian board + items: + - enum: + - iodata,landisk # LANDISK HDL-U + - iodata,usl-5p # USL-5P + - const: renesas,sh7751r + +additionalProperties: true + +... From patchwork Tue Nov 14 08:00:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454942 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26ADDC4167D for ; Tue, 14 Nov 2023 08:01:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232306AbjKNIBT (ORCPT ); Tue, 14 Nov 2023 03:01:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232323AbjKNIBS (ORCPT ); Tue, 14 Nov 2023 03:01:18 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 2883619E for ; Tue, 14 Nov 2023 00:01:15 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 866781C050D; Tue, 14 Nov 2023 17:01:14 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rich Felker , John Paul Adrian Glaubitz , Geert Uytterhoeven , Magnus Damm Subject: [PATCH v4 29/37] sh: SH7751R SoC Internal peripheral definition dtsi. Date: Tue, 14 Nov 2023 17:00:20 +0900 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org SH7751R internal peripherals device tree. Signed-off-by: Yoshinori Sato --- arch/sh/boot/dts/sh7751r.dtsi | 151 ++++++++++++++++++++++++++++++++++ 1 file changed, 151 insertions(+) create mode 100644 arch/sh/boot/dts/sh7751r.dtsi diff --git a/arch/sh/boot/dts/sh7751r.dtsi b/arch/sh/boot/dts/sh7751r.dtsi new file mode 100644 index 000000000000..81455b1592fc --- /dev/null +++ b/arch/sh/boot/dts/sh7751r.dtsi @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the SH7751R SoC + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "renesas,sh4", "renesas,sh2"; + device_type = "cpu"; + reg = <0>; + clocks = <&cpg SH7750_CPG_ICK>; + clock-names = "ick"; + icache-size = <16384>; + icache-line-size = <32>; + dcache-size = <32768>; + dcache-line-size = <32>; + }; + }; + + xtal: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "xtal"; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&shintc>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cpg: clock-controller@ffc00000 { + #clock-cells = <1>; + #power-domain-cells = <0>; + compatible = "renesas,sh7751r-cpg"; + clocks = <&xtal>; + clock-names = "xtal"; + reg = <0xffc00000 20>, <0xfe0a0000 16>; + reg-names = "FRQCR", "CLKSTP00"; + renesas,mode = <0>; + }; + + shintc: interrupt-controller@ffd00000 { + compatible = "renesas,sh7751-intc"; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0xffd00000 20>, <0xfe080000 128>; + reg-names = "ICR", "INTPRI00"; + renesas,ipr-map = <0x240 IPRD IPR_B12>, /* IRL0 */ + <0x2a0 IPRD IPR_B8>, /* IRL1 */ + <0x300 IPRD IPR_B4>, /* IRL2 */ + <0x360 IPRD IPR_B0>, /* IRL3 */ + <0x400 IPRA IPR_B12>, /* TMU0 */ + <0x420 IPRA IPR_B8>, /* TMU1 */ + <0x440 IPRA IPR_B4>, /* TMU2 TNUI */ + <0x460 IPRA IPR_B4>, /* TMU2 TICPI */ + <0x480 IPRA IPR_B0>, /* RTC ATI */ + <0x4a0 IPRA IPR_B0>, /* RTC PRI */ + <0x4c0 IPRA IPR_B0>, /* RTC CUI */ + <0x4e0 IPRB IPR_B4>, /* SCI ERI */ + <0x500 IPRB IPR_B4>, /* SCI RXI */ + <0x520 IPRB IPR_B4>, /* SCI TXI */ + <0x540 IPRB IPR_B4>, /* SCI TEI */ + <0x560 IPRB IPR_B12>, /* WDT */ + <0x580 IPRB IPR_B8>, /* REF RCMI */ + <0x5a0 IPRB IPR_B4>, /* REF ROVI */ + <0x600 IPRC IPR_B0>, /* H-UDI */ + <0x620 IPRC IPR_B12>, /* GPIO */ + <0x640 IPRC IPR_B8>, /* DMAC DMTE0 */ + <0x660 IPRC IPR_B8>, /* DMAC DMTE1 */ + <0x680 IPRC IPR_B8>, /* DMAC DMTE2 */ + <0x6a0 IPRC IPR_B8>, /* DMAC DMTE3 */ + <0x6c0 IPRC IPR_B8>, /* DMAC DMAE */ + <0x700 IPRC IPR_B4>, /* SCIF ERI */ + <0x720 IPRC IPR_B4>, /* SCIF RXI */ + <0x740 IPRC IPR_B4>, /* SCIF BRI */ + <0x760 IPRC IPR_B4>, /* SCIF TXI */ + <0x780 IPRC IPR_B8>, /* DMAC DMTE4 */ + <0x7a0 IPRC IPR_B8>, /* DMAC DMTE5 */ + <0x7c0 IPRC IPR_B8>, /* DMAC DMTE6 */ + <0x7e0 IPRC IPR_B8>, /* DMAC DMTE7 */ + <0xa00 INTPRI00 IPR_B0>, /* PCIC PCISERR */ + <0xa20 INTPRI00 IPR_B4>, /* PCIC PCIDMA3 */ + <0xa40 INTPRI00 IPR_B4>, /* PCIC PCIDMA2 */ + <0xa60 INTPRI00 IPR_B4>, /* PCIC PCIDMA1 */ + <0xa80 INTPRI00 IPR_B4>, /* PCIC PCIDMA0 */ + <0xaa0 INTPRI00 IPR_B4>, /* PCIC PCIPWON */ + <0xac0 INTPRI00 IPR_B4>, /* PCIC PCIPWDWN */ + <0xae0 INTPRI00 IPR_B4>, /* PCIC PCIERR */ + <0xb00 INTPRI00 IPR_B8>, /* TMU3 */ + <0xb80 INTPRI00 IPR_B12>; /* TMU4 */ + }; + + /* sci0 is rarely used, so it is not defined here. */ + scif1: serial@ffe80000 { + compatible = "renesas,scif-sh7751", "renesas,scif"; + reg = <0xffe80000 0x100>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "bri"; + clocks = <&cpg SH7750_MSTP_SCIF>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + /* Normally ch0 and ch1 are used, so we will define ch0 to ch2 here. */ + tmu0: timer@ffd80000 { + compatible = "renesas,tmu-sh7750", "renesas,tmu"; + reg = <0xffd80000 12>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg SH7750_MSTP_TMU012>; + clock-names = "fck"; + power-domains = <&cpg>; + #renesas,channels = <3>; + }; + + pcic: pci@fe200000 { + compatible = "renesas,sh7751-pci"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + bus-range = <0 0>; + ranges = <0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>, + <0x01000000 0 0x00000000 0xfe240000 0 0x00040000>; + reg = <0xfe200000 0x0400>, + <0x0c000000 0x04000000>, + <0xff800000 0x0030>; + status = "disabled"; + }; + }; +}; From patchwork Tue Nov 14 08:00:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454943 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66804C07533 for ; Tue, 14 Nov 2023 08:01:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232323AbjKNIBU (ORCPT ); Tue, 14 Nov 2023 03:01:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48428 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232326AbjKNIBT (ORCPT ); Tue, 14 Nov 2023 03:01:19 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 15BDF19B for ; Tue, 14 Nov 2023 00:01:16 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 843381C0515; Tue, 14 Nov 2023 17:01:15 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rich Felker , John Paul Adrian Glaubitz , Geert Uytterhoeven , Magnus Damm Subject: [PATCH v4 30/37] sh: add RTS7751R2D Plus DTS Date: Tue, 14 Nov 2023 17:00:21 +0900 Message-Id: <6fb41232e2293f2c4fcc027b6f1b0ad72667dda5.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Renesas RTS7751R2D Plus devicetree. Signed-off-by: Yoshinori Sato --- arch/sh/boot/dts/rts7751r2dplus.dts | 158 ++++++++++++++++++++++++++++ 1 file changed, 158 insertions(+) create mode 100644 arch/sh/boot/dts/rts7751r2dplus.dts diff --git a/arch/sh/boot/dts/rts7751r2dplus.dts b/arch/sh/boot/dts/rts7751r2dplus.dts new file mode 100644 index 000000000000..c835a20beb4c --- /dev/null +++ b/arch/sh/boot/dts/rts7751r2dplus.dts @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Renesas RTS7751R2D Plus + */ + +/dts-v1/; + +#include "sh7751r.dtsi" +#include + +/ { + model = "Renesas RTS7715R2D Plus"; + compatible = "renesas,rts7751r2d", "renesas,sh7751r"; + + aliases { + serial0 = &scif1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@c000000 { + device_type = "memory"; + reg = <0x0c000000 0x4000000>; + }; + + r2dintc: sh7751irl_encoder@a4000000 { + compatible = "renesas,sh7751-irl-ext"; + reg = <0xa4000000 0x02>; + interrupt-controller; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <1>; + renesas,width = <16>; + renesas,enable-bit = <0 11>, /* PCI INTD */ + <1 9>, /* CF IDE */ + <2 8>, /* CF CD */ + <3 12>, /* PCI INTC */ + <4 10>, /* SM501 */ + <5 6>, /* KEY */ + <6 5>, /* RTC ALARM */ + <7 4>, /* RTC T */ + <8 7>, /* SDCARD */ + <9 14>, /* PCI INTA */ + <10 13>, /* PCI INTB */ + <11 0>, /* EXT */ + <12 15>; /* TP */ + }; + + display@0 { + compatible = "smi,sm501"; + reg = <0x10000000 0x03e00000 + 0x13e00000 0x00200000>; + interrupt-parent = <&r2dintc>; + interrupts = <4>; + mode = "640x480-16@60"; + little-endian; + smi,devices = <(SM501_USE_USB_HOST | SM501_USE_UART0)>; + interrupt-name = "sm501"; + swap-fb-endian; + + crt { + smi,flags = <(SM501FB_FLAG_USE_INIT_MODE | + SM501FB_FLAG_DISABLE_AT_EXIT | + SM501FB_FLAG_USE_HWCURSOR | + SM501FB_FLAG_USE_HWACCEL)>; + }; + + panel { + bpp = <16>; + edid = [00 ff ff ff ff ff ff 00 00 00 00 00 00 00 00 00 + 00 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 f0 0a 80 fb 20 e0 25 10 32 60 + 02 00 00 00 00 00 00 06 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 bd]; + smi,flags = <(SM501FB_FLAG_USE_INIT_MODE | + SM501FB_FLAG_DISABLE_AT_EXIT | + SM501FB_FLAG_USE_HWCURSOR | + SM501FB_FLAG_USE_HWACCEL)>; + }; + }; + + compact-flash@b4001000 { + compatible = "renesas,rts7751r2d-ata", "ata-generic"; + reg = <0xb4001000 0x0e>, <0xb400080c 2>; + reg-shift = <1>; + interrupt-parent = <&r2dintc>; + interrupts = <1>; + }; + + flash@0 { + compatible = "cfi-flash"; + reg = <0x00000000 0x02000000>; + device-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x00000000 0x00040000>; + }; + + partition@1 { + label = "Environemt"; + reg = <0x00040000 0x00040000>; + }; + + partition@2 { + label = "Kernel"; + reg = <0x00080000 0x001c0000>; + }; + + partition@3 { + label = "Flash_FS"; + reg = <0x00240000 0x00dc0000>; + }; + }; +}; + +&xtal { + clock-frequency = <22222222>; +}; + +&cpg { + renesas,mode = <5>; +}; + +&scif1 { + status = "okay"; +}; + +&pcic { + interrupt-parent = <&r2dintc>; + renesas,bcr1 = <0x40080000>; + renesas,intm = <0x0000c3ff>; + renesas,aintm = <0x0000380f>; + renesas,config = <1 0xfb900047>, <4 0xab000001>; + renesas,mcrmask = <0x40000004>; + + interrupt-map = <0x0000 0 0 1 &r2dintc 9>, + <0x0000 0 0 2 &r2dintc 10>, + <0x0000 0 0 3 &r2dintc 3>, + <0x0000 0 0 4 &r2dintc 0>, + <0x0800 0 0 1 &r2dintc 10>, + <0x0800 0 0 2 &r2dintc 3>, + <0x0800 0 0 3 &r2dintc 0>, + <0x0800 0 0 4 &r2dintc 9>, + <0x1000 0 0 1 &r2dintc 3>, + <0x1000 0 0 2 &r2dintc 0>, + <0x1000 0 0 3 &r2dintc 9>, + <0x1000 0 0 4 &r2dintc 10>; + interrupt-map-mask = <0x1800 0 0 7>; + status = "okay"; +}; From patchwork Tue Nov 14 08:00:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454944 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED1B6C4332F for ; Tue, 14 Nov 2023 08:01:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232326AbjKNIBU (ORCPT ); Tue, 14 Nov 2023 03:01:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232327AbjKNIBT (ORCPT ); Tue, 14 Nov 2023 03:01:19 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 0F8C3195 for ; Tue, 14 Nov 2023 00:01:16 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 7469E1C0509; Tue, 14 Nov 2023 17:01:16 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rich Felker , John Paul Adrian Glaubitz , Geert Uytterhoeven , Magnus Damm Subject: [PATCH v4 31/37] sh: Add IO DATA LANDISK dts Date: Tue, 14 Nov 2023 17:00:22 +0900 Message-Id: <3cfcf423eec19ce0b349093dd54b8a9959ed80eb.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org IO DATA DEVICE Inc. LANDISK HDL-U devicetree. Signed-off-by: Yoshinori Sato --- arch/sh/boot/dts/landisk.dts | 74 ++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 arch/sh/boot/dts/landisk.dts diff --git a/arch/sh/boot/dts/landisk.dts b/arch/sh/boot/dts/landisk.dts new file mode 100644 index 000000000000..2985cba0202a --- /dev/null +++ b/arch/sh/boot/dts/landisk.dts @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the IO DATA DEVICE LANDISK + */ + +/dts-v1/; + +#include "sh7751r.dtsi" + +/ { + model = "IO DATA Device LANDISK"; + compatible = "iodata,landisk", "renesas,sh7751r"; + + aliases { + serial0 = &scif1; + }; + + chosen { + stdout-path = "serial0:9600n8"; + }; + + memory@c000000 { + device_type = "memory"; + reg = <0x0c000000 0x4000000>; + }; + + julianintc: sh7751irl_encoder@b0000005 { + compatible = "renesas,sh7751-irl-ext"; + reg = <0xb0000005 0x01>; + interrupt-controller; + #interrupt-cells = <1>; + renesas,width = <8>; + renesas,enable-bit = <5 0>, /* PCI INTA */ + <6 1>, /* PCI INTB */ + <7 2>, /* PCI INTC */ + <8 3>, /* PCI INTD */ + <9 4>, /* ATA */ + <10 5>, /* CF */ + <11 6>, /* Power Switch */ + <12 7>; /* Button */ + }; +}; + +&xtal { + clock-frequency = <22222222>; +}; + +&cpg { + renesas,mode = <5>; +}; + +&scif1 { + status = "okay"; +}; + +&pcic { + renesas,bcr1 = <0x00080000>; + renesas,config = <6 0xd0000000>; + renesas,mcrmask = <0x40000004>; + interrupt-map = <0x0000 0 0 1 &julianintc 5>, + <0x0000 0 0 2 &julianintc 6>, + <0x0000 0 0 3 &julianintc 7>, + <0x0000 0 0 4 &julianintc 8>, + <0x0800 0 0 1 &julianintc 6>, + <0x0800 0 0 2 &julianintc 7>, + <0x0800 0 0 3 &julianintc 8>, + <0x0800 0 0 4 &julianintc 5>, + <0x1000 0 0 1 &julianintc 7>, + <0x1000 0 0 2 &julianintc 8>, + <0x1000 0 0 3 &julianintc 5>, + <0x1000 0 0 4 &julianintc 6>; + interrupt-map-mask = <0x1800 0 0 7>; + status = "okay"; +}; From patchwork Tue Nov 14 08:00:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454945 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A865C4167B for ; Tue, 14 Nov 2023 08:01:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232330AbjKNIBW (ORCPT ); Tue, 14 Nov 2023 03:01:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232327AbjKNIBV (ORCPT ); Tue, 14 Nov 2023 03:01:21 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id F2803195 for ; Tue, 14 Nov 2023 00:01:17 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 6D0E11C0540; Tue, 14 Nov 2023 17:01:17 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rich Felker , John Paul Adrian Glaubitz , Geert Uytterhoeven , Magnus Damm Subject: [PATCH v4 32/37] sh: Add IO DATA USL-5P dts Date: Tue, 14 Nov 2023 17:00:23 +0900 Message-Id: <59c11b5e41d94b5b10e12fe5d8179adc0138a666.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org IO DATA DEVICE Inc. USL-5P devicetree. Signed-off-by: Yoshinori Sato --- arch/sh/boot/dts/usl-5p.dts | 84 +++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 arch/sh/boot/dts/usl-5p.dts diff --git a/arch/sh/boot/dts/usl-5p.dts b/arch/sh/boot/dts/usl-5p.dts new file mode 100644 index 000000000000..fba37472ebae --- /dev/null +++ b/arch/sh/boot/dts/usl-5p.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the IO DATA DEVICE USL-5P + */ + +/dts-v1/; + +#include "sh7751r.dtsi" + +/ { + model = "IO-DATA Device USL-5P"; + compatible = "iodata,usl-5p", "renesas,sh7751r"; + + aliases { + serial0 = &scif1; + }; + + chosen { + stdout-path = "serial0:9600n8"; + }; + + memory@c000000 { + device_type = "memory"; + reg = <0x0c000000 0x4000000>; + }; + + julianintc: sh7751irl_encoder@b0000005 { + compatible = "renesas,sh7751-irl-ext"; + reg = <0xb0000005 0x01>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + renesas,width = <8>; + renesas,enable-bit = <5 0>, /* PCI INTA */ + <6 1>, /* PCI INTB */ + <7 2>, /* PCI INTC */ + <8 3>, /* PCI INTD */ + <9 4>, /* ATA */ + <10 5>, /* CF */ + <11 6>, /* Power Switch */ + <12 7>; /* Button */ + }; + + compact-flash@b4000040 { + compatible = "iodata,usl-5p-ata", "ata-generic"; + reg = <0xb4000040 0x0e>, <0xb400002c 2>; + reg-shift = <1>; + interrupt-parent = <&julianintc>; + interrupts = <10>; + }; +}; + +&xtal { + clock-frequency = <22222222>; +}; + +&cpg { + renesas,mode = <5>; +}; + +&scif1 { + status = "okay"; +}; + +&pcic { + renesas,bcr1 = <0x00080000>; + renesas,config = <6 0xd0000000>; + renesas,mcrmask = <0x40000004>; + interrupt-map = <0x0000 0 0 1 &julianintc 5>, + <0x0000 0 0 2 &julianintc 6>, + <0x0000 0 0 3 &julianintc 7>, + <0x0000 0 0 4 &julianintc 8>, + <0x0800 0 0 1 &julianintc 6>, + <0x0800 0 0 2 &julianintc 7>, + <0x0800 0 0 3 &julianintc 8>, + <0x0800 0 0 4 &julianintc 5>, + <0x1000 0 0 1 &julianintc 7>, + <0x1000 0 0 2 &julianintc 8>, + <0x1000 0 0 3 &julianintc 5>, + <0x1000 0 0 4 &julianintc 6>; + interrupt-map-mask = <0x1800 0 0 7>; + status = "okay"; +}; From patchwork Tue Nov 14 08:00:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454946 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9BCDC072A2 for ; Tue, 14 Nov 2023 08:01:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232327AbjKNIBW (ORCPT ); Tue, 14 Nov 2023 03:01:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232328AbjKNIBV (ORCPT ); Tue, 14 Nov 2023 03:01:21 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id AE5C719E for ; Tue, 14 Nov 2023 00:01:18 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id D3DF81C0546; Tue, 14 Nov 2023 17:01:17 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rich Felker , John Paul Adrian Glaubitz , Geert Uytterhoeven , Magnus Damm Subject: [PATCH v4 33/37] sh: j2_mimas_v2.dts update Date: Tue, 14 Nov 2023 17:00:24 +0900 Message-Id: <21b24a80dd5847c234aa44b15f1684d0d6ceb0f5.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Signed-off-by: Yoshinori Sato --- arch/sh/boot/dts/j2_mimas_v2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/sh/boot/dts/j2_mimas_v2.dts b/arch/sh/boot/dts/j2_mimas_v2.dts index fa9562f78d53..5dfe20866a1c 100644 --- a/arch/sh/boot/dts/j2_mimas_v2.dts +++ b/arch/sh/boot/dts/j2_mimas_v2.dts @@ -16,7 +16,7 @@ cpus { cpu@0 { device_type = "cpu"; - compatible = "jcore,j2"; + compatible = "jcore,j2", "renesas,sh2"; reg = <0>; clock-frequency = <50000000>; d-cache-size = <8192>; From patchwork Tue Nov 14 08:00:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454947 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E92CC41535 for ; Tue, 14 Nov 2023 08:01:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232328AbjKNIBW (ORCPT ); Tue, 14 Nov 2023 03:01:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232329AbjKNIBW (ORCPT ); Tue, 14 Nov 2023 03:01:22 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 0EC2B195 for ; Tue, 14 Nov 2023 00:01:18 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 7A6151C0527; Tue, 14 Nov 2023 17:01:18 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rich Felker , John Paul Adrian Glaubitz Subject: [PATCH v4 34/37] sh: Add dtbs target support. Date: Tue, 14 Nov 2023 17:00:25 +0900 Message-Id: <07bc52ec3c6f27735bb2f95e8f6b02ad9d9dac2c.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Signed-off-by: Yoshinori Sato --- arch/sh/boot/dts/Makefile | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/sh/boot/dts/Makefile b/arch/sh/boot/dts/Makefile index 4a6dec9714a9..e6b93360c213 100644 --- a/arch/sh/boot/dts/Makefile +++ b/arch/sh/boot/dts/Makefile @@ -1,2 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_USE_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_SOURCE)) + +dtb-$(CONFIG_CPU_J2) += j2_mimas_v2.dtb +dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += landisk.dtb +dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += rts7751r2dplus.dtb +dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += usl-5p.dtb From patchwork Tue Nov 14 08:00:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454948 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0AEFC4332F for ; Tue, 14 Nov 2023 08:01:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232332AbjKNIBZ (ORCPT ); Tue, 14 Nov 2023 03:01:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232329AbjKNIBY (ORCPT ); Tue, 14 Nov 2023 03:01:24 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id CA18D195 for ; Tue, 14 Nov 2023 00:01:21 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id EAFA41C0559; Tue, 14 Nov 2023 17:01:20 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Rich Felker , John Paul Adrian Glaubitz , David Rientjes , Hyeonggon Yoo <42.hyeyoo@gmail.com>, Vlastimil Babka , Helge Deller Subject: [PATCH v4 35/37] sh: RTS7751R2D Plus OF defconfig Date: Tue, 14 Nov 2023 17:00:26 +0900 Message-Id: <80d77e4bfaf9ceb21ef2940362e488c4dde949eb.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Signed-off-by: Yoshinori Sato --- arch/sh/configs/rts7751r2dplus-of_defconfig | 93 +++++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 arch/sh/configs/rts7751r2dplus-of_defconfig diff --git a/arch/sh/configs/rts7751r2dplus-of_defconfig b/arch/sh/configs/rts7751r2dplus-of_defconfig new file mode 100644 index 000000000000..82019a233b6e --- /dev/null +++ b/arch/sh/configs/rts7751r2dplus-of_defconfig @@ -0,0 +1,93 @@ +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_NAMESPACES=y +CONFIG_EXPERT=y +CONFIG_PROFILING=y +CONFIG_CPU_SUBTYPE_SH7751R=y +CONFIG_MEMORY_START=0x0c000000 +CONFIG_SH_OF_BOARD=y +CONFIG_HEARTBEAT=y +CONFIG_ZERO_PAGE_OFFSET=0x00010000 +CONFIG_MODULES=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_IPV6 is not set +CONFIG_PCI=y +CONFIG_HOTPLUG_PCI=y +CONFIG_PCI_SH7751=y +CONFIG_UEVENT_HELPER=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_PHYSMAP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_SD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ATA=y +CONFIG_PATA_OF_PLATFORM=y +CONFIG_NETDEVICES=y +CONFIG_8139CP=y +CONFIG_8139TOO=y +# CONFIG_8139TOO_PIO is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_EARLYCON=y +CONFIG_HW_RANDOM=y +CONFIG_SPI=y +CONFIG_SPI_SH_SCI=y +CONFIG_MFD_SM501=y +CONFIG_FB=y +CONFIG_FB_SH_MOBILE_LCDC=m +CONFIG_FB_SM501=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +# CONFIG_LOGO_SUPERH_MONO is not set +# CONFIG_LOGO_SUPERH_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=m +CONFIG_SND_YMFPCI=m +CONFIG_HID_A4TECH=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_ITE=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_REDRAGON=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SUNPLUS=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_R9701=y +CONFIG_RENESAS_SH7751_INTC=y +CONFIG_RENESAS_SH7751IRL_INTC=y +CONFIG_EXT2_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_MINIX_FS=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_CRC_T10DIF=y +CONFIG_DEBUG_FS=y +# CONFIG_FTRACE is not set From patchwork Tue Nov 14 08:00:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454949 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C091C4332F for ; Tue, 14 Nov 2023 08:01:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232338AbjKNIB2 (ORCPT ); Tue, 14 Nov 2023 03:01:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59622 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232329AbjKNIB1 (ORCPT ); Tue, 14 Nov 2023 03:01:27 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 822CE19E for ; Tue, 14 Nov 2023 00:01:24 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 7FD4B1C053F; Tue, 14 Nov 2023 17:01:23 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Rich Felker , John Paul Adrian Glaubitz , "Jiri Slaby (SUSE)" , Geert Uytterhoeven , Hyeonggon Yoo <42.hyeyoo@gmail.com>, David Rientjes , Vlastimil Babka Subject: [PATCH v4 36/37] sh: LANDISK OF defconfig Date: Tue, 14 Nov 2023 17:00:27 +0900 Message-Id: <86981feb74e4c310fa5d29773630b88a1ca082bc.1699856600.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Signed-off-by: Yoshinori Sato --- arch/sh/configs/landisk-of_defconfig | 111 +++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) create mode 100644 arch/sh/configs/landisk-of_defconfig diff --git a/arch/sh/configs/landisk-of_defconfig b/arch/sh/configs/landisk-of_defconfig new file mode 100644 index 000000000000..406de7d7b8a2 --- /dev/null +++ b/arch/sh/configs/landisk-of_defconfig @@ -0,0 +1,111 @@ +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_NAMESPACES=y +CONFIG_EXPERT=y +CONFIG_KEXEC=y +CONFIG_CPU_SUBTYPE_SH7751R=y +CONFIG_MEMORY_START=0x0c000000 +CONFIG_SH_OF_BOARD=y +CONFIG_HEARTBEAT=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_PNP=y +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +CONFIG_ATALK=m +CONFIG_PCI=y +CONFIG_PCI_SH7751=y +CONFIG_PCCARD=y +CONFIG_YENTA=y +CONFIG_UEVENT_HELPER=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ATA=y +CONFIG_PATA_ARTOP=y +CONFIG_PATA_OF_PLATFORM=y +CONFIG_ATA_GENERIC=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_MD_LINEAR=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_NETDEVICES=y +CONFIG_TUN=m +CONFIG_8139CP=y +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_EARLYCON=y +CONFIG_HW_RANDOM=y +CONFIG_SOUND=m +CONFIG_HID_A4TECH=m +CONFIG_HID_BELKIN=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_EZKEY=m +CONFIG_HID_GYRATION=m +CONFIG_HID_ITE=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_REDRAGON=y +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SUNPLUS=m +CONFIG_USB_HID=m +CONFIG_USB=y +CONFIG_USB_MON=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_PRINTER=m +CONFIG_USB_STORAGE=m +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_SISUSBVGA=m +CONFIG_RENESAS_SH7751_INTC=y +CONFIG_RENESAS_SH7751IRL_INTC=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_REISERFS_FS=y +CONFIG_ISO9660_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=m +CONFIG_NTFS_RW=y +CONFIG_TMPFS=y +CONFIG_ROMFS_FS=y +CONFIG_UFS_FS=m +CONFIG_NFS_FS=m +CONFIG_NFSD=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_INIT_STACK_NONE=y +CONFIG_CRC_T10DIF=y +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_FTRACE is not set +CONFIG_SH_STANDARD_BIOS=y From patchwork Tue Nov 14 08:00:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13454950 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 356A6C4167D for ; Tue, 14 Nov 2023 08:01:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232329AbjKNIB2 (ORCPT ); Tue, 14 Nov 2023 03:01:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232336AbjKNIB2 (ORCPT ); Tue, 14 Nov 2023 03:01:28 -0500 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 549611A3 for ; Tue, 14 Nov 2023 00:01:25 -0800 (PST) Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id A5FBA1C058A; Tue, 14 Nov 2023 17:01:24 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Rich Felker , John Paul Adrian Glaubitz Subject: [PATCH v4 37/37] sh: j2_defconfig: update Date: Tue, 14 Nov 2023 17:00:28 +0900 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org I've changed some symbols related to DeviceTree, so let's take care of those changes. Signed-off-by: Yoshinori Sato --- arch/sh/configs/j2_defconfig | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/sh/configs/j2_defconfig b/arch/sh/configs/j2_defconfig index 2eb81ebe3888..cdc8ed244618 100644 --- a/arch/sh/configs/j2_defconfig +++ b/arch/sh/configs/j2_defconfig @@ -1,18 +1,15 @@ -CONFIG_SMP=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_CPU_SUBTYPE_J2=y CONFIG_MEMORY_START=0x10000000 -CONFIG_MEMORY_SIZE=0x04000000 CONFIG_CPU_BIG_ENDIAN=y -CONFIG_SH_DEVICE_TREE=y -CONFIG_SH_JCORE_SOC=y +CONFIG_SH_OF_BOARD=y CONFIG_HZ_100=y +CONFIG_SMP=y CONFIG_CMDLINE_OVERWRITE=y CONFIG_CMDLINE="console=ttyUL0 earlycon" -CONFIG_BINFMT_ELF_FDPIC=y CONFIG_BINFMT_FLAT=y CONFIG_NET=y CONFIG_PACKET=y @@ -21,7 +18,6 @@ CONFIG_INET=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_NETDEVICES=y -CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_UARTLITE=y CONFIG_SERIAL_UARTLITE_CONSOLE=y CONFIG_I2C=y @@ -30,8 +26,6 @@ CONFIG_SPI_JCORE=y CONFIG_WATCHDOG=y CONFIG_MMC=y CONFIG_MMC_SPI=y -CONFIG_CLKSRC_JCORE_PIT=y -CONFIG_JCORE_AIC=y CONFIG_EXT4_FS=y CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_IOCHARSET="ascii" @@ -40,3 +34,4 @@ CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_UTF8=y +CONFIG_INIT_STACK_NONE=y