From patchwork Tue Nov 14 22:58:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 13456094 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6FAC7C46CC7 for ; Tue, 14 Nov 2023 23:00:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C0CB210E403; Tue, 14 Nov 2023 23:00:30 +0000 (UTC) Received: from mail-qv1-xf36.google.com (mail-qv1-xf36.google.com [IPv6:2607:f8b0:4864:20::f36]) by gabe.freedesktop.org (Postfix) with ESMTPS id A707510E403 for ; Tue, 14 Nov 2023 23:00:28 +0000 (UTC) Received: by mail-qv1-xf36.google.com with SMTP id 6a1803df08f44-66d190a8f87so35999916d6.0 for ; Tue, 14 Nov 2023 15:00:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek.ca; s=google; t=1700002827; x=1700607627; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HCsm7VCedF16OrkkHsKZ3GlEGsmWacvBMw8jR+/V2pU=; b=aKDza6OOh4io8K8PVUqWuraHjXS6IynCGkqMx4lrvP5wjCqxWa77CE4P8YRaMQDPsp emqit4CiVBJBdMdGRzmmerGBaFzEr+qCF1twPQGhUBten2uCZ6xfq4joG7Sq2BcpScFQ ZII9Zt09b+yGD2uHZ6q2KI46V9I5pte4DLDU09ja9gT/KIEh26YM/yQ6zhH0CspregYc ViuKJyR0+dqlI6obIae4oDLZO9TF+7N5/zy2ivdsS1LavU6Xk0UcIhxhmZScwAxlUEtR HlJsQLrchZgrQGJMt1XwvSrVG/J84augZ4KyxiwpjVeNW1txnJa06Xicmu9clYZ9FCXq W6MQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700002827; x=1700607627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HCsm7VCedF16OrkkHsKZ3GlEGsmWacvBMw8jR+/V2pU=; b=mTwvM3mpDd0mVt4ZMqPumqgOLnNdYdJHuDMuHEUDdRAX/DmKcHrqwyc/MfgNulwAdp DezulwNXn82cgi4ijMg30drrxAH82IE+q3c/s6b+bnn94Gz5dMHM+rsMnJuVKUFz/46a RLQPKwsa9rUwxaBrj1ac2TuZ4gSQMKIq0bCr68lghKJ7mBsNoNH/IbM4Ut7ZAHTIIWn1 hCgwMPlpIlPJzGv7iNFTsdqwwjlPx+MXf1HjcPIy8tkFdQlQHdlPGNU6FwICDUPGuvyy T5JE8Yjh850LtzUo7t1UJejQAyI8qLvQf/892Gl0qO4Rz+aS9zoH7Z0wncBlkag9PLh7 kgzA== X-Gm-Message-State: AOJu0YymN0PGDvmtUvRSLOg4Pwy9QnaANJZWHjhpYLdO2WJSQTffdZVV 2HlYpspnvAcp6mjf5YeBQWyDgw== X-Google-Smtp-Source: AGHT+IGhxfGR9iFdmqeZtNyN8JXoHEt4QSyhdvoHgLMcAm8gIgPgRQ/R51UTcNkf5EfuQLRv6LpEbw== X-Received: by 2002:a0c:be88:0:b0:677:9fb2:26e9 with SMTP id n8-20020a0cbe88000000b006779fb226e9mr3489562qvi.14.1700002827707; Tue, 14 Nov 2023 15:00:27 -0800 (PST) Received: from localhost.localdomain (modemcable125.110-19-135.mc.videotron.ca. [135.19.110.125]) by smtp.gmail.com with ESMTPSA id u2-20020a05621411a200b00674a45499dcsm25274qvv.88.2023.11.14.15.00.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 15:00:27 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Subject: [PATCH v2 1/6] drm/msm/dpu: fix video mode DSC for DSI Date: Tue, 14 Nov 2023 17:58:29 -0500 Message-Id: <20231114225857.19702-2-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20231114225857.19702-1-jonathan@marek.ca> References: <20231114225857.19702-1-jonathan@marek.ca> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kalyan Thota , open list , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Abhinav Kumar , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Kuogee Hsieh , Konrad Dybcio , Jessica Zhang , Dmitry Baryshkov , Marijn Suijten , Vinod Polimera , Sean Paul , Arnaud Vrac Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add necessary DPU changes for DSC to work with DSI video mode. Note this changes the logic to enable HCTL to match downstream, it will now be enabled for the no-DSC no-widebus case. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 11 +++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 13 ++++++++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 1 + 5 files changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 1cf7ff6caff4..d745c8678b9d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2477,7 +2477,7 @@ enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder) return INTF_MODE_NONE; } -unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc) +unsigned int dpu_encoder_helper_get_dsc(const struct dpu_encoder_phys *phys_enc) { struct drm_encoder *encoder = phys_enc->parent; struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index 6f04c3d56e77..7e27a7da0887 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -332,7 +332,7 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( * used for this encoder. * @phys_enc: Pointer to physical encoder structure */ -unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc); +unsigned int dpu_encoder_helper_get_dsc(const struct dpu_encoder_phys *phys_enc); /** * dpu_encoder_helper_split_config - split display configuration helper function diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index a01fda711883..df10800a9615 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -100,6 +100,8 @@ static void drm_mode_to_intf_timing_params( } timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent); + if (dpu_encoder_helper_get_dsc(phys_enc)) + timing->compression_en = true; /* * for DP, divide the horizonal parameters by 2 when @@ -112,6 +114,15 @@ static void drm_mode_to_intf_timing_params( timing->h_front_porch = timing->h_front_porch >> 1; timing->hsync_pulse_width = timing->hsync_pulse_width >> 1; } + + /* + * for DSI, if compression is enabled, then divide the horizonal active + * timing parameters by compression ratio. + */ + if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) { + timing->width = timing->width / 3; /* XXX: don't assume 3:1 compression ratio */ + timing->xres = timing->width; + } } static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index e8b8908d3e12..d6fe45a6da2d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -166,10 +166,21 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, * video timing. It is recommended to enable it for all cases, except * if compression is enabled in 1 pixel per clock mode */ + if (!p->compression_en || p->wide_bus_en) + intf_cfg2 |= INTF_CFG2_DATA_HCTL_EN; + if (p->wide_bus_en) - intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN | INTF_CFG2_DATA_HCTL_EN; + intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN; data_width = p->width; + if (p->wide_bus_en && !dp_intf) + data_width = p->width >> 1; + + if (p->compression_en) + intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; + + if (p->compression_en && dp_intf) + DPU_ERROR("missing adjustments for DSC+DP\n"); hsync_data_start_x = hsync_start_x; hsync_data_end_x = hsync_start_x + data_width - 1; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h index c539025c418b..15a5fdadd0a0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -33,6 +33,7 @@ struct dpu_hw_intf_timing_params { u32 hsync_skew; bool wide_bus_en; + bool compression_en; }; struct dpu_hw_intf_prog_fetch { From patchwork Tue Nov 14 22:58:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 13456095 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 43895C46CC7 for ; Tue, 14 Nov 2023 23:00:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 79BDC10E404; Tue, 14 Nov 2023 23:00:35 +0000 (UTC) Received: from mail-qv1-xf2d.google.com (mail-qv1-xf2d.google.com [IPv6:2607:f8b0:4864:20::f2d]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2D9ED10E404 for ; Tue, 14 Nov 2023 23:00:33 +0000 (UTC) Received: by mail-qv1-xf2d.google.com with SMTP id 6a1803df08f44-67131800219so36473026d6.3 for ; Tue, 14 Nov 2023 15:00:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek.ca; s=google; t=1700002832; x=1700607632; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w/GFqO4G/MklaH9jw4JV/Pzz1KPVstRySwUanh5xWC0=; b=g3M4RqkLjuhZ10uqJARdmTzHtANaeZp9p5r8ct/dPxgv+Wk+MSLqdIaQCN7NQqDgh3 blq40+OIJbxCqB22b6qcw9PbeY+E7fjYKQgxHbOl9V4YYkxaWO/+OmuU7FNnJstIDy5d L0f4nPIvfm52LdScvNTisydRv+nO6ekfkMyJx6mPgd0S7AN85451XkrzS6QugJUV4e+z wGjSi09pDp6fGx0dq/Q2qHxscUuwjgu/yxcPOWZmz7GgNi5/fpanGyrL+QOXHEu6p8+C hc0bRVD1bYWVJaHvsAqBf4HMu369ghHdLaz4ByEhmFMZNdtKu5SJh/01LvwGcauJnBi0 uj/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700002832; x=1700607632; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w/GFqO4G/MklaH9jw4JV/Pzz1KPVstRySwUanh5xWC0=; b=R6y74Ld0njdatrsMWUxVjzEEu9yRl0rOGHkwjDwawM3/2iFOqSHfpnfIMguYZWUMfG +XQvYlRtAydcyzoMDKXnb4h+5lMe/zk0K+OsuAYNomx5WpTI34ezKIu1i0rjyfXDEOjh mTdZN+X18H/HC51wVBNi0KtmUFPp+eObX/4/0HT4zq1URqQxd/wdPTmjZg44iDSarSDg cSzXZ3aP/IxXHQvEO4hlEAQz+mLLtjA1ivZGCzDdWoGXOVwKmdKt/QQM0cyJjMQPjITA zmehOWdct9O9LPnewVfEhiAmeP3ajkSj8Pq4tlHcbUBYH8MAI0jtwPNorKMYtY8n4YT/ RdLA== X-Gm-Message-State: AOJu0Yx8EOcSllg+rkt5B3oAFRXtCFd60NOQZSLkCbPsU69YSdyd8EiF F2UcWrxV1YZhynTh691k2B2VKQ== X-Google-Smtp-Source: AGHT+IGs8pOHCMY63Ix8FFyLk36FFEv+XiIXC0agrgFQ+oxUKW/tRhs6EBRxYa3gRpVrFgUGoNzaIw== X-Received: by 2002:ad4:5987:0:b0:677:a0a5:c226 with SMTP id ek7-20020ad45987000000b00677a0a5c226mr3522207qvb.19.1700002832113; Tue, 14 Nov 2023 15:00:32 -0800 (PST) Received: from localhost.localdomain (modemcable125.110-19-135.mc.videotron.ca. [135.19.110.125]) by smtp.gmail.com with ESMTPSA id u2-20020a05621411a200b00674a45499dcsm25274qvv.88.2023.11.14.15.00.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 15:00:31 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Subject: [PATCH v2 2/6] drm/msm/dsi: set video mode widebus enable bit when widebus is enabled Date: Tue, 14 Nov 2023 17:58:30 -0500 Message-Id: <20231114225857.19702-3-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20231114225857.19702-1-jonathan@marek.ca> References: <20231114225857.19702-1-jonathan@marek.ca> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:DRM DRIVER FOR MSM ADRENO GPU" , Jiasheng Jiang , Abhinav Kumar , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list , Konrad Dybcio , Jessica Zhang , Dmitry Baryshkov , Marijn Suijten , Sean Paul Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The value returned by msm_dsi_wide_bus_enabled() doesn't match what the driver is doing in video mode. Fix that by actually enabling widebus for video mode. Fixes: efcbd6f9cdeb ("drm/msm/dsi: Enable widebus for DSI") Signed-off-by: Jonathan Marek Reviewed-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Reviewed-by: Jessica Zhang --- drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 + drivers/gpu/drm/msm/dsi/dsi_host.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h index 2a7d980e12c3..f0b3cdc020a1 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h @@ -231,6 +231,7 @@ static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val) #define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000 #define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000 #define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000 +#define DSI_VID_CFG0_DATABUS_WIDEN 0x02000000 #define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000 #define REG_DSI_VID_CFG1 0x0000001c diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index deeecdfd6c4e..f2c1cbd08d4d 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -745,6 +745,8 @@ static void dsi_ctrl_enable(struct msm_dsi_host *msm_host, data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); + if (msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) + data |= DSI_VID_CFG0_DATABUS_WIDEN; dsi_write(msm_host, REG_DSI_VID_CFG0, data); /* Do not swap RGB colors */ From patchwork Tue Nov 14 22:58:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 13456096 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5E00BC46CC7 for ; Tue, 14 Nov 2023 23:00:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 68D8D10E405; Tue, 14 Nov 2023 23:00:38 +0000 (UTC) Received: from mail-qv1-xf30.google.com (mail-qv1-xf30.google.com [IPv6:2607:f8b0:4864:20::f30]) by gabe.freedesktop.org (Postfix) with ESMTPS id E8E4210E4C9 for ; Tue, 14 Nov 2023 23:00:35 +0000 (UTC) Received: by mail-qv1-xf30.google.com with SMTP id 6a1803df08f44-6705379b835so37069596d6.1 for ; Tue, 14 Nov 2023 15:00:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek.ca; s=google; t=1700002835; x=1700607635; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3bXNM4Q60WzU91mEPZf4VyqZpLI234VBPPnXZJAmol4=; b=ZcSNWng+1qS+yVfnLfo1DHZ/T9autJXP2CXxE4co7Hm4QBLAx29umyjVpeox5A9Swg ZfJOI1eOVo4knDa1o+uTuWNKF5Qh0QNDbhZO93pPgBGmX4TzS6t6sZlLBw0LBxIC/pa1 GMEA7y2CPrJTSvhwAgfbXnzTGxrD5GboTnrojlJTRKdqyrXp3zj+0Gf92HMUcoE2cBzR 3SHnGAE2k1/d14NSemo64sgkdInAHozjv9bJ/jNd/N7l4JIVsV8V7H3Braoz50NWqnnQ GpsddM39qLzklgeSGsQpvTzBrhFYaXFDMkxnbTv8IVrH++nfzFeZds/Qfro1Zga4lwAv DfzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700002835; x=1700607635; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3bXNM4Q60WzU91mEPZf4VyqZpLI234VBPPnXZJAmol4=; b=BSNDgBbqkiV8zcdUwDEn0nmyUA1ukyknGtgp3rRlBo23oFP4HbYwq93WXJpFi4daGw mUFmZPdPY4SqMLKuGQpeKgLPoQNJkOUILyFw9GvMDfKyPWXG9wWbdJkEI/Pml7smE8xk hEVXa38CfsHZewAOB9o9H5dOMVxJfipGPHaf9m/Y/4/NwXNdCtSSMLdw12Sz386bIpWS zqggBjlXdMv1jZEoqD+qJf/KaE0q0QB500a2U4yHDcH3FdQaXIFsfK+m5AMxmR5H4/55 UrJwTN3MDSq2GItX2UE6z5M7an+7bhYvN8DNhkKp66nx4TD5bh2wCx/e0taUzpTW74bv 1IMg== X-Gm-Message-State: AOJu0YxEuE7Hd7IhLDQyy9a24fotozWUbRZbEYGd5k4hAmFreUIZ5UX+ 7jDACWv37OOz2HB4p3iqnhklNA== X-Google-Smtp-Source: AGHT+IHCQG3eL93xOKOvyP2tHydGdXl7lNnMKJaAkchLjAmxahJp9qdvYkmh1PrCIEgA8PmuVIkUJA== X-Received: by 2002:ad4:544b:0:b0:677:af51:da43 with SMTP id h11-20020ad4544b000000b00677af51da43mr3858770qvt.0.1700002834910; Tue, 14 Nov 2023 15:00:34 -0800 (PST) Received: from localhost.localdomain (modemcable125.110-19-135.mc.videotron.ca. [135.19.110.125]) by smtp.gmail.com with ESMTPSA id u2-20020a05621411a200b00674a45499dcsm25274qvv.88.2023.11.14.15.00.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 15:00:34 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Subject: [PATCH v2 3/6] drm/msm/dsi: set VIDEO_COMPRESSION_MODE_CTRL_WC (fix video mode DSC) Date: Tue, 14 Nov 2023 17:58:31 -0500 Message-Id: <20231114225857.19702-4-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20231114225857.19702-1-jonathan@marek.ca> References: <20231114225857.19702-1-jonathan@marek.ca> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vinod Koul , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Jiasheng Jiang , Abhinav Kumar , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list , Konrad Dybcio , Jessica Zhang , Dmitry Baryshkov , Marijn Suijten , Sean Paul Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Video mode DSC won't work if this field is not set correctly. Set it to fix video mode DSC (for slice_per_pkt==1 cases at least). Fixes: 08802f515c3 ("drm/msm/dsi: Add support for DSC configuration") Signed-off-by: Jonathan Marek Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_host.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index f2c1cbd08d4d..66f198e21a7e 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -849,6 +849,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod u32 slice_per_intf, total_bytes_per_intf; u32 pkt_per_line; u32 eol_byte_num; + u32 bytes_per_pkt; /* first calculate dsc parameters and then program * compress mode registers @@ -856,6 +857,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay); total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; + bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */ eol_byte_num = total_bytes_per_intf % 3; @@ -893,6 +895,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl); dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); } else { + reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(bytes_per_pkt); dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); } } From patchwork Tue Nov 14 22:58:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 13456097 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 735D8C46CC7 for ; Tue, 14 Nov 2023 23:00:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C5D7610E4C9; Tue, 14 Nov 2023 23:00:42 +0000 (UTC) Received: from mail-yw1-x112a.google.com (mail-yw1-x112a.google.com [IPv6:2607:f8b0:4864:20::112a]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9610210E409 for ; Tue, 14 Nov 2023 23:00:38 +0000 (UTC) Received: by mail-yw1-x112a.google.com with SMTP id 00721157ae682-5a81ab75f21so71371457b3.2 for ; Tue, 14 Nov 2023 15:00:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek.ca; s=google; t=1700002838; x=1700607638; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cpJg20SvqJHFde7hdRwbQhfmXK7eKDJA+6y+igvktAk=; b=Ws2GeoH854bwBmXOGv8LdesCm95OB4rjk9W3/zOf6d46JmO3X9J/buVCWGpnYmGhg3 ESDV6u6PYwRCq41rhSqyem6GPUbtkahv+Tyxvd0AECahNaUU4N5j9bKRVd2nEuvcLn2c jBHemnEVHpCg0VIhwGNLqTaQILnhbVk7hY2OFyLzpE7H8odHvabYxc3KneyOzGwt4Qea 4pZyDi+DPhIkJxENCJ08sdSd2LEgXBA93Z9aG1GiY/JbzlXslEt3k3m4qhPqrOOBL6T6 vbi4+JvHGO5tK2hUeKAElKJlntbHoIsTOQZFJGCLgko+gCPodXlE6MfTS6IB4PLF7nSX AY8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700002838; x=1700607638; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cpJg20SvqJHFde7hdRwbQhfmXK7eKDJA+6y+igvktAk=; b=fa3NHjC9ypjc9D7qygQGYNV/PSylppHvBYOHyFO4dhoN1WkktorODheHY06eB+O1gS 8xgoos8H5pxDJMPvTO8f5Yllo6LxITCGEp9GjbH5lA2lcNelfrJYQgcvLNvysrDnHN2Z rwTv38XRyYT0SifsK/OhU5QPaQyyPJ4cuQHXvlxslx9SYu+9etE0PtVxJ/UyjcypRDF/ PzHeZF6Qzp6BQSqJ0d0++HcFrhmSbarFs4pAM53CiZ+E51dmra3TcQTsdoll7NCZq9G/ dOJbCsLqoZFDfPrVb5tmEWSWxxDWJ8tl1kt4IEfo3STSLX8BpfVu3v4hjRl5xdsgvTMq CIbA== X-Gm-Message-State: AOJu0Yy9HxpqRfreoVE4pNfgvVO3Q826tyZu1/xD8uwQK5m7FAVSSlCD FYfKujhYVHSY1aaKgkykcZbb3g== X-Google-Smtp-Source: AGHT+IF625S3cBQuZUFbUGBAhZkGCmiGu+ZC9noNuDSK6oc2pQ7dDTxwb4mFW7Ih4VTIW4LqjLUQKA== X-Received: by 2002:a0d:ca84:0:b0:5a7:bfbf:1bbb with SMTP id m126-20020a0dca84000000b005a7bfbf1bbbmr11185827ywd.17.1700002837716; Tue, 14 Nov 2023 15:00:37 -0800 (PST) Received: from localhost.localdomain (modemcable125.110-19-135.mc.videotron.ca. [135.19.110.125]) by smtp.gmail.com with ESMTPSA id u2-20020a05621411a200b00674a45499dcsm25274qvv.88.2023.11.14.15.00.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 15:00:37 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Subject: [PATCH v2 4/6] drm/msm/dsi: add a comment to explain pkt_per_line encoding Date: Tue, 14 Nov 2023 17:58:32 -0500 Message-Id: <20231114225857.19702-5-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20231114225857.19702-1-jonathan@marek.ca> References: <20231114225857.19702-1-jonathan@marek.ca> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:DRM DRIVER FOR MSM ADRENO GPU" , Jiasheng Jiang , Abhinav Kumar , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list , Konrad Dybcio , Jessica Zhang , Dmitry Baryshkov , Marijn Suijten , Sean Paul Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Make it clear why the pkt_per_line value is being "divided by 2". Signed-off-by: Jonathan Marek Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_host.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 66f198e21a7e..842765063b1b 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -877,6 +877,8 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE * registers have similar offsets, so for below common code use * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits + * + * pkt_per_line is log2 encoded, >>1 works for supported values (1,2,4) */ reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1); reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num); From patchwork Tue Nov 14 22:58:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 13456098 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5E0C0C46CA6 for ; Tue, 14 Nov 2023 23:00:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 90BD610E4E1; Tue, 14 Nov 2023 23:00:43 +0000 (UTC) Received: from mail-yw1-x1134.google.com (mail-yw1-x1134.google.com [IPv6:2607:f8b0:4864:20::1134]) by gabe.freedesktop.org (Postfix) with ESMTPS id C2D0E10E4C9 for ; Tue, 14 Nov 2023 23:00:41 +0000 (UTC) Received: by mail-yw1-x1134.google.com with SMTP id 00721157ae682-5a7dd65052aso72678297b3.0 for ; Tue, 14 Nov 2023 15:00:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek.ca; s=google; t=1700002841; x=1700607641; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QnYJwckhVUb/hQ+VqWd+HwwnYfkR02viqwW11QKBHpA=; b=TI7uKmsJ6YQ9l0IPa8acb1XFL2xqmXbCs6+t764hYCK0nZZEoRomhFtFhcq9QW6kUA 5vZYPoa8g5/3QTqzWhjfAVXMZhjlFQdAVCLC5UBLMp45Q5FPZ4l4eghjev+LvQ0MdLgF EUWP2BoWprLpH0Dp+x1k7wa1sSfzkyP8f+MZA+SpljCIQZqWVYw3K3rCpNebzLQ7rcny Z0TEG8E0WFFmtEX+qmwsRRUR1njoJBZUVxTsarW0EN9ciXgDyW76jVKjLDAnBYopASsM XrRuL0cWiVkzsVULzy5qNFTVi58cqGy71yCJa79HsdiJZOZcrr4MKXi8u3spmVqkzFD+ FTCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700002841; x=1700607641; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QnYJwckhVUb/hQ+VqWd+HwwnYfkR02viqwW11QKBHpA=; b=Kv5h5560UGg4BOQi1OtpFuZHQyko1SxwkooHNnr1IhY9yK/APC4DFVvlaHGwWxsVaA tzAXxEUC2vGjONlKce9OcdNBfHBMbSnJKujiOlzDxrn10YpnDPp045dcJi1tkhxbHKzz 8qY+D7d8Tu+k/RjtddH9EUh3WWddcnnwO2Fi0gRr+jCP1KKfAx36EUJI+mmliagPqVb8 w49EX6DIdyrgOYn643Z5B/9LLA7d4jwZ2/sUcKKjt4gz0wMxHc8yIMGSOQV7wiYgLsYP LfuIasgzn6+2ucZOUtWj2ErlbJHQzP45aVA/n/k/trEJHZ6LyXUHgKT2Iv7Qv0vBoReI 1dVA== X-Gm-Message-State: AOJu0YzzfOxNOz9DxmLVh/KZF+zmN3SbouNLwafWxMoirJzxa0bwd9MK AUXIbOislSAjMwsSpd+qJdArFg== X-Google-Smtp-Source: AGHT+IF5YfJuojzCU5ZWpyNCZKZW27YiSBpBSE/rs8E1m68mg6G6/rODESlNkQJ5KMcm5C8qahqevA== X-Received: by 2002:a81:5241:0:b0:5be:94a6:d919 with SMTP id g62-20020a815241000000b005be94a6d919mr12307437ywb.25.1700002840841; Tue, 14 Nov 2023 15:00:40 -0800 (PST) Received: from localhost.localdomain (modemcable125.110-19-135.mc.videotron.ca. [135.19.110.125]) by smtp.gmail.com with ESMTPSA id u2-20020a05621411a200b00674a45499dcsm25274qvv.88.2023.11.14.15.00.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 15:00:40 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Subject: [PATCH v2 5/6] drm/msm/dsi: support DSC configurations with slice_per_pkt > 1 Date: Tue, 14 Nov 2023 17:58:33 -0500 Message-Id: <20231114225857.19702-6-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20231114225857.19702-1-jonathan@marek.ca> References: <20231114225857.19702-1-jonathan@marek.ca> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Zimmermann , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Jiasheng Jiang , Abhinav Kumar , Maxime Ripard , open list , Konrad Dybcio , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Jessica Zhang , Dmitry Baryshkov , Marijn Suijten , Sean Paul Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a dsc_slice_per_pkt field to mipi_dsi_device struct and the necessary changes to msm driver to support this field. Note that the removed "pkt_per_line = slice_per_intf * slice_per_pkt" comment is incorrect. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/dsi/dsi_host.c | 25 ++++++++++--------------- include/drm/drm_mipi_dsi.h | 1 + 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 842765063b1b..892a463a7e03 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -161,6 +161,7 @@ struct msm_dsi_host { struct drm_display_mode *mode; struct drm_dsc_config *dsc; + unsigned int dsc_slice_per_pkt; /* connected device info */ unsigned int channel; @@ -857,17 +858,10 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay); total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; - bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */ + bytes_per_pkt = dsc->slice_chunk_size * msm_host->dsc_slice_per_pkt; eol_byte_num = total_bytes_per_intf % 3; - - /* - * Typically, pkt_per_line = slice_per_intf * slice_per_pkt. - * - * Since the current driver only supports slice_per_pkt = 1, - * pkt_per_line will be equal to slice per intf for now. - */ - pkt_per_line = slice_per_intf; + pkt_per_line = slice_per_intf / msm_host->dsc_slice_per_pkt; if (is_cmd_mode) /* packet data type */ reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE); @@ -1004,12 +998,8 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) else /* * When DSC is enabled, WC = slice_chunk_size * slice_per_pkt + 1. - * Currently, the driver only supports default value of slice_per_pkt = 1 - * - * TODO: Expand mipi_dsi_device struct to hold slice_per_pkt info - * and adjust DSC math to account for slice_per_pkt. */ - wc = msm_host->dsc->slice_chunk_size + 1; + wc = msm_host->dsc->slice_chunk_size * msm_host->dsc_slice_per_pkt + 1; dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | @@ -1636,8 +1626,13 @@ static int dsi_host_attach(struct mipi_dsi_host *host, msm_host->lanes = dsi->lanes; msm_host->format = dsi->format; msm_host->mode_flags = dsi->mode_flags; - if (dsi->dsc) + if (dsi->dsc) { msm_host->dsc = dsi->dsc; + msm_host->dsc_slice_per_pkt = dsi->dsc_slice_per_pkt; + /* for backwards compatibility, assume 1 if not set */ + if (!msm_host->dsc_slice_per_pkt) + msm_host->dsc_slice_per_pkt = 1; + } /* Some gpios defined in panel DT need to be controlled by host */ ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev); diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index c9df0407980c..3e32fa52d94b 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -193,6 +193,7 @@ struct mipi_dsi_device { unsigned long hs_rate; unsigned long lp_rate; struct drm_dsc_config *dsc; + unsigned int dsc_slice_per_pkt; }; #define MIPI_DSI_MODULE_PREFIX "mipi-dsi:" From patchwork Tue Nov 14 22:58:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 13456099 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6FB1AC46CC7 for ; Tue, 14 Nov 2023 23:00:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D9F5510E4E4; Tue, 14 Nov 2023 23:00:51 +0000 (UTC) Received: from mail-vk1-xa30.google.com (mail-vk1-xa30.google.com [IPv6:2607:f8b0:4864:20::a30]) by gabe.freedesktop.org (Postfix) with ESMTPS id 63FDB10E409 for ; Tue, 14 Nov 2023 23:00:48 +0000 (UTC) Received: by mail-vk1-xa30.google.com with SMTP id 71dfb90a1353d-4af6a700087so1302308e0c.0 for ; Tue, 14 Nov 2023 15:00:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek.ca; s=google; t=1700002847; x=1700607647; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YR/mkTlXJRgIJS/EJMZQRz4ww5S2W5Npa8fLQfW52YM=; b=IwT/9jn/dhF+WDrtmcTwKNaQczreaUADV7nNS70BY6ikvuY6LVPKCxDrAEYurVOb94 LXAdZR8E7fl8c3WBd2RPFDUbEF25hK0VVw/fxbxZS/uS1LJEelFFghtEw6qw5D505ZsM G++LQI3iayFJWnLLqt3kgkyR2MRfhz3OE+nvmgc/kfbWRpCaq3kW9alF/MWMb5ytr6Xd ZK8zswq4DZ+mvB+uzyj5J3f5C/6C4dXzJdD8mFI4A2pXqWkxghECeu/9wqIemPVDSfw/ ey5eAxKPHBdVoOYNGYq2s5mW/jtUcjXDGUn6KD+Akk1jPraLs0T0zPJ9RZ7qvhEwVIz2 sgBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700002847; x=1700607647; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YR/mkTlXJRgIJS/EJMZQRz4ww5S2W5Npa8fLQfW52YM=; b=TdEqjcekujOxgD9RkcgqglJxrT5WQf9Sy1kn85PcK4iRdiU5w1wNlSY6vm3IfPukL5 QAiXNIqQOZZUyRCKMpp4Z1P/6g2qmWB6FMmqQh2jFxO7IxbwXzmbTwca8IFR06mYcJDH aIxuAklutKSbr8ozYh2PmmKO4Z0v8mjYctZHgJu14T+kQ4hAKhfnxzWoLiJnwXluZqjF Yn1sL0gijzrPjen7IFfMgOgtzgFw9+YO1B+8LqPu7Yb2mtb6LVIpEgRgoS4wV4YNmThX mRhLeSwQvoKBOovY0SnXu72wjjuZ6Wfdx/r+p9Q/Uy1ZW305BP8lUrPuGEa3E4c69USg FNcQ== X-Gm-Message-State: AOJu0YzGR0YwOXbxJ6HQ4cOQek2DvZIfs0oNs7kpRsQiup6mVn15d0yz tNznvnHNfTZ5XMK+KQ25l3YHLw== X-Google-Smtp-Source: AGHT+IGEipMZ0wWdCFEW37YaqFstmZB087eBM8BroWKdjsRAujSSep+py5so9+Y1GvtCk8GaGlxZ6A== X-Received: by 2002:a67:e002:0:b0:45d:8f83:e10f with SMTP id c2-20020a67e002000000b0045d8f83e10fmr10524052vsl.4.1700002847082; Tue, 14 Nov 2023 15:00:47 -0800 (PST) Received: from localhost.localdomain (modemcable125.110-19-135.mc.videotron.ca. [135.19.110.125]) by smtp.gmail.com with ESMTPSA id u2-20020a05621411a200b00674a45499dcsm25274qvv.88.2023.11.14.15.00.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 15:00:46 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Subject: [PATCH v2 6/6] drm/msm/dsi: fix DSC for the bonded DSI case Date: Tue, 14 Nov 2023 17:58:34 -0500 Message-Id: <20231114225857.19702-7-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20231114225857.19702-1-jonathan@marek.ca> References: <20231114225857.19702-1-jonathan@marek.ca> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:DRM DRIVER FOR MSM ADRENO GPU" , Jiasheng Jiang , Abhinav Kumar , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Doug Anderson , Konrad Dybcio , Jessica Zhang , Dmitry Baryshkov , Marijn Suijten , Sean Paul , open list Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" For the bonded DSI case, DSC pic_width and timing calculations should use the width of a single panel instead of the total combined width. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/dsi/dsi.h | 3 ++- drivers/gpu/drm/msm/dsi/dsi_host.c | 20 +++++++++++--------- drivers/gpu/drm/msm/dsi/dsi_manager.c | 2 +- 3 files changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 28379b1af63f..3a641e69447c 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -93,7 +93,8 @@ int msm_dsi_host_power_off(struct mipi_dsi_host *host); int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, const struct drm_display_mode *mode); enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, - const struct drm_display_mode *mode); + const struct drm_display_mode *mode, + bool is_bonded_dsi); unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host); int msm_dsi_host_register(struct mipi_dsi_host *host); void msm_dsi_host_unregister(struct mipi_dsi_host *host); diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 892a463a7e03..cf06736e5a60 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -940,8 +940,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) mode->hdisplay, mode->vdisplay); return; } - - dsc->pic_width = mode->hdisplay; + dsc->pic_width = hdisplay; dsc->pic_height = mode->vdisplay; DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); @@ -952,6 +951,11 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) if (ret) return; + if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) + dsi_update_dsc_timing(msm_host, false, hdisplay); + else + dsi_update_dsc_timing(msm_host, true, hdisplay); + /* Divide the display by 3 but keep back/font porch and * pulse width same */ @@ -968,9 +972,6 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) } if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { - if (msm_host->dsc) - dsi_update_dsc_timing(msm_host, false, mode->hdisplay); - dsi_write(msm_host, REG_DSI_ACTIVE_H, DSI_ACTIVE_H_START(ha_start) | DSI_ACTIVE_H_END(ha_end)); @@ -989,9 +990,6 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); } else { /* command mode */ - if (msm_host->dsc) - dsi_update_dsc_timing(msm_host, true, mode->hdisplay); - /* image data and 1 byte write_memory_start cmd */ if (!msm_host->dsc) wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; @@ -2479,7 +2477,8 @@ int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, } enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, - const struct drm_display_mode *mode) + const struct drm_display_mode *mode, + bool is_bonded_dsi) { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); struct drm_dsc_config *dsc = msm_host->dsc; @@ -2489,6 +2488,9 @@ enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, if (!msm_host->dsc) return MODE_OK; + if (is_bonded_dsi) + pic_width = mode->hdisplay / 2; + if (pic_width % dsc->slice_width) { pr_err("DSI: pic_width %d has to be multiple of slice %d\n", pic_width, dsc->slice_width); diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 896f369fdd53..2ca1a7ca3659 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -455,7 +455,7 @@ static enum drm_mode_status dsi_mgr_bridge_mode_valid(struct drm_bridge *bridge, return MODE_ERROR; } - return msm_dsi_host_check_dsc(host, mode); + return msm_dsi_host_check_dsc(host, mode, IS_BONDED_DSI()); } static const struct drm_bridge_funcs dsi_mgr_bridge_funcs = {