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Y. Srinivasan" , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hyperv@vger.kernel.org, linux-mips@vger.kernel.org, linux-riscv@lists.infradead.org, linux-snps-arc@lists.infradead.org, linux-tegra@vger.kernel.org, Russell King , Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Palmer Dabbelt , patches@lists.linux.dev, Paul Walmsley , "Rafael J. Wysocki" , Robert Moore , Rob Herring , Robin Murphy , Sudeep Holla , Suravee Suthikulpanit , Sven Peter , Thierry Reding , Thomas Bogendoerfer , Krishna Reddy , Vineet Gupta , virtualization@lists.linux.dev, Wei Liu , Will Deacon Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , Lu Baolu , Christoph Hellwig , Jerry Snitselaar , Moritz Fischer , Zhenhua Huang , "Rafael J. Wysocki" , Rob Herring Subject: [PATCH v2 01/17] iommu: Remove struct iommu_ops *iommu from arch_setup_dma_ops() Date: Wed, 15 Nov 2023 10:05:52 -0400 Message-ID: <1-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> In-Reply-To: <0-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR15CA0030.namprd15.prod.outlook.com (2603:10b6:208:1b4::43) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|SJ0PR12MB7007:EE_ X-MS-Office365-Filtering-Correlation-Id: 529d66cd-e412-498d-4a9f-08dbe5e40483 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0gCY+Ym8EtLaXF0idmv8eBZsOt0ZR2YAsRF660hQrp3EIl0O6FwmkLEeAzh9gegD1+OZViyptSfLDyCVZ8826Rth4QZlWhd+DnRy4kP/CuhXiDB/QZQEINH480RqnKTQff7ttp4NOtw0+5IH1aXRIRuBom3NfUm0fJatj6B3CfHOcHYbKJS4GyFdNVzfQN3vSNPD73aZ73Ja4Vg76QdBaKMKcCu9lL43i75SRNA0dzF3vzMJMIev0UA3oNh4A4tCyH96r7y9lKRLKfS/a1DR1KjkmfbcbaAfeK7IAPKW+1RZ4sG9wcejEwIVqFiG0QoFDhO8RL4navaXuJTgiApDtTTBt3Y+gpr8XhFXgOiwqlGwMuKKOt5wqFF3oLdtOcBMhCaNU54UJwiIiGne4QlSWd8hLLOX3oDmFyaqcOKHYHqfinluOSfKLc9qEGQLjLqIArX0J2CYFy5OmbRN2aeQeKOn+4/aM48mFhxw44hEamovQnxVB/150REIRW3RGxu4eSmTRTkx75rOmbkT+3wtG8IYfMbBhbB3r07nGac0dRDwPhC5wjsBQrbV2IFsOUK3tB0FOTYx5zK0mM2RyDjTw86EkkSUj4Td872gA/iE+ESsdJcPJeje9OhZyLXbsHHW X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(136003)(346002)(376002)(366004)(39860400002)(396003)(230922051799003)(451199024)(1800799009)(186009)(64100799003)(7406005)(6666004)(6506007)(2616005)(6512007)(83380400001)(7416002)(41300700001)(8676002)(5660300002)(4326008)(7366002)(8936002)(478600001)(2906002)(6486002)(66476007)(54906003)(110136005)(66946007)(66556008)(316002)(86362001)(36756003)(38100700002)(26005)(921008)(66899024)(4216001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: zxicClb42zqzzbk5CRq5SS7TF8hlGviEoIfKZmp6AgFTjqC5x1+eWNO5F+1WnS3wdz01ItY/EugCvFGcRQAu2TC2IbZ4m2ZBtfZ2Zm5lF2CHVtyXeisYO8kjjLF8ENUZKTnoWSesByLNpqwHpEoMgodKMg0CaXWMGnEEdi4YhhkqhHB7p5+GTXTrYN6VEX3wVMXKyihQ/MtJoGJfOWya6V01IYIHASaskSfSsKHxHYCwDc2/KqqTVJpHd8Kwx6qcRKtwCOKNRM69hfeFDL35sk1QpHLTsjtiWetB0IpMXPyWj+q6u7UUD7aB0ZFmBJRusUov6Mh/kw7H06Q1Blbhstp26d07pYLnoGJkv/VR42IHhV9YKu8UO+PlbRmXO3s7FAydcESyMPVf468UnVSKXIR9f/5kd10JFa4o6Sra1Dkoj/gWIQBu/kjHHpZ0Q4pnRRztX0TP4oNDu1g4hWIavPT9ZAlx8qnYuvSemJ2FR44oJLXomAv/XS9AOJ2XRBEL77o/OF72yDBbSAfd6aH6RT6BQ7iO1f8Vsv6U/QwNsX6FaDaEgccTjlXFtYWXGt7nfrxbBarmWGANR+fvKsI9pO26STUhuPiOjT7WEQsty6ynUQVF2MJmUDjorDz4tfJHmzKwKQBGyL5kH+c87usv0T/UrOFsq1PSkaiywEHKrTqCDc08IVc3dwCfrAGGMy1/xtrBAR01ZtZ5e1DcB1zX/EyApueplcWvJc7KoCD8T+Ckhi+r9LtsZjj9XK9Y5sEiTLbp1Y1TCuN8w/PEjz6AOblp3G6PvhA7rj7jeAUskLYxAbffGqdJUluIAbu5mU6qGA1eZastn019VYVA/Ksw878amMLRS+OEpcSTHR8Pk6UlZgR59rhhITaco7ETJ/LBL3zpPubBxuF5rRm4hbjuv5Tr5bGDAXsNYq4Xt9/DDemMUu4vvB3qIko0cVLIYWpF7RLiFIOypmYYOfUqCu7VauGdWITuHs93PyQAKT5Y+mwTRIIRGi2wrCobmY3LVbAvjZniYQWgOBLrEzlsoKDEmZCJAUBjH4oFHwwMBlWvJ6xrtAncye6pdUn8QRdZREplARwrBiioqwZPeWo4NjT3lWJ5++7V3yIWez5SZ5buENfpg8riphhQ8NeR7rR9wgK8+cqEPR4cfeC6wnU6ProrTmBzgBnYhuc+cos4h+Q7zRDvieuTEFyV03JT5y3sq0/C32JrKLixaQz1f3WL8vLB4fewt7bKTiuAe8wD6sBB3y27g/+NdDdzXGmKUT8HirHguuE6r0DLEtSvW6550cZtodI7c/VBkWEJLvCHrTja3sPePhFX5TNrePplqjO1n65CNEiyjhL1tHUCbnZIcKCqWyiMgvwLDIcDnn5AUD6VeSJEUgL91FvvgfgfLszrPjOQshwSxaV1NfZYW1LtYFO0Rfn6vwGOBFjm5TwjhF7yj+MsFqsXnxZSnV7dczgUcEKcg7GND92FYHLcAi2mMGKXpcWSOuqfi/DJ3Z5yvfU8jj8I62ulcRWljZb9s3dxl6ShDCdxe20AjBrMItTLNtqVRZVXg1pc8nrYBpCUZFXIQsY= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 529d66cd-e412-498d-4a9f-08dbe5e40483 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 14:06:09.7177 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: hTHc7Zw1a9Fani+aerdNTNjb/5AZQI3t2tk74t7C6SUiSrPZbqsYPslwg7m2DeSN X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7007 This is not being used to pass ops, it is just a way to tell if an iommu driver was probed. These days this can be detected directly via device_iommu_mapped(). Call device_iommu_mapped() in the two places that need to check it and remove the iommu parameter everywhere. Reviewed-by: Jerry Snitselaar Reviewed-by: Lu Baolu Reviewed-by: Moritz Fischer Acked-by: Christoph Hellwig Acked-by: Rob Herring Signed-off-by: Jason Gunthorpe --- arch/arc/mm/dma.c | 2 +- arch/arm/mm/dma-mapping-nommu.c | 2 +- arch/arm/mm/dma-mapping.c | 10 +++++----- arch/arm64/mm/dma-mapping.c | 4 ++-- arch/mips/mm/dma-noncoherent.c | 2 +- arch/riscv/mm/dma-noncoherent.c | 2 +- drivers/acpi/scan.c | 3 +-- drivers/hv/hv_common.c | 2 +- drivers/of/device.c | 2 +- include/linux/dma-map-ops.h | 4 ++-- 10 files changed, 16 insertions(+), 17 deletions(-) diff --git a/arch/arc/mm/dma.c b/arch/arc/mm/dma.c index 2a7fbbb83b7056..197707bc765889 100644 --- a/arch/arc/mm/dma.c +++ b/arch/arc/mm/dma.c @@ -91,7 +91,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, * Plug in direct dma map ops. */ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, - const struct iommu_ops *iommu, bool coherent) + bool coherent) { /* * IOC hardware snoops all DMA traffic keeping the caches consistent diff --git a/arch/arm/mm/dma-mapping-nommu.c b/arch/arm/mm/dma-mapping-nommu.c index cfd9c933d2f09c..b94850b579952a 100644 --- a/arch/arm/mm/dma-mapping-nommu.c +++ b/arch/arm/mm/dma-mapping-nommu.c @@ -34,7 +34,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, } void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, - const struct iommu_ops *iommu, bool coherent) + bool coherent) { if (IS_ENABLED(CONFIG_CPU_V7M)) { /* diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 5409225b4abc06..6c359a3af8d9c7 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -1713,7 +1713,7 @@ void arm_iommu_detach_device(struct device *dev) EXPORT_SYMBOL_GPL(arm_iommu_detach_device); static void arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size, - const struct iommu_ops *iommu, bool coherent) + bool coherent) { struct dma_iommu_mapping *mapping; @@ -1748,7 +1748,7 @@ static void arm_teardown_iommu_dma_ops(struct device *dev) #else static void arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size, - const struct iommu_ops *iommu, bool coherent) + bool coherent) { } @@ -1757,7 +1757,7 @@ static void arm_teardown_iommu_dma_ops(struct device *dev) { } #endif /* CONFIG_ARM_DMA_USE_IOMMU */ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, - const struct iommu_ops *iommu, bool coherent) + bool coherent) { /* * Due to legacy code that sets the ->dma_coherent flag from a bus @@ -1776,8 +1776,8 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, if (dev->dma_ops) return; - if (iommu) - arm_setup_iommu_dma_ops(dev, dma_base, size, iommu, coherent); + if (device_iommu_mapped(dev)) + arm_setup_iommu_dma_ops(dev, dma_base, size, coherent); xen_setup_dma_ops(dev); dev->archdata.dma_ops_setup = true; diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c index 3cb101e8cb29ba..61886e43e3a10f 100644 --- a/arch/arm64/mm/dma-mapping.c +++ b/arch/arm64/mm/dma-mapping.c @@ -47,7 +47,7 @@ void arch_teardown_dma_ops(struct device *dev) #endif void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, - const struct iommu_ops *iommu, bool coherent) + bool coherent) { int cls = cache_line_size_of_cpu(); @@ -58,7 +58,7 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, ARCH_DMA_MINALIGN, cls); dev->dma_coherent = coherent; - if (iommu) + if (device_iommu_mapped(dev)) iommu_setup_dma_ops(dev, dma_base, dma_base + size - 1); xen_setup_dma_ops(dev); diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c index 3c4fc97b9f394b..0f3cec663a12cd 100644 --- a/arch/mips/mm/dma-noncoherent.c +++ b/arch/mips/mm/dma-noncoherent.c @@ -138,7 +138,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, #ifdef CONFIG_ARCH_HAS_SETUP_DMA_OPS void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, - const struct iommu_ops *iommu, bool coherent) + bool coherent) { dev->dma_coherent = coherent; } diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index 4e4e469b8dd66c..843107f834b231 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -129,7 +129,7 @@ void arch_dma_prep_coherent(struct page *page, size_t size) } void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, - const struct iommu_ops *iommu, bool coherent) + bool coherent) { WARN_TAINT(!coherent && riscv_cbom_block_size > ARCH_DMA_MINALIGN, TAINT_CPU_OUT_OF_SPEC, diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index fa5dd71a80fad9..9682291188c49c 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -1636,8 +1636,7 @@ int acpi_dma_configure_id(struct device *dev, enum dev_dma_attr attr, if (PTR_ERR(iommu) == -EPROBE_DEFER) return -EPROBE_DEFER; - arch_setup_dma_ops(dev, 0, U64_MAX, - iommu, attr == DEV_DMA_COHERENT); + arch_setup_dma_ops(dev, 0, U64_MAX, attr == DEV_DMA_COHERENT); return 0; } diff --git a/drivers/hv/hv_common.c b/drivers/hv/hv_common.c index 4372f5d146ab22..0285a74363b3d1 100644 --- a/drivers/hv/hv_common.c +++ b/drivers/hv/hv_common.c @@ -488,7 +488,7 @@ void hv_setup_dma_ops(struct device *dev, bool coherent) * Hyper-V does not offer a vIOMMU in the guest * VM, so pass 0/NULL for the IOMMU settings */ - arch_setup_dma_ops(dev, 0, 0, NULL, coherent); + arch_setup_dma_ops(dev, 0, 0, coherent); } EXPORT_SYMBOL_GPL(hv_setup_dma_ops); diff --git a/drivers/of/device.c b/drivers/of/device.c index 1ca42ad9dd159d..65c71be71a8d45 100644 --- a/drivers/of/device.c +++ b/drivers/of/device.c @@ -193,7 +193,7 @@ int of_dma_configure_id(struct device *dev, struct device_node *np, dev_dbg(dev, "device is%sbehind an iommu\n", iommu ? " " : " not "); - arch_setup_dma_ops(dev, dma_start, size, iommu, coherent); + arch_setup_dma_ops(dev, dma_start, size, coherent); if (!iommu) of_dma_set_restricted_buffer(dev, np); diff --git a/include/linux/dma-map-ops.h b/include/linux/dma-map-ops.h index f2fc203fb8a1a2..2cb98a12c50348 100644 --- a/include/linux/dma-map-ops.h +++ b/include/linux/dma-map-ops.h @@ -426,10 +426,10 @@ bool arch_dma_unmap_sg_direct(struct device *dev, struct scatterlist *sg, #ifdef CONFIG_ARCH_HAS_SETUP_DMA_OPS void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, - const struct iommu_ops *iommu, bool coherent); + bool coherent); #else static inline void arch_setup_dma_ops(struct device *dev, u64 dma_base, - u64 size, const struct iommu_ops *iommu, bool coherent) + u64 size, bool coherent) { } #endif /* CONFIG_ARCH_HAS_SETUP_DMA_OPS */ From patchwork Wed Nov 15 14:05:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13456733 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CAAB1CABB; Wed, 15 Nov 2023 14:06:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="OT870ieV" Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2043.outbound.protection.outlook.com [40.107.244.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B582AE1; Wed, 15 Nov 2023 06:06:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=YMg85ApV3yzPwnem5jB4F1qBHOoJdE3uLgImB/r871whav85uvXRzU9r0+9WAXJeI6AeZDaISnuyd/RrHZV/Bt6a8XZi353V9rBsa1+2FLfJlqkPinbbRixOFWli4E+rffYL75T0aOfal3mzzeDgD8znJhGH1NMCrj+qGZqDa6G8E4pwb2mKpT9e0jWFUsk4pptsZ2x6fQPEVbExiIuKbMdAzASqyOA6gXo7v2nVd42HrG+raQk2/yfAf0qypeob3fBAx0bjrfLg+FaFqEVLErmU55uVAzZL/O/wojKxYCmXfCWh2mG7F5qZl0VXDygU1nTdX48P8PVgGOlW4PNcYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=4gXhMM8cpNC/Vatg733GVNojGpIsusgxeMA/9bWA1jo=; b=Jv2y0eBisZm718LpJvxsBSaaEAoq+z4e8NM7/oOxLAgcN+hgmM4eigJNgUZruo0F/p2m0bG61At19KSdS/lRWHji7zwTJLK/833v0gnVJGa/GEZw9w5uot3649L9EXJFVstpideI3xbo2TXIiL/G7yVfWsYW0xstAAQO36+GXlXkHj88DGBwVEGFOqnCaMFo945BtAtCW1Mg6ZKmQig87AQnoi5aV6gdDyq2cIFzwcqhWdi/WVZkdkr3ffv+WoyyjPLwN1Gyq7QmhMTjngKzjZkOE8GWp8weI3a/WUkADnY3g1LB5ZIP16uwi1EVcRsVsWyGeKLqB6MyQpKzRQqWrw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4gXhMM8cpNC/Vatg733GVNojGpIsusgxeMA/9bWA1jo=; b=OT870ieVx+l4kdLmD6x9RfZCx1ofZ+DWeRWqujr4NYQ4mJ6/rrlm4KrzX/DWX/Hvm/wy2Cxcraswh+bXj2fpm+OrcBrobSK7D0/r0HR7SAKf6fD7ZYKyx00PbPQbHqqGmQj0g351XBygwqqG2RbXZOs2VCGiNuiS9U4N5kfpWXKfk0f9TT3IcgbPxXdOd7p1hILNGTu+iT7Rqlo5JL1i8b4dUSyfzngSpmt/BUEFgos7rstTAUKCgyTASbjFmnvNUpaPmoNVj10J4OhTCrHyfCQobo9lqae/2yXmajKg1RIEM9r8TLBtEwnhV/WtaKSk2EMveKNqizMVM5ltByWunw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by SJ0PR12MB7007.namprd12.prod.outlook.com (2603:10b6:a03:486::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6977.31; Wed, 15 Nov 2023 14:06:10 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.6977.029; Wed, 15 Nov 2023 14:06:10 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Alyssa Rosenzweig , Albert Ou , asahi@lists.linux.dev, Catalin Marinas , Dexuan Cui , devicetree@vger.kernel.org, David Woodhouse , Frank Rowand , Hanjun Guo , Haiyang Zhang , iommu@lists.linux.dev, Jean-Philippe Brucker , Jonathan Hunter , Joerg Roedel , "K. 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Wysocki" , Rob Herring Subject: [PATCH v2 02/17] iommmu/of: Do not return struct iommu_ops from of_iommu_configure() Date: Wed, 15 Nov 2023 10:05:53 -0400 Message-ID: <2-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> In-Reply-To: <0-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR15CA0002.namprd15.prod.outlook.com (2603:10b6:208:1b4::15) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|SJ0PR12MB7007:EE_ X-MS-Office365-Filtering-Correlation-Id: 15b3794d-c7da-493b-4a9f-08dbe5e40483 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BMdSz/B6hBZaWAAOSdl1M3jgRKTNnNe/zFYo+Reeeu3cx/SCP1KpuaLWvzPpmr96R9M4+bUnbUtcxNFM9ckhHDU3gSP2ZEJmHTFD5d1E51+raq/cP5QSe9//f4qLsrHs+A9Q+53hgqGtwI3gj6PqRGXwFRY/5bVmlbPTzb/0EF44b+0r+7gyvFlKXeE/c+6Dqr6LdgvUpwZi7pVqjnsrO2dfZ+awsoubPFcYxZSbTkWWhbmyIlf+2Li7wRA3Xe3msPf4lD3su9jjOo5OvCPLUTL4IHxrKKnyIoPibKfJPrelT3zwSGQoSRHf+UKRkYNs7g/18F0//H8DhKfQ4DBTdSSeSGSkXX6Ec2rUHjeUwGn5W2jdsqun2t6Hs4qfrgK2EimwzewaoZ76AQAxuK7coXH8SNw/yNCEnYEd+1kPUwrqfHV7249Pgx7nFeCa2fnOJdymTfmO++2GXB1KOT/epW0a59auimrodXQqdrQIW0IsLSnEaN/MJLjW3q0PtIB8B5pxJGCD5qm/alkHNSescz+lsilvQaYG8h4pZNmUgiJRbJUloHRU9zx8xvP4/2Yt8OJfmaW0Q/eo/EUQVxxi9tuTkvxpnLR/40YFXQm2Z7++udFJS1f/hJpxx7JDog9h X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(136003)(346002)(376002)(366004)(39860400002)(396003)(230922051799003)(451199024)(1800799009)(186009)(64100799003)(7406005)(6666004)(6506007)(2616005)(6512007)(83380400001)(7416002)(41300700001)(8676002)(5660300002)(4326008)(7366002)(8936002)(478600001)(2906002)(6486002)(66476007)(54906003)(110136005)(66946007)(66556008)(316002)(86362001)(36756003)(38100700002)(26005)(921008)(4216001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 6hMYGtjx+oacwgj+16f6fhxgZnMc8b2bi580ESJ+M93DhnxDO+NDWO9i6dVLPBSNY66he4/VxjN/Xv5Ff6GQ5f8hYfQAuKVPXrjF2voW4mXGmJzLByAfu9eu/0tjEFClOATtwtY5TOuOuTC5foFCle0utIelGTrb0zyAfKwsYQRwffzMsa1NAzNrL30wbJT5wcy65kaURR6ChHlIpqZFzwuqJAyf+qjT41ZNPlv97dSeXVoX+V1qM9QyhaoQlps9EKvzfhI59inKW4L68z55Vm6GvWb+sJO2VAcN3yrV0x1ZiFwTFbYZukBVKlLLM7tGBUqAkCp7JW2evl1eGVwzJWi7ID6X6Gz+NlHY+tm5qWdQR8sSjs7HVRGdZ4KtprO2PqoGLuDGZZNlhTg18l7VBszAgABF57cziBtt7i4PH8KCQ/pUVrpghYw/40nLiTrlBLCAkln3Vx9X50eB5obS1qWsiGflq7/FWQezdHIxZI7F7a7dlrrVkw+LA6C+GY0x7crzzI2deL0nPVCWbScmfUhw0C8yFZXlRR1giJUylNjENGuCs5ntLVLvozWzf1wjNjJshuYUY+LhwPGkkI8aVsWs+kS2mYzb5VR+QX6BwEzVHgxPsrq2lOke65ICyGsktyhSc4oSs58NvFnGoTVAQUq554VWB8eqkqfVqAmdyiqe0JpdjWux7B0B4sq++50QyPHYrcqCX/6EZ7KClzexKDb8Q6ySnFJAXinytf/28A6qHUixmUYgEAyqqRHLdQxsd1SLkQ1fitCJPvenNn6M2GAZMY8jVbWvBt84MKL1+nxgTFl8eNIH+owoqad3Ju9XdJw5ib5652rx1mt18eiFupdwnnPPq8ELCAL2M4nCGMMXGqqiMecdtN0AKib8UCRuOah2RvxNwB+zv6DJznkEPpwXMZV2UWJB2f6/bZ/xsTqPufGm1eqLfL4GhtpdasHFABGzW0pzSoZFxgK2Se7VP6E1W6lv5VH6PKorN4qjAJmk9RdXRnG66bhzDmnQcoqYL9uEo1/E2WRvGEek8HvQ/b4yaj+kUt7Ep7L1nKN48Ec4bJTNLOmnv5oWhp/iykYfIPRlcpeYsGfbJYSixFhbk+Z7F8wjs/RBL7DuqIo2uFVOJ0DMwhjps+qagAYMCyA23UeQ6xjai9YuOlpZyLEhsLKZBie0ROV0Yo3PCWaY5l8aUR5kOX5kJ6SgVVoq9KYCm+uIxnyFP+9rlnX4t70DFdwYxDclGIl493MZ49Xzn/NbVzsgPMWN47XiQhKWAwudvWUVbf8JZ+LD4UUEs08yPUl/oAU6G46kASn7qw2fOVxJFQCNT0c8RD+Tbs2f6Kz7ppXGUH44VTC0Er2lzq3X8A9hslcEhGi9Wrk+4W7EZ4YwfMe0M18lds7CaX60lNp7LJ2i7wGeaAyvfRTGOzFHQtWG9bYu1HTxdYzLENfROZ2WeodwQOZQUcBL6slEU5MJj5mK5bDmBXKq9CgN48u90Kf0svnE+ubYBcSn3PBeBWe7tA3g4ak4tVLPgBztd0HPT01QAbSaOugUUxUoc0q3kC0zXS2kG8CCIdJtKcd0v1s= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 15b3794d-c7da-493b-4a9f-08dbe5e40483 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 14:06:09.7081 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: DxBC5xm4tS+nONgRE/3t6mULKCxKO1nd3XFhHlv8woPsivA1cR60LaUSu1+HgDKZ X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7007 Nothing needs this pointer. Return a normal error code with the usual IOMMU semantic that ENODEV means 'there is no IOMMU driver'. Reviewed-by: Jerry Snitselaar Acked-by: Rob Herring Signed-off-by: Jason Gunthorpe --- drivers/iommu/of_iommu.c | 31 +++++++++++++++++++------------ drivers/of/device.c | 22 +++++++++++++++------- include/linux/of_iommu.h | 13 ++++++------- 3 files changed, 40 insertions(+), 26 deletions(-) diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 157b286e36bf3a..b47dcb66cde98d 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -107,20 +107,26 @@ static int of_iommu_configure_device(struct device_node *master_np, of_iommu_configure_dev(master_np, dev); } -const struct iommu_ops *of_iommu_configure(struct device *dev, - struct device_node *master_np, - const u32 *id) +/* + * Returns: + * 0 on success, an iommu was configured + * -ENODEV if the device does not have any IOMMU + * -EPROBEDEFER if probing should be tried again + * -errno fatal errors + */ +int of_iommu_configure(struct device *dev, struct device_node *master_np, + const u32 *id) { const struct iommu_ops *ops = NULL; struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); int err = NO_IOMMU; if (!master_np) - return NULL; + return -ENODEV; if (fwspec) { if (fwspec->ops) - return fwspec->ops; + return 0; /* In the deferred case, start again from scratch */ iommu_fwspec_free(dev); @@ -163,14 +169,15 @@ const struct iommu_ops *of_iommu_configure(struct device *dev, err = iommu_probe_device(dev); /* Ignore all other errors apart from EPROBE_DEFER */ - if (err == -EPROBE_DEFER) { - ops = ERR_PTR(err); - } else if (err < 0) { - dev_dbg(dev, "Adding to IOMMU failed: %d\n", err); - ops = NULL; + if (err < 0) { + if (err == -EPROBE_DEFER) + return err; + dev_dbg(dev, "Adding to IOMMU failed: %pe\n", ERR_PTR(err)); + return err; } - - return ops; + if (!ops) + return -ENODEV; + return 0; } static enum iommu_resv_type __maybe_unused diff --git a/drivers/of/device.c b/drivers/of/device.c index 65c71be71a8d45..873d933e8e6d1d 100644 --- a/drivers/of/device.c +++ b/drivers/of/device.c @@ -93,12 +93,12 @@ of_dma_set_restricted_buffer(struct device *dev, struct device_node *np) int of_dma_configure_id(struct device *dev, struct device_node *np, bool force_dma, const u32 *id) { - const struct iommu_ops *iommu; const struct bus_dma_region *map = NULL; struct device_node *bus_np; u64 dma_start = 0; u64 mask, end, size = 0; bool coherent; + int iommu_ret; int ret; if (np == dev->of_node) @@ -181,21 +181,29 @@ int of_dma_configure_id(struct device *dev, struct device_node *np, dev_dbg(dev, "device is%sdma coherent\n", coherent ? " " : " not "); - iommu = of_iommu_configure(dev, np, id); - if (PTR_ERR(iommu) == -EPROBE_DEFER) { + iommu_ret = of_iommu_configure(dev, np, id); + if (iommu_ret == -EPROBE_DEFER) { /* Don't touch range map if it wasn't set from a valid dma-ranges */ if (!ret) dev->dma_range_map = NULL; kfree(map); return -EPROBE_DEFER; - } + } else if (iommu_ret == -ENODEV) { + dev_dbg(dev, "device is not behind an iommu\n"); + } else if (iommu_ret) { + dev_err(dev, "iommu configuration for device failed with %pe\n", + ERR_PTR(iommu_ret)); - dev_dbg(dev, "device is%sbehind an iommu\n", - iommu ? " " : " not "); + /* + * Historically this routine doesn't fail driver probing + * due to errors in of_iommu_configure() + */ + } else + dev_dbg(dev, "device is behind an iommu\n"); arch_setup_dma_ops(dev, dma_start, size, coherent); - if (!iommu) + if (iommu_ret) of_dma_set_restricted_buffer(dev, np); return 0; diff --git a/include/linux/of_iommu.h b/include/linux/of_iommu.h index 9a5e6b410dd2fb..e61cbbe12dac6f 100644 --- a/include/linux/of_iommu.h +++ b/include/linux/of_iommu.h @@ -8,20 +8,19 @@ struct iommu_ops; #ifdef CONFIG_OF_IOMMU -extern const struct iommu_ops *of_iommu_configure(struct device *dev, - struct device_node *master_np, - const u32 *id); +extern int of_iommu_configure(struct device *dev, struct device_node *master_np, + const u32 *id); extern void of_iommu_get_resv_regions(struct device *dev, struct list_head *list); #else -static inline const struct iommu_ops *of_iommu_configure(struct device *dev, - struct device_node *master_np, - const u32 *id) +static inline int of_iommu_configure(struct device *dev, + struct device_node *master_np, + const u32 *id) { - return NULL; + return -ENODEV; } static inline void of_iommu_get_resv_regions(struct device *dev, From patchwork Wed Nov 15 14:05:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13456777 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABCED1EB5C; Wed, 15 Nov 2023 14:06:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="rCE+8TMj" Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 852A7E1; Wed, 15 Nov 2023 06:06:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=fyLqbV09LUBPSZSauUYeDEJksXuLvDKOwitA75fiYSi4jzpQhhTfyBaCuLFQJXgSNx3/rWFpoefd7V96Mccjkdfa45+l4LvyOzP98Y3kMGtzFtRRK41X9od525XT2TQqAitv3ZlPAuAHZP48ZJj60xzEquBoYruGnVEKHw/VppWsjngzhnQAZJmm5xUi3ItziLmYyJ8WQHjZGnlnQny4IDwEzjSI2kz87WlKVP2HSOB6JTRT/4N8r6i4J3dd5B36f3EK+0z1M8k4qdi/331pBMS4m+YNZKlxvJ9PZyPo2XWvc7aWIo9R3Cw5FNM3eN6354LCMFuB9aGsSsdRufArMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=xT0oaRCdHSsmf4+v0+ddHaxBeQzVTnNF6zGPPo0PbgI=; b=VCuojikndcIuDags3IDn/K4h0PTGo/7Ih6SgrjvMoWEYkjQukeAZR1HFH4kQBkbwR2XMshK/XCxvF+3TBKV7xBEwLb6Lm2atHDfrYHhEZeR/UV4RH2pSQxOtFaddhjvat2SDLAw/FdqxkTnVnaQeRCtnkGqIUMLAejpExPcjjgq2mgnWIM4O7pPpHDLqoSEUx3Ao+dR+MPi8yN3LsIdCu0F6HMjruD8VmzLdJuVS294O4bnfgl0iHJH6frp5vU19l3I4H1DPWd+AQ3++hj9DH6s9/n8QQZHShVlkf23YaNvx4Flr+iPhxqdoT9BNgvMFx451GtgV+o8uXkdKKTAFBg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=xT0oaRCdHSsmf4+v0+ddHaxBeQzVTnNF6zGPPo0PbgI=; b=rCE+8TMjWWvXiVfknLRIBcFfbAx9oVylXxGOAKN4g36LooS48GlWUNBN6uCyMi5mval1xBciKrQhSgo0/Gfs3mOtMorUONxsZVmS5YlMH5JDEByntsETj/d5dw9icxAJf/CXWD5+s2kGqcc0yZSV03ykKIJirXmP+G4N13ftq/QFEZdEpNJxQUtE0litQacptsB8TDwskH+pA04Brimbs1YNQT0Xz5Lc4qWuFzpqIb3955a2ulfaot8XotG7vxiQsVyVgU2oE2ApiVoLNWmzTJBmfJejtppSf0iT6ZpDX48jd2GyKWTh5Asq8v5WwrXgKIrk1g9nNfVrJ4t3wZGgmA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH8PR12MB6916.namprd12.prod.outlook.com (2603:10b6:510:1bd::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6977.31; Wed, 15 Nov 2023 14:06:17 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.6977.029; Wed, 15 Nov 2023 14:06:17 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Alyssa Rosenzweig , Albert Ou , asahi@lists.linux.dev, Catalin Marinas , Dexuan Cui , devicetree@vger.kernel.org, David Woodhouse , Frank Rowand , Hanjun Guo , Haiyang Zhang , iommu@lists.linux.dev, Jean-Philippe Brucker , Jonathan Hunter , Joerg Roedel , "K. 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Wysocki" , Rob Herring Subject: [PATCH v2 03/17] iommu/of: Use -ENODEV consistently in of_iommu_configure() Date: Wed, 15 Nov 2023 10:05:54 -0400 Message-ID: <3-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> In-Reply-To: <0-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> References: X-ClientProxiedBy: BLAPR03CA0101.namprd03.prod.outlook.com (2603:10b6:208:32a::16) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH8PR12MB6916:EE_ X-MS-Office365-Filtering-Correlation-Id: 20007c76-5aca-415a-8d98-08dbe5e40589 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: IHHuA9EODUzelcV8jJpF238NtJu8OK8Pgq2dkaJN+LNIqilGug7SL2Ybvys6JC/WCCsBTU3EuypO4BRI3ycYxxbveFC648Zx7upCxC843j9aqMz/6LoSsEFxkr5SKvNomY5WbppRP1U//3R9S69uwskKCrsUFInjIf8X1hOp0Ov2qsPg43dpB7ov5CBkeeTHToS6NXA+eoSgE0arpumsI30lhm7A4Rwj9gr0eGaZbbGTSAN43qFowQ5QkG5hISFUMDMWYorym3wWovkgm2EVIArWtqf+i4M2x7P9q/GiRlKk3YfEiP97At9UDnN6ht1d/Z62ZkGNOiG3Ja+hed/Zx7pCARqstdDmFnM0NyfAMmvqQf0z42igneXpnst7fjVXpGkMeGp6Bg4p/nCRAm50ca5LiKN4bHxf5486wuyNj62qx5iDRIiqTtaMFSVplWQkWIRurYAyi1vnBHzWEH5xRnH2xKLImoSR8OzHuROlQ2Y/1wXw9AY4EHOBv98gIb+nN4f1coKH6GwtnwwMeZMqxdqWtU2X+NDpxTwgoxNV2L214Kte6HsSx3cMCjmMVA6qqOSkDqXCxonu2zp/GzxxOIu09AZi/Yf9A9nQbLUMbYBsl7XT3Ydh17Jt9LKXo3JA X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(39860400002)(376002)(346002)(396003)(366004)(136003)(230922051799003)(1800799009)(64100799003)(186009)(451199024)(110136005)(316002)(66946007)(54906003)(66476007)(66556008)(6486002)(478600001)(6666004)(7366002)(86362001)(5660300002)(7406005)(7416002)(921008)(41300700001)(2906002)(36756003)(8676002)(4326008)(8936002)(2616005)(38100700002)(26005)(83380400001)(6506007)(6512007)(4216001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: XehaVCvFAMxHoIuLmOBpxBw83s8Uc0D98/WLtTOUn0G5Sjgr4linvCUJTwSHXqMENNq7MgiZ/MoBiQ6Txcv7mGkbrAHoGsg1vGgEgci9ysJJqoZonMkt0q6HkRNeNAqC90KDVR+LKBNW4UsF6BXXqhr5Ow5uPha1kDy5zHXdbmGPwAA8an33WSpNqTJh5xc2FvTZ/3+lkaW4Qlx5ZPHsKEIt9NzuZnZ5GRsEohvYSGFzvMNcWZwdjyJQCUUzHfasfaJpRourW6Sujog7BHJTebigKzTPb6ONU8bCu1I/RLgMXc1lj2oRQOfpGRrut41pw0hMa08TReONkq3rCTQ5O9p5Q6STQWcunq+K0+un/Bw4We8FNqriY+gnI+mu8lfFAooCPeDUehOm+jIjOCuKKWs4z2VwWEfNaLTiMmbdpMOyWsiGhX24NJuMYXRH3Id6ptG9Cr9OFOWutzuklk8jfzgnEb2OmlQZtc45V3aQwo9u/BMb+FWQxPXQpUipGDcgnzOlUEPzwAmPPok3DiXRNvlcLfksDgbkzR/9xnZPwDmpQWogRlxntDzmQSq5f/mFbEJTJ+Z68h27opxxtaUYpDSFDDRYP633zGbaLu+5r8BRNdtBInsJYfxqZ+g+HLFiE7dl577hyvqX09mejVuRCP4a/dGXCjoGRcYEtWaJLBGf81hGhBgvzsZhnyDoj4B8FNBt7Km1irrG2rOIntuqXmy+m+ezO8XVX7+ZKkmU3jqDsop5mdtikWUeciXIRJwB5g8Q0PFjF0Almh0qgkMLk8vRlPTdlQVOeLQkDWXLr3cr2AIoXDezmBY+pY37PLUQST4L2p6zCnZh0sEeB4Au6I37olImpHWhpC1P3pk60b3XLzB1rr0VrrPOLdvyhIQjazlnZmppVQl8JSx2SItAsteplP0u0hq64dhMZNypM0D/YnH0e+eDI8fDOsQpJ5TSD1xlYgFEH2Bn1Obm2ykq9ZCMSkpaTIwImE4X8Ju+Mr24EzNJ5L6FPCiIHywt6aP0VAHYgWtUoJenVf+3OJ79aaKtOnM9qFnS8qnoXRRYrTa6XMZx4jJxJofP89J5/Y5ol1dwr6h0d6/G0jT8D+4gmlCIeW+p3yrNnavzYEvB4XSoF2U5R4nhFaaK/6FEuWmGaAVBnJ4pkuIvJd+FvWkI/ASA0Pvo1sgBxIaR5w4amre5+I9qRq14Lu7vHTT5Pm/+E/JbuTt2TtPdRX5wfT0OyTJSWjZtiyyp+efXXRAz6Jt/sW1jMm8h/U3yqKBbPfv9RYS+ZDgZdBzD0GjSIRif5YOVAnlj2lK6vrbqSPXCzO5/1dBftnUOO8Lfyj3BX24ffDfgW95abn5KAf748alC4KNbqbR2q6yAD69U5iEsH3/hLhcMuipYXREbE39o3aYLatSz5adsuQg6UefehnPPoA0tdhwiJRzlAz3f4l+d7qggFAF5zP1WaMyUrd1TNKzCN3Bd6Q/mtmRpOyjA7yl8dP3/+aj8vnm9/tjJkxU5yiwY9c1c30JAGKEx9/kOA3/Koo5dppOdWooeVofOrAxAGn1g8IyZQBFT0gMISu4kSGE= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 20007c76-5aca-415a-8d98-08dbe5e40589 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 14:06:11.3690 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: IaesOnVJV6cSI8hK0CRBDC1o0ULfoU5uikyskLZ3qRQQWneg0TCKpN4/k0kksxdK X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6916 Instead of returning 1 and trying to handle positive error codes just stick to the convention of returning -ENODEV. Remove references to ops from of_iommu_configure(), a NULL ops will already generate an error code. There is no reason to check dev->bus, if err=0 at this point then the called configure functions thought there was an iommu and we should try to probe it. Remove it. Signed-off-by: Jason Gunthorpe Reviewed-by: Jerry Snitselaar --- drivers/iommu/of_iommu.c | 48 +++++++++++++--------------------------- 1 file changed, 15 insertions(+), 33 deletions(-) diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index b47dcb66cde98d..a68a4d1dc0725c 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -17,8 +17,6 @@ #include #include -#define NO_IOMMU 1 - static int of_iommu_xlate(struct device *dev, struct of_phandle_args *iommu_spec) { @@ -29,7 +27,7 @@ static int of_iommu_xlate(struct device *dev, ops = iommu_ops_from_fwnode(fwnode); if ((ops && !ops->of_xlate) || !of_device_is_available(iommu_spec->np)) - return NO_IOMMU; + return -ENODEV; ret = iommu_fwspec_init(dev, &iommu_spec->np->fwnode, ops); if (ret) @@ -61,7 +59,7 @@ static int of_iommu_configure_dev_id(struct device_node *master_np, "iommu-map-mask", &iommu_spec.np, iommu_spec.args); if (err) - return err == -ENODEV ? NO_IOMMU : err; + return err; err = of_iommu_xlate(dev, &iommu_spec); of_node_put(iommu_spec.np); @@ -72,7 +70,7 @@ static int of_iommu_configure_dev(struct device_node *master_np, struct device *dev) { struct of_phandle_args iommu_spec; - int err = NO_IOMMU, idx = 0; + int err = -ENODEV, idx = 0; while (!of_parse_phandle_with_args(master_np, "iommus", "#iommu-cells", @@ -117,9 +115,8 @@ static int of_iommu_configure_device(struct device_node *master_np, int of_iommu_configure(struct device *dev, struct device_node *master_np, const u32 *id) { - const struct iommu_ops *ops = NULL; struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - int err = NO_IOMMU; + int err; if (!master_np) return -ENODEV; @@ -150,34 +147,19 @@ int of_iommu_configure(struct device *dev, struct device_node *master_np, err = of_iommu_configure_device(master_np, dev, id); } - /* - * Two success conditions can be represented by non-negative err here: - * >0 : there is no IOMMU, or one was unavailable for non-fatal reasons - * 0 : we found an IOMMU, and dev->fwspec is initialised appropriately - * <0 : any actual error - */ - if (!err) { - /* The fwspec pointer changed, read it again */ - fwspec = dev_iommu_fwspec_get(dev); - ops = fwspec->ops; - } - /* - * If we have reason to believe the IOMMU driver missed the initial - * probe for dev, replay it to get things in order. - */ - if (!err && dev->bus) - err = iommu_probe_device(dev); - - /* Ignore all other errors apart from EPROBE_DEFER */ - if (err < 0) { - if (err == -EPROBE_DEFER) - return err; - dev_dbg(dev, "Adding to IOMMU failed: %pe\n", ERR_PTR(err)); + if (err == -ENODEV || err == -EPROBE_DEFER) return err; - } - if (!ops) - return -ENODEV; + if (err) + goto err_log; + + err = iommu_probe_device(dev); + if (err) + goto err_log; return 0; + +err_log: + dev_dbg(dev, "Adding to IOMMU failed: %pe\n", ERR_PTR(err)); + return err; } static enum iommu_resv_type __maybe_unused From patchwork Wed Nov 15 14:05:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13456732 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 118D3200DE; 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Wysocki" , Rob Herring Subject: [PATCH v2 04/17] acpi: Do not return struct iommu_ops from acpi_iommu_configure_id() Date: Wed, 15 Nov 2023 10:05:55 -0400 Message-ID: <4-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> In-Reply-To: <0-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> References: X-ClientProxiedBy: BLAPR03CA0117.namprd03.prod.outlook.com (2603:10b6:208:32a::32) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|SJ0PR12MB7007:EE_ X-MS-Office365-Filtering-Correlation-Id: cf7309fe-f1c9-4419-4a9f-08dbe5e40483 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ePTi3F+oZbUMQCUcsp2v6wREhVh00swp1NKNuUMA+WByeY6evt7aCVb5o7P+kKM+17tuVIcqtnhkfc/s9UviyPhvZjIGoq+dVwV3dSnIX/mAhnHLgbWFHX4aUcs/ikXVaDRVzhFRZSSjViTy1KYNYtvzAVrwPYThjo3EblJVfb6X+w8cCbzBh8Q9jIC3btPT0DqCAQ4SCHzkOBEESoBI+vjIcAU5Rp8QZ2eeVGHQOqz4/tLeAe+bFTtTq/LTq3rlfE8P4RKFg+58FUYpOAnzKS1VLTk8ARWSSs31+zZbCCiK/UPlH1XFKRBcETqDyzb3JNaX6FKbe6sgRpdIg2D3EFulaqE/9ICeNLdVoGpdiHK/6nW+8nA5uRXPG0Gs+w60xK6xgyI+R2SpRWF2Uq/9xcSLeHDLwH18JwWIVFtVcjpe0wmMoGFnCJTzH+7fIYP3aj1gtVhETh9V2svW9ui/0unvRrDbxndthSrMFiQ2Y0jZP1mARSgiAE+Wp3lhwcrt6EJibDEryo4PpXFTmpsIhI3/nvt3PNu8DTp/FJGy4eOUbUlEPfsjo4kCyASFVUECQy8nlW+ufAsQHB9BsYiBt5aO+MsPNEanlUSsdmNTNouA4AV9k8ArzArid/Bys72z X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(136003)(346002)(376002)(366004)(39860400002)(396003)(230922051799003)(451199024)(1800799009)(186009)(64100799003)(7406005)(6666004)(6506007)(2616005)(6512007)(83380400001)(7416002)(41300700001)(8676002)(5660300002)(4326008)(7366002)(8936002)(478600001)(2906002)(6486002)(66476007)(54906003)(110136005)(66946007)(66556008)(316002)(86362001)(36756003)(38100700002)(26005)(921008)(4216001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YRGOVSeiGcR8haEtk0a6r13M2MCGQQsWdOny4DOIvVSG9ekISERiqrl+BlI1Ae+gJE8O1HTogKTeSHzE6OTE0p2AkumI8sIcY+iTSTITfyLr7lVSpVUSbBMyC6H87OGYuQmjc8EYjrzoAJScq09BHnia1WL45L8MZSyUfEJ0hu8xwnh+pqREKcmYbiEjG//ahYcTUgBo7uGGI26okf0sUM8+3+pDA6pImrzgxPgLOkWwKaR/a/0MR83StkkZd4ihyV4sqT4TcqJdFdSHo+25KBvLMX4Kq6KoTaZB36LpOrEw3XSlkFwiML4H0hdmmwoeOtiO3YIwYPy56yJRtF/a5VOIIS0Bm5nwGmdwQidE8g6VnqJTc1n2DdCFVsZdCQeWpcd1x3Y8OA+W2geb4DMNuz26atSMxDcEwEzfS5r/GP84o1pCWe6E2awafcnCvNIxXt1SkhTW3Yq2ISnG6Hu2QzGb7X2u5kzd23wV+HO698CtKN+31tUtypC1YPkGKEvBwplgwKOH+Mwidxx4BKL1D0YNhn+opephCQmnNRTEbITJAPig09IKMMvz9uT4A7DNaDZDy/gTGqtQo4QU3qmGABAgd4MtLW81p8xMmX+HEtwlogNS8LdtfxeKf0VCfMXblq11+wfrsFOVJ1rJN3/StH4ENxSXoh4M9k1rkm5WCPnydV+mghKHpp3R1eGpkpo6hbAjjapQAWuhX/7HMcF5EHUC4G+jcl+/KSf7TWUAyse243nOgFaa9D43GXy/CaHwJbYXv3BoegqBqQQlE0Y319KErjlvD1tGDyKrfAFyP3fgTiwXfEXTxV+bGa3S7EvihU/WPPXdgBdX/2HH0DMzV7yny3tOqZLR7TgYq3uv68McslMtdU6CJbVP7Vn/HiP7QL8A5d7QJhf6a0RJqrnmga+kPimv/aOsY6WUSciPxevPUH+bBwm74k35PfG2bQfNA0nbr1J6Jjx3ONzS6oY9OPtSnywOLZLaW/g9XcYmNBSBEP099YYLpwBAEltqs3Xl/vInVXNbge40xVHxbHnE6azBbHSVtow2A0lBnSkNN30oawDIDxtuwL9F3EWcugJ1y42MiNBCN2TwsKKlhUbC1079un9s5gZpFNiBjVnDTZ1X0WlEiftbJpZGFmO19fVaXmkjexrUbC20yQI4Rv/2TWGFgP6WmZUITxwYEAaRssI62nU5W+HLDJa6eRv1xvH4ay+4GSZ7MXB61Wa6raAXbRslTAKSuERkoDDxDN/mZT1StAfxd0Fhln8mOK9i9cBGT+Or4AjCI8/upadts+ETqz8PA0/RcRDZFqJAe1c5lalq0t2Rc9P+2U8jwgUBGeqk20B842DwLzyvDjXs89oLnNdR1yfEYjZaxyh/S2NE+pwBFXUXUNRpaz44ddQ2Um94KcnKCiMtLJtS9lUDEiQZkLlNDr0M92O0kR5uC55ICGSocsKBCDQ9lvUq99D3cPWBfcupepb/diJlN8CZ/l5NJQqfJRyCZX6diU345QGBnl5QYvH7LFOdyKC647XMVcUpNrdpSaDNfj8eQfO/jH81usxXF+LlrXAdBO0HJ7DGb+4= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: cf7309fe-f1c9-4419-4a9f-08dbe5e40483 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 14:06:09.6989 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: lYuiPds6pWGE/2wRJv4qtFqt3GYu5J5zYrSN0uxlcZZflI5NSJ/YZMpaAd6xWKg9 X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7007 Nothing needs this pointer. Return a normal error code with the usual IOMMU semantic that ENODEV means 'there is no IOMMU driver'. Acked-by: Rafael J. Wysocki Signed-off-by: Jason Gunthorpe Reviewed-by: Jerry Snitselaar --- drivers/acpi/scan.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 9682291188c49c..d171d193f2a51c 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -1562,8 +1562,7 @@ static inline const struct iommu_ops *acpi_iommu_fwspec_ops(struct device *dev) return fwspec ? fwspec->ops : NULL; } -static const struct iommu_ops *acpi_iommu_configure_id(struct device *dev, - const u32 *id_in) +static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in) { int err; const struct iommu_ops *ops; @@ -1574,7 +1573,7 @@ static const struct iommu_ops *acpi_iommu_configure_id(struct device *dev, */ ops = acpi_iommu_fwspec_ops(dev); if (ops) - return ops; + return 0; err = iort_iommu_configure_id(dev, id_in); if (err && err != -EPROBE_DEFER) @@ -1589,12 +1588,14 @@ static const struct iommu_ops *acpi_iommu_configure_id(struct device *dev, /* Ignore all other errors apart from EPROBE_DEFER */ if (err == -EPROBE_DEFER) { - return ERR_PTR(err); + return err; } else if (err) { dev_dbg(dev, "Adding to IOMMU failed: %d\n", err); - return NULL; + return -ENODEV; } - return acpi_iommu_fwspec_ops(dev); + if (!acpi_iommu_fwspec_ops(dev)) + return -ENODEV; + return 0; } #else /* !CONFIG_IOMMU_API */ @@ -1623,7 +1624,7 @@ static const struct iommu_ops *acpi_iommu_configure_id(struct device *dev, int acpi_dma_configure_id(struct device *dev, enum dev_dma_attr attr, const u32 *input_id) { - const struct iommu_ops *iommu; + int ret; if (attr == DEV_DMA_NOT_SUPPORTED) { set_dma_ops(dev, &dma_dummy_ops); @@ -1632,10 +1633,15 @@ int acpi_dma_configure_id(struct device *dev, enum dev_dma_attr attr, acpi_arch_dma_setup(dev); - iommu = acpi_iommu_configure_id(dev, input_id); - if (PTR_ERR(iommu) == -EPROBE_DEFER) + ret = acpi_iommu_configure_id(dev, input_id); + if (ret == -EPROBE_DEFER) return -EPROBE_DEFER; + /* + * Historically this routine doesn't fail driver probing due to errors + * in acpi_iommu_configure_id() + */ + arch_setup_dma_ops(dev, 0, U64_MAX, attr == DEV_DMA_COHERENT); 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Wysocki" , Rob Herring Subject: [PATCH v2 05/17] iommu: Make iommu_fwspec->ids a distinct allocation Date: Wed, 15 Nov 2023 10:05:56 -0400 Message-ID: <5-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> In-Reply-To: <0-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR15CA0023.namprd15.prod.outlook.com (2603:10b6:208:1b4::36) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|SJ0PR12MB7007:EE_ X-MS-Office365-Filtering-Correlation-Id: ee058122-8022-4a80-f556-08dbe5e4050f X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: W6CMbmioqyjiSGYWJfc9PqlfMlO3AXk7XEGRtmmOsYLNGx/n9tewVmkAIJRUWrz9BeXtqFLS8yeseODoaXIQf+m9dSbuNYc/3py5wnWNAQzJBY/1V6Oaf47qedLltDOd/N8zx9L3A5emCStmxGETmRniXX2mVl6/hyWuIB1vg55MlsspcxkOupuwcv1p9NA+8xvAZJzosdpKkrx7WOf26WmdlC3p7uz+P8IO5rs7d96xLTFC6/+wotedkkpeXHuiLxr5Dp8ZSr34neTgyevJZT8vicOfycJXNqiBoNFEkVxN3NStHTsNDYzvApbmgi0HyxqO4tmJW1DO4ss4w8AdJKBJ4vIEHf6/me7XMDsbbT2CuzwSO730ssxduwAwqJf1ZLnfTAKC3A0N3BgaCaWh231+AzPejBwLA5+SVklFJpBNVZa57gfioVLJDohENaUAljX81o5LMOYxzy6tksIlg07g00So+FG99wbHfYyHI68TC5lQCdOOSr+quNDJ31QsC1BVtAJ0616DQ3jCuwa5E88W2fNFdsOCcO+jU2aNeuBPfM6UO9aarlDdbdfSGSV3Np7YyRnjvvFueVD9uvi3ExGxofwt8L/JXLVUYJ5HC9chYn115E5ky9QOnu/E+L+c X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(136003)(346002)(376002)(366004)(39860400002)(396003)(230922051799003)(451199024)(1800799009)(186009)(64100799003)(7406005)(6666004)(6506007)(2616005)(6512007)(83380400001)(7416002)(41300700001)(8676002)(5660300002)(4326008)(7366002)(8936002)(478600001)(2906002)(6486002)(66476007)(54906003)(110136005)(66946007)(66556008)(316002)(86362001)(36756003)(38100700002)(26005)(921008)(4216001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 6X2JMKqSHzDrJ78DtAE7TzMnYfdbnxODPlK7rnDDhlz+0Wu/cL+lQoeES1a6AYcx1nHLBDz6KrswYmO+wnuEczYFG2H03sw0HPS5DXJp3cIl3b0Vauj73Tm7MgF8SGSXPJDlsAPigxqHnOJbXClRKyW1DpiqHErtvJbGs1O/zsaCepIRZ9nilEhG5POAlB+rwjPxVlxqwdERH2qRevfFdL+syFJTkUGz04yY/i5VdZvCLs8p57A8K41GyPmgcxEljwyv2Tn3ZHhSvnSQUk4kSeVeWfT5ZcPSvmFXgYCTxzqnrVl8kzIuWweK5lbD+WyKxw1BPspDunHDC2n0AjZAsKdtDeOK+Qaq7PGTXPEGFkzyRdk878SwOEl+d4I6SVdgAscLW12srej5wr8b3yRyX3AYyU1pTBfkRXNcpUTk7daT6hPj64hZRYgJ/+PeziHxW9mhmNqOqo6YbWpG9bTMQwzvRvfSoZYrHwgQVz/iGPtOZtQGZhFQblTxQfUgojWR5eCx+MnvvlC9YjyvbcumDw8T0zdcvIrhDXnbYxmBU9Ayy3hg4L9FAs4AqNxBBgYEhgg+Q/LwuXoF/49b4g4AETsD+q5KI8RoUtrCuBNk6LkGOfeqt4KRhOrkPwbKUEZNL0eAb2VMulaDqP9L3ouXOL7aSLfQQogtuUKRZXx6v+Okx6EDDS0/tmOiDMEIJExiZh96dRVNwp412G8GG2DNYaXWIzswu7xlWG8qZDAwRqEmqT4zLWMsqyFMWcloAD7a8OjdEskdxYW1DnFJIpiLy918IbLkE+P08UZuuup78vd1rC2osProDkSazTuYCLpeMRHmXQfV9YlqzXhTC7cc9SMPUGK4dhrQM9E3fy+GXbFnWXgMjDCNxVNmI99QVXFL7D4mvYizebvY9cRz0TSBcpNv4Ejp6ZyeguteC9whaozGhleyaENcFMhIJKjwXixxFkMmDZ8Ammfi1c92nAzMtKvxWJeBygT51YA+GZcH1Dj4hvIbRa4CX0bHSE99xUVRzcg25cjz8Uy9WCdOptg/Azxd5c886IIF5KBmatw7S+R5m/ZNynXwEzyUhmfAJR2igWRe1McS38ydeVtCY8Nvc8jcjV3RByKLIv8NC83a4LBYeLth+snUaQAXfSE+Tdu0RNc5BkNe4eQ0PaPz7iXAnGh1p2SHysQgBx0BqbjVYakvP62+jtQXaaT7FSLm9JAip70PRC0R/DxLzakPN800gVFKFAgZecm2IcWSujeNI5nBnbUeOe+1PUPSuoV5G18DmABrQov/aGiaSGsbMgvKaGTcnkwEdvP+DB5dfQ8C3HApGPz2D2UzhBKlHApuCm5iQHIlsJL/BabbNBvSJvSRersRqkXmCm36/GIrWxOwU1wz48GcQNU1qcgUKzI+1w5BFXQ8U/N7g1vitGtUmDd5dOIVt3906VnYPlfFJRTTUVVGe3IGxviFSAg0Lz5zH0+fKLED2kVvZAhxOLoKIP9Yi/ViL/mh63Ec+p/4ZAr9amMJTusxWloefIKm+4jHHUWqTFvQsjnko7reIKYk6QC+BNta55rJ5DpDEIOnnKVS2Ws= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: ee058122-8022-4a80-f556-08dbe5e4050f X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 14:06:10.5131 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: O0gGaxX4BIqwi2WRHAi7DsbX6MGO+ovYQ9g7Nskhb+7lX+2dJyzg8gWZRTuDedoU X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7007 The optimization of kreallocing the entire fwspec only works if the fwspec pointer is always stored in the dev->iommu. Since we want to change this remove the optimization and make the ids array a distinct allocation. Allow a single id to be stored inside the iommu_fwspec as a common case optimization. Reviewed-by: Jerry Snitselaar Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommu.c | 20 ++++++++++++-------- include/linux/iommu.h | 3 ++- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index f17a1113f3d6a3..18a82a20934d53 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -2931,8 +2931,7 @@ int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, if (!dev_iommu_get(dev)) return -ENOMEM; - /* Preallocate for the overwhelmingly common case of 1 ID */ - fwspec = kzalloc(struct_size(fwspec, ids, 1), GFP_KERNEL); + fwspec = kzalloc(sizeof(*fwspec), GFP_KERNEL); if (!fwspec) return -ENOMEM; @@ -2965,13 +2964,18 @@ int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids) return -EINVAL; new_num = fwspec->num_ids + num_ids; - if (new_num > 1) { - fwspec = krealloc(fwspec, struct_size(fwspec, ids, new_num), - GFP_KERNEL); - if (!fwspec) + if (new_num <= 1) { + if (fwspec->ids != &fwspec->single_id) + kfree(fwspec->ids); + fwspec->ids = &fwspec->single_id; + } else if (new_num > fwspec->num_ids) { + ids = krealloc_array( + fwspec->ids != &fwspec->single_id ? fwspec->ids : NULL, + new_num, sizeof(fwspec->ids[0]), + GFP_KERNEL | __GFP_ZERO); + if (!ids) return -ENOMEM; - - dev_iommu_fwspec_set(dev, fwspec); + fwspec->ids = ids; } for (i = 0; i < num_ids; i++) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index ec289c1016f5f2..e98a4ca8f536b7 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -798,7 +798,8 @@ struct iommu_fwspec { struct fwnode_handle *iommu_fwnode; u32 flags; unsigned int num_ids; - u32 ids[]; + u32 single_id; + u32 *ids; }; /* ATS is supported */ From patchwork Wed Nov 15 14:05:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13456778 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2159D28DDB; Wed, 15 Nov 2023 14:06:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="PuP9lH3K" Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 642BF101; Wed, 15 Nov 2023 06:06:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=BeFtZ2oBEnRSk6pcAbR9UPHhDr5buxBf6cvEHVlu+FXnmYmfe/iYVdIGA99I5QHCO7R3gPrCuLrlv2/BeC2csuuFOJeyn4RH10uVowqm0Sq3gmZRAQ6lCPMO4N6LsQfjMSLCMTDww0SLX1K7ejSn/cEhAqTuxoIzazPNOZUAe6Cy1nC9u52wWJBtRlzxr7zPR2OzuZo3jn3rjlvLB72xvKElY3SFy55YnfYd6J67Uv73weav8nAdF0uUUDykRIgSn2WYW0N775Z3ZsuG8MPDa/A4RBduIPHMn2yTph7JfyySkHvN0SbEVfRlxoLfXp5D85L0ZqpM7UU9Hh0ZpWY9RA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PmGfuwpBfs0ZJ2gl8sOhab20hFl7awpkh2gd4isoKzQ=; b=K9wD3KaVgC9JZIQLzdxksAqwqF3BIZJq4M5I8WX5q97rsGydI41DhvYAQ3yIu6/OsCLDv2irRq+k37z7PH1m3lwgaCtMpbXTB5jzx0Z416v2ara2fTnROvOo/JxBrgN/M/i2ecel87Cwk6BdyR6Od86qOaksK3dC8YPJy3ms2h7baX/L2K5nlAVnKDIQjSN7rXNogm7cRtlQ2wxYsPeYYIY5sVoPiWMLBNAHqtjx0u/jT4rVFeR3jDUZyZWrhtDNXT+D8rZyyZRJStF2wKvsPy7HoD1KSk8IEh6wbvVMGH2Cdd+bni3ZCWafntecBjO90YPUh9w3hSj5giOz1+jSEg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PmGfuwpBfs0ZJ2gl8sOhab20hFl7awpkh2gd4isoKzQ=; b=PuP9lH3K4NeaYY7XmJaMFKhttIWANqTx2kZKoNgXr/svmAO6+Wac2y8dTkIsa5bnub12R2timnIh7YL62LaBRqH0c80hN29y4W0O5Ui+E4F/Oa2gwWXutCOH2IxlRCSQffZvofCwgR/mzstYvJM0ek96fX/H5kF5KsOh+FsYEKJbbwCOc/d0eNJhIgT0Rcm+S+dfjDycp1w/64ZkvXAr9gm3JqP/k/Qbcn49Aainu297+iZEpMjPOnwUCi9elmsE1RMRpr2Qo+033hVaALrX1pixkmjQMrqyolY5qaZB7fGsEN+iQlmn5LOl5+6DUo01dKYqL4FYAaWESO5cHqQIAQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH8PR12MB6916.namprd12.prod.outlook.com (2603:10b6:510:1bd::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6977.31; Wed, 15 Nov 2023 14:06:19 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.6977.029; Wed, 15 Nov 2023 14:06:19 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Alyssa Rosenzweig , Albert Ou , asahi@lists.linux.dev, Catalin Marinas , Dexuan Cui , devicetree@vger.kernel.org, David Woodhouse , Frank Rowand , Hanjun Guo , Haiyang Zhang , iommu@lists.linux.dev, Jean-Philippe Brucker , Jonathan Hunter , Joerg Roedel , "K. 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Wysocki" , Rob Herring Subject: [PATCH v2 06/17] iommu: Add iommu_fwspec_alloc/dealloc() Date: Wed, 15 Nov 2023 10:05:57 -0400 Message-ID: <6-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> In-Reply-To: <0-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> References: X-ClientProxiedBy: BLAPR03CA0103.namprd03.prod.outlook.com (2603:10b6:208:32a::18) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH8PR12MB6916:EE_ X-MS-Office365-Filtering-Correlation-Id: 2479645a-7070-4d20-26fc-08dbe5e405e4 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qvQIGdIbnetbXvAiA6j+3d7hEfbp/uXG3r5kcdKULkMblPlrXKIFOwVQP9t/rKPABrYGjMjix5ugjbCXkl96xGpK2wTtA/yUqfZo+IonC2jVYU1S5jb+BCOfsTYiTb7qbkOGuqjbqHg2VNVABfJ3Zq4IvP3hxHHmybJy1qguxaqckyCJuD4NDl5xqHk0RUoUliB7562reBUgGw2umeCkbTCPItMC//APp+5ljbtyzouJB0OI7Ir68SDpGHif4agRSoWFaiX3P5O3wSYwX19KP/OYle6FJ+iSk5mWYSx1LnVpQibd/LfnZslIU/RN318tTMwA00cB5MgeoovdLtDCVZeLb6o6bICBha94K3mbVDQaVDG2EEOiCmIkL3N/B1bu0Gz+iNDIQZCrK1eMADzP5luY2/KXi3dBipRYZHu97UQe9JHImtMDKeDiKuAwlUrVPfoBBZXAFPXID8F/x4zBZ6t3hMc0fnMUM3vn7mXbwYhP1S6vinLT1YgOypZtNRB0O0OvIbCDkZ0UpzGdUedMGy0hB17fivOJ/EGQ86DkG26CEuSNRllW2M5xi+OJWfS8OOFByiUfnUxgNVWc9ggtMb2qmWmZduXyYl5Nmq3i74iqABgglDCLvwupU0JBCJb4 X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(39860400002)(376002)(346002)(396003)(366004)(136003)(230922051799003)(1800799009)(64100799003)(186009)(451199024)(66899024)(110136005)(316002)(66946007)(54906003)(66476007)(66556008)(6486002)(478600001)(6666004)(7366002)(86362001)(5660300002)(7406005)(7416002)(921008)(41300700001)(2906002)(36756003)(8676002)(4326008)(8936002)(2616005)(38100700002)(26005)(83380400001)(6506007)(6512007)(4216001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 9QkYoRJepClUNE4YNwnegy7f7IidUvmYAfAYOSdSy7dysEHSP0felu1PXoanGkz7+nSXJZ9HqW2IJsgPYAdePSfh3vAciROtKGZSQBQrbYKfujqCxqeJbxTyW4Np8xznCCF2mVpmo0txiEwqMkBsmkdEbkNcxFK9TTUQMrubUjbBhaJynE06eUVaqWGHW8UGUd0bS0sXVHwc7RiDSQB0GwR2CTvYdGju+7sY+DL+6n2W5DT+CEoSNs3xvlgU2BQ3i4EmLj8QjZ855YI1hHDGkr03XjuCllTw3PHDmIPyxn6/a5Sga3zi+pdDDhuC1Bh7j/ehKi2LcTTehdPNTa0dV+8nFj0gldU6vcX+c30nUNkF44OgwMvgnPHBgE9K9eyyO4atdwTfGPI3xbDce5QRDbSaH0K6Nv0d8Lrvve4P0KGKF9T83JqXMCL035Rlqbf30jGMA9P1jV03ZwZ8tmC/tVH5wP4ULFwaGVA6XzyiVyMOvef/pQGcI50OEMk/ECH+Moo0ICKyNIvEB47vG4Jn9qOCptXsxo93cOMGIzpEsTw6Wy8i/1Q+OzXeQE2iSVTYOU3cTAchjr9odB1QSI8p8HOzaOidAucJRAFG8xEfbqTAFc9j+or15tTP/8E+GxUpax+zCbCHX4njXeDKwmiK4wdEdrtPzWgHCHrDhT7QDXQYKxpQwp+93zc3f5J2vBWv68UnUERIzsrpnJ8+B1yszR2JPT2OD8PghJxKjgFev1r4XL+z9aQqByHgpuxdF9a7aDqumWLNAB1tBlnAlV8+eFeXFeoLglGeCYJ+4gQp+u6V2KyE8ghQM100IvoWIudCW6x4DipdLP5RUOkaHvvlYcjyWZq0pcCWqLOMKuZEe6BB4FLEggzV5PZuJeoUitKD/2cXavDPgyATzpuw1Q4tj+DSmL521DXdNFtQu62AXmpHK5rt/3+n12X1i1SgBoswC2LU+rocdIlqHwwvgJzqr5rysynFJebcl1lSKikE1+B4NUa7TJutp3nOpghYdClvwlq0QTY/1Fxs7bJQc/ElW8pjcwC6s6LSMsQ4jwpnrqAYKe4phGa6u+a/VD8cjUFDkgjZyLTULlLQgsW+bxYZDtzSfzDCNFpvsm+dNC/ADH4kDPQIZqaMTwj88p/NZd+y+uoDmwI9sO32Zt6H+34iWxRv2O2IexQLCJLBGAnH6NMD5FYr7ROBYt5qIFbKBzd4u1+kGaHCFrVNlwrq3KpsojvLmrYoCjqJddngHj3T9M/tZPodH0kX+kdn5u7a9z6oUuinvjMk8FqkhlUWm69oP+mEG4s/UxfXxQJpqx4NbcFwQsqJ6u9BGqgLNZXdCWImLv5CbvowUb3Rteb682oLZB+u3oKR0qp8jzFVdOq2PWYGi8FlzLGsyC94ktwcn9uzteiqfzYMrHbFAGFzMEqVYmkwpG66ZdMXsATXOqsTL3Fmtg0FDycC44fkqprQb/wNd6um6wfpaw1E2MroJEgGJV4gQhUGK8Vy6j9neXXXK45apLh8iZ0Lmy4fnpAbwLCn6yZnop7Dl9zJhdZSzjbbno7q3cUv2Bbne/jHEctu1tU= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2479645a-7070-4d20-26fc-08dbe5e405e4 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 14:06:11.9033 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: GBTxd3rAglNhCUI2cE+3v3noBNm3Tz+pgAZKI7bxEYyFvTT4dJKpeuq5pnMFjkgE X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6916 Allow fwspec to exist independently from the dev->iommu by providing functions to allow allocating and freeing the raw struct iommu_fwspec. Reflow the existing paths to call the new alloc/dealloc functions. Reviewed-by: Jerry Snitselaar Signed-off-by: Jason Gunthorpe Tested-by: Hector Martin --- drivers/iommu/iommu.c | 82 ++++++++++++++++++++++++++++++++----------- include/linux/iommu.h | 11 +++++- 2 files changed, 72 insertions(+), 21 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 18a82a20934d53..86bbb9e75c7e03 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -361,10 +361,8 @@ static void dev_iommu_free(struct device *dev) struct dev_iommu *param = dev->iommu; dev->iommu = NULL; - if (param->fwspec) { - fwnode_handle_put(param->fwspec->iommu_fwnode); - kfree(param->fwspec); - } + if (param->fwspec) + iommu_fwspec_dealloc(param->fwspec); kfree(param); } @@ -2920,10 +2918,61 @@ const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode) return ops; } +static int iommu_fwspec_assign_iommu(struct iommu_fwspec *fwspec, + struct device *dev, + struct fwnode_handle *iommu_fwnode) +{ + const struct iommu_ops *ops; + + if (fwspec->iommu_fwnode) { + /* + * fwspec->iommu_fwnode is the first iommu's fwnode. In the rare + * case of multiple iommus for one device they must point to the + * same driver, checked via same ops. + */ + ops = iommu_ops_from_fwnode(iommu_fwnode); + if (fwspec->ops != ops) + return -EINVAL; + return 0; + } + + if (!fwspec->ops) { + ops = iommu_ops_from_fwnode(iommu_fwnode); + if (!ops) + return driver_deferred_probe_check_state(dev); + fwspec->ops = ops; + } + + of_node_get(to_of_node(iommu_fwnode)); + fwspec->iommu_fwnode = iommu_fwnode; + return 0; +} + +struct iommu_fwspec *iommu_fwspec_alloc(void) +{ + struct iommu_fwspec *fwspec; + + fwspec = kzalloc(sizeof(*fwspec), GFP_KERNEL); + if (!fwspec) + return ERR_PTR(-ENOMEM); + return fwspec; +} + +void iommu_fwspec_dealloc(struct iommu_fwspec *fwspec) +{ + if (!fwspec) + return; + + if (fwspec->iommu_fwnode) + fwnode_handle_put(fwspec->iommu_fwnode); + kfree(fwspec); +} + int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, const struct iommu_ops *ops) { struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + int ret; if (fwspec) return ops == fwspec->ops ? 0 : -EINVAL; @@ -2931,29 +2980,22 @@ int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, if (!dev_iommu_get(dev)) return -ENOMEM; - fwspec = kzalloc(sizeof(*fwspec), GFP_KERNEL); - if (!fwspec) - return -ENOMEM; + fwspec = iommu_fwspec_alloc(); + if (IS_ERR(fwspec)) + return PTR_ERR(fwspec); - of_node_get(to_of_node(iommu_fwnode)); - fwspec->iommu_fwnode = iommu_fwnode; fwspec->ops = ops; + ret = iommu_fwspec_assign_iommu(fwspec, dev, iommu_fwnode); + if (ret) { + iommu_fwspec_dealloc(fwspec); + return ret; + } + dev_iommu_fwspec_set(dev, fwspec); return 0; } EXPORT_SYMBOL_GPL(iommu_fwspec_init); -void iommu_fwspec_free(struct device *dev) -{ - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - - if (fwspec) { - fwnode_handle_put(fwspec->iommu_fwnode); - kfree(fwspec); - dev_iommu_fwspec_set(dev, NULL); - } -} -EXPORT_SYMBOL_GPL(iommu_fwspec_free); int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids) { diff --git a/include/linux/iommu.h b/include/linux/iommu.h index e98a4ca8f536b7..c7c68cb59aa4dc 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -813,9 +813,18 @@ struct iommu_sva { struct iommu_domain *domain; }; +struct iommu_fwspec *iommu_fwspec_alloc(void); +void iommu_fwspec_dealloc(struct iommu_fwspec *fwspec); + int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, const struct iommu_ops *ops); -void iommu_fwspec_free(struct device *dev); +static inline void iommu_fwspec_free(struct device *dev) +{ + if (!dev->iommu) + return; + iommu_fwspec_dealloc(dev->iommu->fwspec); + dev->iommu->fwspec = NULL; +} int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids); const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode); From patchwork Wed Nov 15 14:05:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13456775 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FA3628DB8; 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Wysocki" , Rob Herring Subject: [PATCH v2 07/17] iommu: Add iommu_probe_device_fwspec() Date: Wed, 15 Nov 2023 10:05:58 -0400 Message-ID: <7-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> In-Reply-To: <0-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> References: X-ClientProxiedBy: BLAPR03CA0109.namprd03.prod.outlook.com (2603:10b6:208:32a::24) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH8PR12MB6916:EE_ X-MS-Office365-Filtering-Correlation-Id: c586f63e-b4e6-4a6a-8d98-08dbe5e40589 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BXUf/SmFrdNP2K0nUEx7X6+NljQ4IDKHlXRa90X1IrI6XtdPIpKWzQtYndq7l7KzSyervLlnXUW5sLUVBila/Lp8mITk417Uv7wCwOl5krNtGLEnanWEp3ltm2Kha8JXbU8ume7fZjrHdn3qn/lIUmYJRLSGXfy+DyIDKGKZxSw+9/c63Lxyhw48q8ia1PUPmcg4AvzZ0kAgsmU5feb2wfC5TUEIqRAlfnuxSvWQntY9eOIyhEvIKB2mtrPHw4k9y77O8j3VQ81AQApfIcrd0IR3aZb876ALrTEUeVZ+I794BmuV7oQA/AfxN5LSAO0DL2lSd3Qa9RJ3iEujWgbuEt7EtHC0Gr6CreOq2hsYwVPuxxPtMLRZhN5CMMpV7KC/Urg4doNcIp1oCi5PBRRosOqywB5rhVaiX8/ykDTBpdWoDDkk2G4B2bDhqIqOQkgWOA5ze7dz5ylO3kfr0myZohnMRNpDwqKnAm4W37q9fIiBqgODxr7xw+0YyxOL5/9lIVEsAaDSx2aYlLBfJbQHfMi4jFNB2qPI+DLGF0oLWsyOHoU1F3AbSTlC6V1fhxSj6kTEofENIYdJ8p1ApuABzMjvvnd0aYFAbIXdTZhLDIhmVPhmkEVJ0dtYxa9LwU6V X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(39860400002)(376002)(346002)(396003)(366004)(136003)(230922051799003)(1800799009)(64100799003)(186009)(451199024)(66899024)(110136005)(316002)(66946007)(54906003)(66476007)(66556008)(6486002)(478600001)(6666004)(7366002)(86362001)(5660300002)(7406005)(7416002)(921008)(41300700001)(2906002)(36756003)(8676002)(4326008)(8936002)(2616005)(38100700002)(26005)(83380400001)(6506007)(6512007)(4216001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: XrtZQZHWMD8kqqPCvKpXuD3uzmrOhjTHtoZoSwZ5gbClYeMNtSVsaLw98QgKfy/NQ2etUkmvvZXqMyYB3VEx0GUob6tpRigD8LLkm02A1r2m0+9K3oTBfh9l7EfCQOWDCQanLAiTjpJhcMrnieGhzDNH8MN1npg36hsvjoH472UKgW6bob62cp6Mts8GooSDvKztNFgzdfOwKk0tDQ/nLA0QsDS6fkKCmW8flNeySGXd+zd1vhsuQRViTEyBmxj0D/UDZUzGZFT55t7MAJfyY3oohUj3KCTmRFdNumrQtN4K75eLZq3tYn7FfjgqgnTZXWjH/Hxpyfp1xLoEBM/WVBB+Sd01U0xldVIBHcue5OeOzJSMi8RDGPHubK4D+du/QcCGFHPJ/ARlQ2ENEXGWUbRRFNpkfwhtSxkqZ6mM71i5QtVbmIjfBqWLYvqZ+qkvwdzZ4sC008iOAdMm/LYTvuKUYoIQ1M/T1zoBaRYM1ljH55lLDzJNVAUZ3SETnyLfdFBP6e8efv6ISgd5wV5gKLytBvLIAC135oZ05yrlzE7uvfI7Fz3syGV/fpmnolMN/YISgdPkYzTNB9dSwxxFJ0nYSs2IHKuoaVDNQcor0SYvxSKLz8Uh3MKKfUrfBD3cdh+sfJifJahKbxUg1yhyP8w33jZQYgKUOXICZEB74c6JWtcZyAnduJjaSf7yxUfwnqtg/m5LxCtvDGGHxF5PXlVh6nAMkHiaHV5BiCAUNF0smYPI7Z7hj/pwBN8JHbHc915moEtl1Fj56WhCzRCWVj7lXoB8SzMHChOmMEIgPPS5fRT2dF4HzH0e/dWu20QMQln2dg54VKfOW/OVikvs+xGjiQOIgYUzB3ZwP3569jNZY4X0/oSdockUrs+rn0j3jOl+1KNdT/giQobMl1JE+VR/VLp7aoJHSKIJJD5Z0ahtmMiO3j5HuzHFIsysbkNSqerBvZ4zMDvHjtnfoZHxxinNs/RKeAWzAMtty+3NPadoK0/jLja+QetlUvOp6SlelTiXzwLwZ7dt1POJ3NkPHBu21TItpI6O4WphAefIomAHbMFx+zxq/c9JnYsFGPGpne9PzBhm+N1MiRji4kGQKL7ayZqDvPl8vWadgQp7M/2/0VO5F0uf3nysY/J1x0p/X0+MRWHlB89S0pBb/H1l47HE2CxCfcQGaoq8LYoXmLiU4MAZsxp0GRe2BTb1h7SRbAJLQlrI8qQHOMMQijGmbGFJWFAe9O74X1vm1TFhQwh37dti2mSW0UqCszJH6+neixbsf+sWC4PVo/G/VW8lSuz8ha1c59QXYFI6iQEUwFon0etZ8Ztge5nLebh1GX4Wtmpv4egtt0Vzfcbh3K9HIIBbP5Cknuoa+T8CJc/BaMZLTwyWE4K6p1sX8WgPz5nJMgyrDS9YYyAivsK5Ok7LxEp0dC+LDOp2HQ+3Ny1QdSdy6XN/LQdm1SCyUhrqr0iiRf3CwU+z3RmL2mxQnTKl+H+FW3IdiEWMA3VN//ez7pwfV7WeF5WfDRjrAZqD4oP0UoOzjeLK7y2Ox3ylmu1i1rp9K0DT7os9h5MQ35C/4V8= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: c586f63e-b4e6-4a6a-8d98-08dbe5e40589 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 14:06:11.4212 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: IPMsRct3UdXDK1DMpHB9irJ5Gk+20sJiuiyAslPXmjUm74Z8hFSYc1wTQrTjuWH/ X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6916 Instead of obtaining an iommu_fwspec from dev->iommu allow a caller allocated fwspec to be passed into the probe logic. To keep the driver ops APIs the same the fwspec is stored in dev->iommu under the iommu_probe_device_lock. If a fwspec is available use it to provide the ops instead of the bus. The lifecycle logic is a bit tortured because of how the existing driver code works. The new routine unconditionally takes ownership, even for failure. This could be simplified we can get rid of the remaining iommu_fwspec_init() callers someday. Reviewed-by: Jerry Snitselaar Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommu.c | 53 +++++++++++++++++++++++++++++++------------ include/linux/iommu.h | 6 ++++- 2 files changed, 44 insertions(+), 15 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 86bbb9e75c7e03..667495faa461f7 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -386,16 +386,24 @@ static u32 dev_iommu_get_max_pasids(struct device *dev) /* * Init the dev->iommu and dev->iommu_group in the struct device and get the - * driver probed + * driver probed. Take ownership of fwspec, it always freed on error + * or freed by iommu_deinit_device(). */ -static int iommu_init_device(struct device *dev, const struct iommu_ops *ops) +static int iommu_init_device(struct device *dev, struct iommu_fwspec *fwspec, + const struct iommu_ops *ops) { struct iommu_device *iommu_dev; struct iommu_group *group; int ret; - if (!dev_iommu_get(dev)) + if (!dev_iommu_get(dev)) { + iommu_fwspec_dealloc(fwspec); return -ENOMEM; + } + + if (dev->iommu->fwspec && dev->iommu->fwspec != fwspec) + iommu_fwspec_dealloc(dev->iommu->fwspec); + dev->iommu->fwspec = fwspec; if (!try_module_get(ops->owner)) { ret = -EINVAL; @@ -483,16 +491,17 @@ static void iommu_deinit_device(struct device *dev) dev_iommu_free(dev); } -static int __iommu_probe_device(struct device *dev, struct list_head *group_list) +static int __iommu_probe_device(struct device *dev, + struct iommu_fwspec *caller_fwspec, + struct list_head *group_list) { - const struct iommu_ops *ops = dev->bus->iommu_ops; + struct iommu_fwspec *fwspec = caller_fwspec; + const struct iommu_ops *ops; struct iommu_group *group; static DEFINE_MUTEX(iommu_probe_device_lock); struct group_device *gdev; int ret; - if (!ops) - return -ENODEV; /* * Serialise to avoid races between IOMMU drivers registering in * parallel and/or the "replay" calls from ACPI/OF code via client @@ -502,13 +511,25 @@ static int __iommu_probe_device(struct device *dev, struct list_head *group_list */ mutex_lock(&iommu_probe_device_lock); - /* Device is probed already if in a group */ - if (dev->iommu_group) { - ret = 0; + if (!fwspec && dev->iommu) + fwspec = dev->iommu->fwspec; + if (fwspec) + ops = fwspec->ops; + else + ops = dev->bus->iommu_ops; + if (!ops) { + ret = -ENODEV; goto out_unlock; } - ret = iommu_init_device(dev, ops); + /* Device is probed already if in a group */ + if (dev->iommu_group) { + ret = 0; + iommu_fwspec_dealloc(caller_fwspec); + goto out_unlock; + } + + ret = iommu_init_device(dev, fwspec, ops); if (ret) goto out_unlock; @@ -566,12 +587,16 @@ static int __iommu_probe_device(struct device *dev, struct list_head *group_list return ret; } -int iommu_probe_device(struct device *dev) +/* + * Ownership of fwspec always transfers to iommu_probe_device_fwspec(), it will + * be free'd even on failure. + */ +int iommu_probe_device_fwspec(struct device *dev, struct iommu_fwspec *fwspec) { const struct iommu_ops *ops; int ret; - ret = __iommu_probe_device(dev, NULL); + ret = __iommu_probe_device(dev, fwspec, NULL); if (ret) return ret; @@ -1820,7 +1845,7 @@ static int probe_iommu_group(struct device *dev, void *data) struct list_head *group_list = data; int ret; - ret = __iommu_probe_device(dev, group_list); + ret = __iommu_probe_device(dev, NULL, group_list); if (ret == -ENODEV) ret = 0; diff --git a/include/linux/iommu.h b/include/linux/iommu.h index c7c68cb59aa4dc..ca86cd3fe50a82 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -855,7 +855,11 @@ static inline void dev_iommu_priv_set(struct device *dev, void *priv) dev->iommu->priv = priv; } -int iommu_probe_device(struct device *dev); +int iommu_probe_device_fwspec(struct device *dev, struct iommu_fwspec *fwspec); +static inline int iommu_probe_device(struct device *dev) +{ + return iommu_probe_device_fwspec(dev, NULL); +} int iommu_dev_enable_feature(struct device *dev, enum iommu_dev_features f); int iommu_dev_disable_feature(struct device *dev, enum iommu_dev_features f); From patchwork Wed Nov 15 14:05:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13456774 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 311C224218; Wed, 15 Nov 2023 14:06:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Mx5OC8Cq" Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF6A4E7; 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Wysocki" , Rob Herring Subject: [PATCH v2 08/17] iommu/of: Do not use dev->iommu within of_iommu_configure() Date: Wed, 15 Nov 2023 10:05:59 -0400 Message-ID: <8-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> In-Reply-To: <0-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR10CA0009.namprd10.prod.outlook.com (2603:10b6:208:120::22) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH8PR12MB6916:EE_ X-MS-Office365-Filtering-Correlation-Id: 4b546f9f-75a5-40b1-de54-08dbe5e40559 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: G6AMEZMitEvuaiglcTrwQIg/qcWtzDKp/3NTt0iKX4S/QPpuEm7UCf4O7xK/X9/MYvEW7hGdtcmwRvRWQ1qo4oA8Z6/GiWl81qByLjhIbdsO1TYEMCqYKFnYu2oo/j+csefd00ijBma24Kj8VpohyTCnEoqtF5+Nk5GvYe421x1we25+5ST94BW7fe3pzCByCmlPq3yt2kCKeDxDeT+ZRQSt6hbm9S3OZqODbEKHJzn+vgtk/ilozM4X20upylFnhwmOsurBjisQhpo0j+oLHF6GnBG8hrif5s7ijjzgldZd3d14vypzpsXmQfh60vCikvRWKU/OnUdsv3MDQhJiW/MWkTaAteM2P+qyq1MLMVndJsPt7JvSvcQxfIlPFKDqzggRl4ZjUtQV9ItaY0AXzymyVkXiXoz2i1lZbTpRX8M7dEj19jaSMR4CcreK6+LExwN5//hiRkTxSpMtkFC/Uj/xmLOKLdBOqC6JUULId8JJZnuaRZ3eLn7UadWEdEGm/p+e1hnd/4gBWIYbvl/poIlA6UwLcL7HWDgy3lgyx120KzvcADJTA7C/jTSKpJ/DlFUo95tPaFjEGfiLmsCK9IyTVRXHBun/pIEBxhLfFwCeljii8KQWoFlPf7MXEljY X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(39860400002)(376002)(346002)(396003)(366004)(136003)(230922051799003)(1800799009)(64100799003)(186009)(451199024)(66899024)(110136005)(316002)(66946007)(54906003)(66476007)(66556008)(6486002)(478600001)(6666004)(7366002)(86362001)(5660300002)(7406005)(7416002)(921008)(41300700001)(2906002)(36756003)(8676002)(4326008)(8936002)(2616005)(38100700002)(26005)(83380400001)(6506007)(6512007)(4216001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: u9H+duPL6lk0TD2IL8f0Z/ZYWd6OEapJOGkD9V8aULhQXjMGHrXIrCbKtoruqObCPKS+bDMxTOCkY3zYdLv5/2lljnBg+CL4O2M8Jksslxs7bpJJjGhXmgwUdQ6t+FU/l4Sj93BcLiVFLF8AYwzbJDQu2sDJ+y8ihV283GkvIc1bay/Tb6yS05EycEqR1TASehYh18stm1OqK20S1u2QVtjOKuyX4vEWyixgwMqrp3R0Ws3Wb5YE7SFkWwxy2wu9Wt8GhPplmGRGcacS4NHJVl+T6FeROCqswaoS9hr6BNl1TlIH9k5mOvNWAHxIVzc8slG846M/lSOASBfLjvpEFp1X7hv9XRpzsm/Wc+Ooi02D6/0Zg8vObXD7f8Q8314HeNLiOhGQ9hm+dFTvSeDfdlDAnWkXaaiVbSFychrb9b0zlpr+e5w0teGRj4Y9IZKmtI9m+bPWdiATL1UuhSckGedO8W/goNtOrbpMJHCmVB+3Y78PYTN4qm9uygW3S8xT8IIib63kteWUuy8PinPh0GJDqbPEbsMHDxcLmc3wmc2cLOY+MAR17v7OC0gA6CW+uA6btX2IqT1KN6Btb0GYUMDtXHzcuC4MjuVz5ffdc1fvjayZYriRnzByMCTI1EVHAsw8FuPtVpSwmTDaVoODFHIahws0q+xMbYsngETrhE7aObzNOEbkF46e/Qb3qM5UOOs6IZhOH9fFxhuHFqK0luHFEWr0gTabFhybeLOjpnZhyNuAsL12b3WJGCcU7Sndth3gSUXgEV7pOwvcQNadIruWiypN9DfOhNIbhrkx8puLFU2nxXiOPmG7Edw4FVWFk5c0hxs6rZDjSOn9uYyOu8O7xz+R8DtuH+rl7RaEk320cyj9PQI1wBJ7pkTd+LiBnBGfV78JNS/wpw2gN5IrbQaI1fZwmLlTEEsE8D465aXRostPQnQiTPnkk0S7+7ii25THyHJZK0MYgV4gcRm/q7Pf2m1XVUeNS2GZVsF/52tkyYdEd8iCdLYMIVwIIDfaZZo1BqCUUCOCX/fTmBE1q+52UV7CosA6j+SBidDs5PGsUjF3mGQijDXXAWXoXkeGaghQDs3uus14nuwQt5NHn+7z2BHuL8M0hI8WaYRRAu2LBe528x1QzDXhSBGVnfBYVML7cJS22sovaVmP6RwiUuP72kCfxMkgRe69TBdViJaLXzeeNH2IYANS8fDV97fvlqDkkGkrzJbGc5+riH1iPl6ZtvR5upR7RI1+s1n2rSK4EEg1bMQIhW/AWW5GcgEkgTbFvYBybJzCflt/3BDq+gNq7wto6l0VaBrlCZoSKHyVSj0uKsau+7myQ+IiDioE4oFGHpsj5uY1RPLOnm6W6nEy/oAyGlHOgrOUClUevycjKL4CiL9xyiBtc8r3BRukf0G/iD6/9H8COynw+85c3QZVVa03HLSCSgRWSU6wEv/ApgewUtRDJ6hWOjcuuW/x2a0YJoEHOLycSepfVlV5b6aaW/8ndG0OBPx4Icrm/exyBIuRWsNcm2AkRZROArLY8qfXKkZsJV1dAgXHgb5zPxDd7K91rF2M/kyOPK1k3x0= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4b546f9f-75a5-40b1-de54-08dbe5e40559 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 14:06:11.1656 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: wBQdEHb0DsdPChlKoXRg7HRrAXEqsVp+aFmehwFP3AdGiVBCmcRmM38CeHfhb59C X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6916 This call chain is using dev->iommu->fwspec to pass around the fwspec between the three parts (of_iommu_configure(), of_iommu_xlate(), iommu_probe_device()). However there is no locking around the accesses to dev->iommu, so this is all racy. Allocate a clean, local, fwspec at the start of of_iommu_configure(), pass it through all functions on the stack to fill it with data, and finally pass it into iommu_probe_device_fwspec() which will load it into dev->iommu under a lock. Move the actual call to ops->of_xlate into the core code under iommu_fwspec_of_xlate(). Reviewed-by: Jerry Snitselaar Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommu.c | 29 ++++++++++++++ drivers/iommu/of_iommu.c | 82 +++++++++++++++++----------------------- include/linux/iommu.h | 3 ++ 3 files changed, 67 insertions(+), 47 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 667495faa461f7..108922829698e9 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -2973,6 +2973,35 @@ static int iommu_fwspec_assign_iommu(struct iommu_fwspec *fwspec, return 0; } +int iommu_fwspec_of_xlate(struct iommu_fwspec *fwspec, struct device *dev, + struct fwnode_handle *iommu_fwnode, + struct of_phandle_args *iommu_spec) +{ + int ret; + + ret = iommu_fwspec_assign_iommu(fwspec, dev, iommu_fwnode); + if (ret) + return ret; + + if (!fwspec->ops->of_xlate) + return -ENODEV; + + if (!dev_iommu_get(dev)) + return -ENOMEM; + + /* + * ops->of_xlate() requires the fwspec to be passed through dev->iommu, + * set it temporarily. + */ + if (dev->iommu->fwspec && dev->iommu->fwspec != fwspec) + iommu_fwspec_dealloc(dev->iommu->fwspec); + dev->iommu->fwspec = fwspec; + ret = fwspec->ops->of_xlate(dev, iommu_spec); + if (dev->iommu->fwspec == fwspec) + dev->iommu->fwspec = NULL; + return ret; +} + struct iommu_fwspec *iommu_fwspec_alloc(void) { struct iommu_fwspec *fwspec; diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index a68a4d1dc0725c..e611cb7455417f 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -17,40 +17,19 @@ #include #include -static int of_iommu_xlate(struct device *dev, +static int of_iommu_xlate(struct iommu_fwspec *fwspec, struct device *dev, struct of_phandle_args *iommu_spec) { - const struct iommu_ops *ops; - struct fwnode_handle *fwnode = &iommu_spec->np->fwnode; - int ret; - - ops = iommu_ops_from_fwnode(fwnode); - if ((ops && !ops->of_xlate) || - !of_device_is_available(iommu_spec->np)) + if (!of_device_is_available(iommu_spec->np)) return -ENODEV; - ret = iommu_fwspec_init(dev, &iommu_spec->np->fwnode, ops); - if (ret) - return ret; - /* - * The otherwise-empty fwspec handily serves to indicate the specific - * IOMMU device we're waiting for, which will be useful if we ever get - * a proper probe-ordering dependency mechanism in future. - */ - if (!ops) - return driver_deferred_probe_check_state(dev); - - if (!try_module_get(ops->owner)) - return -ENODEV; - - ret = ops->of_xlate(dev, iommu_spec); - module_put(ops->owner); - return ret; + return iommu_fwspec_of_xlate(fwspec, dev, &iommu_spec->np->fwnode, + iommu_spec); } -static int of_iommu_configure_dev_id(struct device_node *master_np, - struct device *dev, - const u32 *id) +static int of_iommu_configure_dev_id(struct iommu_fwspec *fwspec, + struct device_node *master_np, + struct device *dev, const u32 *id) { struct of_phandle_args iommu_spec = { .args_count = 1 }; int err; @@ -61,12 +40,13 @@ static int of_iommu_configure_dev_id(struct device_node *master_np, if (err) return err; - err = of_iommu_xlate(dev, &iommu_spec); + err = of_iommu_xlate(fwspec, dev, &iommu_spec); of_node_put(iommu_spec.np); return err; } -static int of_iommu_configure_dev(struct device_node *master_np, +static int of_iommu_configure_dev(struct iommu_fwspec *fwspec, + struct device_node *master_np, struct device *dev) { struct of_phandle_args iommu_spec; @@ -75,7 +55,7 @@ static int of_iommu_configure_dev(struct device_node *master_np, while (!of_parse_phandle_with_args(master_np, "iommus", "#iommu-cells", idx, &iommu_spec)) { - err = of_iommu_xlate(dev, &iommu_spec); + err = of_iommu_xlate(fwspec, dev, &iommu_spec); of_node_put(iommu_spec.np); idx++; if (err) @@ -88,6 +68,7 @@ static int of_iommu_configure_dev(struct device_node *master_np, struct of_pci_iommu_alias_info { struct device *dev; struct device_node *np; + struct iommu_fwspec *fwspec; }; static int of_pci_iommu_init(struct pci_dev *pdev, u16 alias, void *data) @@ -95,14 +76,16 @@ static int of_pci_iommu_init(struct pci_dev *pdev, u16 alias, void *data) struct of_pci_iommu_alias_info *info = data; u32 input_id = alias; - return of_iommu_configure_dev_id(info->np, info->dev, &input_id); + return of_iommu_configure_dev_id(info->fwspec, info->np, info->dev, + &input_id); } -static int of_iommu_configure_device(struct device_node *master_np, +static int of_iommu_configure_device(struct iommu_fwspec *fwspec, + struct device_node *master_np, struct device *dev, const u32 *id) { - return (id) ? of_iommu_configure_dev_id(master_np, dev, id) : - of_iommu_configure_dev(master_np, dev); + return (id) ? of_iommu_configure_dev_id(fwspec, master_np, dev, id) : + of_iommu_configure_dev(fwspec, master_np, dev); } /* @@ -115,19 +98,15 @@ static int of_iommu_configure_device(struct device_node *master_np, int of_iommu_configure(struct device *dev, struct device_node *master_np, const u32 *id) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct iommu_fwspec *fwspec; int err; if (!master_np) return -ENODEV; - if (fwspec) { - if (fwspec->ops) - return 0; - - /* In the deferred case, start again from scratch */ - iommu_fwspec_free(dev); - } + fwspec = iommu_fwspec_alloc(); + if (IS_ERR(fwspec)) + return PTR_ERR(fwspec); /* * We don't currently walk up the tree looking for a parent IOMMU. @@ -138,27 +117,36 @@ int of_iommu_configure(struct device *dev, struct device_node *master_np, struct of_pci_iommu_alias_info info = { .dev = dev, .np = master_np, + .fwspec = fwspec, }; pci_request_acs(); err = pci_for_each_dma_alias(to_pci_dev(dev), of_pci_iommu_init, &info); } else { - err = of_iommu_configure_device(master_np, dev, id); + err = of_iommu_configure_device(fwspec, master_np, dev, id); } if (err == -ENODEV || err == -EPROBE_DEFER) - return err; + goto err_free; if (err) goto err_log; - err = iommu_probe_device(dev); - if (err) + err = iommu_probe_device_fwspec(dev, fwspec); + if (err) { + /* + * Ownership for fwspec always passes into + * iommu_probe_device_fwspec() + */ + fwspec = NULL; goto err_log; + } return 0; err_log: dev_dbg(dev, "Adding to IOMMU failed: %pe\n", ERR_PTR(err)); +err_free: + iommu_fwspec_dealloc(fwspec); return err; } diff --git a/include/linux/iommu.h b/include/linux/iommu.h index ca86cd3fe50a82..cea65461eed01c 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -815,6 +815,9 @@ struct iommu_sva { struct iommu_fwspec *iommu_fwspec_alloc(void); void iommu_fwspec_dealloc(struct iommu_fwspec *fwspec); +int iommu_fwspec_of_xlate(struct iommu_fwspec *fwspec, struct device *dev, + struct fwnode_handle *iommu_fwnode, + struct of_phandle_args *iommu_spec); int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, const struct iommu_ops *ops); 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Wysocki" , Rob Herring Subject: [PATCH v2 09/17] iommu: Add iommu_fwspec_append_ids() Date: Wed, 15 Nov 2023 10:06:00 -0400 Message-ID: <9-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> In-Reply-To: <0-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR10CA0023.namprd10.prod.outlook.com (2603:10b6:208:120::36) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|SJ0PR12MB7007:EE_ X-MS-Office365-Filtering-Correlation-Id: 33ad3f50-13aa-4549-3376-08dbe5e404cd X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rIiay2NCxliPyHXv5Jhwhak+QEYovlcgLHri+HBj/lqJ/Huss/R/N+al8tHiQlnRxqXZ4NjfGZZ1MGBHqDkiXDID+E2AsjzbvJ0xS62Lh1HW6UzqCLB9Lgm4QbsDmf2h8Amr6QRrlaIbb0AM/5b9iB4IMWFBEPfCZjaNedLZyuegJKMljY02boJWIjoUUsU0JHj9dwHU/O2efZGC5uRC9BNEpCyJ+5kDIV4+6cALC1V1wMVbvvdua1kmzgU/mjcbDzFVoZM7eLvIuw0EUCmCoRsBGlRuT3L9JcOA0D+HAfEX1NHPPAiUXi02ERy/jLWGZ/uRkgsbzWxr/g43yu5SWbX6zY8CRjEal58+yVQSApnopIx9tSW7T0ksl5QBVbgnLu5cS0bmXEM5MJ5HgOgKLCpFFSzOZsCHphdbPx7ouCWP/8bVlx2wPd7YgzVHf/Lp7hv1X5RFtxZSNjo0N+KpgtYJ3dECigyW7h6Na1w7zNpqiRPmWEhPmt9O43Wr1sJu4uQzBgeyCiytVt89+qgrBLGdxJa/OohzQftSkI4F1Liiv+ene+PXlCNLvQlFuG7ZwHl5BVF7nj1kEc+lkctetXSVRBpsB0FxsmSwkppW+dBQ8+iUnWCiTTSRuwg3QRCS X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(136003)(346002)(376002)(366004)(39860400002)(396003)(230922051799003)(451199024)(1800799009)(186009)(64100799003)(7406005)(6666004)(6506007)(2616005)(6512007)(83380400001)(7416002)(41300700001)(8676002)(5660300002)(4326008)(7366002)(8936002)(478600001)(2906002)(6486002)(66476007)(54906003)(110136005)(66946007)(66556008)(316002)(86362001)(36756003)(38100700002)(26005)(921008)(4216001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: TTFO2FTfQnEJbkqUqgYbWqZACAHaI36v/Mm2uGf08oXgabC3v+jwv8d67nHdAGcRYgqwdzavYTohdSde8add8Cniz6YcYsP3B2xnbxUmQ0ZfTSZl6Qs/ZzxX/ZuAx2qUjcf0pVOFzNFmUSZh1osEH5TTpnnzvt10njccKIWtoIpEYik9uHI4k1GQljoclmXJ7VkQEyIhbNsugDM3sJhBnt0X93RZnlCKphPwinIvXZ2IgVseiwmtaOADV9FMyA4eZtDmE6wa3ZWQmEiDgiHra+OibjOktslUo8R/6eMmYmNyoHESHZK0D/55ITnl1W5q/JbRt1wP1l8eiHhZrFtN31wZTPFYBFvPgXynD0sKbNl/C5p2LtFsze0WvZXAOuT17WE0K4HSp2xUzfb13uu3Hnu90EmBs8hWQ/4ZWX8QTLb6Ps8kqB2HjfABJrBP3NYJdvP73/nEM5J65TgsWWQyi/1V4/1tJt958Cj9CQNp684igGyd71fLVz2EfIZ/wPLMqyoekCsVqd+tadKqTiypO2yjtmZwFNyvHXStdTTwj/Mlh4S8A4tF5TxjIDXCKuusIp/Da2ltYuzhoDvFf1GkiS0fiz6V8iecQEVFVuvig8EEov4BAIQXDNaTyqS4DvhBCVBgBL6jmiTJjQnPOmMauZUBJGFjgnRATmxEmAQkbsEzsw9bz7hoHYqCNiax2V91jg4DLxegJJKv1mhIJ2VF+2ns8yeZAG/V3glnuNXFZzshR+iK83F/Z/U3QCfgoe+qg5+1Smg1ncvLrGMK9H+GnOdC9eBVpezTXZ2II6yo2VIELmOiXh24MrzLrihdJ4RuNuI3QUha+Gwrs8+Rz+8sCt4Lv2j0s47CS/6PYQHifEH73rlh+nZK0LSizFKCigzoEeAa7XT5v61rf0grKRzxmagxJhHtAgSnJLKTST+GPtUowW34KApl9Ybfb8xXHj/S5sYJ/RfgHacngV5F2gBqBXhw9jo7AH7/wVyuDvCXsYjGIw1FYw4KBK5wPGIsBTdJtLTzZszzx993+7GNi3KRK3mmqdm335PPtw1NjDuYWiBTS/CmtYd2AOP7lV0wbi5aVN1kKCbcCeioel+9jLxOq/A1P8TVIaaAwbVDYXm+QP/02jxzi4FA/ulgFhvgndOLuaRmWXI2qNU8n/hw74IaHdJEoW5gRXoXkZLwoPvINkfM/jrvqpz8jiJpZ7vvO7sm+DR6WN32xst7e0VyAHpPF6yu6eam9LA6IX3fw/hHZohNg/3Ak2l397wYy4zyIE2jVgSazZ33O87Av2W/Ann2dMkYtVXSXZbWvxEacjC4V3Ge8sZQBNBXswryKZDwPrvBYiDr/NYINsog0m6CJpGsKs6LBtfHVbxoadD41dS8tScxnDJB8baLbNCHf9ImN8N9zeD+yuI7VOrGLm0LPc+ISTvgHbR/9RoJkV3ksB/JAKadbwNg2153ZRkgM2/90mirwJJizPT34lEkXQAFHGJghio9vqjoMgTw5ofzgI6EJA2628yJRJNs20dsTgdiFPGX5ekdtjFy2ed6k71oFX45gPSLsob8LQfscJp2mPEnIDE= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 33ad3f50-13aa-4549-3376-08dbe5e404cd X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 14:06:10.1118 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: UUFWjpVht75NL7joEA7Pd7bn/x6kguLYegv2d8j4HF4nChVq2doVAG4uHXBIIK6V X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7007 This is a version of iommu_fwspec_add_ids() that takes in the fwspec as an argument instead of getting it through dev->iommu. Reviewed-by: Jerry Snitselaar Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommu.c | 17 +++++++++++------ include/linux/iommu.h | 1 + 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 108922829698e9..2076345d0d6653 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -3050,15 +3050,10 @@ int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, } EXPORT_SYMBOL_GPL(iommu_fwspec_init); - -int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids) +int iommu_fwspec_append_ids(struct iommu_fwspec *fwspec, u32 *ids, int num_ids) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); int i, new_num; - if (!fwspec) - return -EINVAL; - new_num = fwspec->num_ids + num_ids; if (new_num <= 1) { if (fwspec->ids != &fwspec->single_id) @@ -3080,6 +3075,16 @@ int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids) fwspec->num_ids = new_num; return 0; } +EXPORT_SYMBOL_GPL(iommu_fwspec_append_ids); + +int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids) +{ + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + + if (!fwspec) + return -EINVAL; + return iommu_fwspec_append_ids(fwspec, ids, num_ids); +} EXPORT_SYMBOL_GPL(iommu_fwspec_add_ids); /* diff --git a/include/linux/iommu.h b/include/linux/iommu.h index cea65461eed01c..bbbba7d0a159ba 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -830,6 +830,7 @@ static inline void iommu_fwspec_free(struct device *dev) } int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids); const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode); +int iommu_fwspec_append_ids(struct iommu_fwspec *fwspec, u32 *ids, int num_ids); static inline struct iommu_fwspec *dev_iommu_fwspec_get(struct device *dev) { From patchwork Wed Nov 15 14:06:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13456739 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41BEB2511F; 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Wysocki" , Rob Herring Subject: [PATCH v2 10/17] acpi: Do not use dev->iommu within acpi_iommu_configure() Date: Wed, 15 Nov 2023 10:06:01 -0400 Message-ID: <10-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> In-Reply-To: <0-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR10CA0036.namprd10.prod.outlook.com (2603:10b6:208:120::49) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|SJ0PR12MB7007:EE_ X-MS-Office365-Filtering-Correlation-Id: 77a99af8-b0d5-4ba6-6eb4-08dbe5e404c8 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: y+g5ujmOvADA+qA01aKR/BKZhSB70UQV949rqZj2tFFwXYkR+gzCxPIirJQec7pjQzenGHr1dTq4Bo2yMOd3faqHzxT1kDnekGGtoKRmn+aCYRQ+aNgFdu3Y99zE471QJ8va1G6joylQT3W1BtxBnyuGGt0qDMjpYUEeKa54HLKIn9nwFyxU9sZSTKmoKxZkjCit3eV+O08bkKLyOxLlTwjMEhhJPs5a30klalWSNbY/WPGMIBrYuvBxlGUlCw3Go2VKZysSExX70xkDnJF/dcxBBISu294RQZUWIieiI1naI4WasKbTiB5MASDYYIFH5xQQlbCHwqRLOS5Qghrg2WR04v+WkoKUnTblRjJol8AgRc/vP/s9vzt/qr2Ug2EqV89vrZk9f0BgfWkXASZjMzk6vBzymU691010PtFZRGS2B76Wki94wFkq9+/Cc7ekIw0tUIHQY85a5jSvKmOjxlyplS4oksCgZryR6s0ictADrlnp9CKocFfe/8jDqnuViHpfmkUoOXA+FnMfaVYQG+NxTZpHbgveBvy3Y+X4wSuQ3p31FUiT/uXP4RW8q91Z1kQOPUFuDag8OumrsTqRnmRlqN8DC+vhivbgQ4jvWvg= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(136003)(346002)(376002)(366004)(39860400002)(396003)(230922051799003)(451199024)(1800799009)(186009)(64100799003)(7406005)(6666004)(6506007)(30864003)(2616005)(6512007)(83380400001)(7416002)(41300700001)(8676002)(5660300002)(4326008)(7366002)(8936002)(478600001)(2906002)(6486002)(66476007)(54906003)(110136005)(66946007)(66556008)(316002)(86362001)(36756003)(38100700002)(26005)(921008)(66899024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 6UCuUwAAUvi/5hac/d8zjw7xI7wl+iPS6zFmKYu552PtLBq2Q9UZxv3aAWyUiGILMpi5QmObIKDrdjSCqC0i3suqGqugOWzzknYDjaatKDYQ7SiUZZB4yY7B6KwYopgLeDOgg9wyrNoaRfvE/P31Oag7uvdsXQ22xh+ixGMKjhOyrYBLKdPWCnufalR9QSQdlEYN5iE6SIfz98kdjK4v+UujntbWdPFSZLTIxASkPc65WyByyMezeKxSUI7ZSlBRTpBbuBloVpxnJaJxaPec0lDyEU3O7j3Rr10Sasd7IAGSb8hvVKw4v9u05LNCepya4lrYm+DF+2bKWhTVetoiQ7YrQLJU20B+P1miftj47+AAlINHeNShfqukvX1kbZQybLdurM5YA/bLzWSMV3vGfEBBRAlcztqoVMcy/83CmiJWbnI1qguRX51AJH+d2Vbd1+QzRGwhOcfbmDlBSo+1tF8+vn5y2vEqKndOAVjkzjlu/Lgbbfgqc/0DUEYDYdNSnKF5QT20V/Rq70du5cpyWOzrjn28J8S/o+l5M04jK8bIjk7eMO0AEIiPltF4vTekorkzfVCHFy3CKq8I+4efRHK06g0wA6LcFuAvNbdrzedVMwTGc0PfEOo2wsPduh7lSZCMRtEWj4xNWcsyCCY4PY3aPzzz8MJy0u8JfetW9+pI/hkCCaahty5VD2TMzR9wZDnBmotFxvsV+JiMyH1Dx+bL7luKY3FLRaLcNLTK3GDDu5wrI118Ye0K7m7jLaTl1JwHvKpF9b4idZI+JQk+wruwi1i28iLhYUzV5vPjncE5jM4sB1hABy/NS2/Zv8/s5U+BhzV1W4r52G9z/OLQzMFsRDB4j1EtfTBgn9VzcO66qN7QIp/KuH5ErlVX/lSTAbx+7cDI8Tbbji+GYWTXnD792qDmHE7GulOV7/ElY9RlMu9XK+Y4jutpahHD2czlbEcCP5cEYgrFqnT2nbNdjvo2hKLh/pp6h9psisxPZIGV/ceMNroVLjOU1ouPt/XzxojSb9sv85kNm5O4aSDQi+4GQfVj9ZP5fOmveHhpk9nNPPYa1YHlx35nvyM6qBPOnOcGIylfZ+B17VL43Q3YWxRptr3Bjw6900dtrZk8KJT+T7nF/s6YdnulS97ODBMsCGTq2yQqoEimOZFcuYesafgDI/ai52QoLqbNgOJcLkcQJGpUf7MwKjQEizOZ6PEVXOpN4esqnOh/w5pB3XZGSrU4DA+UCsBF8UCujmfjZiWQ3Pb6jUoiMfJU0mR49IdSDCR+Rvup2W5Dzbr+oF9QdbUVnt6PV4qOugsk17gF/5p0QQixtPtjLTaH/v11i06PYyu0WRzrWzrgSWu6rYCw1/4X4njBhjXPVu29bnqdGUV5IIC9Z+AUabyq9DaHYfNaK2Hb1b+05+Weekn12+z9LyihnXTPEl1Ref9fusCOInvowZhVNK2FzDt3QBEgdIpMbNxOYviXqZGLnrYyhYlL2OLqO0G0zJ621fiu0PViHmWTByw02zr4GYgzoNX3MaTuwz4D3q9GD5/se47uWeAqpcX2MWS4H9CMqM7CKyS5pr4= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 77a99af8-b0d5-4ba6-6eb4-08dbe5e404c8 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 14:06:10.0973 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: AJHwmDGFKgtBAjP5g3TK/Gq5bA66/g1pHAKrclSsxUnncSaIZjZBBsCqmdG7VGi6 X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7007 This call chain is using dev->iommu->fwspec to pass around the fwspec between the three parts (acpi_iommu_configure_id(), acpi_iommu_fwspec_init(), iommu_probe_device()). However there is no locking around the accesses to dev->iommu, so this is all racy. Allocate a clean, local, fwspec at the start of acpi_iommu_configure_id(), pass it through all functions on the stack to fill it with data, and finally pass it into iommu_probe_device_fwspec() which will load it into dev->iommu under a lock. Acked-by: Rafael J. Wysocki Reviewed-by: Jerry Snitselaar Reviewed-by: Moritz Fischer Signed-off-by: Jason Gunthorpe --- drivers/acpi/arm64/iort.c | 42 +++++++++--------- drivers/acpi/scan.c | 89 ++++++++++++++++++--------------------- drivers/acpi/viot.c | 45 +++++++++++--------- drivers/iommu/iommu.c | 5 +-- include/acpi/acpi_bus.h | 8 ++-- include/linux/acpi_iort.h | 8 +++- include/linux/acpi_viot.h | 5 ++- include/linux/iommu.h | 2 + 8 files changed, 103 insertions(+), 101 deletions(-) diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index 6496ff5a6ba20d..b08682282ee5a7 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -1218,10 +1218,9 @@ static bool iort_pci_rc_supports_ats(struct acpi_iort_node *node) return pci_rc->ats_attribute & ACPI_IORT_ATS_SUPPORTED; } -static int iort_iommu_xlate(struct device *dev, struct acpi_iort_node *node, - u32 streamid) +static int iort_iommu_xlate(struct iommu_fwspec *fwspec, struct device *dev, + struct acpi_iort_node *node, u32 streamid) { - const struct iommu_ops *ops; struct fwnode_handle *iort_fwnode; if (!node) @@ -1239,17 +1238,14 @@ static int iort_iommu_xlate(struct device *dev, struct acpi_iort_node *node, * in the kernel or not, defer the IOMMU configuration * or just abort it. */ - ops = iommu_ops_from_fwnode(iort_fwnode); - if (!ops) - return iort_iommu_driver_enabled(node->type) ? - -EPROBE_DEFER : -ENODEV; - - return acpi_iommu_fwspec_init(dev, streamid, iort_fwnode, ops); + return acpi_iommu_fwspec_init(fwspec, dev, streamid, iort_fwnode, + iort_iommu_driver_enabled(node->type)); } struct iort_pci_alias_info { struct device *dev; struct acpi_iort_node *node; + struct iommu_fwspec *fwspec; }; static int iort_pci_iommu_init(struct pci_dev *pdev, u16 alias, void *data) @@ -1260,7 +1256,7 @@ static int iort_pci_iommu_init(struct pci_dev *pdev, u16 alias, void *data) parent = iort_node_map_id(info->node, alias, &streamid, IORT_IOMMU_TYPE); - return iort_iommu_xlate(info->dev, parent, streamid); + return iort_iommu_xlate(info->fwspec, info->dev, parent, streamid); } static void iort_named_component_init(struct device *dev, @@ -1280,7 +1276,8 @@ static void iort_named_component_init(struct device *dev, dev_warn(dev, "Could not add device properties\n"); } -static int iort_nc_iommu_map(struct device *dev, struct acpi_iort_node *node) +static int iort_nc_iommu_map(struct iommu_fwspec *fwspec, struct device *dev, + struct acpi_iort_node *node) { struct acpi_iort_node *parent; int err = -ENODEV, i = 0; @@ -1293,13 +1290,13 @@ static int iort_nc_iommu_map(struct device *dev, struct acpi_iort_node *node) i++); if (parent) - err = iort_iommu_xlate(dev, parent, streamid); + err = iort_iommu_xlate(fwspec, dev, parent, streamid); } while (parent && !err); return err; } -static int iort_nc_iommu_map_id(struct device *dev, +static int iort_nc_iommu_map_id(struct iommu_fwspec *fwspec, struct device *dev, struct acpi_iort_node *node, const u32 *in_id) { @@ -1308,7 +1305,7 @@ static int iort_nc_iommu_map_id(struct device *dev, parent = iort_node_map_id(node, *in_id, &streamid, IORT_IOMMU_TYPE); if (parent) - return iort_iommu_xlate(dev, parent, streamid); + return iort_iommu_xlate(fwspec, dev, parent, streamid); return -ENODEV; } @@ -1317,20 +1314,22 @@ static int iort_nc_iommu_map_id(struct device *dev, /** * iort_iommu_configure_id - Set-up IOMMU configuration for a device. * + * @fwspec: The iommu_fwspec to fill in with fw information about the device * @dev: device to configure * @id_in: optional input id const value pointer * * Returns: 0 on success, <0 on failure */ -int iort_iommu_configure_id(struct device *dev, const u32 *id_in) +int iort_iommu_configure_id(struct iommu_fwspec *fwspec, struct device *dev, + const u32 *id_in) { struct acpi_iort_node *node; int err = -ENODEV; if (dev_is_pci(dev)) { - struct iommu_fwspec *fwspec; struct pci_bus *bus = to_pci_dev(dev)->bus; - struct iort_pci_alias_info info = { .dev = dev }; + struct iort_pci_alias_info info = { .dev = dev, + .fwspec = fwspec }; node = iort_scan_node(ACPI_IORT_NODE_PCI_ROOT_COMPLEX, iort_match_node_callback, &bus->dev); @@ -1341,8 +1340,7 @@ int iort_iommu_configure_id(struct device *dev, const u32 *id_in) err = pci_for_each_dma_alias(to_pci_dev(dev), iort_pci_iommu_init, &info); - fwspec = dev_iommu_fwspec_get(dev); - if (fwspec && iort_pci_rc_supports_ats(node)) + if (iort_pci_rc_supports_ats(node)) fwspec->flags |= IOMMU_FWSPEC_PCI_RC_ATS; } else { node = iort_scan_node(ACPI_IORT_NODE_NAMED_COMPONENT, @@ -1350,8 +1348,8 @@ int iort_iommu_configure_id(struct device *dev, const u32 *id_in) if (!node) return -ENODEV; - err = id_in ? iort_nc_iommu_map_id(dev, node, id_in) : - iort_nc_iommu_map(dev, node); + err = id_in ? iort_nc_iommu_map_id(fwspec, dev, node, id_in) : + iort_nc_iommu_map(fwspec, dev, node); if (!err) iort_named_component_init(dev, node); @@ -1363,8 +1361,6 @@ int iort_iommu_configure_id(struct device *dev, const u32 *id_in) #else void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head) { } -int iort_iommu_configure_id(struct device *dev, const u32 *input_id) -{ return -ENODEV; } #endif static int nc_dma_get_range(struct device *dev, u64 *size) diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index d171d193f2a51c..5d467ff58ff24b 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -1543,74 +1543,67 @@ int acpi_dma_get_range(struct device *dev, const struct bus_dma_region **map) } #ifdef CONFIG_IOMMU_API -int acpi_iommu_fwspec_init(struct device *dev, u32 id, - struct fwnode_handle *fwnode, - const struct iommu_ops *ops) +int acpi_iommu_fwspec_init(struct iommu_fwspec *fwspec, struct device *dev, + u32 id, struct fwnode_handle *fwnode, + bool iommu_driver_available) { - int ret = iommu_fwspec_init(dev, fwnode, ops); + int ret; - if (!ret) - ret = iommu_fwspec_add_ids(dev, &id, 1); - - return ret; -} - -static inline const struct iommu_ops *acpi_iommu_fwspec_ops(struct device *dev) -{ - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - - return fwspec ? fwspec->ops : NULL; + ret = iommu_fwspec_assign_iommu(fwspec, dev, fwnode); + if (ret) { + if (ret == -EPROBE_DEFER && !iommu_driver_available) + return -ENODEV; + return ret; + } + return iommu_fwspec_append_ids(fwspec, &id, 1); } static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in) { int err; - const struct iommu_ops *ops; + struct iommu_fwspec *fwspec; - /* - * If we already translated the fwspec there is nothing left to do, - * return the iommu_ops. - */ - ops = acpi_iommu_fwspec_ops(dev); - if (ops) - return 0; + fwspec = iommu_fwspec_alloc(); + if (IS_ERR(fwspec)) + return PTR_ERR(fwspec); - err = iort_iommu_configure_id(dev, id_in); - if (err && err != -EPROBE_DEFER) - err = viot_iommu_configure(dev); + err = iort_iommu_configure_id(fwspec, dev, id_in); + if (err == -ENODEV) + err = viot_iommu_configure(fwspec, dev); + if (err == -ENODEV || err == -EPROBE_DEFER) + goto err_free; + if (err) + goto err_log; - /* - * If we have reason to believe the IOMMU driver missed the initial - * iommu_probe_device() call for dev, replay it to get things in order. - */ - if (!err && dev->bus) - err = iommu_probe_device(dev); - - /* Ignore all other errors apart from EPROBE_DEFER */ - if (err == -EPROBE_DEFER) { - return err; - } else if (err) { - dev_dbg(dev, "Adding to IOMMU failed: %d\n", err); - return -ENODEV; + err = iommu_probe_device_fwspec(dev, fwspec); + if (err) { + /* + * Ownership for fwspec always passes into + * iommu_probe_device_fwspec() + */ + fwspec = NULL; + goto err_log; } - if (!acpi_iommu_fwspec_ops(dev)) - return -ENODEV; - return 0; + +err_log: + dev_dbg(dev, "Adding to IOMMU failed: %d\n", err); +err_free: + iommu_fwspec_dealloc(fwspec); + return err; } #else /* !CONFIG_IOMMU_API */ -int acpi_iommu_fwspec_init(struct device *dev, u32 id, - struct fwnode_handle *fwnode, - const struct iommu_ops *ops) +int acpi_iommu_fwspec_init(struct iommu_fwspec *fwspec, struct device *dev, + u32 id, struct fwnode_handle *fwnode, + bool iommu_driver_available) { return -ENODEV; } -static const struct iommu_ops *acpi_iommu_configure_id(struct device *dev, - const u32 *id_in) +static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in) { - return NULL; + return -ENODEV; } #endif /* !CONFIG_IOMMU_API */ diff --git a/drivers/acpi/viot.c b/drivers/acpi/viot.c index c8025921c129b2..1d0da99e65e6af 100644 --- a/drivers/acpi/viot.c +++ b/drivers/acpi/viot.c @@ -304,11 +304,9 @@ void __init acpi_viot_init(void) acpi_put_table(hdr); } -static int viot_dev_iommu_init(struct device *dev, struct viot_iommu *viommu, - u32 epid) +static int viot_dev_iommu_init(struct iommu_fwspec *fwspec, struct device *dev, + struct viot_iommu *viommu, u32 epid) { - const struct iommu_ops *ops; - if (!viommu) return -ENODEV; @@ -316,19 +314,20 @@ static int viot_dev_iommu_init(struct device *dev, struct viot_iommu *viommu, if (device_match_fwnode(dev, viommu->fwnode)) return -EINVAL; - ops = iommu_ops_from_fwnode(viommu->fwnode); - if (!ops) - return IS_ENABLED(CONFIG_VIRTIO_IOMMU) ? - -EPROBE_DEFER : -ENODEV; - - return acpi_iommu_fwspec_init(dev, epid, viommu->fwnode, ops); + return acpi_iommu_fwspec_init(fwspec, dev, epid, viommu->fwnode, + IS_ENABLED(CONFIG_VIRTIO_IOMMU)); } +struct viot_pci_alias_info { + struct device *dev; + struct iommu_fwspec *fwspec; +}; + static int viot_pci_dev_iommu_init(struct pci_dev *pdev, u16 dev_id, void *data) { u32 epid; struct viot_endpoint *ep; - struct device *aliased_dev = data; + struct viot_pci_alias_info *info = data; u32 domain_nr = pci_domain_nr(pdev->bus); list_for_each_entry(ep, &viot_pci_ranges, list) { @@ -339,14 +338,15 @@ static int viot_pci_dev_iommu_init(struct pci_dev *pdev, u16 dev_id, void *data) epid = ((domain_nr - ep->segment_start) << 16) + dev_id - ep->bdf_start + ep->endpoint_id; - return viot_dev_iommu_init(aliased_dev, ep->viommu, - epid); + return viot_dev_iommu_init(info->fwspec, info->dev, + ep->viommu, epid); } } return -ENODEV; } -static int viot_mmio_dev_iommu_init(struct platform_device *pdev) +static int viot_mmio_dev_iommu_init(struct iommu_fwspec *fwspec, + struct platform_device *pdev) { struct resource *mem; struct viot_endpoint *ep; @@ -357,24 +357,29 @@ static int viot_mmio_dev_iommu_init(struct platform_device *pdev) list_for_each_entry(ep, &viot_mmio_endpoints, list) { if (ep->address == mem->start) - return viot_dev_iommu_init(&pdev->dev, ep->viommu, - ep->endpoint_id); + return viot_dev_iommu_init(fwspec, &pdev->dev, + ep->viommu, ep->endpoint_id); } return -ENODEV; } /** * viot_iommu_configure - Setup IOMMU ops for an endpoint described by VIOT + * @fwspec: The iommu_fwspec to fill in with fw information about the device * @dev: the endpoint * * Return: 0 on success, <0 on failure */ -int viot_iommu_configure(struct device *dev) +int viot_iommu_configure(struct iommu_fwspec *fwspec, struct device *dev) { - if (dev_is_pci(dev)) + if (dev_is_pci(dev)) { + struct viot_pci_alias_info info = { .dev = dev, + .fwspec = fwspec }; return pci_for_each_dma_alias(to_pci_dev(dev), - viot_pci_dev_iommu_init, dev); + viot_pci_dev_iommu_init, &info); + } else if (dev_is_platform(dev)) - return viot_mmio_dev_iommu_init(to_platform_device(dev)); + return viot_mmio_dev_iommu_init(fwspec, + to_platform_device(dev)); return -ENODEV; } diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 2076345d0d6653..f7bda1c0959d34 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -2943,9 +2943,8 @@ const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode) return ops; } -static int iommu_fwspec_assign_iommu(struct iommu_fwspec *fwspec, - struct device *dev, - struct fwnode_handle *iommu_fwnode) +int iommu_fwspec_assign_iommu(struct iommu_fwspec *fwspec, struct device *dev, + struct fwnode_handle *iommu_fwnode) { const struct iommu_ops *ops; diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index afeed6e72049e4..4197c0004a30b0 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -12,6 +12,8 @@ #include #include +struct iommu_fwspec; + struct acpi_handle_list { u32 count; acpi_handle* handles; @@ -628,9 +630,9 @@ struct acpi_pci_root { bool acpi_dma_supported(const struct acpi_device *adev); enum dev_dma_attr acpi_get_dma_attr(struct acpi_device *adev); -int acpi_iommu_fwspec_init(struct device *dev, u32 id, - struct fwnode_handle *fwnode, - const struct iommu_ops *ops); +int acpi_iommu_fwspec_init(struct iommu_fwspec *fwspec, struct device *dev, + u32 id, struct fwnode_handle *fwnode, + bool iommu_driver_available); int acpi_dma_get_range(struct device *dev, const struct bus_dma_region **map); int acpi_dma_configure_id(struct device *dev, enum dev_dma_attr attr, const u32 *input_id); diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 1cb65592c95dd3..7644922ecb0705 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -11,6 +11,8 @@ #include #include +struct iommu_fwspec; + #define IORT_IRQ_MASK(irq) (irq & 0xffffffffULL) #define IORT_IRQ_TRIGGER_MASK(irq) ((irq >> 32) & 0xffffffffULL) @@ -40,7 +42,8 @@ void iort_put_rmr_sids(struct fwnode_handle *iommu_fwnode, struct list_head *head); /* IOMMU interface */ int iort_dma_get_ranges(struct device *dev, u64 *size); -int iort_iommu_configure_id(struct device *dev, const u32 *id_in); +int iort_iommu_configure_id(struct iommu_fwspec *fwspec, struct device *dev, + const u32 *id_in); void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head); phys_addr_t acpi_iort_dma_get_max_cpu_address(void); #else @@ -57,7 +60,8 @@ void iort_put_rmr_sids(struct fwnode_handle *iommu_fwnode, struct list_head *hea /* IOMMU interface */ static inline int iort_dma_get_ranges(struct device *dev, u64 *size) { return -ENODEV; } -static inline int iort_iommu_configure_id(struct device *dev, const u32 *id_in) +static inline int iort_iommu_configure_id(struct iommu_fwspec *fwspec, + struct device *dev, const u32 *id_in) { return -ENODEV; } static inline void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head) diff --git a/include/linux/acpi_viot.h b/include/linux/acpi_viot.h index a5a12243156377..f1874cb6d43c09 100644 --- a/include/linux/acpi_viot.h +++ b/include/linux/acpi_viot.h @@ -8,11 +8,12 @@ #ifdef CONFIG_ACPI_VIOT void __init acpi_viot_early_init(void); void __init acpi_viot_init(void); -int viot_iommu_configure(struct device *dev); +int viot_iommu_configure(struct iommu_fwspec *fwspec, struct device *dev); #else static inline void acpi_viot_early_init(void) {} static inline void acpi_viot_init(void) {} -static inline int viot_iommu_configure(struct device *dev) +static inline int viot_iommu_configure(struct iommu_fwspec *fwspec, + struct device *dev) { return -ENODEV; } diff --git a/include/linux/iommu.h b/include/linux/iommu.h index bbbba7d0a159ba..72ec71bd31a376 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -818,6 +818,8 @@ void iommu_fwspec_dealloc(struct iommu_fwspec *fwspec); int iommu_fwspec_of_xlate(struct iommu_fwspec *fwspec, struct device *dev, struct fwnode_handle *iommu_fwnode, struct of_phandle_args *iommu_spec); +int iommu_fwspec_assign_iommu(struct iommu_fwspec *fwspec, struct device *dev, + struct fwnode_handle *iommu_fwnode); int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, const struct iommu_ops *ops); From patchwork Wed Nov 15 14:06:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13456776 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F3D628DC3; Wed, 15 Nov 2023 14:06:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="tNBiXw5Q" Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F773C5; 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Wysocki" , Rob Herring Subject: [PATCH v2 11/17] iommu: Hold iommu_probe_device_lock while calling ops->of_xlate Date: Wed, 15 Nov 2023 10:06:02 -0400 Message-ID: <11-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> In-Reply-To: <0-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR10CA0001.namprd10.prod.outlook.com (2603:10b6:208:120::14) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH8PR12MB6916:EE_ X-MS-Office365-Filtering-Correlation-Id: 30034502-39d2-49f7-9f19-08dbe5e405bb X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qKoJ00Kq5CZ2mVHAIGxnEG5vMgGT8yPlYAykGDKukVtHl2dra88qrT24dDn3QSCNHs+vTVQgBQnqqjgcURQzVyWH6Q/h8FyjYCFSUQGIr3AVO8YPJlIy5CaLbCcTj9faTr94rZsq1NTyUx7R9ttZsXARlsLEQphPM82VoQvmD7hlgmzaBXIv5BVVsSeSuJkoDOKhAAVfqEEroBKS5n9pn5it9UrXNNVtYVnjGHWc9nWOYoTOClm1X+SN/FVsYSJ/FRRbW8nmVkDxrXQpQ1q+0h8nJbTF1o/NDcMbX9In2ntch/0Ow4No3R6LVBC4BB8VnReXOi+wFSRVCBX48zQU9ug1SHp1Osls26vrKwvFdaPQRTTF6inoMFKo3FhROBljyjDf8EyHElunNojjM7+g0mpppyk9y9XwdIc6s4k2Yl0pT6PF+RDgBTb1W6xbvt2qocTu9FZqejOgomGgP2WYArJMGCeqYZ937zf3a6cI9T/hL7P4xlffYr6piuX/07bej8+XcEFa2G8hOpzB4LRtLl9nLuTi/7yTaRxx+d2ncbR1Mu4/TirP6ovtptHx5HZ1pkdAwa3jISCNB0IgKDnwnFPQE2KsLYJgLgc8X3uHF975GFPUD+u5vIbqLsSSy4xHhO+1FzB5POkavCAOWbafNA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(39860400002)(376002)(346002)(396003)(366004)(136003)(230922051799003)(1800799009)(64100799003)(186009)(451199024)(110136005)(316002)(66946007)(54906003)(66476007)(66556008)(6486002)(478600001)(6666004)(966005)(7366002)(86362001)(5660300002)(7406005)(7416002)(921008)(41300700001)(2906002)(36756003)(8676002)(4326008)(8936002)(2616005)(38100700002)(26005)(83380400001)(6506007)(6512007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: rySRiIxMGJm/2YFKWF8mJCVwoQpBp6kRUByba4rKQmAyTgtcfi3ZPg1b0Vlfm7ftJuRJHBe4dNkgF4pQTEr48rSsQefCde21wPPLdaCngzy7/6vF/CF5Ll2cwzA9vAlKFhiMUS7Q1e1fjDewNV0vFYDzB1mv9nwsQ02ve/uYNl/tRQpQbK0DQRBsBgYZNb8hw8oUX+fCy++C0faaEmfYeavEvYLl+c/Mus0HauriQi4SHWPF9J/kwBInHqtWRl3E2qG3yhNsm5mQeME1FtA7Xik433DG0vm04l44wpQr/Ldu+8pay/9t12xamGmU4LsUpgdL6v7ZZNYEOrN4J6z6IG1/OzHaS32st36H6zbquUytUkUgWK8RK5JsV86yKKZcke5A6PUsIGTJ21aiUcQtI6d0O/9YW0HsgyJNtWoQUbwK5nAeZ0CWaMrGi4MBvSAC5T4XTyCtk8x00Jo5ByQsUYi2hyYglEEUax9ozGLPvHNSjpge3WK679awSw8llAXO+RcMDiYTVXKrTc5n1JN19sEGCkLzTOP6iX2igrV6EHvUb3r7pKSqor9QYNcJmDV27Hb5k8OYz9DiYDGqK77B5ygiU3l4TYgbPIeKSOs8hbqDFaZDTmp24JzQLfkl+sm/oOVzt6LPf8Y3Vl5onNgayAomp216tU+zzXJQH8mMdKlLSg/kn3c9g++DDQSPGUAeFtFsu57jrG6V2VqzdP+vCYkKu0So7ZJdJz5GEUfcCIvzMvx/xGM3fECI69rO3FZAN6CuXjN8maV6/pAb5OLOYTDddbjqyale3LIWB6tRuu4ePARiOb7wjc7dPpqxJQagxsfOFLcwLlTyQPhxAYT9tp5uqiVlJE6Kkj/5u14bk3DWuSZrF60AnO4QIu0bvw5ngCvUW7paOQ4E/zFdFf3HRSmFYBbnf8MxIhICdB5XcmXwwZVm0Br7/EnCuyhAmuvLSU8yFF2KbdJUC5N2NJf3Wa61OAQcsXQRvA+rgweX9U9LZ1E+w0KymLA0H5NAYIglm7NxcgzYM/S5FL9mWdQVlL13GQEPsiX4sMbkkk8QwANYAncQFprD89VksPyX4RfT3y+tbwnxVNhp/G6m3UBjqyJcySlnNMsm1oxRIpwB7lVQNH2DoDcUtCihP9VtaKVbMdeLFtfDnBHHizKz5x3D5kjBpaZB1pB7BWNvvdro7EsWh1PRVe2OctvYL1jmGw4m6ID+QbvLpJUU8JmbxZOhFPlRhgGper89BSUFH4HAbpw/SyU0xlY7M/A6wGvn7hr+ib6rDvfxuaEvuEdJ2OwMFnc5eAck23guC6ZMVfiZLCmdSEYcIk8XMUc7eEVtMRMU7I4ZMFOCfakrFjg63DkL7dfO3wuC9gzK5v7flVi0euoC5iW1LZQkoMK/7uiTpmvcjHWgQwH4IdTRR+MBZGBMQgYNrhYXKDMnsM8A17RAZdl2c79XYrTFuYge3scdFvZGKsg/ZsAnt6we/ajiQVxf62mit40Ua4MXDURZTDhzybO0zewFWQaId2y+FVu3ciGbeQ60xR0uPCqv8qKBZvi+os3MIOsmywqOh0Zg23dfzfo= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 30034502-39d2-49f7-9f19-08dbe5e405bb X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 14:06:11.6009 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Xxv/yogWBUqY8nO/7z3Pm/iRPB3M9BTC1RZPsj/xm/FUhbu5Zm2MrcmEYwCNu3zf X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6916 This resolves the race around touching dev->iommu while generating the OF fwspec on the of_iommu_configure() flow: CPU0 CPU1 of_iommu_configure() iommu_device_register() .. bus_iommu_probe() iommu_fwspec_of_xlate() __iommu_probe_device() iommu_init_device() dev_iommu_get() .. ops->probe fails, no fwspec .. dev_iommu_free() dev->iommu->fwspec *crash* CPU1 is holding the iommu_probe_device_lock for iommu_init_device(), holding it around the of_xlate() and its related manipulation of dev->iommu will close it. The approach also closes a similar race for what should be a successful probe where the above basic construction results in ops->probe observing a partially initialized fwspec. Reviewed-by: Jerry Snitselaar Reported-by: Zhenhua Huang Closes: https://lore.kernel.org/linux-arm-kernel/20231017163337.GE282036@ziepe.ca/T/#mee0d7bdc375541934a571ae69f43b9660f8e7312 Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommu.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index f7bda1c0959d34..5af98cad06f9ef 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -41,6 +41,7 @@ static struct kset *iommu_group_kset; static DEFINE_IDA(iommu_group_ida); static DEFINE_IDA(iommu_global_pasid_ida); +static DEFINE_MUTEX(iommu_probe_device_lock); static unsigned int iommu_def_domain_type __read_mostly; static bool iommu_dma_strict __read_mostly = IS_ENABLED(CONFIG_IOMMU_DEFAULT_DMA_STRICT); @@ -498,7 +499,6 @@ static int __iommu_probe_device(struct device *dev, struct iommu_fwspec *fwspec = caller_fwspec; const struct iommu_ops *ops; struct iommu_group *group; - static DEFINE_MUTEX(iommu_probe_device_lock); struct group_device *gdev; int ret; @@ -2985,8 +2985,11 @@ int iommu_fwspec_of_xlate(struct iommu_fwspec *fwspec, struct device *dev, if (!fwspec->ops->of_xlate) return -ENODEV; - if (!dev_iommu_get(dev)) + mutex_lock(&iommu_probe_device_lock); + if (!dev_iommu_get(dev)) { + mutex_unlock(&iommu_probe_device_lock); return -ENOMEM; + } /* * ops->of_xlate() requires the fwspec to be passed through dev->iommu, @@ -2998,6 +3001,7 @@ int iommu_fwspec_of_xlate(struct iommu_fwspec *fwspec, struct device *dev, ret = fwspec->ops->of_xlate(dev, iommu_spec); if (dev->iommu->fwspec == fwspec) dev->iommu->fwspec = NULL; + mutex_unlock(&iommu_probe_device_lock); return ret; } @@ -3027,6 +3031,8 @@ int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); int ret; + lockdep_assert_held(&iommu_probe_device_lock); + if (fwspec) return ops == fwspec->ops ? 0 : -EINVAL; @@ -3080,6 +3086,8 @@ int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids) { struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + lockdep_assert_held(&iommu_probe_device_lock); + if (!fwspec) return -EINVAL; return iommu_fwspec_append_ids(fwspec, ids, num_ids); From patchwork Wed Nov 15 14:06:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13456914 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0845F1EB45; Wed, 15 Nov 2023 15:07:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="XPy2nhu3" Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2079.outbound.protection.outlook.com [40.107.94.79]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D5FAB8; Wed, 15 Nov 2023 07:07:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=oToTNxK/3k+YwTPeOrPScCq1Ruc56U3Ttd9535IToPHv2xqc5ZJ1qd52DTz1Lay4ATEZx4DLo+IN3FcQOWXmqt459rWrgrUw+LLFzOQgNmfLQkDGeXqYTUMOAgcJI8vnaxwk0hOJ5x/twBAbcPiTt8QW0ChF1iomPnyEp0+CauqJJA28eazMCUnlulelPpQd8TPevkPdf+J9/lyQ55M4Kogj0F+SAkU707pwsEiu0TKHPxrmm1q9qRHaVZ0LQ9iWt/9mj5t2scV10UPG11rlreeXc1ci7uSoek9C87W+9huaotjgXpso6I2Uvz0xka6M8oe2lybni/KU6FbrBGyFWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=z7HFA1wAtG0csX5SIcxeCgmNi95dTiOCE5SEtGWaiKQ=; b=EmtrVKzX+l/dDjm/A8uYSrOOqv9Putznm0B3z5lM3jYZVPlqoANeVjuSt54LBzDzXB7GIL2I4jYX1DGVtLkycAY9wvWjYtMUuHH28pqYtSExkgqFEguFYPujigtBQ7dPBRPyWCa9nCFcuCNnMQGpsyLBkUDRYT0cNB4VtuDlz6v3bU/L6O/rLOHLDQpwzZTAPnThHHzjYinUYcZTtNgcqq7OKsZY76IahpyOKRjzh5BBcRQ+8f1XLWZeyU7ohRSfWSfsPM0wm8BZQuWa3dLm5OumLimYbSlP5Mqx/qocP69//8cM5wLUEic0zAn2y5jO6/uVD/VsaAMVXeqiR1O9bQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=z7HFA1wAtG0csX5SIcxeCgmNi95dTiOCE5SEtGWaiKQ=; b=XPy2nhu3512SOLvM/FXkuKfj0O4xlLOFPILPelrJ4GJlnQOJi9yfY+HRG8PAwYh18CGANHs5Eq0FUZKV1uwzDTyo2JMcnMOJTv3y0aSrMChw/F8NZD3+Cy6D9UcNx385lhPNteRzI1e8K84flk8sOr7EOA89Hs8VVKgRc7S9KHzg+/wwSMj41fgNgf1Z+hMoURD9Nc4JUUZC1SGOy1edZ/McJsjChGterU4Pj8Cv0rB8TMd1P6OsOvj177wQgMAoKeKMKzvLnqzpB9Wx6UOgWAGSLVlcnCn2xvRXXiRrhcJ5xL4ZBkO/cLsGHo1Rd/RRKNwKRt0InG6A2WZUcx0+Fg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by CYYPR12MB8989.namprd12.prod.outlook.com (2603:10b6:930:c2::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6977.31; Wed, 15 Nov 2023 15:07:51 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.6977.029; Wed, 15 Nov 2023 15:07:51 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Alyssa Rosenzweig , Albert Ou , asahi@lists.linux.dev, Catalin Marinas , Dexuan Cui , devicetree@vger.kernel.org, David Woodhouse , Frank Rowand , Hanjun Guo , Haiyang Zhang , iommu@lists.linux.dev, Jean-Philippe Brucker , Jonathan Hunter , Joerg Roedel , "K. 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Wysocki" , Rob Herring Subject: [PATCH v2 12/17] iommu: Make iommu_ops_from_fwnode() static Date: Wed, 15 Nov 2023 10:06:03 -0400 Message-ID: <12-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> In-Reply-To: <0-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> References: X-ClientProxiedBy: BLAPR05CA0038.namprd05.prod.outlook.com (2603:10b6:208:335::19) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|CYYPR12MB8989:EE_ X-MS-Office365-Filtering-Correlation-Id: 0f368c15-69c7-45cb-f022-08dbe5eca2d2 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Xym5bd0OZ1BC647cc/VJVki59kPeo04QQhE0kW3PfT3GElEZO9z38lqW8DIa2WeEtPSJRYq+niFpNAsRO1q6wZ41FzNrgWy7viI5R5A268OOetoc3m+FzYA9HzKp534oZyWRiX/VITXR4a7Gegljrtbi7sPz+4t26SJh2GTi8V8+3Xy3Xl0A9JEua5cQIx7GqLdLy6HpvRKm4p3CNsHZ/AradyYxbmL/ByUviWZvml/2L9UZLsg7F3ObFViZC9C4h/0pGhg4X3PWrca9QKKc2+27YnveEdGLmoZDwBRxfXMtbW1tqW0dbZv575p+R7QpWBHOGHaTmprx40nAMjBzFMwBnLwsOSLM3IeGM/6sy9dyug+RY45Rn357pKh8QQo+naz8w5BYd6PEZ19RqI42PDTURdVi4F18nGj96tKR6kgFXX6W3unC9HPUzMihraFNA8ir9sDs4MZIy7vWmPdLJU/jrsPKCDVAeaXbQm472B5OjARtXN0oVlHQxLg8D/540VpI7m63LhWyZnznVv7TnFmIj4Cj+Dr7NsRQxPI2TKMZq7GadCZZ9s2FVwjNBxKBRZ9/UmLIT7e87egphQY61J+n248LeGYAiIGWBNd0o3PkVQoKdMrDjplIv7XhqJjNRaKeC94MipxvQmPqx5cYOA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(376002)(396003)(136003)(39860400002)(346002)(366004)(230273577357003)(230173577357003)(230922051799003)(451199024)(64100799003)(1800799009)(186009)(66946007)(6506007)(6666004)(26005)(2616005)(83380400001)(7406005)(6512007)(8936002)(4326008)(5660300002)(8676002)(7366002)(2906002)(7416002)(41300700001)(6486002)(316002)(110136005)(54906003)(66556008)(66476007)(478600001)(36756003)(38100700002)(86362001)(921008);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: LzwSwNC3UdwlGthEtWZssfe+fIm6hPyA1Z39LEjmY07qGJ2H6OWg8VMnjcrjA4t9wdgya8gKNrjp4GyMV2FC0vE90IMXKjdWpdG10ncBkZqEsUVdrChu7U8gJlgSO9SfFEo6yG06TEcqU6YyCvYFsBAfoHv50063GZYW1uOvf97ua7KSs4QzWn0KGQV19UV7tYTYgvp+OyoxJv43ygXd9c+kIy5gp2G+0cUj6wrWqY58ZjGkcD7hF4AhZKQVqY53HdR660cDm8ujWWKX5zoDhMvewFf5wpjQAyK/xdvMxxrJbA4jZUrcwb8waeO5TJOvJETv+vj+WWRJheHSc74mAYRKluE8UWT1So2awa2fJtH6lvXxyHgQyZtBumtQDpgHBZPql8IwMyKdZDeYiQaGnn46Y5bk9IZLDJ06y922dOJ8X2MTBhUkvJ8fZtVdn/rdLI5ci7/Yroje9K9cuvqTkW6OVYNA5erkfwrGi8QECfiBQGcJJcrzv45p7GZHD84BSogBoIHKogiaxvjyh0af0k9r9T8Q8aL+vJFotYm8KBcLssyYYNikrCcmxiLpgl3i5Cgj9U2KoyPA38u+onDc21giBl0VYUJqxxPRgswXMqcYtXwcbGv797gw0+VkzNi6YtZEv5mozvtqv6RXUvpsNGumUf2Fzic6+LpSNTKqCwaIfQvalvaJarUaAc4oGeTwwsTNRfx5sFE+J4dIj0m5/af7XTHPcxeXj+lwFNh0OkZO8yOSXUQ5P6B6lTN3SeOLwVnp8SDcmpkUDxLeSsbYA7U5Av09YXI3J8MwA5+H/eKroEYfP9iYD4rzhxCSKWsUfpC1N95Nx7ltWivXPN5kXMYMAw+XmJuHGiZhZCzS5+85dbcjerpoUNeWRMXJFMFIfQvdOkytD0xW3FDabm1okZyK3xO6YB0AuP7Ym3gWPNvcSU88+dW7fg60JPyKp0ioHuEc5a066ajTPFM+obIs2DJlytUxIlzmu5x8huF68LpVvloD1uZr0AxrjpcX1meqGyhqMWVzuGL4Hj3z3ZbNwYSZBKN0jP0yD5cPooiTEWkW6jhKCZtMKRMGhJ7FPCdkiKDnqHddBja/hrvSxFEKF+v0g5nT6wk/xuVNbxHzxOD1xe28Bi4d3dl8Wh2cbinh/PPVjZJEuio3dMK6o56ViZ2qfYmnysq2mBrASnf8W7dQDlwXvHaJ5qV6tyPJbJQTJNp/JPI0q227CZ5L7QSArrHfXRlMuW94JmTIY2l/TFOOhefFA5OZy+f1cNDdHgFOMrjRcTN1ScFqLxSMgWrVvBd+pfQ6s2kCdZ38ljXwvs6td2r2E1ZdOtXy91zNPyoQeO+bbtVHDRNWrIg+A+/mtlsynjFfQypGHyrAMYvK1LHoVmNqwIDKL/NX6kBixwvViZJUliVkfP/TQV/wSbt8O1d605eBKDVtPC9fAaBbwFQipIulelWPJLXdiEsvNSMZ2LRj4VG5uIUgKcY878eWcO5mKgsa3CDTwbueFit01W4AgJdq+ISftinyCb5lrYSJ8h5gEf8UZ22IwfLAuZlMNZXSlMa23pAA4RUV3knEgGk= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0f368c15-69c7-45cb-f022-08dbe5eca2d2 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 15:07:51.1387 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: EuAF3swyi52gNyQ/wE2Ko+9LRO6tOxhWA7NM5NAyq5GdaIlSz0Xm8/SmvLHUeAO7 X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8989 There are no external callers now. Signed-off-by: Jason Gunthorpe Reviewed-by: Jerry Snitselaar Reviewed-by: Moritz Fischer --- drivers/iommu/iommu.c | 3 ++- include/linux/iommu.h | 7 ------- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 5af98cad06f9ef..ea6aede326131e 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -2928,7 +2928,8 @@ bool iommu_default_passthrough(void) } EXPORT_SYMBOL_GPL(iommu_default_passthrough); -const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode) +static const struct iommu_ops * +iommu_ops_from_fwnode(struct fwnode_handle *fwnode) { const struct iommu_ops *ops = NULL; struct iommu_device *iommu; diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 72ec71bd31a376..05c5ad6bad6339 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -831,7 +831,6 @@ static inline void iommu_fwspec_free(struct device *dev) dev->iommu->fwspec = NULL; } int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids); 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Wysocki" , Rob Herring Subject: [PATCH v2 13/17] iommu: Remove dev_iommu_fwspec_set() Date: Wed, 15 Nov 2023 10:06:04 -0400 Message-ID: <13-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> In-Reply-To: <0-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> References: X-ClientProxiedBy: BLAPR03CA0113.namprd03.prod.outlook.com (2603:10b6:208:32a::28) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH8PR12MB6916:EE_ X-MS-Office365-Filtering-Correlation-Id: cd89d7f4-a005-4189-2ded-08dbe5e40549 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: eRsF/Dt4+HJ45bmYjKY9aho5heb5YUbg+V6U5kyIBLb6LHovnzZ34SDbOJTAJBZuLvaubWeNHh2M4ABzp0o2asxHRJ9OxX9Bf/sxG15jmpbgmPh7XGCi5F/sjpli03dAxP9JlXcfCsdt6JT9kWw+lTTV9f/4v4y4HFClZZKq8lHm8IAg03PTtWSNOmCbKxQiF0ddQxInRAPAhYw0AdxkW+3AofwTL4u1J4zELwitQeE6Lcwj50zwvUYMe2DJd7Js7T9PYDYZNaymQgkFHbMn9LgA8s7/aCjW/3pySx9mvwMWwza9xKgTccTcdqDDsvdTchMrs65mXmUMHoj+4FnZ1b3RjkqXBoA+tI15j2AO2YkKFM1A3zfIo7mZJGZ9X9PuV+60nI30bHeZHghdNpwq2dZcw0VLWyXxeX8zu3tNq0g5SiHvYQ68Wc7eGjykUv3EoaZeO+FT/+LphB2Nf3d5moUH//tMbcN9JKQSyl25g0IwnruyaASTyhY5yiRQ4gIbJImdGizFaeokUVJWai5lEKiCddQM1ukmwMhIg/c2BmLHKpiWr+mhEHqFseaU8hDIlwxSxlDzgV1l9f154Fe29ttRFbF4sKYiTuMaMwtpgL8= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(39860400002)(376002)(346002)(396003)(366004)(136003)(230922051799003)(1800799009)(64100799003)(186009)(451199024)(110136005)(316002)(66946007)(54906003)(66476007)(66556008)(6486002)(478600001)(6666004)(7366002)(86362001)(5660300002)(7406005)(7416002)(921008)(41300700001)(2906002)(36756003)(8676002)(4326008)(8936002)(2616005)(38100700002)(26005)(83380400001)(6506007)(6512007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: c/8zn0V4WhrkbUndJSfWrc/9uOTwc12pIBG8vkm6KPQa14TPV5PosFq4zIE9PfGLNSgsBKF9X4ae9rsMJkrHigqOb9WdH0s9wT2g1DYMAOPvHnJn1okSGaPepxbDC2kKPGV5K+H8KWwelcnRPzvNBXhreNoO74Z3eo+N7XE6FqamMMH0HYXWLUwKH2colznhNMwcV4BYQ1TmtAGwAapRkXehUuGySlyTBZWvngMb0P8xknPFYyipIqDBCw/wl2GYlb3h+ocARwKAT8/cK2Cyq8mFM30zBONAW/NSrGfNYDOEdHUmknbLc44m0as1Vgc2e8MG5LfUVr9vg4++yVO++wOMK3qM68zJB+DEuHmFOMaROfb4iqLBmbaZ9rNzYZ72OU0kO2bPnWjuozw8gUv9rUlcC6F7TFKbjMtE99OMhKTVvhZ6pNmFCnhfUq+Nh9+g5lXegDvurCWi3pot80nrAbuxDWs4wFqyHKy7MGLMiTnO8A+ZvLWcWU9WIdLpgAPx3iXHJTayVRTLI0bUS5lOf1b/CqyXOPbdMbTP78rHtEKc+OMW0Be2NTlu5ssOiEwuKf0jACVENPR08iTUh0bEzrkTfem7ENP5S1GsdmGT2XW3g48iZk0hyTnzmkjErK4yEdvBDCIMvbZbZIE2v5VHwNlfDP/0NI2gaYhvHZ93JcGbedOwr0VFHfyE/N5UqNeALKKFcupWDaUvtHaVIFxCgcReIqB429Z8+8dmW3vHHVn/gcKtjQGzU68H9nIi1IxnVRPG4wmYjRb7Asm62I5iXMeu46cu0PkDqUl/tgiwUrxUmjkIUXg39TOiJIsF8AImppOqn8jrdqA//Xb4Bb1qP1T4IWPFZVWaAZTX1bmS9VZ34h1DS5lZ7DYUsn7RhMmgIzJbr7Ge3j08267xRt2fTvHc80gMQj45ilx9UM4jahcvqaV2EbAir6HdrtqsjiK7mtTyrn67ISL3COpXDe/3N5hGq5tmEUjm8GFMPG+aHTRYCYtyvvTOyTS+eFfIg5i5geRku2UyV2TCR7PXPevGbv7JV4dXjk4PTvovGHYd8vi2RFt9zUpqM+tQoQ6g+n/7CJhWEKxjotPg2QO85V0hHsio/TXAWmSKDc69sX9tAkKm6Ebq3/0EljMm6ayVA3nQEBsiIf3C+oU+YPV0jS6QA7eRSaVYOH5/Wgt0RCjc+oIqdj6R514z7ugxOSE0ppGRuhQM9ZLcXAIxeH8dHgBl7+Z/JJVwLG9yLsx630PSv396Qr3Jq16vqa3ZILfeSa0eZsfsHDn0YYNnVqOWnIW/NwRg2ebz/D5hju6+jzGg4aySaF8dYsW0sZwQc3eaaAqbuEskz9U3Y8A5StdaJiVoh5dA0NWK65T9dyBl/t5QW9/U/a85l+2rd8mSLowq953wvS8/wVOxy4O7Ki4Kbkyb8GY9Bn02YdUZqcmBnPbY+vamfJwaLwOTUFntPI8dAk9EnimawN9l8WJ7qQZlBV/PjY9Jor3P9n7YVUc9wCEyEPLTKTvZfWTR8+ySrGWi9x3upPO63Xbqo27GyrMZvBzgfnHFaeiv/9bm0oKHtvvRXhA= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: cd89d7f4-a005-4189-2ded-08dbe5e40549 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 14:06:10.8975 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: zgeO7tGFptytqnbpGROYfI+//vuQKlJcj8GG14hT8X/d5Xj1dLhtNx9cUmz4898w X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6916 This is only used internally to iommu.c now, get rid of it to discourage things outside iommu.c from trying to manipulate dev->iommu->fwspec. Reviewed-by: Jerry Snitselaar Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommu.c | 2 +- include/linux/iommu.h | 6 ------ 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index ea6aede326131e..8fc3d0ff881260 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -3051,7 +3051,7 @@ int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, return ret; } - dev_iommu_fwspec_set(dev, fwspec); + dev->iommu->fwspec = fwspec; return 0; } EXPORT_SYMBOL_GPL(iommu_fwspec_init); diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 05c5ad6bad6339..352070c3ab3126 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -841,12 +841,6 @@ static inline struct iommu_fwspec *dev_iommu_fwspec_get(struct device *dev) return NULL; } -static inline void dev_iommu_fwspec_set(struct device *dev, - struct iommu_fwspec *fwspec) -{ - dev->iommu->fwspec = fwspec; -} - static inline void *dev_iommu_priv_get(struct device *dev) { if (dev->iommu) From patchwork Wed Nov 15 14:06:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13456740 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20147286B2; Wed, 15 Nov 2023 14:06:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Vcm7pksB" Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2043.outbound.protection.outlook.com [40.107.244.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C35CDAC; Wed, 15 Nov 2023 06:06:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=CdmHegBcy0EzF4/7tz0ElUWuZvWvVxbNxXODoqughxs1lSBXLk4mSRq5UGl/b5Zc+U6QIE6XGJIbwXXDJJheIVz3zW5N6AvuADc0qyRGCDrx0lNYha9KP/g/woiNO/hcrVnDwPSJ112r/3iN4yNuY8/ZJWONb/XdADdMgs5i4CyW6xvk6M4m4kwxGCUXRBBoqWO8fyLfKw/io6hpp2LItpXKqxOhPx/sy95q6hnQ6LaIm/XxMkNNYNeDWhi/eyE6/jLJqR7MmvrdbVFmnDMseCnpOh4NmTpcmqf8iPYLAF0bulNIw9VLLJH+WR2lyc1NPZShcgvNEvu1G3qLUZgemw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=9ttRQdDT1iUTyxqOUZ4d5fqMjqgasJxTCJ5kIwrGzsM=; b=fe5l1UeLe41+A2KceTAeEKtuDMSVKCtbcutXwJhT7bUjWurn/FJ7MFu08G+ggQg2AtWWMrlw5W1U2BT8OrMI9az7fbpIkw9FmDv7lQwwZ2HdNOLAluTJekxu3vuw/MPPTUWaQfSj9ShCF0Aajp8BWmFHjWyYAmjJES8iXlkmkFrDAYR3NgpLHgzxPqcdGSU3vOpos/2qMF2gq/+87mw6XqmK8jxhLctos00c8kSPol1KP3csyJ+lz4xy/2cHKBSsd0lHawJkllpsosFy48noPbsw6U19hBtttZhIl+MNGb2ZZDamo+orbR2RpVKfqXHgZMzjPzQkEBEgIjAWkasmkw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9ttRQdDT1iUTyxqOUZ4d5fqMjqgasJxTCJ5kIwrGzsM=; b=Vcm7pksBiSVh3xCEjWOXj2fGlP4FrEIAZto7e/Uu99uP7L4wjFdDiIZpLn4uVYPsHzwnSvo6IyoHr33+Rem3j15dXZl95jFbH/iq7WTzkO6n+/Iu7kitJHGpDObgqK0vMQTE+Gd5F+ERVI3jU7mEMG+JKXkvTmfZ32ydLkx3SUrA07d37ELAG7/1YiVap/DCMIj+m1bJREyydpWO3H7IC0Hk+1duboXTAI9MEQDfjQ7f1eMY1QxhHBe/JzJyJw7jFfLc/2KOMcjBF2VAFlkrZWKJx6hDINMqjyMhMbRo4jLb95/wu9deRPhxUwtp1ourTZoirW1ydUKf6BecY1qc7w== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by SJ0PR12MB7007.namprd12.prod.outlook.com (2603:10b6:a03:486::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6977.31; Wed, 15 Nov 2023 14:06:13 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.6977.029; Wed, 15 Nov 2023 14:06:13 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Alyssa Rosenzweig , Albert Ou , asahi@lists.linux.dev, Catalin Marinas , Dexuan Cui , devicetree@vger.kernel.org, David Woodhouse , Frank Rowand , Hanjun Guo , Haiyang Zhang , iommu@lists.linux.dev, Jean-Philippe Brucker , Jonathan Hunter , Joerg Roedel , "K. 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Wysocki" , Rob Herring Subject: [PATCH v2 14/17] iommu: Remove pointless iommu_fwspec_free() Date: Wed, 15 Nov 2023 10:06:05 -0400 Message-ID: <14-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> In-Reply-To: <0-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR15CA0024.namprd15.prod.outlook.com (2603:10b6:208:1b4::37) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|SJ0PR12MB7007:EE_ X-MS-Office365-Filtering-Correlation-Id: 78ae980c-9d84-4f0b-3376-08dbe5e404cd X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qNmDKqSnJLF7/mzcfUL3cdjdbWYGFSmiWcRhg3H/850VdC+MxC6XzeTI6wKOtue2Eow7mvswV5oxNoz3Q30rQQzir+DPkZT3qmQoncSburTIML1ArD/d01682Gernsf1rrK8Xoe1Ypk1X4o6WLFR7Tlr1/VJLxbg+pUo9YR3CeJh5wNCrvGYrIKbbWBd5ZQAIjs4QX0l2HuQr3Exp+1SkMO/PPJG/rXvaomlA5LFmLRvwTb64bzFTUF9i2kVaigOtAr4OXexg9DPCLqPEMFvfujBI3YTqQXjvjeoNhLCKqKxMkLxrZ7Lxb/o2zAgmA9v6bnTguhrDUztVr/ejYBSmuFtEov/ggJquauI6E3fvnAM2J8xzNCCAycOVmlrPXY+K1cA52UvkLLcLMCW8k4CMdBF55a5xETLgWRevIHXeBZv1yvP/uMxLssDQeS+Spg+DE00kQ8vDzxOjsAefV9u2Ca9DY08jPGuSCJ2OoeYmyHCeqz/Rx/2CAcfOw2sDF3ytsiumWA88sXkNlorIBAL6qijOqj3kftAUUB+ImMvVWAxa8EREqI1dNMllHpDdEMDrdsLwrcTQBfPG5SEGOeWiKaNF8hh1+29tlpqHy5X2hA= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(136003)(346002)(376002)(366004)(39860400002)(396003)(230922051799003)(451199024)(1800799009)(186009)(64100799003)(7406005)(6666004)(6506007)(2616005)(6512007)(83380400001)(7416002)(41300700001)(8676002)(5660300002)(4326008)(7366002)(8936002)(478600001)(2906002)(6486002)(66476007)(54906003)(110136005)(66946007)(66556008)(316002)(86362001)(36756003)(38100700002)(26005)(921008);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: enoFHoBcZzDseAw7me972qrcOM9YkN59Ur/T55dFTwh1YTESvUUzW882tL9+3T/UwkDCLFOMHLaZYvtd54nFvHV+e/ac2pHK02bQN9Y/RQTXyDxBMr8oHrWim/5xZtmvrjsW/x07ESAp4Kgx9k1MpOozsprEmhasiFSNuO6yfcypkEpWszoOqzpO6Kf/OvWOp4FqxzfrMHMjx3ES7gp8Z3u/zhUMaBsd1m60YbQUEkiV62wZGpdQZefW8dvCWUY7+/i7cpVyidT2VCi9oglNbvo3N/0o/Dger1FawsL00YV1nhJh+q0NjKuT6sx8SutQVy/rEBUZn2vHGgRA5pTdIvVR8dYgIMJwzJa2cwxd8F+mfhUZzmUAZHtEduL2F2Jk5DOxhbMoRfsrXk1smFtm272aKf5RWYx6xDtocf0zlxtNvugvu67GW31Lms88zMxUke4gy2CKim1OydAa+c9U2qSvcHaOBfPJe94og064QuHtD5tk5E7VbIPbnyI/wnV3bNGGXSrFlZkKCjkmlqjknXYKJP0Ffm3aowNufDEJOwc5+L5dMGNKEQb8/y29aur0H1KoMPS0gSH9XM58u4L/5GuCebpjvU4Q5uwrWanFeu/s335kZ2S0y3J7n6szyIUABR338f5V7jWzO3qydX6cIMPnm4G3Zhr9rkwVu+AFiwBWFD7JAj5OdEs1LOXaxSQAd8AO5OFdJpgSWtnRr6FuswyNH/LmC51/NW+iv0gIQ4FYElDKirTWmDoGR+TpjVz4X6S3+zOdOc9qd22W3qzH6zEE/js46WuuMykapplofUAKtzDOEk6w20Jfn15lJWF3ijMOjCdCbH9JPR/v9y5oCSCTyAzJ2YEzs70iX/732DVrYua6w3UldVfB3aYRHPxAUh7MoE/+R+EIz51sKxUC7uMVa3iHfYByS7Ualp3RKEpGG/0hsG6wmrtIN7wSHw1zNETwn6IQv2TQ+mUrwYfYjVlO+Y187jnIQq9iV+kENZVOAMn9s1Sarxytk+OkvmXBKYi2QJaZcIjjbfOJpMHCclZ8rTZSwBSabM2OHMyZXKe7BuqlSCJV4L4IBnLLzovDboLPj1SqFHktj64fJyI86/DzjF2nEGJIUWJ6v7C+/+shB8SHoWymKWDO17q8mnqeD7z7dhsQM3+pE4YfW3+QpfPsecYdxvCULRN636zMAMLAIraZrntGnXXOfwi0GiBWyvd00BFXbSTQ80SO2tohu/+mfKzNMCgflwIiygjYWaeGzHQQVnfvi410JFYWoC3LxPpB5F0SiFEER03H7xYnWULqzfCtBnGkNPPxIxv5JmTrw6oaS1Xyztz7BdY6Bv5zUCW2XiMcEJ6P78t8F6+ZN67PKlwATkAQTtuLgcPT6Gd2nZLig5im3hbmwX4EhsPg2uJv2v8MCsmHVZpE5yTite+Hvsx9CcpPmC5Pdfq5/nmJRIQwPTvnL3zRccRR+8lA0TsUaDZELMR+gNfvb5FR+K0itQg3dk9LiRwc6UAoIzTqqlJFsCgJPe/XzxJxuL43P7VoQhlY98AylstkS05PLqw9UlPnKd7/3wvfCorEoVM= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 78ae980c-9d84-4f0b-3376-08dbe5e404cd X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 14:06:10.1336 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 86fgSq9JBJCJJvzy4+WJNLBtVDmNvNFopwEByebpkwvow0MF4maohj/deHLFiEWf X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7007 These days the core code will free the fwspec if probe fails, no reason for any driver to call this on a probe failure path. Reviewed-by: Jerry Snitselaar Signed-off-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 14 +++++--------- drivers/iommu/tegra-smmu.c | 1 - 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index d6d1a2a55cc069..854efcb1b84ddf 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1348,6 +1348,8 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) if (using_legacy_binding) { ret = arm_smmu_register_legacy_master(dev, &smmu); + if (ret) + return ERR_PTR(ret); /* * If dev->iommu_fwspec is initally NULL, arm_smmu_register_legacy_master() @@ -1355,15 +1357,12 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) * later use. */ fwspec = dev_iommu_fwspec_get(dev); - if (ret) - goto out_free; } else if (fwspec && fwspec->ops == &arm_smmu_ops) { smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); } else { return ERR_PTR(-ENODEV); } - ret = -EINVAL; for (i = 0; i < fwspec->num_ids; i++) { u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); u16 mask = FIELD_GET(ARM_SMMU_SMR_MASK, fwspec->ids[i]); @@ -1371,20 +1370,19 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) if (sid & ~smmu->streamid_mask) { dev_err(dev, "stream ID 0x%x out of range for SMMU (0x%x)\n", sid, smmu->streamid_mask); - goto out_free; + return ERR_PTR(-EINVAL); } if (mask & ~smmu->smr_mask_mask) { dev_err(dev, "SMR mask 0x%x out of range for SMMU (0x%x)\n", mask, smmu->smr_mask_mask); - goto out_free; + return ERR_PTR(-EINVAL); } } - ret = -ENOMEM; cfg = kzalloc(offsetof(struct arm_smmu_master_cfg, smendx[i]), GFP_KERNEL); if (!cfg) - goto out_free; + return ERR_PTR(-ENOMEM); cfg->smmu = smmu; dev_iommu_priv_set(dev, cfg); @@ -1408,8 +1406,6 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) out_cfg_free: kfree(cfg); -out_free: - iommu_fwspec_free(dev); return ERR_PTR(ret); } diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 310871728ab4b6..e3101aa2f35689 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -844,7 +844,6 @@ static int tegra_smmu_configure(struct tegra_smmu *smmu, struct device *dev, err = ops->of_xlate(dev, args); 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Wysocki" , Rob Herring Subject: [PATCH v2 15/17] iommu: Add ops->of_xlate_fwspec() Date: Wed, 15 Nov 2023 10:06:06 -0400 Message-ID: <15-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> In-Reply-To: <0-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR11CA0027.namprd11.prod.outlook.com (2603:10b6:208:23b::32) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|SJ0PR12MB7007:EE_ X-MS-Office365-Filtering-Correlation-Id: b1c2f9f8-00a0-479c-f556-08dbe5e4050f X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AuVXENTqbrGQCV1jo64LTEDBXP9j3MJFPxnDJU47drDW6sE73fS6p88avtxNclsClzrlyHs/V0nhmBbuLyyTDpiRrorZFwVBLVgnDQfmVeOLvXihhUBfAyergBUgSHpOXYhRTL6GYhBHgpSY1WnX68S8Xr8aFDiZJleHw16pa35JGNtmztODZwda8a551/ZifZTyDRFJG94Lf2a/lqLX29F2QzAjRRVnehVXAwZFqjIM3VzSajOvy6CKzMPrQd0qgD4CSbcvKU7KHZXfZ/PmCsQAO3DXBGVh9msO7trFhWhvO2QS8MMvqJOFWrXkbO4GGe7S7d7U9vi44xbj0PmfmwvNBqIHWYfu4p7ovQFZlL6GgXRxCkJVZ0GbXmtWdSbbMND3zqQW9cAcBeBuZLBGK5WVjB3gaGJG5JqSrb/HT+mCXl43UoDcr99mu7LUUcfk9jQUk14uZsMYrTDWRpGVT4bH0JKaZK+a1tL2hZoLsFftm2J9rpPQbXDn5DjW7UZ44ITqgnd52/RFeQbk3dzovrDfEfqAwIB2Yxbb5TALHaOVnhQ6BRAYiNCkOnoZDbnPy+ZmbDHo4TiFXD6nCwmsGowxG8ePTiREYL4AnouCEUU= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(136003)(346002)(376002)(366004)(39860400002)(396003)(230922051799003)(451199024)(1800799009)(186009)(64100799003)(7406005)(6666004)(6506007)(2616005)(6512007)(83380400001)(7416002)(41300700001)(8676002)(5660300002)(4326008)(7366002)(8936002)(478600001)(2906002)(6486002)(66476007)(54906003)(110136005)(66946007)(66556008)(316002)(86362001)(36756003)(38100700002)(26005)(921008);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 6+ZxTZH4tMQT+XeOCjsnZ4kqX9jC/ju2Pxg1G6R1k60K9MyC0cD6w9CVS8mRJoeHM5QYrgZCC9FLxip9JnFSvNlmpVwOVVcPUsDd5D/Dh694Nbay6gtSfKFJNLHrwB+X4dQuZQmP135EWFSdashAjZa7RBnU4vH/+z0peWKGgaZMo0zkb5s+vSzF9VI/0Rcic3pxHXq4UqMfcNVOpGTo/2e2mhlJ0t0GAI+IlidxH0CMnG2Px2Er+k9eTIU2wPs1UTjbnzbYW/1paeBas1puvYsoYsxDMhYUmzQNnvefao2YLAEFrSBQP1XpRp0Z3nByaKlZZutV21sFFbBLbigAzU1daBUE0KDdqQFbbnUrT9VY/8XdgW4+62EXFa6rXrW5yjB71Pxi7MpJ3eRn7LA2mmABWYyDbZtF9sVQPVuQReLBLpXxh6P2gmT102Ejk6vd4YH2b5fsU36vLXRZaivUSHQqNSFseqRVBiBi1GdC13MEJw2V7QK0A9MslV1pRnVVENpzWDtvDMJmvjxtxJ0YUtjEvV6N/mh3Bumlbfky3eplgQ/xTzulZ9RwYW+NqPJNoWw35YnUOEScALP0cTw437YRtJO/F7rE/j0dXS73EeGwqM/UBJs5VGmgOd9Ez+7J9ivabEVHRV5l6JsrbtGYX+GGPWwkTFArpTrcanRidtz1calvJsx2IjcTpmbPRV8MJOBl0SPYzUvR+3t/QrwrHHIL9OGG5nm0geFsVw2dY4LKAj4raQOJOzIEaCxYxp9cioR54nBDoTJYc65i0C8KHUV3lmJ0/Q1Ah8E5p39X2qBgEHnqdxPBALYtOFuQ0kbgy9YOQxjN+/tXYY8bnmflvO/6nYGOnRppcl4WydKJf9F7QftvQWtf89URNbljzDauBmeNZpGnbsnq8OurZNFD+brBFiwivHK5REzxfzNVDkyONV01xE9b4OW2LLSyKpc4tDbTKjkcI979+dBRX5UU+twkKu/kXe3gpa+3sKpkhpAkwJjNDpXAHvxWzEhF1rpxy/usfuc43wBjWQePCGQDHzRUi5OkBg8Hr2+/m2pWUP+d1rLhTaSqx6XEEnWP96GR8jQgd0HVLo9ikXpBC6KFdSphnjKC7VyEVB2n0P9MWYJmvWKn7AkIDmKD1+r7umCJ2QqzBeqy0X7DIKJgNW126yxAWcLjqRrFFIFo3h16bm68mamgC6LmRNlMudCsEOQQ9A6WNAvyBphaFIfmGr0byf/6362nCWgSWJOAOz57tfE/f5bFx/WG62tfY4K7EXRD54GvRsWt5UdzX2RjcsnipJ99hSjKJBHRqaoJAZGdRrap56vMGQNzrVCRnUG0j4pj7uhhxkbekOkCx5OY5rtz5ORA5UY2YZsPzx1Rb+uiKxvBYExF5M9/uqIXKGzu+Q2YrOCPPxhYrNUDX7oMDmhKIRfJxFWOtVEvOTHRrx0A3iFHdgD4Uup4tZ4NusyWgt1HnZfdRAyTGglHYXYSERoFzY81iajuHflFbzyxra2cs5Ej5Blmoeu2rTsi0RODnmjyF76eGs6EnL4ggWVju0RYNbgIXe+OPVNdKwv29uoturg= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: b1c2f9f8-00a0-479c-f556-08dbe5e4050f X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 14:06:10.5041 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: pUipwaw1jn/9ZE0o6HKl6sPblNHjYOGgLuv/Ik/MnFR9uCME0ffxG9PcqJGV1z1j X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7007 The new callback takes in the fwspec instead of retrieving it from the dev->iommu. Provide iommu_fwspec_append_ids() to work directly on the fwspec. Convert SMMU, SMMUv3, and virtio to use iommu_fwspec_append_ids() and the new entry point. This avoids having to touch dev->iommu at all, and doesn't require the iommu_probe_device_lock. Reviewed-by: Jerry Snitselaar Signed-off-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 +++++--- drivers/iommu/arm/arm-smmu/arm-smmu.c | 8 +++++--- drivers/iommu/iommu.c | 3 +++ drivers/iommu/virtio-iommu.c | 8 +++++--- include/linux/iommu.h | 3 +++ 5 files changed, 21 insertions(+), 9 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 7445454c2af244..b1309f04ebc0d9 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2748,9 +2748,11 @@ static int arm_smmu_enable_nesting(struct iommu_domain *domain) return ret; } -static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args) +static int arm_smmu_of_xlate_fwspec(struct iommu_fwspec *fwspec, + struct device *dev, + struct of_phandle_args *args) { - return iommu_fwspec_add_ids(dev, args->args, 1); + return iommu_fwspec_append_ids(fwspec, args->args, 1); } static void arm_smmu_get_resv_regions(struct device *dev, @@ -2858,7 +2860,7 @@ static struct iommu_ops arm_smmu_ops = { .probe_device = arm_smmu_probe_device, .release_device = arm_smmu_release_device, .device_group = arm_smmu_device_group, - .of_xlate = arm_smmu_of_xlate, + .of_xlate_fwspec = arm_smmu_of_xlate_fwspec, .get_resv_regions = arm_smmu_get_resv_regions, .remove_dev_pasid = arm_smmu_remove_dev_pasid, .dev_enable_feat = arm_smmu_dev_enable_feature, diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 854efcb1b84ddf..8c4a60d8e5d522 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1510,7 +1510,9 @@ static int arm_smmu_set_pgtable_quirks(struct iommu_domain *domain, return ret; } -static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args) +static int arm_smmu_of_xlate_fwspec(struct iommu_fwspec *fwspec, + struct device *dev, + struct of_phandle_args *args) { u32 mask, fwid = 0; @@ -1522,7 +1524,7 @@ static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args) else if (!of_property_read_u32(args->np, "stream-match-mask", &mask)) fwid |= FIELD_PREP(ARM_SMMU_SMR_MASK, mask); - return iommu_fwspec_add_ids(dev, &fwid, 1); + return iommu_fwspec_append_ids(fwspec, &fwid, 1); } static void arm_smmu_get_resv_regions(struct device *dev, @@ -1562,7 +1564,7 @@ static struct iommu_ops arm_smmu_ops = { .release_device = arm_smmu_release_device, .probe_finalize = arm_smmu_probe_finalize, .device_group = arm_smmu_device_group, - .of_xlate = arm_smmu_of_xlate, + .of_xlate_fwspec = arm_smmu_of_xlate_fwspec, .get_resv_regions = arm_smmu_get_resv_regions, .def_domain_type = arm_smmu_def_domain_type, .pgsize_bitmap = -1UL, /* Restricted during device attach */ diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 8fc3d0ff881260..de6dcb244bff4a 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -2983,6 +2983,9 @@ int iommu_fwspec_of_xlate(struct iommu_fwspec *fwspec, struct device *dev, if (ret) return ret; + if (fwspec->ops->of_xlate_fwspec) + return fwspec->ops->of_xlate_fwspec(fwspec, dev, iommu_spec); + if (!fwspec->ops->of_xlate) return -ENODEV; diff --git a/drivers/iommu/virtio-iommu.c b/drivers/iommu/virtio-iommu.c index 379ebe03efb6d4..2283f1d1155981 100644 --- a/drivers/iommu/virtio-iommu.c +++ b/drivers/iommu/virtio-iommu.c @@ -1027,9 +1027,11 @@ static struct iommu_group *viommu_device_group(struct device *dev) return generic_device_group(dev); } -static int viommu_of_xlate(struct device *dev, struct of_phandle_args *args) +static int viommu_of_xlate_fwspec(struct iommu_fwspec *fwspec, + struct device *dev, + struct of_phandle_args *args) { - return iommu_fwspec_add_ids(dev, args->args, 1); + return iommu_fwspec_append_ids(fwspec, args->args, 1); } static bool viommu_capable(struct device *dev, enum iommu_cap cap) @@ -1050,7 +1052,7 @@ static struct iommu_ops viommu_ops = { .release_device = viommu_release_device, .device_group = viommu_device_group, .get_resv_regions = viommu_get_resv_regions, - .of_xlate = viommu_of_xlate, + .of_xlate_fwspec = viommu_of_xlate_fwspec, .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = viommu_attach_dev, diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 352070c3ab3126..3495db0c3e4631 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -43,6 +43,7 @@ struct notifier_block; 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Wysocki" , Rob Herring Subject: [PATCH v2 16/17] iommu: Mark dev_iommu_get() with lockdep Date: Wed, 15 Nov 2023 10:06:07 -0400 Message-ID: <16-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> In-Reply-To: <0-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR15CA0030.namprd15.prod.outlook.com (2603:10b6:208:1b4::43) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH8PR12MB6916:EE_ X-MS-Office365-Filtering-Correlation-Id: cd57df2f-70fa-4365-9035-08dbe5e4054b X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5+PCHwyQoTgcnmOhU0+wAdo5BJF9MNJThP2tjYcfTlDLIRfE6+NZFNDhHZ5MLgPyVYyONBOoLyAV1MuagOj6dvFwDmvWvybBwzKbma+IubR/CmGpimfDV4kInJMssRgZ5fKwarqEs+m00IWa+mQuCyqJjq7/sguQDYXTor4LsPV5doaLPU7liKDX5yehsQb3rRrM2fA7dHhCbzVtNXxeFcUiVVVJMIXXYtkEmcMbY5yXtIGPTsmRtD0O+CE9PqMdiw5QHGfHGRbAccHZ6gEu6YEpBN37yp/Ul7g5XSRVhctH8Y5mUn36Xbq7lSrCAs5Sc6xw1r/hm4YxVq0ZdAl5cWrf4AKawUqTiG6oWedoldwvuxqDZxSybt6Uriqv7SzcAAz1IuQSkUHj5/UUJtJHPe9mIyAeaqDCdbSCYJ7OZIeyvikaYjWZbL2jqej7v9vlZ3HLftk0rSZQxwsBYp3tWgnUNXkGlUurxJWLuX5rIsJ0iX0qZV4EKTm91RwdWnu2WXT369LCWCKQBZT/pRjy+hoclCIbhqIxCqr6SBQzWIRGHT9HqAmPy/zcWdJ1+ZYpb+9Qe7DRas9HEhYutmmHGpBZL9nFu2lp5iLSbBqoUf0= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(39860400002)(376002)(346002)(396003)(366004)(136003)(230922051799003)(1800799009)(64100799003)(186009)(451199024)(110136005)(316002)(66946007)(54906003)(66476007)(66556008)(6486002)(478600001)(6666004)(7366002)(86362001)(5660300002)(7406005)(7416002)(4744005)(921008)(41300700001)(2906002)(36756003)(8676002)(4326008)(8936002)(2616005)(38100700002)(26005)(83380400001)(6506007)(6512007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Ua2aJLcFIbc5+itcPpnHBFBTlyrcf8EJZLPTpR0ouZnfSMAVqcDM5urushXdtM4fFQeqXnOxgbygNVorw3yAXqF1vRXU1ZLhbzBf0IRGQNjCgB3751V0B1BTeNCU5YtpkhyHXoMPCa4iN314wodKSjs55dTx3LMdgovijS+2zVNiSYhcaWYhXPfI7S1n5sa9MznopuU0TOKac4LZLVug2FmeCSSe8cZM6WE6WnBxVM4aXaiCCh5TVTU3RIA96Gp3HwFRoW/SrFa2qQRijp4hLffit5rmOaBGuzDajX6jM6zlFOCMOREIqiOXjUsfVvnavoPdKxTJymkp5XHxNzqJQ/f/DYRKKSQxqHHWKNdQpLDwAXLo3lQ81vlkISlkiZ5vA/Q8fePktKFFIHffVFkg7kGV1oKrOwsywfHlQw7JD93NcsAbRHBUjCB0601qmYqjayjfvyojvTI+on1ZH13TJ+pLDMG6UpoRQw74ZP4/UmtqM2hIDt9IMK2H+xC2AW1kDts7QRpehkhyiwXdO9puJhSv22sT2sC2gi6Nby7EgVV0tunGZyHIib8ZDdr94rBojMMHZPIfI+WRwyTYmC9cfMZj1o4hbGza38ly2GoQ1xF+uF+rvMWqNPAr1YRtk1mVNPbN+0Ohyqr3LcVIrwkX0RJaw21NtjbQDth7I6mDdIAHYKrXetcFgeOR95rKep4xewWhSb3gSb6mdTK/hXkkHN4nPRB/ymSaO94Z9tnFhWYl9XzcMzttEmv5RKSI15U9IAEPc/84b/s1YsOk6QCkl1fMVaEh1F+n/6uxJfmzc3mB301LKpjOthZpfY17+WpXHiAp7KbMWXK/tC5DdigVRrsYrUveo1TTn0LYQwfwU85f7XB759LVfeZbGOzyTQ4wQ6+eEiDwBdh+hcvlEXnrvdaBGVsxUWFKNf5NDAAz7iodlOWlGYFMbylGTT10l7tn/L0ivb0iWEFRsAi5hj/PAaLgERunztWXDa0u8p8mLAP9bwBz6pTPmVahN44xSPmYcrAONazAds2lbHRtz/kGlLSBWiXHx1RIxbYNcqxK9r94ExnvSpXqrxV30XxZOGOYx+pxyJ4A8bj9q8pUcqT3cj81BhivsviRa0s6O8VXc8jql435vd4NTAdFlOADzqr1+aKhQlYEIRgoB3IR/oJldgApuX96E1PulMK/CmNwzbJ8xHC/stRQzwTJAWtn8t833ZeKznY6A0yjfOnDD75SEjkXPHH+2EQzAxGi8n+tacxcxMFwwo9cn/jVyAGSIL+kiLbppyKEx+2/BkApgjBDLNaPeJcDWJIDb2ch1yI/Rei9ca7RFjj+D4F3i9PpbWzdoIwh7e8C7MKa3HpNP2f07Uk9cIJyCpmRKq+Q/RDNfGa/sBSkRYmPnSsqlPTAkWfmwppCQKK4jr9VGeqE0d8W7CUakGAjRhfW/Qrbw6PaRMSz/fK8u1jet2BwJKlSpE+mKfr71Siwvxo1TgqSjKCALDobUHKVYOpM1W7pTYgdjwqIK0YpG7CXbIVw/nksIJFTheYhzPl+hpqk8z0FCetxEIuB68Ob4w59P2k4cJInqHk= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: cd57df2f-70fa-4365-9035-08dbe5e4054b X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 14:06:10.9323 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: TfvvkzP18CpfUqZFB3Z1GoS5XhWLYoplp+SyiKUoGPeZB5/IG2hxCOyiQvqFe3qg X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6916 Allocation of dev->iommu must be done under the iommu_probe_device_lock. Mark this with lockdep to discourage future mistakes. Reviewed-by: Jerry Snitselaar Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index de6dcb244bff4a..34c4b07a6aafae 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -345,6 +345,8 @@ static struct dev_iommu *dev_iommu_get(struct device *dev) { struct dev_iommu *param = dev->iommu; + lockdep_assert_held(&iommu_probe_device_lock); + if (param) return param; From patchwork Wed Nov 15 14:06:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13456736 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 402C5208CA; Wed, 15 Nov 2023 14:06:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="IVhPFLV5" Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88A4011D; Wed, 15 Nov 2023 06:06:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=e77UutjJtK2uoNSL0JhrSh09GOFve/uwDy0qY7X9ugyGfO18F+HChWT2Yd1ySwxWtRcaw/de5HehtXd5BmZbCM9kpnKyxPCfbJ6+2g0oe4tyGhk1X+vUw6DQf30PoUhpV4p35sGgkRABVIsqQKLwHAhjLm+r4pQfKByIiuDfc7Kgf4pxu96aq2vKKkOv49ZYg9awAp+cz/ZZejkefORaTGeGYnu18iNlsQ0AnmL5976GCEUi7Ew10N4xcZE5XiEMM3tf8bgqzOEqAflsJihrXfyFRpnuc/RgKvd5kuhNumFsWMm59E/aF7pPgYsbsx2SNgUTcbleEn8CyXndDgoqKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=h1GujaaPcQbdHtiaRGjCcNI83AftjT8Nj3eA/aJbfRg=; b=OK4pHeuKIoow80ktkUWHf5j449fMsilxNZPy+z62rLg7Fh5p6aAr+Sv+kLvsV9e5gstWkWap9ZW7VvoVdocgl/0PegQNqKuU8UWkTF9Rq32mS5QkXeghueRIzXUR3elkC1vQEGA+nAPTZk+LWZBWdPXuWNhXPzeWoKTqzPiqNtfjYRO+NPuG9hskZOlUVUNrHXdCt4U+lF+8NIBiOUFqz+mbJMax974lhMcw8/m+5TX6MbIIiwNcLFZI+jtORl3ctQ2l6ixFLW6c/2rDsBj5OdGRzX4RWyhTqBJ2NqfdeaG0wXm5DrYBwV3JRO0Ifxi+u6JsgqMHHYpXnV5gmV4wyg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=h1GujaaPcQbdHtiaRGjCcNI83AftjT8Nj3eA/aJbfRg=; b=IVhPFLV5h8oQ5RHN73YYWym7TYHqgqfaFf8F+evXaQuwk0Ue6o3NwXlPvFLnnsqDGYHxnC1+uRZBnlY888mvsOpWO1OAmynwQVyDtwA3MmvdRcMPstLqlyeEP2OFvhUP+YRguV4RlznuAaLPxCj0Fc8KncMa/33Nzudd1rlJerMIO+WVMoPAISxB+s1uja8hl6TNPC8qDiQUJrmVTwiUPFB+y+EzmIr5JtamtvYSKKXTP+mg31KSexGZ9VMCpca3xkcBnN2wU4qpkSj34RrMjSrUpm+Mt9QhxQPsucaYnC0TuXOafoC07MdvHKs5ZIrsj5qbsj9muBbUoNyWWRn7AQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH8PR12MB6916.namprd12.prod.outlook.com (2603:10b6:510:1bd::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6977.31; Wed, 15 Nov 2023 14:06:15 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.6977.029; Wed, 15 Nov 2023 14:06:15 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Alyssa Rosenzweig , Albert Ou , asahi@lists.linux.dev, Catalin Marinas , Dexuan Cui , devicetree@vger.kernel.org, David Woodhouse , Frank Rowand , Hanjun Guo , Haiyang Zhang , iommu@lists.linux.dev, Jean-Philippe Brucker , Jonathan Hunter , Joerg Roedel , "K. Y. Srinivasan" , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hyperv@vger.kernel.org, linux-mips@vger.kernel.org, linux-riscv@lists.infradead.org, linux-snps-arc@lists.infradead.org, linux-tegra@vger.kernel.org, Russell King , Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Palmer Dabbelt , patches@lists.linux.dev, Paul Walmsley , "Rafael J. Wysocki" , Robert Moore , Rob Herring , Robin Murphy , Sudeep Holla , Suravee Suthikulpanit , Sven Peter , Thierry Reding , Thomas Bogendoerfer , Krishna Reddy , Vineet Gupta , virtualization@lists.linux.dev, Wei Liu , Will Deacon Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , Lu Baolu , Christoph Hellwig , Jerry Snitselaar , Moritz Fischer , Zhenhua Huang , "Rafael J. Wysocki" , Rob Herring Subject: [PATCH v2 17/17] iommu: Mark dev_iommu_priv_set() with a lockdep Date: Wed, 15 Nov 2023 10:06:08 -0400 Message-ID: <17-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> In-Reply-To: <0-v2-36a0088ecaa7+22c6e-iommu_fwspec_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR11CA0028.namprd11.prod.outlook.com (2603:10b6:208:23b::33) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH8PR12MB6916:EE_ X-MS-Office365-Filtering-Correlation-Id: 3f8cf913-e808-4457-e104-08dbe5e4051b X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NBnV+3+sCeD6bpEZFjODNEbAsY7ndRKIQKbI/7waKsRhxVYz6miBgl2fhZJMAe/RXYfts7OYc7KTGyTtFSD1F6wUB0subQxNM58t59M9zcUd4Ff5GZ/0V0HCbXXN/tMw7jXWuRbxfzBNztSGFfDoXobpFTioFHaJviptZkOyr/Xq3PEmvoir8zeaFzVH9B/mpY2qm27K1ZL9VckFYShtbyAr0dz+e/mJcMA7GbINB48PizlS27YzFzKVVlSD/WiSwWllmx3JvUnxCkdQGD5MvKVRfMLBVYYhRLeNytTpNxMq3Tkc2mPZz1mLJfwTyO1TrU5CN/txqvVFFFm7aijEPPnNlCO0iAofQR60GrDDk4U0opPjUBrOpRcTSOt0xF0Rup1Je1obygi2reRgArHm246GqPyAXEvoxj+lC15zzZrSF9lXwpXS1iBQygQVic3KoEORNdzU3PLawfg8i/1STn8SQ81cyl9l6n9zbIGbKsoDwjB/iZKwL3mmhXotfdAwph2P1k2w8KOP0CW8Xl0vP4MVf6TRp2OjZ91OzvHL7/wCIwdw8/mhp81sPCyC3yHiPvfnQHR4BUDbOzHBUvFxcNOwNxicfqOysq4LWEI9NaQ= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(39860400002)(376002)(346002)(396003)(366004)(136003)(230922051799003)(1800799009)(64100799003)(186009)(451199024)(110136005)(316002)(66946007)(54906003)(66476007)(66556008)(6486002)(478600001)(6666004)(7366002)(86362001)(5660300002)(7406005)(7416002)(921008)(41300700001)(2906002)(36756003)(8676002)(4326008)(8936002)(2616005)(38100700002)(26005)(83380400001)(6506007)(6512007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: e0if6SP1GlB9PDzgRPtOZWHLnGvb/YeRiMRnt0KYqynBMhSZen24QMDVcB0qfbxQoLAYuEMleO3c+u4yfxHV/tfbSc6HGSoqapW3ohxGJnPdeoht7LPak3XmGGtse7Aa7eX3J/faF3NP/wJS+nCKgBumkTSojcT8vrZDuPlThmw69K441S/s44c29mqjIYMKzQvOA6RS36ljUkhTTXvc2h9y0uLloa1W8eoaV8KGxT0tmdruFJXDCCFC44V/0C+slM66e9qBW39/QlrNF5KtUcW0NfHYHRrZNMSWu8mxr/KNWphEHgfj10Rsrxg73ZMHpf4dGSo8ELaCgXjXwSIiM7OTUs1ac1mFV5ReZ6JugObpR+y8FjH9szIw7wdumL8cL0wxG4tppkqUUZIEtDfvqc0333yDnOA6RE+aHKQczKLM1PTm83DeZicz0oVtBgR49GiyZnohvYpvjKL1jYuwWxqK1/crPqwJ6KscOFIjsyQV3yzE1YcHgPiOySjSMsJAtOGVCcWgu5sY8Id0JvkOwLUs7YQXbgNmFRJB08cTL0VxEudjLJ59hWvYvVDmCyJjYZ4EtFgNSN9ozyiXMk7cRJHcTZQSB6fxrjTLL0kxk4XKU2oeVz0ptFAuqEk/L7B8rsK5QdBrOaLtcjWstGlBtwfxSfrdJOoPzUHSxAmwSNcZR7Ly3fs6Pe6CZygsL7cBzx2Kwu7PhNynN69oWE+WnZr3NdJvZb0mIHw+68stfW6x4YB78xpmz30s1XgBmJJlDsRSdPolU/+iNdh1rVSSuLHYzG9oJSLUNUklwYen7YuXpVRop57mRfymBvTnI0f2J/iyQe5rAW6QOaRlm7orfmnN11/yUoYurBf3VWkytDCPzEe/SVf8wg9MKA0nbvv8PWuPfxaNnHFha5WiwJSIVBHvGR5/05cmH7QUeLSC7aXYTwuGEWcUilxojfiJMwJiRgBB3ZfLlp2GWLO5VrXusF62I34S/7aVavn78SLAQO+Aljpsls+vkMRZNyRQXS5B1fGJ+NZSMxHI6Vpux3Mg3QaKj/2Rp12dj5x+EG1zXaHJfCCVbrgoHWYh4IlJ/MzhWCKEXK5vmvtta8/NjIZJS4AuT1pvmnELyQJaYZmuBbZ/XD9XrmKHiYTfYY8OhQ07mwWon6r/iyWTgt3aobYvL14ztjM686zxFGM1IWegljBK+PyZif9r957gvTASIGKubBpylxDWdzHqq1xhh4Z2O88jne2HxolChUYt30kjkrK/0iGjbwurSkcjyZsBhB37677N4acK1jJ0eGQjQP6iNTywPFnwS0yX8KksDrLvHF0BB6OdKZWG1prHYQ7FccUamti7RXtKhRRGzO943AyYQMsabQnCmJ/pecSdX+brAtv7knvU2dU9Mo86475/oaKnIwi4aS7hP/Rt/FAz+MBoOF+BnfIjeZkKslSX2HXKHSmW9QwMxrHnfk5UL6vNk9mvDLq2u+K/EGC0dCCVA7+w4SOLUSm024vCbbXWHHOP/4MFXqS0G8xOqvLOGSuXJ/lYGJwXiKOdNboIGfc0prtCDjg+OwX+nXxIdgvh1TK97Ps= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3f8cf913-e808-4457-e104-08dbe5e4051b X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 14:06:10.6128 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: jYB4zXZxebzO9WEXDZ4ZJaJRplN3TWVB05TDh50kBnIo457V1UZKTVQEx6vynJQn X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6916 A perfect driver would only call dev_iommu_priv_set() from its probe callback. We've made it functionally correct to call it from the of_xlate by adding a lock around that call. lockdep assert that iommu_probe_device_lock is held to discourage misuse. Exclude PPC kernels with CONFIG_FSL_PAMU turned on because FSL_PAMU uses a global static for its priv and abuses priv for its domain. Remove the pointless stores of NULL, all these are on paths where the core code will free dev->iommu after the op returns. Reviewed-by: Lu Baolu Reviewed-by: Jerry Snitselaar Signed-off-by: Jason Gunthorpe --- drivers/iommu/amd/iommu.c | 2 -- drivers/iommu/apple-dart.c | 1 - drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 1 - drivers/iommu/arm/arm-smmu/arm-smmu.c | 1 - drivers/iommu/intel/iommu.c | 2 -- drivers/iommu/iommu.c | 9 +++++++++ drivers/iommu/omap-iommu.c | 1 - include/linux/iommu.h | 5 +---- 8 files changed, 10 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index fcc987f5d4edc3..8199c678c2dc2a 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -551,8 +551,6 @@ static void amd_iommu_uninit_device(struct device *dev) if (dev_data->domain) detach_device(dev); - dev_iommu_priv_set(dev, NULL); - /* * We keep dev_data around for unplugged devices and reuse it when the * device is re-plugged - not doing so would introduce a ton of races. diff --git a/drivers/iommu/apple-dart.c b/drivers/iommu/apple-dart.c index ee05f4824bfad1..56cfc33042e0b5 100644 --- a/drivers/iommu/apple-dart.c +++ b/drivers/iommu/apple-dart.c @@ -740,7 +740,6 @@ static void apple_dart_release_device(struct device *dev) { struct apple_dart_master_cfg *cfg = dev_iommu_priv_get(dev); - dev_iommu_priv_set(dev, NULL); kfree(cfg); } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index b1309f04ebc0d9..df81fcd25a75b0 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2698,7 +2698,6 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) err_free_master: kfree(master); - dev_iommu_priv_set(dev, NULL); return ERR_PTR(ret); } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 8c4a60d8e5d522..6fc040a4168aa3 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1423,7 +1423,6 @@ static void arm_smmu_release_device(struct device *dev) arm_smmu_rpm_put(cfg->smmu); - dev_iommu_priv_set(dev, NULL); kfree(cfg); } diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 3531b956556c7d..4a5792888e6433 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4457,7 +4457,6 @@ static struct iommu_device *intel_iommu_probe_device(struct device *dev) ret = intel_pasid_alloc_table(dev); if (ret) { dev_err(dev, "PASID table allocation failed\n"); - dev_iommu_priv_set(dev, NULL); kfree(info); return ERR_PTR(ret); } @@ -4475,7 +4474,6 @@ static void intel_iommu_release_device(struct device *dev) dmar_remove_one_dev_info(dev); intel_pasid_free_table(dev); intel_iommu_debugfs_remove_dev(info); - dev_iommu_priv_set(dev, NULL); kfree(info); set_dma_ops(dev, NULL); } diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 34c4b07a6aafae..fbfb9ba4da0ee2 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -387,6 +387,15 @@ static u32 dev_iommu_get_max_pasids(struct device *dev) return min_t(u32, max_pasids, dev->iommu->iommu_dev->max_pasids); } +void dev_iommu_priv_set(struct device *dev, void *priv) +{ + /* FSL_PAMU does something weird */ + if (!IS_ENABLED(CONFIG_FSL_PAMU)) + lockdep_assert_held(&iommu_probe_device_lock); + dev->iommu->priv = priv; +} +EXPORT_SYMBOL_GPL(dev_iommu_priv_set); + /* * Init the dev->iommu and dev->iommu_group in the struct device and get the * driver probed. Take ownership of fwspec, it always freed on error diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index c66b070841dd41..c9528065a59afa 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -1719,7 +1719,6 @@ static void omap_iommu_release_device(struct device *dev) if (!dev->of_node || !arch_data) return; - dev_iommu_priv_set(dev, NULL); kfree(arch_data); } diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 3495db0c3e4631..8be153a54c8ca2 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -852,10 +852,7 @@ static inline void *dev_iommu_priv_get(struct device *dev) return NULL; } -static inline void dev_iommu_priv_set(struct device *dev, void *priv) -{ - dev->iommu->priv = priv; -} +void dev_iommu_priv_set(struct device *dev, void *priv); int iommu_probe_device_fwspec(struct device *dev, struct iommu_fwspec *fwspec); static inline int iommu_probe_device(struct device *dev)