From patchwork Thu Nov 16 13:18:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13457891 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2BF70C197A0 for ; Thu, 16 Nov 2023 13:18:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CA86A10E5DA; Thu, 16 Nov 2023 13:18:47 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5CC1B10E5D8; Thu, 16 Nov 2023 13:18:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700140725; x=1731676725; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JfV7Uu+OT5A/m9+BJcsKjzT8vpmqyhGWO9tixPjFoYs=; b=Bi0ZCQfIk1G/XnGvGkKw0LPtPSrYNoLsVii+Yn8oAdgGarrKwKdYx9BO TzOebkFgvXJ+2ShxIOXvLvYE+mfQ7VV/sJlApuiCsRJZv+AdBHKgBXgBB kd7zueW+fqDyetkYZ9f9Vvt2a84bHQL5/XJExdpSsaDSNDMLtAVpxCxJF LYu50pbvAKKMRk3a1MuGn5J1hePEHEKu/s9/JnnYEShriovJxg1hxvWwA OsX+bv9klGGZPobHfpwltSORBRYWfXhRp84oVVqlucme1dnv65NshWx7w +c+LLlJcOaKN81qNzPlVEfTEGhe5F+MI78U6JYxOQ1jJHtOlXq6fgFpFm A==; X-IronPort-AV: E=McAfee;i="6600,9927,10895"; a="422177147" X-IronPort-AV: E=Sophos;i="6.04,308,1695711600"; d="scan'208";a="422177147" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 05:18:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10895"; a="938834328" X-IronPort-AV: E=Sophos;i="6.04,308,1695711600"; d="scan'208";a="938834328" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 05:18:42 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Thu, 16 Nov 2023 15:18:31 +0200 Message-Id: <20231116131841.1588781-2-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231116131841.1588781-1-imre.deak@intel.com> References: <20231116131841.1588781-1-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 01/11] drm/dp_mst: Store the MST PBN divider value in fixed point format X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Wayne Lin , Alex Deucher , Harry Wentland Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On UHBR links the PBN divider is a fractional number, accordingly store it in fixed point format. For now drm_dp_get_vc_payload_bw() always returns a whole number and all callers will use only the integer part of it which should preserve the current behavior. The next patch will fix drm_dp_get_vc_payload_bw() for UHBR rates returning a fractional number for those (also accounting for the channel coding efficiency correctly). Cc: Lyude Paul Cc: Harry Wentland Cc: Alex Deucher Cc: Wayne Lin Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++-- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 3 ++- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 5 +++-- drivers/gpu/drm/display/drm_dp_mst_topology.c | 22 +++++++++++++------ drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 ++- drivers/gpu/drm/nouveau/dispnv50/disp.c | 6 +++-- include/drm/display/drm_dp_mst_helper.h | 7 +++--- 7 files changed, 33 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 74f9f02abcdec..12346b21d0b05 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -85,6 +85,7 @@ #include #include #include +#include #include #include #include @@ -6909,8 +6910,8 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, if (IS_ERR(mst_state)) return PTR_ERR(mst_state); - if (!mst_state->pbn_div) - mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link); + if (!mst_state->pbn_div.full) + mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link)); if (!state->duplicated) { int max_bpc = conn_state->max_requested_bpc; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index ed784cf27d396..63024393b516e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -31,6 +31,7 @@ #include #include #include +#include #include "dm_services.h" #include "amdgpu.h" @@ -210,7 +211,7 @@ static void dm_helpers_construct_old_payload( struct drm_dp_mst_atomic_payload *old_payload) { struct drm_dp_mst_atomic_payload *pos; - int pbn_per_slot = mst_state->pbn_div; + int pbn_per_slot = dfixed_trunc(mst_state->pbn_div); u8 next_payload_vc_start = mgr->next_start_slot; u8 payload_vc_start = new_payload->vc_start_slot; u8 allocated_time_slots; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 9a58e1a4c5f49..d1ba3ae228b08 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "dm_services.h" #include "amdgpu.h" #include "amdgpu_dm.h" @@ -941,10 +942,10 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, link_timeslots_used = 0; for (i = 0; i < count; i++) - link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, mst_state->pbn_div); + link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, dfixed_trunc(mst_state->pbn_div)); fair_pbn_alloc = - (63 - link_timeslots_used) / remaining_to_increase * mst_state->pbn_div; + (63 - link_timeslots_used) / remaining_to_increase * dfixed_trunc(mst_state->pbn_div); if (initial_slack[next_index] > fair_pbn_alloc) { vars[next_index].pbn += fair_pbn_alloc; diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c index 4d72c9a32026e..000d05e80352a 100644 --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@ -43,6 +43,7 @@ #include #include #include +#include #include #include @@ -3578,16 +3579,22 @@ static int drm_dp_send_up_ack_reply(struct drm_dp_mst_topology_mgr *mgr, * value is in units of PBNs/(timeslots/1 MTP). This value can be used to * convert the number of PBNs required for a given stream to the number of * timeslots this stream requires in each MTP. + * + * Returns the BW / timeslot value in 20.12 fixed point format. */ -int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr, - int link_rate, int link_lane_count) +fixed20_12 drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr, + int link_rate, int link_lane_count) { + fixed20_12 ret; + if (link_rate == 0 || link_lane_count == 0) drm_dbg_kms(mgr->dev, "invalid link rate/lane count: (%d / %d)\n", link_rate, link_lane_count); /* See DP v2.0 2.6.4.2, VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */ - return link_rate * link_lane_count / 54000; + ret.full = dfixed_const(link_rate * link_lane_count / 54000); + + return ret; } EXPORT_SYMBOL(drm_dp_get_vc_payload_bw); @@ -4335,7 +4342,7 @@ int drm_dp_atomic_find_time_slots(struct drm_atomic_state *state, } } - req_slots = DIV_ROUND_UP(pbn, topology_state->pbn_div); + req_slots = DIV_ROUND_UP(pbn, dfixed_trunc(topology_state->pbn_div)); drm_dbg_atomic(mgr->dev, "[CONNECTOR:%d:%s] [MST PORT:%p] TU %d -> %d\n", port->connector->base.id, port->connector->name, @@ -4872,7 +4879,8 @@ void drm_dp_mst_dump_topology(struct seq_file *m, state = to_drm_dp_mst_topology_state(mgr->base.state); seq_printf(m, "\n*** Atomic state info ***\n"); seq_printf(m, "payload_mask: %x, max_payloads: %d, start_slot: %u, pbn_div: %d\n", - state->payload_mask, mgr->max_payloads, state->start_slot, state->pbn_div); + state->payload_mask, mgr->max_payloads, state->start_slot, + dfixed_trunc(state->pbn_div)); seq_printf(m, "\n| idx | port | vcpi | slots | pbn | dsc | status | sink name |\n"); for (i = 0; i < mgr->max_payloads; i++) { @@ -5330,10 +5338,10 @@ drm_dp_mst_atomic_check_payload_alloc_limits(struct drm_dp_mst_topology_mgr *mgr } if (!payload_count) - mst_state->pbn_div = 0; + mst_state->pbn_div.full = dfixed_const(0); drm_dbg_atomic(mgr->dev, "[MST MGR:%p] mst state %p TU pbn_div=%d avail=%d used=%d\n", - mgr, mst_state, mst_state->pbn_div, avail_slots, + mgr, mst_state, dfixed_trunc(mst_state->pbn_div), avail_slots, mst_state->total_avail_slots - avail_slots); return 0; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 0cb9405f59eaa..e5d6b811c22ef 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include "i915_drv.h" @@ -202,7 +203,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, */ drm_WARN_ON(&i915->drm, remote_m_n.tu < crtc_state->dp_m_n.tu); crtc_state->dp_m_n.tu = remote_m_n.tu; - crtc_state->pbn = remote_m_n.tu * mst_state->pbn_div; + crtc_state->pbn = remote_m_n.tu * dfixed_trunc(mst_state->pbn_div); slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr, connector->port, diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index 493fe4660f651..11fe75b68e95c 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include @@ -946,7 +947,8 @@ nv50_msto_prepare(struct drm_atomic_state *state, if (ret == 0) { nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index, payload->vc_start_slot, payload->time_slots, - payload->pbn, payload->time_slots * mst_state->pbn_div); + payload->pbn, + payload->time_slots * dfixed_trunc(mst_state->pbn_div)); } else { nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index, 0, 0, 0, 0); } @@ -990,7 +992,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder, if (IS_ERR(mst_state)) return PTR_ERR(mst_state); - if (!mst_state->pbn_div) { + if (!mst_state->pbn_div.full) { struct nouveau_encoder *outp = mstc->mstm->outp; mst_state->pbn_div = drm_dp_get_vc_payload_bw(&mstm->mgr, diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h index a4aad6df71f18..9b19d8bd520af 100644 --- a/include/drm/display/drm_dp_mst_helper.h +++ b/include/drm/display/drm_dp_mst_helper.h @@ -25,6 +25,7 @@ #include #include #include +#include #if IS_ENABLED(CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS) #include @@ -617,7 +618,7 @@ struct drm_dp_mst_topology_state { * @pbn_div: The current PBN divisor for this topology. The driver is expected to fill this * out itself. */ - int pbn_div; + fixed20_12 pbn_div; }; #define to_dp_mst_topology_mgr(x) container_of(x, struct drm_dp_mst_topology_mgr, base) @@ -839,8 +840,8 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port); -int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr, - int link_rate, int link_lane_count); +fixed20_12 drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr, + int link_rate, int link_lane_count); int drm_dp_calc_pbn_mode(int clock, int bpp); From patchwork Thu Nov 16 13:18:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13457892 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32F1BC5AD4C for ; Thu, 16 Nov 2023 13:18:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0B38610E5DC; Thu, 16 Nov 2023 13:18:49 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id DC09610E5D8; Thu, 16 Nov 2023 13:18:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700140726; x=1731676726; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SVdzxX+o76uHs97K1GMJS2pvOT9GVhRRg9CCqdfPUNQ=; b=ZfQAe/MQsN/SogaEsqA3apbNNEtTuJStfkVxlVOeCr7aWjrnRRvjkA+j yd8uWTGD4p04NvkSOBZQJQPGEHrZnUo62OGAFby5eUosXrTQnFt12jaSv XtIXcLlNOcPAhlpBI1Lxe8oG++2rWcarcsPfURsN7dJCxJE43YKU2CfRm WUFNkhAMflIQmd2Ak5r2+wexR9QsfeGT41qDIYQfVIdpSE0DjBaySQ/w/ iTKTwuJou36g8mlTAh+0M4dJF29nA1ZwUHHkRxOhT3g5Quap0kBMxj88e V/mrfOB6o/T8Zb0mAiO+CfVgtVdYDrdpDf0AJN/IsjAKzmnI5X+Pfo1bS w==; X-IronPort-AV: E=McAfee;i="6600,9927,10895"; a="422177151" X-IronPort-AV: E=Sophos;i="6.04,308,1695711600"; d="scan'208";a="422177151" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 05:18:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10895"; a="938834333" X-IronPort-AV: E=Sophos;i="6.04,308,1695711600"; d="scan'208";a="938834333" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 05:18:45 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Thu, 16 Nov 2023 15:18:32 +0200 Message-Id: <20231116131841.1588781-3-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231116131841.1588781-1-imre.deak@intel.com> References: <20231116131841.1588781-1-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 02/11] drm/dp_mst: Fix PBN divider calculation for UHBR rates X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The current way of calculating the pbn_div value, the link BW per each MTP slot, worked only for DP 1.4 link rates. Fix things up for UHBR rates calculating with the correct channel coding efficiency based on the link rate. v2: - Return the fractional pbn_div value from drm_dp_get_vc_payload_bw(). Cc: Lyude Paul Cc: dri-devel@lists.freedesktop.org Signed-off-by: Imre Deak --- drivers/gpu/drm/display/drm_dp_mst_topology.c | 13 ++++++++++--- include/drm/display/drm_dp_helper.h | 13 +++++++++++++ 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c index 000d05e80352a..3fbd5585d5e6c 100644 --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@ -3585,14 +3585,18 @@ static int drm_dp_send_up_ack_reply(struct drm_dp_mst_topology_mgr *mgr, fixed20_12 drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr, int link_rate, int link_lane_count) { + int ch_coding_efficiency = + drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(link_rate)); fixed20_12 ret; if (link_rate == 0 || link_lane_count == 0) drm_dbg_kms(mgr->dev, "invalid link rate/lane count: (%d / %d)\n", link_rate, link_lane_count); - /* See DP v2.0 2.6.4.2, VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */ - ret.full = dfixed_const(link_rate * link_lane_count / 54000); + /* See DP v2.0 2.6.4.2, 2.7.6.3 VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */ + ret.full = DIV_ROUND_DOWN_ULL(mul_u32_u32(link_rate * link_lane_count, + ch_coding_efficiency), + (1000000ULL * 8 * 5400) >> 12); return ret; } @@ -4315,6 +4319,7 @@ int drm_dp_atomic_find_time_slots(struct drm_atomic_state *state, struct drm_dp_mst_atomic_payload *payload = NULL; struct drm_connector_state *conn_state; int prev_slots = 0, prev_bw = 0, req_slots; + fixed20_12 req_slots_fp; topology_state = drm_atomic_get_mst_topology_state(state, mgr); if (IS_ERR(topology_state)) @@ -4342,7 +4347,9 @@ int drm_dp_atomic_find_time_slots(struct drm_atomic_state *state, } } - req_slots = DIV_ROUND_UP(pbn, dfixed_trunc(topology_state->pbn_div)); + req_slots_fp.full = dfixed_div((fixed20_12)dfixed_init(pbn), topology_state->pbn_div); + req_slots_fp.full = dfixed_ceil(req_slots_fp); + req_slots = dfixed_trunc(req_slots_fp); drm_dbg_atomic(mgr->dev, "[CONNECTOR:%d:%s] [MST PORT:%p] TU %d -> %d\n", port->connector->base.id, port->connector->name, diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h index c5f1079acb3b1..863b2e7add29e 100644 --- a/include/drm/display/drm_dp_helper.h +++ b/include/drm/display/drm_dp_helper.h @@ -252,6 +252,19 @@ drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP); } +/** + * drm_dp_is_uhbr_rate - Determine if a link rate is UHBR + * @link_rate: link rate in 10kbits/s units + * + * Determine if the provided link rate is an UHBR rate. + * + * Returns: %True if @link_rate is an UHBR rate. + */ +static inline bool drm_dp_is_uhbr_rate(int link_rate) +{ + return link_rate >= 1000000; +} + /* * DisplayPort AUX channel */ From patchwork Thu Nov 16 13:18:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13457893 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4FDDEC5ACB3 for ; Thu, 16 Nov 2023 13:18:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 45ED410E5DE; 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16 Nov 2023 05:18:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10895"; a="938834336" X-IronPort-AV: E=Sophos;i="6.04,308,1695711600"; d="scan'208";a="938834336" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 05:18:46 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Thu, 16 Nov 2023 15:18:33 +0200 Message-Id: <20231116131841.1588781-4-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231116131841.1588781-1-imre.deak@intel.com> References: <20231116131841.1588781-1-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 03/11] drm/dp_mst: Add kunit tests for drm_dp_get_vc_payload_bw() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add kunit test cases for drm_dp_get_vc_payload_bw() with all the DP1.4 and UHBR link configurations. Cc: Lyude Paul Cc: dri-devel@lists.freedesktop.org Signed-off-by: Imre Deak --- .../gpu/drm/tests/drm_dp_mst_helper_test.c | 145 ++++++++++++++++++ 1 file changed, 145 insertions(+) diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c index e3c818dfc0e6d..cafb463124f71 100644 --- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c +++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c @@ -68,6 +68,150 @@ static void dp_mst_calc_pbn_mode_desc(const struct drm_dp_mst_calc_pbn_mode_test KUNIT_ARRAY_PARAM(drm_dp_mst_calc_pbn_mode, drm_dp_mst_calc_pbn_mode_cases, dp_mst_calc_pbn_mode_desc); +struct drm_dp_mst_calc_pbn_div_test { + int link_rate; + int lane_count; + fixed20_12 expected; +}; + +#define fp_init(__int, __frac) { \ + .full = (__int) * (1 << 12) + \ + (__frac) * (1 << 12) / 100000 \ +} + +static const struct drm_dp_mst_calc_pbn_div_test drm_dp_mst_calc_pbn_div_dp1_4_cases[] = { + /* + * DP1.4 rates: + * .expected = .link_rate * .lane_count * 0.8000 / 8 / 54 / 100 + * UHBR rates: + * .expected = .link_rate * .lane_count * 0.9671 / 8 / 54 / 100 + * truncated to 5 decimal places. + */ + { + .link_rate = 162000, + .lane_count = 1, + .expected = fp_init(3, 0), + }, + { + .link_rate = 162000, + .lane_count = 2, + .expected = fp_init(6, 0), + }, + { + .link_rate = 162000, + .lane_count = 4, + .expected = fp_init(12, 0), + }, + { + .link_rate = 270000, + .lane_count = 1, + .expected = fp_init(5, 0), + }, + { + .link_rate = 270000, + .lane_count = 2, + .expected = fp_init(10, 0), + }, + { + .link_rate = 270000, + .lane_count = 4, + .expected = fp_init(20, 0), + }, + { + .link_rate = 540000, + .lane_count = 1, + .expected = fp_init(10, 0), + }, + { + .link_rate = 540000, + .lane_count = 2, + .expected = fp_init(20, 0), + }, + { + .link_rate = 540000, + .lane_count = 4, + .expected = fp_init(40, 0), + }, + { + .link_rate = 810000, + .lane_count = 1, + .expected = fp_init(15, 0), + }, + { + .link_rate = 810000, + .lane_count = 2, + .expected = fp_init(30, 0), + }, + { + .link_rate = 810000, + .lane_count = 4, + .expected = fp_init(60, 0), + }, + { + .link_rate = 1000000, + .lane_count = 1, + .expected = fp_init(22, 38657), + }, + { + .link_rate = 1000000, + .lane_count = 2, + .expected = fp_init(44, 77314), + }, + { + .link_rate = 1000000, + .lane_count = 4, + .expected = fp_init(89, 54629), + }, + { + .link_rate = 1350000, + .lane_count = 1, + .expected = fp_init(30, 22187), + }, + { + .link_rate = 1350000, + .lane_count = 2, + .expected = fp_init(60, 44375), + }, + { + .link_rate = 1350000, + .lane_count = 4, + .expected = fp_init(120, 88750), + }, + { + .link_rate = 2000000, + .lane_count = 1, + .expected = fp_init(44, 77314), + }, + { + .link_rate = 2000000, + .lane_count = 2, + .expected = fp_init(89, 54629), + }, + { + .link_rate = 2000000, + .lane_count = 4, + .expected = fp_init(179, 9259), /* 179.09259 */ + }, +}; + +static void drm_test_dp_mst_calc_pbn_div(struct kunit *test) +{ + const struct drm_dp_mst_calc_pbn_div_test *params = test->param_value; + /* mgr->dev is only needed by drm_dbg_kms(), but it's not called for the test cases. */ + struct drm_dp_mst_topology_mgr mgr = {}; + + KUNIT_EXPECT_EQ(test, drm_dp_get_vc_payload_bw(&mgr, params->link_rate, params->lane_count).full, + params->expected.full); +} + +static void dp_mst_calc_pbn_div_desc(const struct drm_dp_mst_calc_pbn_div_test *t, char *desc) +{ + sprintf(desc, "Link rate %d lane count %d", t->link_rate, t->lane_count); +} + +KUNIT_ARRAY_PARAM(drm_dp_mst_calc_pbn_div, drm_dp_mst_calc_pbn_div_dp1_4_cases, + dp_mst_calc_pbn_div_desc); + static u8 data[] = { 0xff, 0x00, 0xdd }; struct drm_dp_mst_sideband_msg_req_test { @@ -416,6 +560,7 @@ KUNIT_ARRAY_PARAM(drm_dp_mst_sideband_msg_req, drm_dp_mst_sideband_msg_req_cases static struct kunit_case drm_dp_mst_helper_tests[] = { KUNIT_CASE_PARAM(drm_test_dp_mst_calc_pbn_mode, drm_dp_mst_calc_pbn_mode_gen_params), + KUNIT_CASE_PARAM(drm_test_dp_mst_calc_pbn_div, drm_dp_mst_calc_pbn_div_gen_params), KUNIT_CASE_PARAM(drm_test_dp_mst_sideband_msg_req_decode, drm_dp_mst_sideband_msg_req_gen_params), { } From patchwork Thu Nov 16 13:18:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13457894 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B953DC197A0 for ; Thu, 16 Nov 2023 13:18:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4159B10E5E5; Thu, 16 Nov 2023 13:18:52 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 71FA810E5DE for ; Thu, 16 Nov 2023 13:18:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700140729; x=1731676729; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=u6mAbQhwh+/1gAdrx3jrYt7IeHZVnr5rIUMJdzfa+H8=; b=GzZ5smPlOWKeMlISxQIjXAsZt701lZ3jwgFw83uQG7Mxza5MQlMUhLRv Bj0WSZrgIO05VJyJp21Iq8AJckRsCYCi03u/qxe0ox3exjoRrUT81+db4 dktKsHBz7gF1wRk3XT4t/RUylrHR9S2TTBm1uo36rrWpHGLgSPdCwSvSr vaUd5Lc4P0aCnbihorKOWvSjVP03r9ZIEii0BaQODmC+0mWHOYHGrY9YI J5a6I72pKrfFXX8IG8CftwvrRScrqxpXM/KcCNzGYwMZczrTXIsGWwOwp 2SQFiHvID+iP8p8NhZZwdTwRylWGq/7H2imtv8VsAQ23i1BwuwwYhAOUJ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10895"; a="422177158" X-IronPort-AV: E=Sophos;i="6.04,308,1695711600"; d="scan'208";a="422177158" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 05:18:49 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10895"; a="938834340" X-IronPort-AV: E=Sophos;i="6.04,308,1695711600"; d="scan'208";a="938834340" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 05:18:48 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Thu, 16 Nov 2023 15:18:34 +0200 Message-Id: <20231116131841.1588781-5-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231116131841.1588781-1-imre.deak@intel.com> References: <20231116131841.1588781-1-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 04/11] drm/i915/dp: Replace intel_dp_is_uhbr_rate() with drm_dp_is_uhbr_rate() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Replace intel_dp_is_uhbr_rate() with the recently added drm_dp_is_uhbr_rate(). Signed-off-by: Imre Deak Reviewed-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 7 +------ drivers/gpu/drm/i915/display/intel_dp.h | 1 - 3 files changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 125903007a292..1e045e4fbe582 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2394,7 +2394,7 @@ add_bw_alloc_overhead(int link_clock, int bw_overhead, int pixel_data_rate, int link_data_rate, u32 *data_m, u32 *data_n) { - bool is_uhbr = intel_dp_is_uhbr_rate(link_clock); + bool is_uhbr = drm_dp_is_uhbr_rate(link_clock); int ch_coding_efficiency = drm_dp_bw_channel_coding_efficiency(is_uhbr); diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 54bd0bffa9f08..1b80747044a80 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -121,15 +121,10 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) static void intel_dp_unset_edid(struct intel_dp *intel_dp); -bool intel_dp_is_uhbr_rate(int rate) -{ - return rate >= 1000000; -} - /* Is link rate UHBR and thus 128b/132b? */ bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) { - return intel_dp_is_uhbr_rate(crtc_state->port_clock); + return drm_dp_is_uhbr_rate(crtc_state->port_clock); } static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp) diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index e80da67554196..664fa93bbf534 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -80,7 +80,6 @@ void intel_dp_audio_compute_config(struct intel_encoder *encoder, struct drm_connector_state *conn_state); bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp); bool intel_dp_is_edp(struct intel_dp *intel_dp); -bool intel_dp_is_uhbr_rate(int rate); bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port, From patchwork Thu Nov 16 13:18:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13457895 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1BB08C197A0 for ; Thu, 16 Nov 2023 13:19:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 987DF10E5E4; Thu, 16 Nov 2023 13:18:56 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4AF2610E5DF for ; Thu, 16 Nov 2023 13:18:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700140731; x=1731676731; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dNjcgLmoC6ndEvhGOaf9giYyqRnO0QOn/R5NTPh5Vm0=; b=Q2Y1UqX6yl9Z5Z5anJ/MNnIVaeRcAbi1rc/MujgpmyEFSSzorb2Q8zwC y5uyS7r3t4pEeQiEXCOtPsanf0BObHCJq9LtLwcyz6rO1M+GL9DGz3G9A czuAZEIWqa8UPahVtjYtrgHapWvJHLh3Ox41nu3+Rk4YAS1KKEJE3PlQB xmKZSc1nHMNvhAD6tDFA3HRvyUO+QO0VUZlUOMl6dEjXo24Xz4eoeZLz3 aDXafTzfLsOc/ZELbCIvJyTPrek/jGR02qKAJvg9vRaku7Eq/59+OzO+M vAYjlLghs0QKsWXxGaniafJEg92sb9krhtWKryYU82qykjjtHleEvxeMI Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10895"; a="422177160" X-IronPort-AV: E=Sophos;i="6.04,308,1695711600"; d="scan'208";a="422177160" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 05:18:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10895"; a="938834352" X-IronPort-AV: E=Sophos;i="6.04,308,1695711600"; d="scan'208";a="938834352" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 05:18:49 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Thu, 16 Nov 2023 15:18:35 +0200 Message-Id: <20231116131841.1588781-6-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231116131841.1588781-1-imre.deak@intel.com> References: <20231116131841.1588781-1-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 05/11] drm/i915/dp: Account for channel coding efficiency on UHBR links X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Apply the correct BW allocation overhead and channel coding efficiency on UHBR link rates, similarly to DP1.4 link rates. Reviewed-by: Arun R Murthy Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_display.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 1e045e4fbe582..9755e0a5042c4 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2398,16 +2398,6 @@ add_bw_alloc_overhead(int link_clock, int bw_overhead, int ch_coding_efficiency = drm_dp_bw_channel_coding_efficiency(is_uhbr); - /* - * TODO: adjust for actual UHBR channel coding efficiency and BW - * overhead. - */ - if (is_uhbr) { - *data_m = pixel_data_rate; - *data_n = link_data_rate * 8 / 10; - return; - } - *data_m = DIV_ROUND_UP_ULL(mul_u32_u32(pixel_data_rate, bw_overhead), 1000000); *data_n = DIV_ROUND_DOWN_ULL(mul_u32_u32(link_data_rate, ch_coding_efficiency), From patchwork Thu Nov 16 13:18:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13457899 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 688B6C5AE5B for ; Thu, 16 Nov 2023 13:19:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E68710E5E9; Thu, 16 Nov 2023 13:18:59 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 34A5210E5E4 for ; Thu, 16 Nov 2023 13:18:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700140732; x=1731676732; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MOjC4lx2GRVClcO6fgd6UnANDZ+ULA0HQ3+IodCNmUk=; b=MvC/+wlDevwFUF9IrLl/G8R5gsuML3kbcqlQI6W7CFd+6r5i7xOGkkpG 6/ezj8C1xiq924V1ks4D0scMKCTqmdCw4plEPg+SA8UD8wSPmGrJqDdZR Tw8qbD90fMM2nsHiiRZ/IUYzk6+cGNJnA1WNhbFPDMPUnP9a0UCZTm19F 11E+1rjOAvHUW6Ip0a1XpRrogVlxsHhWG8jTO5Os1JXF5O5dbvFYwaD2q tc7lZ/9bnAKb+PdZpm006PNKlxxTIsh5npDKAfhGkw0nm+GGFylYUyUeS rVoOmkyAE72MpYmkURkQ04yp5c4bTDoy+UUzxDIFctZ8i7gNp0g7zBIyA A==; X-IronPort-AV: E=McAfee;i="6600,9927,10895"; a="422177166" X-IronPort-AV: E=Sophos;i="6.04,308,1695711600"; d="scan'208";a="422177166" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 05:18:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10895"; a="938834356" X-IronPort-AV: E=Sophos;i="6.04,308,1695711600"; d="scan'208";a="938834356" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 05:18:50 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Thu, 16 Nov 2023 15:18:36 +0200 Message-Id: <20231116131841.1588781-7-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231116131841.1588781-1-imre.deak@intel.com> References: <20231116131841.1588781-1-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 06/11] drm/i915/dp: Fix UHBR link M/N values X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The link M/N ratio is the data rate / link symbol clock rate, fix things up accordingly. On DP 1.4 this ratio was correct as the link symbol clock rate in that case matched the link data rate (in bytes/sec units, the symbol size being 8 bits), however it wasn't correct for UHBR rates where the symbol size is 32 bits. Kudos to Arun noticing in Bspec the incorrect use of link data rate in the ratio's N value. Reviewed-by: Arun R Murthy Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_display.c | 16 ++++++++----- drivers/gpu/drm/i915/display/intel_dp.c | 24 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ 3 files changed, 36 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 9755e0a5042c4..744c321792fcf 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2411,6 +2411,7 @@ intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes, struct intel_link_m_n *m_n) { u32 data_clock = DIV_ROUND_UP(bits_per_pixel_x16 * pixel_clock, 16); + u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock); u32 data_m; u32 data_n; @@ -2431,7 +2432,7 @@ intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes, 0x8000000); compute_m_n(&m_n->link_m, &m_n->link_n, - pixel_clock, link_clock, + pixel_clock, link_symbol_clock, 0x80000); } @@ -3943,20 +3944,23 @@ int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n) { /* - * The calculation for the data clock is: + * The calculation for the data clock -> pixel clock is: * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp * But we want to avoid losing precison if possible, so: * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) * - * and the link clock is simpler: - * link_clock = (m * link_clock) / n + * and for link freq (10kbs units) -> pixel clock it is: + * link_symbol_clock = link_freq * 10 / link_symbol_size + * pixel_clock = (m * link_symbol_clock) / n + * or for more precision: + * pixel_clock = (m * link_freq * 10) / (n * link_symbol_size) */ if (!m_n->link_n) return 0; - return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq), - m_n->link_n); + return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10), + m_n->link_n * intel_dp_link_symbol_size(link_freq)); } int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 1b80747044a80..521838caa1979 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -127,6 +127,30 @@ bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) return drm_dp_is_uhbr_rate(crtc_state->port_clock); } +/** + * intel_dp_link_symbol_size - get the link symbol size for a given link rate + * @rate: link rate in 10kbit/s units + * + * Returns the link symbol size in bits/symbol units depending on the link + * rate -> channel coding. + */ +int intel_dp_link_symbol_size(int rate) +{ + return drm_dp_is_uhbr_rate(rate) ? 32 : 10; +} + +/** + * intel_dp_link_symbol_clock - convert link rate to link symbol clock + * @rate: link rate in 10kbit/s units + * + * Returns the link symbol clock frequency in kHz units depending on the + * link rate and channel coding. + */ +int intel_dp_link_symbol_clock(int rate) +{ + return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate)); +} + static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp) { intel_dp->sink_rates[0] = 162000; diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 664fa93bbf534..777aa858f899c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -81,6 +81,8 @@ void intel_dp_audio_compute_config(struct intel_encoder *encoder, bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp); bool intel_dp_is_edp(struct intel_dp *intel_dp); bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); +int intel_dp_link_symbol_size(int rate); +int intel_dp_link_symbol_clock(int rate); bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd); From patchwork Thu Nov 16 13:18:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13457900 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 10B6BC5AE4B for ; Thu, 16 Nov 2023 13:19:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E051210E5EB; Thu, 16 Nov 2023 13:18:59 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 31F5110E5E4 for ; Thu, 16 Nov 2023 13:18:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700140733; x=1731676733; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=fYZ8WicssfxLXgWlmCflTh6lJkl6vAQulfHp93iVrBY=; b=gwPolT2cXZiSB0oCtp80DsGu6meTJE5mdtfmAZlGtdXE0fzJRufxBL7N Y/sU1XOMGbmwmokVz0ceAf4uWCgGGMqQodbK65sZM63GpBQpyfrXNv97t NUU+U5s7ev4JAIgG9bgF3E1TIC4HVcylxcBKjgZovL+tmXaeHkwEjXewA nkJWArupyRR5C71yEhX8/c06fCTEwfq70OmjO1lwyUICGzZyskuVbz+cC AY3YH+VTOxPJvceNvNAzJd7G/5HA+Cx4Wfgmp9Cm2bl/zkW4wCynxm8rL /VZ65HCfUWyVEBY9bERWyymoe40VUn6QFj7aoa9AM5VJsYJyrU6Og8wKJ w==; X-IronPort-AV: E=McAfee;i="6600,9927,10895"; a="422177170" X-IronPort-AV: E=Sophos;i="6.04,308,1695711600"; d="scan'208";a="422177170" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 05:18:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10895"; a="938834358" X-IronPort-AV: E=Sophos;i="6.04,308,1695711600"; d="scan'208";a="938834358" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 05:18:52 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Thu, 16 Nov 2023 15:18:37 +0200 Message-Id: <20231116131841.1588781-8-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231116131841.1588781-1-imre.deak@intel.com> References: <20231116131841.1588781-1-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 07/11] drm/i915/dp_mst: Calculate the BW overhead in intel_dp_mst_find_vcpi_slots_for_bpp() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The next patch will calculate the PBN value directly from the pixel data rate and the BW allocation overhead, not requiring the data, link M/N and TU values for this. To prepare for that move the calculation of BW overheads from intel_dp_mst_compute_m_n() to intel_dp_mst_find_vcpi_slots_for_bpp(). While at it store link_bpp in a .4 fixed point format. Signed-off-by: Imre Deak Reviewed-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 27 ++++++++++++++------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index e5d6b811c22ef..a5ddd1781969d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -108,15 +108,12 @@ static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state, static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state, const struct intel_connector *connector, - bool ssc, bool dsc, + int overhead, int bpp_x16, struct intel_link_m_n *m_n) { const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - int overhead = intel_dp_mst_bw_overhead(crtc_state, - connector, - ssc, dsc, bpp_x16); intel_link_compute_m_n(bpp_x16, crtc_state->lane_count, adjusted_mode->crtc_clock, @@ -171,7 +168,9 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) { struct intel_link_m_n remote_m_n; - int link_bpp; + int local_bw_overhead; + int remote_bw_overhead; + int link_bpp_x16; drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp); @@ -179,12 +178,22 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, if (ret) continue; - link_bpp = dsc ? bpp : - intel_dp_output_bpp(crtc_state->output_format, bpp); + link_bpp_x16 = to_bpp_x16(dsc ? bpp : + intel_dp_output_bpp(crtc_state->output_format, bpp)); - intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc, to_bpp_x16(link_bpp), + local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector, + false, dsc, link_bpp_x16); + remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector, + true, dsc, link_bpp_x16); + + intel_dp_mst_compute_m_n(crtc_state, connector, + local_bw_overhead, + link_bpp_x16, &crtc_state->dp_m_n); - intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc, to_bpp_x16(link_bpp), + + intel_dp_mst_compute_m_n(crtc_state, connector, + remote_bw_overhead, + link_bpp_x16, &remote_m_n); /* From patchwork Thu Nov 16 13:18:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13457898 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 89C1CC5AD4C for ; Thu, 16 Nov 2023 13:19:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3BF1B10E5E8; Thu, 16 Nov 2023 13:18:59 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id A3C2B10E5E4 for ; Thu, 16 Nov 2023 13:18:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700140734; x=1731676734; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4OjKx8LlWJ/uM2aD9a4tZ6dTzdiMcXiAnJQvkaeM3+g=; b=LSB2Z1g0hx0MwtX7XJ62IpTogsXFAGPrD0fVSbg99nzTmX0jUi9Sj/Ed VKIkeygEEjD+5N3pcVd4nsRI6xXlmLdJvmr3nSRXR9awGY6GyOfQ5ThaP IBFvvIG4XqrVYXQkNmfkIRdPMQv+d9UahlfEM8jtmyJoCHN26ivYBM6hs hqhphK47rS4FDXv4VUHb3Pqh5xrX1yCPjmoakGAveHs90UmxFCAyBzHoy ddBpi/ZIsMQNe6JypsHevR7VzatR/63mDqfut7Ti8Nv4da7pktinReeoH SI6EtiL+U58Ecmx5H2rEchUhDMF/IFNZ7vGjYKE6BBnq72CiGLpKutAUK w==; X-IronPort-AV: E=McAfee;i="6600,9927,10895"; a="422177177" X-IronPort-AV: E=Sophos;i="6.04,308,1695711600"; d="scan'208";a="422177177" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 05:18:54 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10895"; a="938834363" X-IronPort-AV: E=Sophos;i="6.04,308,1695711600"; d="scan'208";a="938834363" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 05:18:53 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Thu, 16 Nov 2023 15:18:38 +0200 Message-Id: <20231116131841.1588781-9-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231116131841.1588781-1-imre.deak@intel.com> References: <20231116131841.1588781-1-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 08/11] drm/i915/dp_mst: Fix PBN / MTP_TU size calculation for UHBR rates X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Atm the allocated MST PBN value is calculated from the TU size (number of allocated MTP slots) as PBN = TU * pbn_div pbn_div being the link BW for each MTP slot. For DP 1.4 link rates this worked, as pbn_div there is guraranteed to be an integer number, however on UHBR this isn't the case. To get a PBN, TU pair where TU is a properly rounded-up value covering all the BW corresponding to PBN, calculate first PBN and from PBN the TU value. Calculate PBN directly from the effective pixel data rate, instead of calculating it indirectly from the corresponding TU and pbn_div values (which are in turn derived from the pixel data rate and BW overhead). Add a helper function to calculate the effective data rate, also adding a note that callers of intel_dp_link_required() may also need to check the effective data rate (vs. the data rate w/o the BW overhead). While at it add a note to check if WA#14013163432 is applicable. v2: - Fix PBN calculation, deriving it from the effective data rate directly instead of using the indirect TU and pbn_div values for this. - Add a note about WA#14013163432. (Arun) Reviewed-by: Arun R Murthy (v1) Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 19 +++++++++++ drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 35 +++++++++++++++------ 3 files changed, 46 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 521838caa1979..120d435d27ff1 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -355,6 +355,9 @@ int intel_dp_max_lane_count(struct intel_dp *intel_dp) /* * The required data bandwidth for a mode with given pixel clock and bpp. This * is the required net bandwidth independent of the data bandwidth efficiency. + * + * TODO: check if callers of this functions should use + * intel_dp_effective_data_rate() instead. */ int intel_dp_link_required(int pixel_clock, int bpp) @@ -363,6 +366,22 @@ intel_dp_link_required(int pixel_clock, int bpp) return DIV_ROUND_UP(pixel_clock * bpp, 8); } +/** + * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead + * @pixel_clock: pixel clock in kHz + * @bpp_x16: bits per pixel .4 fixed point format + * @bw_overhead: BW allocation overhead in 1ppm units + * + * Return the effective pixel data rate in kB/sec units taking into account + * the provided SSC, FEC, DSC BW allocation overhead. + */ +int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, + int bw_overhead) +{ + return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead), + 1000000 * 16 * 8); +} + /* * Given a link rate and lanes, get the data bandwidth. * diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 777aa858f899c..05db46b111f21 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -103,6 +103,8 @@ bool intel_dp_source_supports_tps4(struct drm_i915_private *i915); bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp); int intel_dp_link_required(int pixel_clock, int bpp); +int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, + int bw_overhead); int intel_dp_max_data_rate(int max_link_rate, int max_lanes); bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp); bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index a5ddd1781969d..297d8c5f88a8b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -115,6 +115,7 @@ static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state, const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + /* TODO: Check WA 14013163432 to set data M/N for full BW utilization. */ intel_link_compute_m_n(bpp_x16, crtc_state->lane_count, adjusted_mode->crtc_clock, crtc_state->port_clock, @@ -124,6 +125,18 @@ static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state, m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n); } +static int intel_dp_mst_calc_pbn(int pixel_clock, int bpp_x16, int bw_overhead) +{ + int effective_data_rate = + intel_dp_effective_data_rate(pixel_clock, bpp_x16, bw_overhead); + + /* + * TODO: Use drm_dp_calc_pbn_mode() instead, once it's converted + * to calculate PBN with the BW overhead passed to it. + */ + return DIV_ROUND_UP(effective_data_rate * 64, 54 * 1000); +} + static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, int max_bpp, @@ -167,10 +180,10 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, min_bpp, max_bpp); for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) { - struct intel_link_m_n remote_m_n; int local_bw_overhead; int remote_bw_overhead; int link_bpp_x16; + fixed20_12 remote_tu; drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp); @@ -191,11 +204,6 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, link_bpp_x16, &crtc_state->dp_m_n); - intel_dp_mst_compute_m_n(crtc_state, connector, - remote_bw_overhead, - link_bpp_x16, - &remote_m_n); - /* * The TU size programmed to the HW determines which slots in * an MTP frame are used for this stream, which needs to match @@ -210,9 +218,16 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, * crtc_state->dp_m_n.tu), provided that the driver doesn't * enable SSC on the corresponding link. */ - drm_WARN_ON(&i915->drm, remote_m_n.tu < crtc_state->dp_m_n.tu); - crtc_state->dp_m_n.tu = remote_m_n.tu; - crtc_state->pbn = remote_m_n.tu * dfixed_trunc(mst_state->pbn_div); + crtc_state->pbn = intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock, + link_bpp_x16, + remote_bw_overhead); + + remote_tu.full = dfixed_div((fixed20_12)dfixed_init(crtc_state->pbn), + mst_state->pbn_div); + remote_tu.full = dfixed_ceil(remote_tu); + + drm_WARN_ON(&i915->drm, dfixed_trunc(remote_tu) < crtc_state->dp_m_n.tu); + crtc_state->dp_m_n.tu = dfixed_trunc(remote_tu); slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr, connector->port, @@ -221,7 +236,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, return slots; if (slots >= 0) { - drm_WARN_ON(&i915->drm, slots != remote_m_n.tu); + drm_WARN_ON(&i915->drm, slots != crtc_state->dp_m_n.tu); break; } From patchwork Thu Nov 16 13:18:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13457897 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CBEB7C5AE4A for ; Thu, 16 Nov 2023 13:19:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E38C610E5E6; Thu, 16 Nov 2023 13:18:58 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id D7A8710E5E4 for ; Thu, 16 Nov 2023 13:18:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700140735; x=1731676735; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2xor/F/ja9poHPy5FHgrhsa1eWBjWMypYd8DRSNnSVE=; b=ibL8XgYQtycdvgWtL9i8w52i/F6vYin0aZKhpLScBvwdTr7ur/ySzCBS JZ/eoO/cWiFPNAX2uB0LPMy/WyyKqIf8YeK9DTvfvXLO+KztdbnLA1Phj 5fZdVLqsa12oilJW9mMrPeh5ctnyIsx1IjDVzhlX40mzeX7G6VQr1dwYf akdC2y86F6wcA80un7ePUS7D+WrGowwD0adVdCvJ0nI4w4p4CTNgItmVI z5Dlh5E1QsETrjoECpBuOS3i361wsH1XR/Yumq+WA4OwZyjuDHi5Ux83R nboJCpRkhh0rPcmOkuYmw5HYnuD5kB9mG0+yJJCCxtw3LOyFY+iX1Jxfs A==; X-IronPort-AV: E=McAfee;i="6600,9927,10895"; a="422177181" X-IronPort-AV: E=Sophos;i="6.04,308,1695711600"; d="scan'208";a="422177181" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 05:18:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10895"; a="938834364" X-IronPort-AV: E=Sophos;i="6.04,308,1695711600"; d="scan'208";a="938834364" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 05:18:54 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Thu, 16 Nov 2023 15:18:39 +0200 Message-Id: <20231116131841.1588781-10-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231116131841.1588781-1-imre.deak@intel.com> References: <20231116131841.1588781-1-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 09/11] drm/i915/dp: Report a rounded-down value as the maximum data rate X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Callers of intel_dp_max_data_rate() use the return value as an upper bound for the BW a given mode requires. As such the rounding shouldn't result in a bigger value than the actual upper bound. Use round-down instead of -closest accordingly. Cc: Jani Nikula Signed-off-by: Imre Deak Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_dp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 120d435d27ff1..209c27167e057 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -413,7 +413,7 @@ intel_dp_max_data_rate(int max_link_rate, int max_lanes) */ int max_link_rate_kbps = max_link_rate * 10; - max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(max_link_rate_kbps, 9671), 10000); + max_link_rate_kbps = DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate_kbps, 9671), 10000); max_link_rate = max_link_rate_kbps / 8; } @@ -423,7 +423,7 @@ intel_dp_max_data_rate(int max_link_rate, int max_lanes) * out to be a nop by coincidence, and can be skipped: * * int max_link_rate_kbps = max_link_rate * 10; - * max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(max_link_rate_kbps * 8, 10); + * max_link_rate_kbps = DIV_ROUND_DOWN_ULL(max_link_rate_kbps * 8, 10); * max_link_rate = max_link_rate_kbps / 8; */ From patchwork Thu Nov 16 13:18:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13457896 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0A51BC5ACB3 for ; Thu, 16 Nov 2023 13:19:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7746110E5E7; Thu, 16 Nov 2023 13:18:58 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id E8A7C10E5E6 for ; Thu, 16 Nov 2023 13:18:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700140736; x=1731676736; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Zcpd0Pofl6bYKgkjg5ll2Em7uUMT6yg6yiZlrtFP9EE=; b=BIbImlqiKehOA/gQHhh+2W/gCTwL/JpTlRIRepjex6RsriFU+n9tgik5 b1kE1pCUB5MfewH6Ex6u6/JfaFzWdZq6lXpTlziqz36So4v+WUi9yvxf7 h4TP3A2MDtAahCGQmjy+MbvxAWj/FdSix0UfIOOW8QTOURrEs+x3cVifj LoIMKsGQFAJwMO/NSAJjP1tfDLudyKIFTWmpNUAxawnZO5/ATtgsQu4hk 6+MbmeboPDFBJ7l/yxtbLCvdJFHQFb9xNubk0MdZXkb0eqMBa379YJSGu EVU2JrVjvpMojeMvY4UURYYF/+T+/37vbVsKdmWYVoyAqOtZzGvOEmbH8 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10895"; a="422177183" X-IronPort-AV: E=Sophos;i="6.04,308,1695711600"; d="scan'208";a="422177183" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 05:18:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10895"; a="938834367" X-IronPort-AV: E=Sophos;i="6.04,308,1695711600"; d="scan'208";a="938834367" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 05:18:55 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Thu, 16 Nov 2023 15:18:40 +0200 Message-Id: <20231116131841.1588781-11-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231116131841.1588781-1-imre.deak@intel.com> References: <20231116131841.1588781-1-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 10/11] drm/i915/dp: Simplify intel_dp_max_data_rate() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Simplify intel_dp_max_data_rate() using drm_dp_bw_channel_coding_efficiency() to calculate the max data rate for both DP1.4 and UHBR link rates. This trades a redundant multiply/divide for readability. Cc: Jani Nikula Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp.c | 26 ++++++++++++------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 209c27167e057..a93e8f6429d85 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -405,29 +405,27 @@ int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, int intel_dp_max_data_rate(int max_link_rate, int max_lanes) { - if (max_link_rate >= 1000000) { - /* - * UHBR rates always use 128b/132b channel encoding, and have - * 97.71% data bandwidth efficiency. Consider max_link_rate the - * link bit rate in units of 10000 bps. - */ - int max_link_rate_kbps = max_link_rate * 10; - - max_link_rate_kbps = DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate_kbps, 9671), 10000); - max_link_rate = max_link_rate_kbps / 8; - } + int ch_coding_efficiency = + drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(max_link_rate)); + int max_link_rate_kbps = max_link_rate * 10; + /* + * UHBR rates always use 128b/132b channel encoding, and have + * 97.71% data bandwidth efficiency. Consider max_link_rate the + * link bit rate in units of 10000 bps. + */ /* * Lower than UHBR rates always use 8b/10b channel encoding, and have * 80% data bandwidth efficiency for SST non-FEC. However, this turns - * out to be a nop by coincidence, and can be skipped: + * out to be a nop by coincidence: * * int max_link_rate_kbps = max_link_rate * 10; * max_link_rate_kbps = DIV_ROUND_DOWN_ULL(max_link_rate_kbps * 8, 10); * max_link_rate = max_link_rate_kbps / 8; */ - - return max_link_rate * max_lanes; + return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate_kbps * max_lanes, + ch_coding_efficiency), + 1000000 * 8); } bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp) From patchwork Thu Nov 16 13:18:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13457901 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB22CC5ACB3 for ; Thu, 16 Nov 2023 13:19:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 56BBD10E5ED; Thu, 16 Nov 2023 13:19:01 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3DDF610E5E6 for ; Thu, 16 Nov 2023 13:18:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700140738; x=1731676738; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IRc4p+jRwfxZroxJSn/irAL2vcaomMYpak79qT8Hwck=; b=hOLtGqTjP6s5n7Jq7nfxXO8H+yNkGovtQJJypiuXzp6Hib+53lcr0InN rnEy8SO28za237X+Ap61sLFzLvyU4E0qjE7JmD1Japk0D3jj57hiEyS+q l6xifVDjxZ8kCcAP9bL4z0MjBeLos22fcpXXr6wJFhjSzBAz08KNyu76D w8pCXYeCkiRWFpaq/6sV/psHFcS6zyuhAzKgZGOhcYYK/dAMTOTlw6ZMI ZAWXcv1VuHB/03LB85dyzlfLOXNo1U3X2rpJBU2O+2z74gwkf5L/rTAX3 mzIaJx5rGnUJZkI+1dNQos8LcH/YRDfkNsxyMX+WukIZEu7vMD9fqdMjL A==; X-IronPort-AV: E=McAfee;i="6600,9927,10895"; a="422177188" X-IronPort-AV: E=Sophos;i="6.04,308,1695711600"; d="scan'208";a="422177188" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 05:18:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10895"; a="938834370" X-IronPort-AV: E=Sophos;i="6.04,308,1695711600"; d="scan'208";a="938834370" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 05:18:56 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Thu, 16 Nov 2023 15:18:41 +0200 Message-Id: <20231116131841.1588781-12-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231116131841.1588781-1-imre.deak@intel.com> References: <20231116131841.1588781-1-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 11/11] drm/i915/dp: Reuse intel_dp_{max, effective}_data_rate in intel_link_compute_m_n() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Reuse intel_dp_max_data_rate() and intel_dp_effective_data_rate() in intel_link_compute_m_n(), instead of open-coding the equivalent. Note the kbit/sec -> kByte/sec unit change in the M/N values, but this not reducing the precision, as the link rate value is based anyway on a less precise 10 kbit/sec value. Suggested-by: Jani Nikula Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 25 +++----------------- 1 file changed, 3 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 744c321792fcf..199ecd8879461 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2389,36 +2389,17 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n, intel_reduce_m_n_ratio(ret_m, ret_n); } -static void -add_bw_alloc_overhead(int link_clock, int bw_overhead, - int pixel_data_rate, int link_data_rate, - u32 *data_m, u32 *data_n) -{ - bool is_uhbr = drm_dp_is_uhbr_rate(link_clock); - int ch_coding_efficiency = - drm_dp_bw_channel_coding_efficiency(is_uhbr); - - *data_m = DIV_ROUND_UP_ULL(mul_u32_u32(pixel_data_rate, bw_overhead), - 1000000); - *data_n = DIV_ROUND_DOWN_ULL(mul_u32_u32(link_data_rate, ch_coding_efficiency), - 1000000); -} - void intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes, int pixel_clock, int link_clock, int bw_overhead, struct intel_link_m_n *m_n) { - u32 data_clock = DIV_ROUND_UP(bits_per_pixel_x16 * pixel_clock, 16); u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock); - u32 data_m; - u32 data_n; + u32 data_m = intel_dp_effective_data_rate(pixel_clock, bits_per_pixel_x16, + bw_overhead); + u32 data_n = intel_dp_max_data_rate(link_clock, nlanes); - add_bw_alloc_overhead(link_clock, bw_overhead, - data_clock, - link_clock * 10 * nlanes, - &data_m, &data_n); /* * Windows/BIOS uses fixed M/N values always. Follow suit. *