From patchwork Fri Nov 17 05:58:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 13458384 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="hyndKeQe" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 927401A8; Thu, 16 Nov 2023 21:59:21 -0800 (PST) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AH5ihef032020; Fri, 17 Nov 2023 05:58:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding; s=qcppdkim1; bh=UTKklDfpFj36LK+7PzsMZPqAWLP+G1q5QwgAnV8Gx0U=; b=hyndKeQeDT7aIchwdg0HigfOjD5JyqEn6KMRreVBRuGDD6AQaiSavFHfeMG51f1JcgTj 8hjE8v6mnfw6jLKRm8gvMYc+Zd+6jiNgbo2/4X+q2viHbCdeLdb4hArdJJ6JZM9a+O+l vM0DR72wdlLLUuiv61sW7jmOUdPpfEW+zYvCwNiKskKc8bkLqNHD+bUUQezt2lGPHrnW 96HVD84PXLgJljKWfvvKcR4RkQrEy7PSRfjgAh4RSl5lgi5i5KYein4cD5q4Z4GkQqbD qcNaPfaHsNb+0TGqHqPqYKV+ZFFMxGxayCAVWQGNLL68Zdl/FD8Zewpf3gUbRwLcqv0O xw== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3udg6f2e1m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 05:58:56 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3AH5wptQ008166; Fri, 17 Nov 2023 05:58:51 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3ua2pkqa78-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 05:58:51 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3AH5wp5a008159; Fri, 17 Nov 2023 05:58:51 GMT Received: from hu-devc-hyd-u20-c-new.qualcomm.com (hu-rohiagar-hyd.qualcomm.com [10.147.246.70]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3AH5wpuQ008158 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 05:58:51 +0000 Received: by hu-devc-hyd-u20-c-new.qualcomm.com (Postfix, from userid 3970568) id 4C3AD2204F; Fri, 17 Nov 2023 11:28:50 +0530 (+0530) From: Rohit Agarwal To: catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, geert+renesas@glider.be, konrad.dybcio@linaro.org, arnd@arndb.de, krzysztof.kozlowski@linaro.org, neil.armstrong@linaro.org, dmitry.baryshkov@linaro.org, nfraprado@collabora.com, m.szyprowski@samsung.com, u-kumar1@ti.com, peng.fan@nxp.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, kernel@quicinc.com, Rohit Agarwal Subject: [PATCH v3] arm64: defconfig: Enable GCC, pinctrl and interconnect for SDX75 Date: Fri, 17 Nov 2023 11:28:49 +0530 Message-Id: <20231117055849.534671-1-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: WQQ4JgxeHDXDvI-gpVnGYSSXsB33omLA X-Proofpoint-GUID: WQQ4JgxeHDXDvI-gpVnGYSSXsB33omLA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-17_03,2023-11-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 clxscore=1015 phishscore=0 mlxscore=0 mlxlogscore=414 priorityscore=1501 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311170041 Enable Global Clock controller, pinctrl and interconnect framework support for Qualcomm's SDX75 SoC which is required to boot to console on sdx75-idp platform. Signed-off-by: Rohit Agarwal Reviewed-by: Dmitry Baryshkov --- Hi, Changes in v3: - Clubbed all the three patches in a single patch. - Link to v2: https://lore.kernel.org/all/20231116093513.14259-1-quic_rohiagar@quicinc.com/ Changes in v2: - Updated the commit message for the patches. Thanks, Rohit. arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index b60aa1f89343..4c0cd428d073 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -599,6 +599,7 @@ CONFIG_PINCTRL_SC8280XP=y CONFIG_PINCTRL_SDM660=y CONFIG_PINCTRL_SDM670=y CONFIG_PINCTRL_SDM845=y +CONFIG_PINCTRL_SDX75=y CONFIG_PINCTRL_SM6115=y CONFIG_PINCTRL_SM6115_LPASS_LPI=m CONFIG_PINCTRL_SM6125=y @@ -1252,6 +1253,7 @@ CONFIG_SDM_GPUCC_845=y CONFIG_SDM_VIDEOCC_845=y CONFIG_SDM_DISPCC_845=y CONFIG_SDM_LPASSCC_845=m +CONFIG_SDX_GCC_75=y CONFIG_SM_CAMCC_8250=m CONFIG_SM_DISPCC_6115=m CONFIG_SM_DISPCC_8250=y @@ -1519,6 +1521,7 @@ CONFIG_INTERCONNECT_QCOM_SC7280=y CONFIG_INTERCONNECT_QCOM_SC8180X=y CONFIG_INTERCONNECT_QCOM_SC8280XP=y CONFIG_INTERCONNECT_QCOM_SDM845=y +CONFIG_INTERCONNECT_QCOM_SDX75=y CONFIG_INTERCONNECT_QCOM_SM8150=m CONFIG_INTERCONNECT_QCOM_SM8250=m CONFIG_INTERCONNECT_QCOM_SM8350=m