From patchwork Sat Nov 18 12:31:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13459993 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="AtETbQCz" Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::224]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56D72D61; Sat, 18 Nov 2023 04:33:01 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 7534EE0004; Sat, 18 Nov 2023 12:32:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1700310779; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=t0oGbCGDDoO0IuxC5hzh9krVhy5dPwQKpeDyRtL3LFM=; b=AtETbQCz70fJDRVZ2q+zWVB+dSJ+JHeLm1UsgRxF9HlTc7F5gvH9h1UDjRJ6uyuiSAZIUs aoHcPLB0ytsh4nmUwDq3xxZeaDqkmMF2FHc6ZR6B1tCLrQ6/V8h9zbf3srYBAtJFz6eRzX ylDCXCGl0yjCZdzXA7zQrdCdduYFhLXuzmh1upRn0fLh+5mTYytengW9soUlDwhsiHPSlY rQnBHBrWs2RWB8MDflsRBmv1nl7GRvJkeE5vS3xmOAizMCahD5JzE3rhqVRKko6bYWlnNj D2Pl27NSoKudNHpq/GB9f83h+lYdHZrBGx2sPdxfhxNdiQxWg9BthUxXWpIXGg== From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com Subject: [PATCH net-next 01/15] net: dsa: mt7530: always trap frames to active CPU port on MT7530 Date: Sat, 18 Nov 2023 15:31:51 +0300 Message-Id: <20231118123205.266819-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231118123205.266819-1-arinc.unal@arinc9.com> References: <20231118123205.266819-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: arinc.unal@arinc9.com X-Patchwork-Delegate: kuba@kernel.org On the MT7530 switch, the CPU_PORT field indicates which CPU port to trap frames to, regardless of the affinity of the inbound user port. When multiple CPU ports are in use, if the DSA conduit interface is down, trapped frames won't be passed to the conduit interface. To make trapping frames work including this case, implement ds->ops->master_state_change() on this subdriver and set the CPU_PORT field to the numerically smallest CPU port which the DSA conduit interface its affine to is up. Introduce the active_cpu_ports field to store the information of the active CPU ports. Correct the macros, CPU_PORT is bits 4 through 6 of the register. Add a comment to explain frame trapping for this switch. Currently, the driver doesn't support the use of multiple CPU ports so this is not necessarily a bug fix. Suggested-by: Vladimir Oltean Suggested-by: Russell King (Oracle) Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 30 ++++++++++++++++++++++++++---- drivers/net/dsa/mt7530.h | 6 ++++-- 2 files changed, 30 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index d27c6b70a2f6..442492d62670 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -1035,10 +1035,6 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int port) mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); - /* Set CPU port number */ - if (priv->id == ID_MT7530 || priv->id == ID_MT7621) - mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); - /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that * is affine to the inbound user port. @@ -3075,6 +3071,31 @@ static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, return 0; } +static void +mt753x_conduit_state_change(struct dsa_switch *ds, + const struct net_device *conduit, + bool operational) +{ + struct mt7530_priv *priv = ds->priv; + struct dsa_port *cpu_dp = conduit->dsa_ptr; + + /* Set the CPU port to trap frames to for MT7530. Trapped frames will be + * forwarded to the numerically smallest CPU port which the DSA conduit + * interface its affine to is up. + */ + if (priv->id != ID_MT7530 && priv->id != ID_MT7621) + return; + + if (operational) + priv->active_cpu_ports |= BIT(cpu_dp->index); + else + priv->active_cpu_ports &= ~BIT(cpu_dp->index); + + if (priv->active_cpu_ports) + mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, CPU_EN | + CPU_PORT(__ffs(priv->active_cpu_ports))); +} + static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface) { return 0; @@ -3130,6 +3151,7 @@ const struct dsa_switch_ops mt7530_switch_ops = { .phylink_mac_link_up = mt753x_phylink_mac_link_up, .get_mac_eee = mt753x_get_mac_eee, .set_mac_eee = mt753x_set_mac_eee, + .conduit_state_change = mt753x_conduit_state_change, }; EXPORT_SYMBOL_GPL(mt7530_switch_ops); diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 17e42d30fff4..96d610f5bcf9 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -41,8 +41,8 @@ enum mt753x_id { #define UNU_FFP(x) (((x) & 0xff) << 8) #define UNU_FFP_MASK UNU_FFP(~0) #define CPU_EN BIT(7) -#define CPU_PORT(x) ((x) << 4) -#define CPU_MASK (0xf << 4) +#define CPU_PORT_MASK GENMASK(6, 4) +#define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x) #define MIRROR_EN BIT(3) #define MIRROR_PORT(x) ((x) & 0x7) #define MIRROR_MASK 0x7 @@ -760,6 +760,7 @@ struct mt753x_info { * @irq_domain: IRQ domain of the switch irq_chip * @irq_enable: IRQ enable bits, synced to SYS_INT_EN * @create_sgmii: Pointer to function creating SGMII PCS instance(s) + * @active_cpu_ports: Holding the active CPU ports */ struct mt7530_priv { struct device *dev; @@ -786,6 +787,7 @@ struct mt7530_priv { struct irq_domain *irq_domain; u32 irq_enable; int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii); + unsigned long active_cpu_ports; }; struct mt7530_hw_vlan_entry { From patchwork Sat Nov 18 12:31:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13459994 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="TA2qB8Qu" Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B563D61; Sat, 18 Nov 2023 04:33:05 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 17AF3E0005; Sat, 18 Nov 2023 12:32:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1700310784; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=A4UChF1BUauN6W28Ee+oXUFPu4N8R5M4US5PAgnczs4=; b=TA2qB8QuA710htbz4O+4ZVHGiqJRarLSXwaFP6VonUbPqFGxug1I3vIVoYnE0FFb+RQjeY yEGQu6us+mrL/TDiFHy6oxEhFjEh2F6eXa8RZ/80WzTYi7+uwpJFuAuiZxM0Oycgiyg7fj XUcI4Z8SUCUFgTgYTm5wDDxmnddh3/3HGIMFTbvZGqYHHxcDAx0LeiPX5VmzYBFTx72X+j u/7tC1ITqjyip38Vx7JT768QVGbJIib4n+umsDXE2gkVwcc0HZnQcFEatskE4l+Py04PPg rG5LdurPtA5EPLWrxMIQyo6D8YTLGOTKdET1tHTp98O3ymMoCEdgjdOd+HsJwQ== From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com Subject: [PATCH net-next 02/15] net: dsa: mt7530: use p5_interface_select as data type for p5_intf_sel Date: Sat, 18 Nov 2023 15:31:52 +0300 Message-Id: <20231118123205.266819-3-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231118123205.266819-1-arinc.unal@arinc9.com> References: <20231118123205.266819-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: arinc.unal@arinc9.com X-Patchwork-Delegate: kuba@kernel.org Use the p5_interface_select enumeration as the data type for the p5_intf_sel field. This ensures p5_intf_sel can only take the values defined in the p5_interface_select enumeration. Remove the explicit assignment of 0 to P5_DISABLED as the first enum item is automatically assigned 0. Signed-off-by: Arınç ÜNAL Acked-by: Daniel Golle Reviewed-by: Vladimir Oltean --- drivers/net/dsa/mt7530.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 96d610f5bcf9..1b10b70c1508 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -683,7 +683,7 @@ struct mt7530_port { /* Port 5 interface select definitions */ enum p5_interface_select { - P5_DISABLED = 0, + P5_DISABLED, P5_INTF_SEL_PHY_P0, P5_INTF_SEL_PHY_P4, P5_INTF_SEL_GMAC5, @@ -776,7 +776,7 @@ struct mt7530_priv { bool mcm; phy_interface_t p6_interface; phy_interface_t p5_interface; - unsigned int p5_intf_sel; + enum p5_interface_select p5_intf_sel; u8 mirror_rx; u8 mirror_tx; struct mt7530_port ports[MT7530_NUM_PORTS]; From patchwork Sat Nov 18 12:31:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13459995 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="nMdC3Sq6" Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E03110D5; Sat, 18 Nov 2023 04:33:09 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 9EED1E0008; Sat, 18 Nov 2023 12:33:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1700310788; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2bNfxMfx1oLYREiPG8xarpZykPwtvPqTMAevp9qpKhs=; b=nMdC3Sq6bg3lnRkoVAyLMyikVBbQBgMHMHrnmxF6elgGG1omTcbaUia9U7BCk7dKf7HJSB yBCYWRarpLmuayBGVx9lGJN4fevfC6lDPOVhgecZmi4xI1viaoa+To/2C49zs375KUNsNA HhevSAPspWs3Eu8BlbDkHTxUys6vLAOJdee7n1Xv92C33CiZz/O8k6N0gpRdr4+Pvx2AvT M8ttJQFW4HnTqCI6A04ZJQUay7S79Eg+1Tg7tfcuYknYE3zfDdSUmwhtuZMF8+awIQWGgg 46+Qkn3yw2DQ+jAv3cayg+3x3M4gnKlio+lZW+fUMuN2YRo0W9Nr+PzctscWGA== From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com Subject: [PATCH net-next 03/15] net: dsa: mt7530: store port 5 SGMII capability of MT7531 Date: Sat, 18 Nov 2023 15:31:53 +0300 Message-Id: <20231118123205.266819-4-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231118123205.266819-1-arinc.unal@arinc9.com> References: <20231118123205.266819-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: arinc.unal@arinc9.com X-Patchwork-Delegate: kuba@kernel.org Introduce the p5_sgmii field to store the information for whether port 5 has got SGMII or not. Instead of reading the MT7531_TOP_SIG_SR register multiple times, the register will be read once and the value will be stored on the p5_sgmii field. This saves unnecessary reads of the register. Move the comment about MT7531AE and MT7531BE to mt7531_setup(), where the switch is identified. Get rid of mt7531_dual_sgmii_supported() now that priv->p5_sgmii stores the information. Address the code where mt7531_dual_sgmii_supported() is used. Get rid of mt7531_is_rgmii_port() which just prints the opposite of priv->p5_sgmii. Instead of calling mt7531_pll_setup() then returning, do not call it if port 5 is SGMII. Remove P5_INTF_SEL_GMAC5_SGMII. The p5_interface_select enum is supposed to represent the mode that port 5 is being used in, not the hardware information of port 5. Set p5_intf_sel to P5_INTF_SEL_GMAC5 instead, if port 5 is not dsa_is_unused_port(). Signed-off-by: Arınç ÜNAL Acked-by: Daniel Golle Reviewed-by: Vladimir Oltean --- drivers/net/dsa/mt7530-mdio.c | 7 ++--- drivers/net/dsa/mt7530.c | 48 ++++++++++++----------------------- drivers/net/dsa/mt7530.h | 6 +++-- 3 files changed, 22 insertions(+), 39 deletions(-) diff --git a/drivers/net/dsa/mt7530-mdio.c b/drivers/net/dsa/mt7530-mdio.c index 088533663b83..fa3ee85a99c1 100644 --- a/drivers/net/dsa/mt7530-mdio.c +++ b/drivers/net/dsa/mt7530-mdio.c @@ -81,17 +81,14 @@ static const struct regmap_bus mt7530_regmap_bus = { }; static int -mt7531_create_sgmii(struct mt7530_priv *priv, bool dual_sgmii) +mt7531_create_sgmii(struct mt7530_priv *priv) { struct regmap_config *mt7531_pcs_config[2] = {}; struct phylink_pcs *pcs; struct regmap *regmap; int i, ret = 0; - /* MT7531AE has two SGMII units for port 5 and port 6 - * MT7531BE has only one SGMII unit for port 6 - */ - for (i = dual_sgmii ? 0 : 1; i < 2; i++) { + for (i = priv->p5_sgmii ? 0 : 1; i < 2; i++) { mt7531_pcs_config[i] = devm_kzalloc(priv->dev, sizeof(struct regmap_config), GFP_KERNEL); diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 442492d62670..45c9698ad9dd 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -487,15 +487,6 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) return 0; } -static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) -{ - u32 val; - - val = mt7530_read(priv, MT7531_TOP_SIG_SR); - - return (val & PAD_DUAL_SGMII_EN) != 0; -} - static int mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) { @@ -510,9 +501,6 @@ mt7531_pll_setup(struct mt7530_priv *priv) u32 xtal; u32 val; - if (mt7531_dual_sgmii_supported(priv)) - return; - val = mt7530_read(priv, MT7531_CREV); top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); hwstrap = mt7530_read(priv, MT7531_HWTRAP); @@ -920,8 +908,6 @@ static const char *p5_intf_modes(unsigned int p5_interface) return "PHY P4"; case P5_INTF_SEL_GMAC5: return "GMAC5"; - case P5_INTF_SEL_GMAC5_SGMII: - return "GMAC5_SGMII"; default: return "unknown"; } @@ -2470,6 +2456,12 @@ mt7531_setup(struct dsa_switch *ds) return -ENODEV; } + /* MT7531AE has got two SGMII units. One for port 5, one for port 6. + * MT7531BE has got only one SGMII unit which is for port 6. + */ + val = mt7530_read(priv, MT7531_TOP_SIG_SR); + priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); + /* all MACs must be forced link-down before sw reset */ for (i = 0; i < MT7530_NUM_PORTS; i++) mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); @@ -2479,21 +2471,18 @@ mt7531_setup(struct dsa_switch *ds) SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); - mt7531_pll_setup(priv); - - if (mt7531_dual_sgmii_supported(priv)) { - priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; - + if (!priv->p5_sgmii) { + mt7531_pll_setup(priv); + } else { /* Let ds->user_mii_bus be able to access external phy. */ mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, MT7531_EXT_P_MDC_11); mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, MT7531_EXT_P_MDIO_12); - } else { - priv->p5_intf_sel = P5_INTF_SEL_GMAC5; } - dev_dbg(ds->dev, "P5 support %s interface\n", - p5_intf_modes(priv->p5_intf_sel)); + + if (!dsa_is_unused_port(ds, 5)) + priv->p5_intf_sel = P5_INTF_SEL_GMAC5; mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, MT7531_GPIO0_INTERRUPT); @@ -2553,11 +2542,6 @@ static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, } } -static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) -{ - return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); -} - static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { @@ -2570,7 +2554,7 @@ static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, break; case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ - if (mt7531_is_rgmii_port(priv, port)) { + if (!priv->p5_sgmii) { phy_interface_set_rgmii(config->supported_interfaces); break; } @@ -2637,7 +2621,7 @@ static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, { u32 val; - if (!mt7531_is_rgmii_port(priv, port)) { + if (priv->p5_sgmii) { dev_err(priv->dev, "RGMII mode is not available for port %d\n", port); return -EINVAL; @@ -2881,7 +2865,7 @@ mt7531_cpu_port_config(struct dsa_switch *ds, int port) switch (port) { case 5: - if (mt7531_is_rgmii_port(priv, port)) + if (!priv->p5_sgmii) interface = PHY_INTERFACE_MODE_RGMII; else interface = PHY_INTERFACE_MODE_2500BASEX; @@ -3033,7 +3017,7 @@ mt753x_setup(struct dsa_switch *ds) mt7530_free_irq_common(priv); if (priv->create_sgmii) { - ret = priv->create_sgmii(priv, mt7531_dual_sgmii_supported(priv)); + ret = priv->create_sgmii(priv); if (ret && priv->irq) mt7530_free_irq(priv); } diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 1b10b70c1508..12c1731d6201 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -687,7 +687,6 @@ enum p5_interface_select { P5_INTF_SEL_PHY_P0, P5_INTF_SEL_PHY_P4, P5_INTF_SEL_GMAC5, - P5_INTF_SEL_GMAC5_SGMII, }; struct mt7530_priv; @@ -756,6 +755,8 @@ struct mt753x_info { * registers * @p6_interface Holding the current port 6 interface * @p5_intf_sel: Holding the current port 5 interface select + * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch + * has got SGMII * @irq: IRQ number of the switch * @irq_domain: IRQ domain of the switch irq_chip * @irq_enable: IRQ enable bits, synced to SYS_INT_EN @@ -777,6 +778,7 @@ struct mt7530_priv { phy_interface_t p6_interface; phy_interface_t p5_interface; enum p5_interface_select p5_intf_sel; + bool p5_sgmii; u8 mirror_rx; u8 mirror_tx; struct mt7530_port ports[MT7530_NUM_PORTS]; @@ -786,7 +788,7 @@ struct mt7530_priv { int irq; struct irq_domain *irq_domain; u32 irq_enable; - int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii); + int (*create_sgmii)(struct mt7530_priv *priv); unsigned long active_cpu_ports; }; From patchwork Sat Nov 18 12:31:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13459996 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="N/JVrIRD" Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A09E610D5; Sat, 18 Nov 2023 04:33:14 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 28A98E0009; Sat, 18 Nov 2023 12:33:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1700310793; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=EIhFn78LcUCgsrVrNcFAERW+GWx7gO9OZl4IQGexLgo=; b=N/JVrIRDeCvEFtu/gWZJRnePW+fMp0pDdOQCeSKAzCmxXiRW09IGAYZ+9ykKbvn5CUybnZ hKUZxAJ5otc6OQpOa5kfH9AmxtsYh82vnWOvXVN6nelPu/LThotwP0D0f1NxPsZ1HjB65L DGuaY+vfYiVc11cKR+d3Xwu8XvE4UsU3Dum3K9vxsbRuQIrMY8h+OcJBkdIgbY1eeKYny7 Mfr6YkKmXIzkT3riiKZWVAdU6BB22iXNS2nT79q/jg6jxaVdgT7AofTYAiPvvpS10xwTIf 4uHRlplfymB2E9jtLmFxwsx0j8N39IItm73ZjyQ88YktiKaYL04awQ+AXMsDRA== From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com Subject: [PATCH net-next 04/15] net: dsa: mt7530: improve comments regarding port 5 and 6 Date: Sat, 18 Nov 2023 15:31:54 +0300 Message-Id: <20231118123205.266819-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231118123205.266819-1-arinc.unal@arinc9.com> References: <20231118123205.266819-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: arinc.unal@arinc9.com X-Patchwork-Delegate: kuba@kernel.org There's no logic to numerically order the CPU ports. State the port number and its capability of being used as a CPU port instead. Remove the irrelevant PHY muxing information from mt7530_mac_port_get_caps(). Explain the supported MII modes instead. Remove the out of place PHY muxing information from mt753x_phylink_mac_config(). The function is for MT7530, MT7531, and the switch on the MT7988 SoC but there's no PHY muxing on MT7531 or the switch on the MT7988 SoC. These comments were gradually introduced with the commits below. ca366d6c889b ("net: dsa: mt7530: Convert to PHYLINK API") 38f790a80560 ("net: dsa: mt7530: Add support for port 5") 88bdef8be9f6 ("net: dsa: mt7530: Extend device data ready for adding a new hardware") c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch") Signed-off-by: Arınç ÜNAL Acked-by: Daniel Golle Reviewed-by: Andrew Lunn --- drivers/net/dsa/mt7530.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 45c9698ad9dd..8623742b35ee 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2520,12 +2520,16 @@ static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { switch (port) { - case 0 ... 4: /* Internal phy */ + /* Internal PHY */ + case 0 ... 4: __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); break; - case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ + /* Port 5 which can be used as a CPU port supports rgmii with delays, + * mii, and gmii. + */ + case 5: phy_interface_set_rgmii(config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); @@ -2533,7 +2537,8 @@ static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, config->supported_interfaces); break; - case 6: /* 1st cpu port */ + /* Port 6 which can be used as a CPU port supports rgmii and trgmii. */ + case 6: __set_bit(PHY_INTERFACE_MODE_RGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_TRGMII, @@ -2548,19 +2553,24 @@ static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, struct mt7530_priv *priv = ds->priv; switch (port) { - case 0 ... 4: /* Internal phy */ + /* Internal PHY */ + case 0 ... 4: __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); break; - case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ + /* Port 5 which can be used as a CPU port supports rgmii with delays on + * MT7531BE, sgmii/802.3z on MT7531AE. + */ + case 5: if (!priv->p5_sgmii) { phy_interface_set_rgmii(config->supported_interfaces); break; } fallthrough; - case 6: /* 1st cpu port supports sgmii/8023z only */ + /* Port 6 which can be used as a CPU port supports sgmii/802.3z. */ + case 6: __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_1000BASEX, @@ -2579,11 +2589,13 @@ static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, phy_interface_zero(config->supported_interfaces); switch (port) { - case 0 ... 4: /* Internal phy */ + /* Internal PHY */ + case 0 ... 4: __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); break; + /* Port 6 which can be used as a CPU port is an internal 10G port. */ case 6: __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); @@ -2747,12 +2759,12 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, u32 mcr_cur, mcr_new; switch (port) { - case 0 ... 4: /* Internal phy */ + case 0 ... 4: if (state->interface != PHY_INTERFACE_MODE_GMII && state->interface != PHY_INTERFACE_MODE_INTERNAL) goto unsupported; break; - case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ + case 5: if (priv->p5_interface == state->interface) break; @@ -2762,7 +2774,7 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, if (priv->p5_intf_sel != P5_DISABLED) priv->p5_interface = state->interface; break; - case 6: /* 1st cpu port */ + case 6: if (priv->p6_interface == state->interface) break; From patchwork Sat Nov 18 12:31:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13459997 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="U5+l9TZ+" Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::224]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B16BD6C; Sat, 18 Nov 2023 04:33:19 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id B2158E0004; Sat, 18 Nov 2023 12:33:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1700310797; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=npb7Ao9l/CLZkgjFezpnANfonUh9O2A/ZCJPtfUfMnI=; b=U5+l9TZ+IK7Yr4bv4g7PNSGI+PdeW+RAX4GjrUWhyFECmwYBtD3svr2LibDejYXIC2ILmb uHzdGChysXMg0QlAyuejFx6heK9wGeYLx22o5oCNc/lMC/QyG9FCx8BbaA1wJgXfVsWs+B 7skVxzBgdlefCDfkhZ/VlC7NTDbcPYNo04UrXmJVqdH8dcNmXewhboEAws8IDhOLWSWsL2 9yDTKB2ilnc6GS3t4smTELZ9sq0334//12fMH11bkITtIQFrlpmdVCd9dVUMUKp15lRnuE YozDG4VvK1cgk90RTu9tdjmM+p0M3WAHOpVXI/Vf1WJiWyZfs8aAFQQIkszG7g== From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com Subject: [PATCH net-next 05/15] net: dsa: mt7530: improve code path for setting up port 5 Date: Sat, 18 Nov 2023 15:31:55 +0300 Message-Id: <20231118123205.266819-6-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231118123205.266819-1-arinc.unal@arinc9.com> References: <20231118123205.266819-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: arinc.unal@arinc9.com X-Patchwork-Delegate: kuba@kernel.org There're two code paths for setting up port 5: mt7530_setup() -> mt7530_setup_port5() mt753x_phylink_mac_config() -> mt753x_mac_config() -> mt7530_mac_config() -> mt7530_setup_port5() Currently mt7530_setup_port5() from mt7530_setup() always runs. If port 5 is used as a CPU, DSA, or user port, mt7530_setup_port5() from mt753x_phylink_mac_config() won't run. That is because priv->p5_interface set on mt7530_setup_port5() will match state->interface on mt753x_phylink_mac_config() which will stop running mt7530_setup_port5() again. Therefore, mt7530_setup_port5() will never run from mt753x_phylink_mac_config(). Address this by not running mt7530_setup_port5() from mt7530_setup() if port 5 is used as a CPU, DSA, or user port. This driver isn't in the dsa_switches_apply_workarounds[] array so phylink will always be present. For the cases of PHY muxing or the port being disabled, call mt7530_setup_port5() from mt7530_setup(). mt7530_setup_port5() from mt753x_phylink_mac_config() won't run when port 5 is disabled or used for PHY muxing as port 5 won't be defined on the devicetree. Do not set priv->p5_intf_sel to P5_DISABLED. It is already set to that when "priv" is allocated. Move setting the interface to a more specific location. It's supposed to be overwritten if PHY muxing is detected. Improve the comment which explains the process. Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 8623742b35ee..069b3dfca6fa 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2308,16 +2308,15 @@ mt7530_setup(struct dsa_switch *ds) return ret; /* Setup port 5 */ - priv->p5_intf_sel = P5_DISABLED; - interface = PHY_INTERFACE_MODE_NA; - if (!dsa_is_unused_port(ds, 5)) { priv->p5_intf_sel = P5_INTF_SEL_GMAC5; - ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); - if (ret && ret != -ENODEV) - return ret; } else { - /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ + /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. + * Set priv->p5_intf_sel to the appropriate value if PHY muxing + * is detected. + */ + interface = PHY_INTERFACE_MODE_NA; + for_each_child_of_node(dn, mac_np) { if (!of_device_is_compatible(mac_np, "mediatek,eth-mac")) @@ -2348,6 +2347,8 @@ mt7530_setup(struct dsa_switch *ds) of_node_put(phy_node); break; } + + mt7530_setup_port5(ds, interface); } #ifdef CONFIG_GPIOLIB @@ -2358,8 +2359,6 @@ mt7530_setup(struct dsa_switch *ds) } #endif /* CONFIG_GPIOLIB */ - mt7530_setup_port5(ds, interface); - /* Flush the FDB table */ ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); if (ret < 0) From patchwork Sat Nov 18 12:31:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13459998 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="SgCnTqu3" Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::224]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DDC3A198A; Sat, 18 Nov 2023 04:33:23 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 3A070E0006; Sat, 18 Nov 2023 12:33:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1700310802; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WDzAot0tfjXO/G8Oe48YLOAZwGpYqezS2fuec9Z3ROY=; b=SgCnTqu3rMvO095WDXiP6Qyq6t5ll1vQXHvwHq0pcbKhNiSkWo4t+vuuUMN0Z1LjE5t051 x5DiHEfLPYs5XZRgH6NgPp48jtRXx6zGkn1PSliVx1YfSLj9qqehoJo80w7y5LUcTiPt0C cZnxT4FMOUAHEgSNiYgPkpC3+CRTCGQaC8F3df+shoC54Omv+0V9deZqyzDNPcTfMMYE8F EJAVS5bqk5IBVhf0hDIaVUnGPlt+uB1Vf9q3JVbGRd3XSsNN6Nchg57fcWkOn2WGlYLoFT QoxVX8a0Q/Kwk9O6JPXVjjhSZflC6BCfJgu+gKbHFLxRtN1+M+1vEin6MfM0Vw== From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com Subject: [PATCH net-next 06/15] net: dsa: mt7530: do not set priv->p5_interface on mt7530_setup_port5() Date: Sat, 18 Nov 2023 15:31:56 +0300 Message-Id: <20231118123205.266819-7-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231118123205.266819-1-arinc.unal@arinc9.com> References: <20231118123205.266819-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: arinc.unal@arinc9.com X-Patchwork-Delegate: kuba@kernel.org Do not set priv->p5_interface on mt7530_setup_port5(). There isn't a case where mt753x_phylink_mac_config() runs after mt7530_setup_port5() which setting priv->p5_interface would prevent mt7530_setup_port5() from running more than once. Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 069b3dfca6fa..fc87ec817672 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -978,8 +978,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); - priv->p5_interface = interface; - unlock_exit: mutex_unlock(&priv->reg_mutex); } From patchwork Sat Nov 18 12:31:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13459999 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="AvJSASRE" Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::224]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E16719B9; Sat, 18 Nov 2023 04:33:28 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id CB0C4E0007; Sat, 18 Nov 2023 12:33:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1700310807; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ymPBPYibgV4VH8D3V5s7Kk5Q9W15/8vLXoPHtxkD1Ak=; b=AvJSASREqKQk+RFBuuZYVhhvjchWruzOouY7Has8VMfqKNLHk9jx4VivtUEKjmrVQcHcah FSsoJR42UVztRm6SGiYbsmIUgIp6blrEOakL7upf5oVj/emfcz8sARgkndC2YX6nM705r0 wr1XqyBUPgH8Ds9Bz/5H0od+Yl9ixbjSGnLSdOtENwS0b3bt7ymbjVEZbtLT4K4qp+teAw XOI6O6tsQq6Z1stf0v6/vJf2DRzK7K6r/3V5nXOLILh5hBoHr5nw2y609HYrdGpqUiTe20 D+LKmLgHBLOpqIDIexQZNSVo4u+yHxD/jB0QspuNQ+ekFIQBNl5s/ToNY33G+g== From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com Subject: [PATCH net-next 07/15] net: dsa: mt7530: do not run mt7530_setup_port5() if port 5 is disabled Date: Sat, 18 Nov 2023 15:31:57 +0300 Message-Id: <20231118123205.266819-8-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231118123205.266819-1-arinc.unal@arinc9.com> References: <20231118123205.266819-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: arinc.unal@arinc9.com X-Patchwork-Delegate: kuba@kernel.org There's no need to run all the code on mt7530_setup_port5() if port 5 is disabled. The only case for calling mt7530_setup_port5() from mt7530_setup() is when PHY muxing is enabled. That is because port 5 is not defined as a port on the devicetree, therefore, it cannot be controlled by phylink. Because of this, run mt7530_setup_port5() if priv->p5_intf_sel is P5_INTF_SEL_PHY_P0 or P5_INTF_SEL_PHY_P4. Remove the P5_DISABLED case from mt7530_setup_port5(). Stop initialising the interface variable as the remaining cases will always call mt7530_setup_port5() with it initialised. Signed-off-by: Arınç ÜNAL Reviewed-by: Vladimir Oltean --- drivers/net/dsa/mt7530.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index fc87ec817672..1aab4c3f28b0 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -942,9 +942,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ val &= ~MHWTRAP_P5_DIS; break; - case P5_DISABLED: - interface = PHY_INTERFACE_MODE_NA; - break; default: dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", priv->p5_intf_sel); @@ -2313,8 +2310,6 @@ mt7530_setup(struct dsa_switch *ds) * Set priv->p5_intf_sel to the appropriate value if PHY muxing * is detected. */ - interface = PHY_INTERFACE_MODE_NA; - for_each_child_of_node(dn, mac_np) { if (!of_device_is_compatible(mac_np, "mediatek,eth-mac")) @@ -2346,7 +2341,9 @@ mt7530_setup(struct dsa_switch *ds) break; } - mt7530_setup_port5(ds, interface); + if (priv->p5_intf_sel == P5_INTF_SEL_PHY_P0 || + priv->p5_intf_sel == P5_INTF_SEL_PHY_P4) + mt7530_setup_port5(ds, interface); } #ifdef CONFIG_GPIOLIB From patchwork Sat Nov 18 12:31:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13460000 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="APJ4DNzi" Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::224]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0FBD91736; Sat, 18 Nov 2023 04:33:32 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 6114DE0003; Sat, 18 Nov 2023 12:33:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1700310811; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rqy+O+1CtWhDF6XEEJjVh7boRblvOVGqqquNaYWwclU=; b=APJ4DNziSv+LqSFMQ+knLWeq9oWPXxr+CeEbG6645Gr89Q5xIEYSenrd8+hhTr1oss7GL9 Nb/D1bjvqzuVLgS+PQUYPesoAg59eR5/20FPdDGr04auLTpZXZ98x4bMqnJQ/bGPsNCor0 YE+Y7ZAiT55Q/PPSF+WW6jQgk4z4VzH3qfTiLpUupMr9IdR9Lr/HLW/R2DtHslRQnb3g1h IsBRjEtDhb/c/lKLfxM7gT4xGPA/BRCsX/36y5ALbLmZBrQafL1W0kSwrgZaq59gO16ig2 WI23zb/40B4Vp2E3j73aKcyNK6JtPKh53/t1B671+PfwXyYd54pAC3GjBpzqCA== From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com Subject: [PATCH net-next 08/15] net: dsa: mt7530: empty default case on mt7530_setup_port5() Date: Sat, 18 Nov 2023 15:31:58 +0300 Message-Id: <20231118123205.266819-9-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231118123205.266819-1-arinc.unal@arinc9.com> References: <20231118123205.266819-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: arinc.unal@arinc9.com X-Patchwork-Delegate: kuba@kernel.org There're two code paths for setting up port 5: mt7530_setup() -> mt7530_setup_port5() mt753x_phylink_mac_config() -> mt753x_mac_config() -> mt7530_mac_config() -> mt7530_setup_port5() On the first code path, priv->p5_intf_sel is either set to P5_INTF_SEL_PHY_P0 or P5_INTF_SEL_PHY_P4 when mt7530_setup_port5() is run. On the second code path, priv->p5_intf_sel is set to P5_INTF_SEL_GMAC5 when mt7530_setup_port5() is run. Empty the default case which will never run but is needed nonetheless to handle all the remaining enumeration values. Signed-off-by: Arınç ÜNAL Reviewed-by: Vladimir Oltean --- drivers/net/dsa/mt7530.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 1aab4c3f28b0..7de55cbf19a4 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -943,9 +943,7 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) val &= ~MHWTRAP_P5_DIS; break; default: - dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", - priv->p5_intf_sel); - goto unlock_exit; + break; } /* Setup RGMII settings */ @@ -975,7 +973,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); -unlock_exit: mutex_unlock(&priv->reg_mutex); } From patchwork Sat Nov 18 12:31:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13460001 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="DsEAibtI" Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::224]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE1EC198D; Sat, 18 Nov 2023 04:33:37 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 09654E0005; Sat, 18 Nov 2023 12:33:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1700310816; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZtdlEhKOyuiPVha2wgsgCEA05URREqqP5nWTX+JvIXk=; b=DsEAibtIejtYsVZTcsXoDs07bY1ctbzGpz5auFD6Q8PRck/RL/Aq2CmgXV8hEeGqByEFO2 Dn3PdQw5ClDM8Ta7em7npYm4kLD4uIunqphB/kznadzOVISczYiv438CozSh8b+hRcrPFO beAXs+9rThPsVCR7U06ySwFNA0ywYUhG1TLyjSIqfWSwGH5xi7zu1J3VukOIK5j4cjBO8n knfNWYRG1TiRuL7Gpgrq21br4W47dlgwAS6o52CKiHlzftQtgSAwxBDE4TTiJYbWuwMPw+ sDv99xDJYH9ZGVfOzwXuJiD1OsG8ZZ1FmC4t+48K+zzuhc9ywSCwhItMnaTnLA== From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com Subject: [PATCH net-next 09/15] net: dsa: mt7530: call port 6 setup from mt7530_mac_config() Date: Sat, 18 Nov 2023 15:31:59 +0300 Message-Id: <20231118123205.266819-10-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231118123205.266819-1-arinc.unal@arinc9.com> References: <20231118123205.266819-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: arinc.unal@arinc9.com X-Patchwork-Delegate: kuba@kernel.org mt7530_pad_clk_setup() is called if port 6 is enabled. It used to do more things than setting up port 6. That part was moved to more appropriate locations, mt7530_setup() and mt7530_pll_setup(). Now that all it does is set up port 6, rename it to mt7530_setup_port6(), and move it to a more appropriate location, under mt7530_mac_config(). Leave an empty mt7530_pad_clk_setup() to satisfy the pad_setup function pointer. This is the code path for setting up the ports before: mt753x_phylink_mac_config() -> mt753x_mac_config() -> mt7530_mac_config() -> mt7530_setup_port5() -> mt753x_pad_setup() -> mt7530_pad_clk_setup() This is after: mt753x_phylink_mac_config() -> mt753x_mac_config() -> mt7530_mac_config() -> mt7530_setup_port5() -> mt7530_setup_port6() Signed-off-by: Arınç ÜNAL Reviewed-by: Vladimir Oltean --- drivers/net/dsa/mt7530.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 7de55cbf19a4..ae037ff7d4c5 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -415,7 +415,7 @@ mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) /* Setup port 6 interface mode and TRGMII TX circuit */ static int -mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) +mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) { struct mt7530_priv *priv = ds->priv; u32 ncpo1, ssc_delta, trgint, xtal; @@ -487,6 +487,12 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) return 0; } +static int +mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) +{ + return 0; +} + static int mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) { @@ -2608,12 +2614,15 @@ mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) { struct mt7530_priv *priv = ds->priv; + int ret; - /* Only need to setup port5. */ - if (port != 5) - return 0; - - mt7530_setup_port5(priv->ds, interface); + if (port == 5) { + mt7530_setup_port5(priv->ds, interface); + } else if (port == 6) { + ret = mt7530_setup_port6(priv->ds, interface); + if (ret) + return ret; + } return 0; } From patchwork Sat Nov 18 13:12:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13460032 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="bHd0p37k" Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::226]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 95927129; Sat, 18 Nov 2023 05:13:02 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 843F6C0002; Sat, 18 Nov 2023 13:12:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1700313181; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YzOyfRf/U6AGI+K5GG0hXjgKzgPakTR5qXuil3Zv10w=; b=bHd0p37kGbLPWYLSjBJQLxjXdTcoG361d/RaaE45H1HUdqaR9UHMTkOhte8MyB9+v1Xlsq nnoz9ii7B40jpqEraXUqORqDm5T5/nSrEfvQ4iB58JiwzbJbarJlzfIY9YPqglvkz7Af4t 7/EcTI10nkV4PPdlSh8xx+Ou65xjIvt48OHBTX1ghrD5qvF1uw5d84kthejmGO/CzdDpIO drPHEuF0dkuqJAWtu/eriFaLlHquih02BMbkMudsro3ap7Vb11L4z31noiAjNuxrVXCIxX x3RUC79i8LQRMC4ijvej51tI5vcjhRNkWReGsC7XZD2qVu09kTNDN0Vh1bdEFA== From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com Subject: [PATCH net-next 10/15] net: dsa: mt7530: remove pad_setup function pointer Date: Sat, 18 Nov 2023 16:12:28 +0300 Message-Id: <20231118131228.294922-1-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231118123205.266819-1-arinc.unal@arinc9.com> References: <20231118123205.266819-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: arinc.unal@arinc9.com X-Patchwork-Delegate: kuba@kernel.org The pad_setup function pointer was introduced with 88bdef8be9f6 ("net: dsa: mt7530: Extend device data ready for adding a new hardware"). It was being used to set up the core clock and port 6 of the MT7530 switch, and pll of the MT7531 switch. All of these were moved to more appropriate locations, and it was never used for the switch on the MT7988 SoC. Therefore, this function pointer hasn't got a use anymore. Remove it. Signed-off-by: Arınç ÜNAL Acked-by: Daniel Golle Reviewed-by: Vladimir Oltean --- drivers/net/dsa/mt7530.c | 36 ++---------------------------------- drivers/net/dsa/mt7530.h | 3 --- 2 files changed, 2 insertions(+), 37 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index ae037ff7d4c5..efe5ffe3455d 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -487,18 +487,6 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) return 0; } -static int -mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) -{ - return 0; -} - -static int -mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) -{ - return 0; -} - static void mt7531_pll_setup(struct mt7530_priv *priv) { @@ -2601,14 +2589,6 @@ static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, } } -static int -mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) -{ - struct mt7530_priv *priv = ds->priv; - - return priv->info->pad_setup(ds, state->interface); -} - static int mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) @@ -2778,8 +2758,6 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, if (priv->p6_interface == state->interface) break; - mt753x_pad_setup(ds, state); - if (mt753x_mac_config(ds, port, mode, state) < 0) goto unsupported; @@ -3092,11 +3070,6 @@ mt753x_conduit_state_change(struct dsa_switch *ds, CPU_PORT(__ffs(priv->active_cpu_ports))); } -static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface) -{ - return 0; -} - static int mt7988_setup(struct dsa_switch *ds) { struct mt7530_priv *priv = ds->priv; @@ -3160,7 +3133,6 @@ const struct mt753x_info mt753x_table[] = { .phy_write_c22 = mt7530_phy_write_c22, .phy_read_c45 = mt7530_phy_read_c45, .phy_write_c45 = mt7530_phy_write_c45, - .pad_setup = mt7530_pad_clk_setup, .mac_port_get_caps = mt7530_mac_port_get_caps, .mac_port_config = mt7530_mac_config, }, @@ -3172,7 +3144,6 @@ const struct mt753x_info mt753x_table[] = { .phy_write_c22 = mt7530_phy_write_c22, .phy_read_c45 = mt7530_phy_read_c45, .phy_write_c45 = mt7530_phy_write_c45, - .pad_setup = mt7530_pad_clk_setup, .mac_port_get_caps = mt7530_mac_port_get_caps, .mac_port_config = mt7530_mac_config, }, @@ -3184,7 +3155,6 @@ const struct mt753x_info mt753x_table[] = { .phy_write_c22 = mt7531_ind_c22_phy_write, .phy_read_c45 = mt7531_ind_c45_phy_read, .phy_write_c45 = mt7531_ind_c45_phy_write, - .pad_setup = mt7531_pad_setup, .cpu_port_config = mt7531_cpu_port_config, .mac_port_get_caps = mt7531_mac_port_get_caps, .mac_port_config = mt7531_mac_config, @@ -3197,7 +3167,6 @@ const struct mt753x_info mt753x_table[] = { .phy_write_c22 = mt7531_ind_c22_phy_write, .phy_read_c45 = mt7531_ind_c45_phy_read, .phy_write_c45 = mt7531_ind_c45_phy_write, - .pad_setup = mt7988_pad_setup, .cpu_port_config = mt7988_cpu_port_config, .mac_port_get_caps = mt7988_mac_port_get_caps, .mac_port_config = mt7988_mac_config, @@ -3227,9 +3196,8 @@ mt7530_probe_common(struct mt7530_priv *priv) /* Sanity check if these required device operations are filled * properly. */ - if (!priv->info->sw_setup || !priv->info->pad_setup || - !priv->info->phy_read_c22 || !priv->info->phy_write_c22 || - !priv->info->mac_port_get_caps || + if (!priv->info->sw_setup || !priv->info->phy_read_c22 || + !priv->info->phy_write_c22 || !priv->info->mac_port_get_caps || !priv->info->mac_port_config) return -EINVAL; diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 12c1731d6201..aabe7f6cffeb 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -704,8 +704,6 @@ struct mt753x_pcs { * @phy_write_c22: Holding the way writing PHY port using C22 * @phy_read_c45: Holding the way reading PHY port using C45 * @phy_write_c45: Holding the way writing PHY port using C45 - * @pad_setup: Holding the way setting up the bus pad for a certain - * MAC port * @phy_mode_supported: Check if the PHY type is being supported on a certain * port * @mac_port_validate: Holding the way to set addition validate type for a @@ -726,7 +724,6 @@ struct mt753x_info { int regnum); int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad, int regnum, u16 val); - int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface); int (*cpu_port_config)(struct dsa_switch *ds, int port); void (*mac_port_get_caps)(struct dsa_switch *ds, int port, struct phylink_config *config); From patchwork Sat Nov 18 13:13:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13460033 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="PWZl8nw7" Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D45EF127; Sat, 18 Nov 2023 05:14:29 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 3ABCD20003; Sat, 18 Nov 2023 13:14:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1700313268; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uXFYiw10a0pMRlEC7kyG2G0OwntK950CTsvbCBCBf30=; b=PWZl8nw7sn+4XH1/1AYHk3tWRGYSS8MU9Q/LVr3grMOWXGARHkH7VDsDb7/NYYewaBi6J5 cra7ROM6eNlyxIzZu5NSD00nRRDnpvTuRe8u2i6S0Xdd/OuUfvMT1GIrNsmcPo5C68F1xy /pN4u2MDFW48jiy6VYJMl/fHiZew8w0WWLoyTUy9wHLc4Vkejcw8tRNpbxaWqQ5WRq7PPc G4ESZvCcRE2biC2hHrxVa9RAXDEMqMWYbmwCO+ZGlkvIa4klNg5vZ5wJKMUcM/2h3FGhz3 zWfXxPCdlc2a5iwAgshoJBaBllTDXSdGIbn+jnzAC9ITgwjel57AZSv6IwmmPg== From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com Subject: [PATCH net-next 11/15] net: dsa: mt7530: move XTAL check to mt7530_setup() Date: Sat, 18 Nov 2023 16:13:13 +0300 Message-Id: <20231118131317.295591-1-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231118123205.266819-1-arinc.unal@arinc9.com> References: <20231118123205.266819-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: arinc.unal@arinc9.com X-Patchwork-Delegate: kuba@kernel.org The crystal frequency concerns the switch core. The frequency should be checked when the switch is being set up so the driver can reject the unsupported hardware earlier and without requiring port 6 to be used. Move it to mt7530_setup(). Drop the unnecessary function printing. Signed-off-by: Arınç ÜNAL Reviewed-by: Andrew Lunn --- drivers/net/dsa/mt7530.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index efe5ffe3455d..167b340350b3 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -422,13 +422,6 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; - if (xtal == HWTRAP_XTAL_20MHZ) { - dev_err(priv->dev, - "%s: MT7530 with a 20MHz XTAL is not supported!\n", - __func__); - return -EINVAL; - } - switch (interface) { case PHY_INTERFACE_MODE_RGMII: trgint = 0; @@ -2235,6 +2228,12 @@ mt7530_setup(struct dsa_switch *ds) return -ENODEV; } + if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_20MHZ) { + dev_err(priv->dev, + "MT7530 with a 20MHz XTAL is not supported!\n"); + return -EINVAL; + } + /* Reset the switch through internal reset */ mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | From patchwork Sat Nov 18 13:13:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13460034 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="SD0WaCM2" Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A920D47; Sat, 18 Nov 2023 05:14:43 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 1474B20002; Sat, 18 Nov 2023 13:14:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1700313282; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=S3MEYC7gqOMpfZ2Sz1eq2IzjVR1wvtK+PgC+zCdTF1s=; b=SD0WaCM256ys8s8rdqlsCKTRgDW5r4oP7kAF4v8vnFA7OdoXbe+ebcUTtnIGkvJ3Tzqy9H CCP6zlQu7MHZGBJ0EFgOyRPnlJswtwj2ripKseEEzOIzuVi6VBVxzcGz0nh9AhpjBXlUtn V3ZtU4KMuWfSnkPUIUq5AsySqo+rBJPR7lNlk9y4wPvF/sZ8yyGaDXWQ6M/zkyUO4+OdSe 6MPcz3us6drJ6mARadUTrdW2dmHz2VJ3xb79ozZf8MZ3eUrKlXeCMbtg9iNG6gTj25jtFs TtYqOt0VmA2OSj0uVyzOCCGeOjNlBkOCGE8gPb2W2ZCyzZNPJRyONjYArsMeJg== From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com Subject: [PATCH net-next 12/15] net: dsa: mt7530: move enabling port 6 to mt7530_setup_port6() Date: Sat, 18 Nov 2023 16:13:14 +0300 Message-Id: <20231118131317.295591-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231118123205.266819-1-arinc.unal@arinc9.com> References: <20231118123205.266819-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: arinc.unal@arinc9.com X-Patchwork-Delegate: kuba@kernel.org Enable port 6 only when port 6 is being used. Update the comment on mt7530_setup() with a better explanation. Do not set MHWTRAP_MANUAL on mt7530_setup_port5() as it's already done on mt7530_setup() beforehand. Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 167b340350b3..2608b09d3295 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -420,6 +420,8 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) struct mt7530_priv *priv = ds->priv; u32 ncpo1, ssc_delta, trgint, xtal; + mt7530_clear(priv, MT7530_MHWTRAP, MHWTRAP_P6_DIS); + xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; switch (interface) { @@ -910,7 +912,7 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) val = mt7530_read(priv, MT7530_MHWTRAP); - val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; + val |= MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; switch (priv->p5_intf_sel) { @@ -2250,9 +2252,11 @@ mt7530_setup(struct dsa_switch *ds) mt7530_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_MASK, RD_TAP(16)); - /* Enable port 6 */ + /* Directly access the PHY registers via C_MDC/C_MDIO. The bit that + * enables modifying the hardware trap must be set for this. + */ val = mt7530_read(priv, MT7530_MHWTRAP); - val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; + val &= ~MHWTRAP_PHY_ACCESS; val |= MHWTRAP_MANUAL; mt7530_write(priv, MT7530_MHWTRAP, val); From patchwork Sat Nov 18 13:13:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13460035 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="IUGvmTrE" Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1CF2CD5B; Sat, 18 Nov 2023 05:14:49 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 8766D20003; Sat, 18 Nov 2023 13:14:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1700313288; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=usciJlF0tBj+65L/MlcGZT5V9mSdub2woDEGmaEy00Q=; b=IUGvmTrE7zpTGuWVyUr1MAfWYeD72X5M9kUZK8NY93Gsl96zfAnW0ZR9hI6NrxtsJ6bt9Z +t8QADbxAftCTShuFDLuT44B41TzpUyUqNXH8yHpFMgmQyNrVgww07n18VGzVLY1HX7W9I bzPBr6TfnxuV4MWjw+87vEA4dygZnAzyiZO3e3sGkwK7FViaKLRTrPTdmXhn+3kUg7Ifcy hw2gZqdykB2UGeGfmOxz1cQdp2MUsgxB0sUun7IN78sRhBPxvWtdi7eEKml+/66xUskX7v o84kCnkBEEv+uRkiXrnKq+Wbhy024z8ckKegMzM9cRdzK8O3MTP8lNvd/XPWUA== From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com Subject: [PATCH net-next 13/15] net: dsa: mt7530: simplify mt7530_setup_port6() and change to void Date: Sat, 18 Nov 2023 16:13:15 +0300 Message-Id: <20231118131317.295591-3-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231118123205.266819-1-arinc.unal@arinc9.com> References: <20231118123205.266819-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: arinc.unal@arinc9.com X-Patchwork-Delegate: kuba@kernel.org This code is from before this driver was converted to phylink API. Phylink deals with the unsupported interface cases before mt7530_setup_port6() is run. Therefore, the default case would never run. However, it must be defined nonetheless to handle all the remaining enumeration values, the phy-modes. Switch to if statement for RGMII and return which simplifies the code and saves an indent. Do not set P6_INTF_MODE, which is the the three least significant bits of the MT7530_P6ECR register, to 0 for RGMII as it will already be 0 after reset. Read XTAL after checking for RGMII as it's only needed for the TRGMII interface mode. Change mt7530_setup_port6() to void now that there're no error cases left. Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 100 ++++++++++++++++----------------------- 1 file changed, 40 insertions(+), 60 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 2608b09d3295..f36f240231b5 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -414,72 +414,56 @@ mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) } /* Setup port 6 interface mode and TRGMII TX circuit */ -static int +static void mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) { struct mt7530_priv *priv = ds->priv; - u32 ncpo1, ssc_delta, trgint, xtal; + u32 ncpo1, ssc_delta, xtal; mt7530_clear(priv, MT7530_MHWTRAP, MHWTRAP_P6_DIS); + if (interface == PHY_INTERFACE_MODE_RGMII) + return; + + mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1)); + xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; - switch (interface) { - case PHY_INTERFACE_MODE_RGMII: - trgint = 0; - break; - case PHY_INTERFACE_MODE_TRGMII: - trgint = 1; + if (xtal == HWTRAP_XTAL_25MHZ) + ssc_delta = 0x57; + else + ssc_delta = 0x87; + + if (priv->id == ID_MT7621) { + /* PLL frequency: 125MHz: 1.0GBit */ + if (xtal == HWTRAP_XTAL_40MHZ) + ncpo1 = 0x0640; if (xtal == HWTRAP_XTAL_25MHZ) - ssc_delta = 0x57; - else - ssc_delta = 0x87; - if (priv->id == ID_MT7621) { - /* PLL frequency: 125MHz: 1.0GBit */ - if (xtal == HWTRAP_XTAL_40MHZ) - ncpo1 = 0x0640; - if (xtal == HWTRAP_XTAL_25MHZ) - ncpo1 = 0x0a00; - } else { /* PLL frequency: 250MHz: 2.0Gbit */ - if (xtal == HWTRAP_XTAL_40MHZ) - ncpo1 = 0x0c80; - if (xtal == HWTRAP_XTAL_25MHZ) - ncpo1 = 0x1400; - } - break; - default: - dev_err(priv->dev, "xMII interface %d not supported\n", - interface); - return -EINVAL; + ncpo1 = 0x0a00; + } else { /* PLL frequency: 250MHz: 2.0Gbit */ + if (xtal == HWTRAP_XTAL_40MHZ) + ncpo1 = 0x0c80; + if (xtal == HWTRAP_XTAL_25MHZ) + ncpo1 = 0x1400; } - mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, - P6_INTF_MODE(trgint)); - - if (trgint) { - /* Disable the MT7530 TRGMII clocks */ - core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); - - /* Setup the MT7530 TRGMII Tx Clock */ - core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); - core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); - core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); - core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); - core_write(priv, CORE_PLL_GROUP4, - RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | - RG_SYSPLL_BIAS_LPF_EN); - core_write(priv, CORE_PLL_GROUP2, - RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | - RG_SYSPLL_POSDIV(1)); - core_write(priv, CORE_PLL_GROUP7, - RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | - RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); + /* Disable the MT7530 TRGMII clocks */ + core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); - /* Enable the MT7530 TRGMII clocks */ - core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); - } + /* Setup the MT7530 TRGMII Tx Clock */ + core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); + core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); + core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); + core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); + core_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | + RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); + core_write(priv, CORE_PLL_GROUP2, RG_SYSPLL_EN_NORMAL | + RG_SYSPLL_VODEN | RG_SYSPLL_POSDIV(1)); + core_write(priv, CORE_PLL_GROUP7, RG_LCDDS_PCW_NCPO_CHG | + RG_LCCDS_C(3) | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); - return 0; + /* Enable the MT7530 TRGMII clocks */ + core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); } static void @@ -2597,15 +2581,11 @@ mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) { struct mt7530_priv *priv = ds->priv; - int ret; - if (port == 5) { + if (port == 5) mt7530_setup_port5(priv->ds, interface); - } else if (port == 6) { - ret = mt7530_setup_port6(priv->ds, interface); - if (ret) - return ret; - } + else if (port == 6) + mt7530_setup_port6(priv->ds, interface); return 0; } From patchwork Sat Nov 18 13:13:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13460036 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="huj0uA40" Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2258127; Sat, 18 Nov 2023 05:14:54 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 308CF20002; Sat, 18 Nov 2023 13:14:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1700313293; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=h1wtPYbuvCrxzK3zVYcy+dqMNAt++iVN9XJT5RdrMlU=; b=huj0uA40EXpEj+N00n8DwlkjzblQ5eqh2gaex0fcBiOFYukZHxlO0s1TA72cAdJUn0vwQS LA22YLgypbPSsoJvecdpGX99+sYre9Bvs71sT2F6U0qO/qjE2fu3mSj5ryE6DzAjpasRrT 1DdzjOLP0qnbbiYjgMgDgbgI2eMHmglslDiD0la2xmw9+6Ci5+SO4C8bfTc1bAZgWhDnN0 pnMNuNgKJutl30lPWa/QyCTSCDv0jUH+XMvxFK0G7cTkq3O2qe7h73rzy7FV0BU62wWORW uCvYETEfp9Oj4l/B1ZdJa5PXuJdxzVm74M8X5cXVWnizKYxwcf6gmzBwiWx6jw== From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com Subject: [PATCH net-next 14/15] net: dsa: mt7530: correct port capabilities of MT7988 Date: Sat, 18 Nov 2023 16:13:16 +0300 Message-Id: <20231118131317.295591-4-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231118123205.266819-1-arinc.unal@arinc9.com> References: <20231118123205.266819-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: arinc.unal@arinc9.com X-Patchwork-Delegate: kuba@kernel.org On the switch on the MT7988 SoC, there are only 4 PHYs. That's port 0 to 3. Set the internal phy cases to '0 ... 3'. Signed-off-by: Arınç ÜNAL Acked-by: Daniel Golle --- drivers/net/dsa/mt7530.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index f36f240231b5..ca42005ff3a9 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2562,7 +2562,7 @@ static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, switch (port) { /* Internal PHY */ - case 0 ... 4: + case 0 ... 3: __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); break; From patchwork Sat Nov 18 13:13:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13460037 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="WaKbZMD9" Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7051ED76; Sat, 18 Nov 2023 05:14:59 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id D183920004; Sat, 18 Nov 2023 13:14:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1700313298; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QHMSEER/SBEH4IqK5yT4ZrjQxH8VpFrbj9NbOVlG2+g=; b=WaKbZMD90W3n3aSXSb3a0ZAU/mvWWrOzYmu/OX+FjY2U++BzndNh1VYokHs8s9NcqXZBQO HjEAkUBwmEAut1Au+7mXn76E7pg4Fvyc9hZYocLl8hf7ondvoS0S/SKOtlHiUzcdSmNQkX wLJNarbKsxYgD8Pod5XGAnzQ6QJ8YK3mRXIe/gI/LxOzODeOHgLAJ0FJ3/4EsT/dY+5pnw 0ank40KApmUlWos2qsif/6/gW7SE8P7aW/Co7YVTgZY5baXpE1j3a5NAH8O+yqto4/L3iY jdYgq6gdqTWVF+RkZF7NRQtgANtLpKvumYvDotECsgxItT2b9J+RS+EAKAVOWQ== From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com Subject: [PATCH net-next 15/15] net: dsa: mt7530: do not clear config->supported_interfaces Date: Sat, 18 Nov 2023 16:13:17 +0300 Message-Id: <20231118131317.295591-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231118123205.266819-1-arinc.unal@arinc9.com> References: <20231118123205.266819-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: arinc.unal@arinc9.com X-Patchwork-Delegate: kuba@kernel.org There's no need to clear the config->supported_interfaces bitmap before reporting the supported interfaces as all bits in the bitmap will already be initialized to zero when the phylink_config structure is allocated. There's no code that would change the bitmap beforehand. Remove it. Signed-off-by: Arınç ÜNAL Acked-by: Daniel Golle --- drivers/net/dsa/mt7530.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index ca42005ff3a9..20ae147b823e 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2558,8 +2558,6 @@ static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { - phy_interface_zero(config->supported_interfaces); - switch (port) { /* Internal PHY */ case 0 ... 3: