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pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 1/3] xen/arm64: head: Move earlyprintk 'hex' string to .rodata.str Date: Tue, 21 Nov 2023 10:45:14 +0100 Message-ID: <20231121094516.24714-2-michal.orzel@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231121094516.24714-1-michal.orzel@amd.com> References: <20231121094516.24714-1-michal.orzel@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD8:EE_|DM4PR12MB6232:EE_ X-MS-Office365-Filtering-Correlation-Id: b81c3e5d-426a-41c1-fb22-08dbea769d2d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: QAawCmonysYyZRy4GSjhFVz50WGC3VQyHobIKimZHxcsdyXKznSCWuVSgJHYpMqbLcZxBfq00kRNSntuip9d8kyanOQ317gXf7ymTwQXizTCxUyoh/BeG0/dxHeKLflnwiQ1EfxX647PKCt+1v+H5UpNf1lT5/memchHgoy1W4sPsqaOs6P2G0vVArnZ1WdSj+voNTYhC36dMxmfTHV4UG8gRzpC9gJUUaytnnngBCn40MMSfSsXsOXc0Oqz9t2BGjECYqRSA1GhDENm9j4AcExGUE1v3tNmwwWLuIurc6ENwQ7agvIzDGMMehBAoZmlZ/VmXz9TQzDS/sYnk7al4L2vmVPJ6b62KadG69WEhVJJ2SCMtBz7XMdYjBhEZSQkcbu1LxQhTOR/whzWkNTKU0re/xO2LUlgVXLFzI7kjYjz0/3piwz+kyI4PI9WXfp4g8YFBI766+CSsRMsnVhK3SUJBBVv/haNpdawXod+HsQXrCHcUCWTxIblyhd3NC+Q/ZuTpSEh5iPcxlBxUpSaaHrQg4TCscfn3B29af8iTTjBJZ1Ws+qJFB6EnT9coFJus1IQC6C0wkS3aQgvoUrbwNP9cBIVmQPXFoAIMefaWbZ/14+xQ2Q/1gML287XdHu7QUqcQVQZ/TRFv/eeiOjRjq00ElaalWrKA6V34KZNZPuvnYaMn8qY44MYxmkUJBLezjkx1OroKG9jolh2TYamRVjovog4q6zYfjs7BzJsQ5zPSKk9hf9Jfylfa90+2CZqrqANZAV1twQxLG+5yW2GbYOGJDJT6Eg6vTJwfq2UF/4= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(396003)(39860400002)(136003)(346002)(230922051799003)(64100799003)(451199024)(186009)(1800799012)(82310400011)(46966006)(40470700004)(36840700001)(2906002)(5660300002)(4326008)(8936002)(8676002)(36860700001)(40460700003)(82740400003)(86362001)(36756003)(41300700001)(81166007)(356005)(478600001)(54906003)(70586007)(70206006)(6916009)(316002)(40480700001)(1076003)(426003)(336012)(26005)(2616005)(83380400001)(47076005)(6666004)(44832011)(142923001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2023 09:45:36.6665 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b81c3e5d-426a-41c1-fb22-08dbea769d2d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6232 At the moment, the 'hex' string is placed right after the 'putn' function in the .text section. This is because of the limited range (+/- 1MB) of PC relative 'adr' instruction 'putn' uses. Modify it to use 'adr_l' instead (range extended to +/- 4GB) and move the string to .rodata.str. This way all the earlyprintk messages will be part of .rodata and the behavior will be consistent with what we already do on arm32. Signed-off-by: Michal Orzel Reviewed-by: Luca Fancellu Tested-by: Luca Fancellu --- xen/arch/arm/arm64/head.S | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 8dbd3300d89f..b6111399e766 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -498,7 +498,7 @@ ENDPROC(asm_puts) * Clobbers x0-x3 */ putn: - adr x1, hex + adr_l x1, hex mov x3, #16 1: early_uart_ready x23, 2 @@ -512,8 +512,7 @@ putn: ret ENDPROC(putn) -hex: .ascii "0123456789abcdef" - .align 2 +RODATA_STR(hex, "0123456789abcdef") #else /* CONFIG_EARLY_PRINTK */ From patchwork Tue Nov 21 09:45:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Orzel X-Patchwork-Id: 13462678 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8C4CDC61D92 for ; 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bh=UQB4kMys3NHsmr+0I1e6qowHc6xEtQRyK9lAZRDr8Go=; b=mwNwugPZ2eiMBae1mhS1F/mdDnW2Inl8VpYH/kbsruX4Q0dBB7cHqoyB1EiVH7TwLEDSOGkZgpJl/MwrOkccABRXGs4KLVb4esH9qqSc5NUo01sMCcNww851FGswiO9kOMrpqvCMZUaV+STZN5roYjO69SXqC2O7E7rL6aYKBfY= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 2/3] xen/arm64: Move print_reg macro to asm/arm64/macros.h Date: Tue, 21 Nov 2023 10:45:15 +0100 Message-ID: <20231121094516.24714-3-michal.orzel@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231121094516.24714-1-michal.orzel@amd.com> References: <20231121094516.24714-1-michal.orzel@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD8:EE_|CY5PR12MB6573:EE_ X-MS-Office365-Filtering-Correlation-Id: dc33c694-241e-49db-7693-08dbea769e6d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2023 09:45:38.7134 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dc33c694-241e-49db-7693-08dbea769e6d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6573 Macro print_reg is used to print a value of a register passed as an argument. While today it is only used from within the common head.S, in the future we might want to make use of it from other files, just like PRINT(). It also serves as a great aid when debugging. Expose print_reg macro by moving it to asm/arm64/macros.h and: - rename putn to asm_putn to denote the usage from assembly only, - use ENTRY() for asm_putn to make it globally visible, - get rid of unneeded stubs for early_puts, init_uart and putn since the calls to them are already protected by #ifdef CONFIG_EARLY_PRINTK. This way the behavior will be consistent with what we already do on arm32. Signed-off-by: Michal Orzel Reviewed-by: Luca Fancellu Tested-by: Luca Fancellu Acked-by: Julien Grall --- xen/arch/arm/arm64/head.S | 32 ++++--------------------- xen/arch/arm/include/asm/arm64/macros.h | 15 ++++++++++++ 2 files changed, 19 insertions(+), 28 deletions(-) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index b6111399e766..a3dbf81ab515 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -74,25 +74,6 @@ * x30 - lr */ - #ifdef CONFIG_EARLY_PRINTK -/* - * Macro to print the value of register \xb - * - * Clobbers x0 - x4 - */ -.macro print_reg xb - mov x0, \xb - mov x4, lr - bl putn - mov lr, x4 -.endm - -#else /* CONFIG_EARLY_PRINTK */ -.macro print_reg xb -.endm - -#endif /* !CONFIG_EARLY_PRINTK */ - .section .text.header, "ax", %progbits /*.aarch64*/ @@ -493,11 +474,12 @@ ENDPROC(asm_puts) /* * Print a 64-bit number in hex. + * Note: This function must be called from assembly. * x0: Number to print. * x23: Early UART base address * Clobbers x0-x3 */ -putn: +ENTRY(asm_putn) adr_l x1, hex mov x3, #16 1: @@ -510,17 +492,11 @@ putn: subs x3, x3, #1 b.ne 1b ret -ENDPROC(putn) +ENDPROC(asm_putn) RODATA_STR(hex, "0123456789abcdef") -#else /* CONFIG_EARLY_PRINTK */ - -ENTRY(early_puts) -init_uart: -putn: ret - -#endif /* !CONFIG_EARLY_PRINTK */ +#endif /* CONFIG_EARLY_PRINTK */ /* This provides a C-API version of __lookup_processor_type * TODO: For now, the implementation return NULL every time diff --git a/xen/arch/arm/include/asm/arm64/macros.h b/xen/arch/arm/include/asm/arm64/macros.h index fb9a0602494d..d108dc3a3a71 100644 --- a/xen/arch/arm/include/asm/arm64/macros.h +++ b/xen/arch/arm/include/asm/arm64/macros.h @@ -45,9 +45,24 @@ mov lr, x3 ; \ RODATA_STR(98, _s) +/* + * Macro to print the value of register \xb + * + * Clobbers x0 - x4 + */ +.macro print_reg xb + mov x0, \xb + mov x4, lr + bl asm_putn + mov lr, x4 +.endm + #else /* CONFIG_EARLY_PRINTK */ #define PRINT(s) +.macro print_reg xb +.endm + #endif /* !CONFIG_EARLY_PRINTK */ /* From patchwork Tue Nov 21 09:45:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Orzel X-Patchwork-Id: 13462677 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 294BCC61D88 for ; Tue, 21 Nov 2023 09:45:58 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.637606.993557 (Exim 4.92) (envelope-from ) id 1r5NKD-0004CY-7g; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 3/3] xen/arm64/mmu: head: Replace load_paddr with adr_l where appropriate Date: Tue, 21 Nov 2023 10:45:16 +0100 Message-ID: <20231121094516.24714-4-michal.orzel@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231121094516.24714-1-michal.orzel@amd.com> References: <20231121094516.24714-1-michal.orzel@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD8:EE_|PH7PR12MB7938:EE_ X-MS-Office365-Filtering-Correlation-Id: 0323ef13-c75b-4fdf-bed3-08dbea769ef7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2023 09:45:39.5727 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0323ef13-c75b-4fdf-bed3-08dbea769ef7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7938 Macros load_paddr and adr_l are equivalent when used before the MMU is enabled, resulting in obtaining physical address of a symbol. The former requires to know the physical offset (PA - VA) and can be used both before and after the MMU is enabled. In the spirit of using something only when truly necessary, replace all instances of load_paddr with adr_l, except in create_table_entry macro. Even though there is currently no use of load_paddr after MMU is enabled, this macro used to be call in such a context and we can't rule out that it won't happen again. This way, the logic behind using load_paddr/adr_l is consistent between arm32 and arm64, making it easier for developers to determine which one to use and when. Take the opportunity to fix a comment with incorrect function name. Signed-off-by: Michal Orzel Reviewed-by: Luca Fancellu Tested-by: Luca Fancellu --- xen/arch/arm/arm64/mmu/head.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/arm64/mmu/head.S b/xen/arch/arm/arm64/mmu/head.S index 10774f30e40e..41779020eb4d 100644 --- a/xen/arch/arm/arm64/mmu/head.S +++ b/xen/arch/arm/arm64/mmu/head.S @@ -146,10 +146,10 @@ create_page_tables: /* * We need to use a stash register because - * create_table_entry_paddr() will clobber the register storing + * create_table_entry_from_paddr() will clobber the register storing * the physical address of the table to point to. */ - load_paddr x4, boot_third + adr_l x4, boot_third ldr x1, =XEN_VIRT_START .rept XEN_NR_ENTRIES(2) mov x0, x4 /* x0 := paddr(l3 table) */ @@ -311,7 +311,7 @@ ENDPROC(enable_mmu) ENTRY(enable_secondary_cpu_mm) mov x6, lr - load_paddr x0, init_ttbr + adr_l x0, init_ttbr ldr x0, [x0] mov x1, #SCTLR_Axx_ELx_WXN /* Enable WxN from the start */ @@ -336,7 +336,7 @@ ENTRY(enable_boot_cpu_mm) mov x6, lr bl create_page_tables - load_paddr x0, boot_pgtable + adr_l x0, boot_pgtable mov x1, #0 /* No extra SCTLR flags */ bl enable_mmu