From patchwork Tue Nov 21 11:54:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jinrong Liang X-Patchwork-Id: 13462906 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="EJCR4V3I" Received: from mail-pl1-x642.google.com (mail-pl1-x642.google.com [IPv6:2607:f8b0:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6BE2918E; Tue, 21 Nov 2023 03:55:35 -0800 (PST) Received: by mail-pl1-x642.google.com with SMTP id d9443c01a7336-1cc9b626a96so40037875ad.2; Tue, 21 Nov 2023 03:55:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700567735; x=1701172535; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kGrm68QoMUrup/7Rp3nNNkMcX2hX6/h9dwhr7ZWgjH8=; b=EJCR4V3I+dsuU7B1YHri5Mr0Ew79yoP5mZnDWFtmoEieWIvBhXLRgzQE6NJrMc/6Yj 8VLJbXtnKL0nnuxoxUubkO5oMoSOZ/3z7LcZUlBEPGgIV9aYyUGhM29peZAt4xBLCQMe dUN+axiqYEssRyELE4KjJpyNeBb9quX6bOG131ng3CXf+paKZUb2oLmUNl1TY3z50cp3 6cFgSRUNTAR4Rtcb+vSWr2d9kUlJhg+LWUoH0FvtO8TofmnvdmXhrkteGZNKoOsj3jcI bVIK5wUZtymwVMGq8VLTcivAv2vi4Urb9pTHXe8OqcC06t6x2kE94AE45LNJP3st8oPj OYUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700567735; x=1701172535; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kGrm68QoMUrup/7Rp3nNNkMcX2hX6/h9dwhr7ZWgjH8=; b=lZ+3tynVBr4EEI8CyznR8hR7H6M1rJGDeyDQ3YcCmjg2hVGGi293jqbLfjfFihGhSY n5HiBfeczRDMe0ZQd9s5c5HsSwxrVHtjO0vHWlcokiM/iXP1f83zukoeUj8IVaARKwRl PLj0I0j1u7IktBKcORk0EW4QZDUFIFCk7F9033/CYMflRqoanF3DW0fq25ahyShBzZqo zgQWQmuDgZNdlxtGliGs6HlsNG9sp/1A+z5p81nqm6p/Ly7ayweYoranZSyoLOaXnWgu 6yQiyunVo57v/zMs1xhQZ/Go0XMKxFWlkUPpRlZAObd16no3/siUkftrVD66OlAa/rTX QoiA== X-Gm-Message-State: AOJu0YwFPX6klCQNTg7syppjXZVmA+r6huIDb3wbNkt4/HJts6O2mSbb j01ht2tnkNg2BZgJQTtvnZ+mfaGo08usS8S7Eno= X-Google-Smtp-Source: AGHT+IEP+yqOSLFwgBXDu3JDmfZuTRtjyupxZQFL9EKAjVcQUqw8SuzN7rkHWoNCrZLQKKVhJnp+mw== X-Received: by 2002:a17:902:f7d1:b0:1cf:6e3d:d8e7 with SMTP id h17-20020a170902f7d100b001cf6e3dd8e7mr1445161plw.26.1700567734754; Tue, 21 Nov 2023 03:55:34 -0800 (PST) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id g10-20020a170902740a00b001cc1dff5b86sm7685431pll.244.2023.11.21.03.55.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 03:55:34 -0800 (PST) From: Jinrong Liang X-Google-Original-From: Jinrong Liang To: Sean Christopherson Cc: Paolo Bonzini , Like Xu , Jim Mattson , Aaron Lewis , Wanpeng Li , Jinrong Liang , Jinrong Liang , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/9] KVM: selftests: Add forced emulation check to fix #UD Date: Tue, 21 Nov 2023 19:54:49 +0800 Message-Id: <20231121115457.76269-2-cloudliang@tencent.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231121115457.76269-1-cloudliang@tencent.com> References: <20231121115457.76269-1-cloudliang@tencent.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Forced emulation uses a magic "prefix" to trigger a #UD, which KVM intercepts. If forced emulation isn't enabled, KVM ignores the magic prefix and reflects the #UD back into the guest. Reported-by: Jinrong Liang Signed-off-by: Sean Christopherson Tested-by: Jinrong Liang --- .../selftests/kvm/x86_64/pmu_counters_test.c | 41 ++++++++++++------- 1 file changed, 26 insertions(+), 15 deletions(-) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c index 248ebe8c0577..7d8094a27209 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -325,6 +325,26 @@ __GUEST_ASSERT(expect_gp ? vector == GP_VECTOR : !vector, \ "Expected " #insn "(0x%x) to yield 0x%lx, got 0x%lx", \ msr, expected_val, val); +static void guest_test_rdpmc(uint32_t rdpmc_idx, bool expect_success, + uint64_t expected_val) +{ + uint8_t vector; + uint64_t val; + + vector = rdpmc_safe(rdpmc_idx, &val); + GUEST_ASSERT_PMC_MSR_ACCESS(RDPMC, rdpmc_idx, !expect_success, vector); + if (expect_success) + GUEST_ASSERT_PMC_VALUE(RDPMC, rdpmc_idx, val, expected_val); + + if (!is_forced_emulation_enabled) + return; + + vector = rdpmc_safe_fep(rdpmc_idx, &val); + GUEST_ASSERT_PMC_MSR_ACCESS(RDPMC, rdpmc_idx, !expect_success, vector); + if (expect_success) + GUEST_ASSERT_PMC_VALUE(RDPMC, rdpmc_idx, val, expected_val); +} + static void guest_rd_wr_counters(uint32_t base_msr, uint8_t nr_possible_counters, uint8_t nr_counters, uint32_t or_mask) { @@ -367,20 +387,15 @@ static void guest_rd_wr_counters(uint32_t base_msr, uint8_t nr_possible_counters if (!expect_gp) GUEST_ASSERT_PMC_VALUE(RDMSR, msr, val, expected_val); + /* + * Redo the read tests with RDPMC, which has different indexing + * semantics and additional capabilities. + */ rdpmc_idx = i; if (base_msr == MSR_CORE_PERF_FIXED_CTR0) rdpmc_idx |= INTEL_RDPMC_FIXED; - /* Redo the read tests with RDPMC, and with forced emulation. */ - vector = rdpmc_safe(rdpmc_idx, &val); - GUEST_ASSERT_PMC_MSR_ACCESS(RDPMC, rdpmc_idx, !expect_success, vector); - if (expect_success) - GUEST_ASSERT_PMC_VALUE(RDPMC, rdpmc_idx, val, expected_val); - - vector = rdpmc_safe_fep(rdpmc_idx, &val); - GUEST_ASSERT_PMC_MSR_ACCESS(RDPMC, rdpmc_idx, !expect_success, vector); - if (expect_success) - GUEST_ASSERT_PMC_VALUE(RDPMC, rdpmc_idx, val, expected_val); + guest_test_rdpmc(rdpmc_idx, expect_success, expected_val); /* * KVM doesn't support non-architectural PMUs, i.e. it should @@ -390,11 +405,7 @@ static void guest_rd_wr_counters(uint32_t base_msr, uint8_t nr_possible_counters GUEST_ASSERT(!expect_success || !pmu_has_fast_mode); rdpmc_idx |= INTEL_RDPMC_FAST; - vector = rdpmc_safe(rdpmc_idx, &val); - GUEST_ASSERT_PMC_MSR_ACCESS(RDPMC, rdpmc_idx, true, vector); - - vector = rdpmc_safe_fep(rdpmc_idx, &val); - GUEST_ASSERT_PMC_MSR_ACCESS(RDPMC, rdpmc_idx, true, vector); + guest_test_rdpmc(rdpmc_idx, false, -1ull); vector = wrmsr_safe(msr, 0); GUEST_ASSERT_PMC_MSR_ACCESS(WRMSR, msr, expect_gp, vector); From patchwork Tue Nov 21 11:54:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jinrong Liang X-Patchwork-Id: 13462907 Authentication-Results: smtp.subspace.kernel.org; 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Tue, 21 Nov 2023 03:55:37 -0800 (PST) From: Jinrong Liang X-Google-Original-From: Jinrong Liang To: Sean Christopherson Cc: Paolo Bonzini , Like Xu , Jim Mattson , Aaron Lewis , Wanpeng Li , Jinrong Liang , Jinrong Liang , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/9] KVM: selftests: Test gp counters overflow interrupt handling Date: Tue, 21 Nov 2023 19:54:50 +0800 Message-Id: <20231121115457.76269-3-cloudliang@tencent.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231121115457.76269-1-cloudliang@tencent.com> References: <20231121115457.76269-1-cloudliang@tencent.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Jinrong Liang Add tests to verify that gp counters overflow interrupt handling works as expected and clean up. Signed-off-by: Jinrong Liang --- .../selftests/kvm/x86_64/pmu_counters_test.c | 121 ++++++++++++++---- 1 file changed, 98 insertions(+), 23 deletions(-) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c index 7d8094a27209..1b108e6718fc 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -6,6 +6,7 @@ #define _GNU_SOURCE /* for program_invocation_short_name */ #include +#include "apic.h" #include "pmu.h" #include "processor.h" @@ -19,14 +20,15 @@ #define NUM_EXTRA_INSNS 7 #define NUM_INSNS_RETIRED (NUM_BRANCHES + NUM_EXTRA_INSNS) +#define PMI_VECTOR 0x20 + static uint8_t kvm_pmu_version; static bool kvm_has_perf_caps; static bool is_forced_emulation_enabled; +static bool pmi_irq_called; static struct kvm_vm *pmu_vm_create_with_one_vcpu(struct kvm_vcpu **vcpu, - void *guest_code, - uint8_t pmu_version, - uint64_t perf_capabilities) + void *guest_code) { struct kvm_vm *vm; @@ -34,6 +36,17 @@ static struct kvm_vm *pmu_vm_create_with_one_vcpu(struct kvm_vcpu **vcpu, vm_init_descriptor_tables(vm); vcpu_init_descriptor_tables(*vcpu); + return vm; +} + +static struct kvm_vm *intel_pmu_vm_create(struct kvm_vcpu **vcpu, + void *guest_code, uint8_t pmu_version, + uint64_t perf_capabilities) +{ + struct kvm_vm *vm; + + vm = pmu_vm_create_with_one_vcpu(vcpu, guest_code); + sync_global_to_guest(vm, kvm_pmu_version); sync_global_to_guest(vm, is_forced_emulation_enabled); @@ -45,6 +58,7 @@ static struct kvm_vm *pmu_vm_create_with_one_vcpu(struct kvm_vcpu **vcpu, vcpu_set_msr(*vcpu, MSR_IA32_PERF_CAPABILITIES, perf_capabilities); vcpu_set_cpuid_property(*vcpu, X86_PROPERTY_PMU_VERSION, pmu_version); + return vm; } @@ -198,6 +212,15 @@ static bool pmu_is_null_feature(struct kvm_x86_pmu_feature event) return !(*(u64 *)&event); } +static uint32_t get_pmc_msr(void) +{ + if (this_cpu_has(X86_FEATURE_PDCM) && + rdmsr(MSR_IA32_PERF_CAPABILITIES) & PMU_CAP_FW_WRITES) + return MSR_IA32_PMC0; + else + return MSR_IA32_PERFCTR0; +} + static void guest_test_arch_event(uint8_t idx) { const struct { @@ -226,18 +249,12 @@ static void guest_test_arch_event(uint8_t idx) /* PERF_GLOBAL_CTRL exists only for Architectural PMU Version 2+. */ bool guest_has_perf_global_ctrl = pmu_version >= 2; struct kvm_x86_pmu_feature gp_event, fixed_event; - uint32_t base_pmc_msr; + uint32_t base_pmc_msr = get_pmc_msr(); unsigned int i; /* The host side shouldn't invoke this without a guest PMU. */ GUEST_ASSERT(pmu_version); - if (this_cpu_has(X86_FEATURE_PDCM) && - rdmsr(MSR_IA32_PERF_CAPABILITIES) & PMU_CAP_FW_WRITES) - base_pmc_msr = MSR_IA32_PMC0; - else - base_pmc_msr = MSR_IA32_PERFCTR0; - gp_event = intel_event_to_feature[idx].gp_event; GUEST_ASSERT_EQ(idx, gp_event.f.bit); @@ -293,8 +310,8 @@ static void test_arch_events(uint8_t pmu_version, uint64_t perf_capabilities, if (!pmu_version) return; - vm = pmu_vm_create_with_one_vcpu(&vcpu, guest_test_arch_events, - pmu_version, perf_capabilities); + vm = intel_pmu_vm_create(&vcpu, guest_test_arch_events, pmu_version, + perf_capabilities); vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH, length); @@ -414,18 +431,12 @@ static void guest_rd_wr_counters(uint32_t base_msr, uint8_t nr_possible_counters static void guest_test_gp_counters(void) { + uint32_t base_msr = get_pmc_msr(); uint8_t nr_gp_counters = 0; - uint32_t base_msr; if (guest_get_pmu_version()) nr_gp_counters = this_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS); - if (this_cpu_has(X86_FEATURE_PDCM) && - rdmsr(MSR_IA32_PERF_CAPABILITIES) & PMU_CAP_FW_WRITES) - base_msr = MSR_IA32_PMC0; - else - base_msr = MSR_IA32_PERFCTR0; - guest_rd_wr_counters(base_msr, MAX_NR_GP_COUNTERS, nr_gp_counters, 0); GUEST_DONE(); } @@ -436,8 +447,8 @@ static void test_gp_counters(uint8_t pmu_version, uint64_t perf_capabilities, struct kvm_vcpu *vcpu; struct kvm_vm *vm; - vm = pmu_vm_create_with_one_vcpu(&vcpu, guest_test_gp_counters, - pmu_version, perf_capabilities); + vm = intel_pmu_vm_create(&vcpu, guest_test_gp_counters, pmu_version, + perf_capabilities); vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_NR_GP_COUNTERS, nr_gp_counters); @@ -503,8 +514,8 @@ static void test_fixed_counters(uint8_t pmu_version, uint64_t perf_capabilities, struct kvm_vcpu *vcpu; struct kvm_vm *vm; - vm = pmu_vm_create_with_one_vcpu(&vcpu, guest_test_fixed_counters, - pmu_version, perf_capabilities); + vm = intel_pmu_vm_create(&vcpu, guest_test_fixed_counters, pmu_version, + perf_capabilities); vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK, supported_bitmask); @@ -516,6 +527,68 @@ static void test_fixed_counters(uint8_t pmu_version, uint64_t perf_capabilities, kvm_vm_free(vm); } +static void pmi_irq_handler(struct ex_regs *regs) +{ + pmi_irq_called = true; + x2apic_write_reg(APIC_EOI, 0); +} + +static void guest_test_counters_pmi_workload(void) +{ + __asm__ __volatile__ + ("sti\n" + "loop .\n" + "cli\n" + : "+c"((int){NUM_BRANCHES}) + ); +} + +static void test_pmi_init_x2apic(void) +{ + x2apic_enable(); + x2apic_write_reg(APIC_ICR, APIC_DEST_SELF | APIC_INT_ASSERT | + APIC_DM_FIXED | PMI_VECTOR); + pmi_irq_called = false; +} + +static void guest_test_gp_counter_pmi(void) +{ + uint8_t guest_pmu_version = guest_get_pmu_version(); + uint32_t base_msr = get_pmc_msr(); + + test_pmi_init_x2apic(); + + wrmsr(base_msr, + (1ULL << this_cpu_property(X86_PROPERTY_PMU_GP_COUNTERS_BIT_WIDTH)) - 2); + wrmsr(MSR_P6_EVNTSEL0, ARCH_PERFMON_EVENTSEL_OS | + ARCH_PERFMON_EVENTSEL_ENABLE | ARCH_PERFMON_EVENTSEL_INT | + INTEL_ARCH_CPU_CYCLES); + + if (guest_pmu_version >= 2) + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, BIT_ULL(0)); + guest_test_counters_pmi_workload(); + + GUEST_ASSERT(pmi_irq_called); + GUEST_DONE(); +} + +static void test_intel_ovf_pmi(uint8_t pmu_version, uint64_t perf_capabilities) +{ + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + + if (!pmu_version) + return; + + vm = intel_pmu_vm_create(&vcpu, guest_test_gp_counter_pmi, pmu_version, + perf_capabilities); + + vm_install_exception_handler(vm, PMI_VECTOR, pmi_irq_handler); + run_vcpu(vcpu); + + kvm_vm_free(vm); +} + static void test_intel_counters(void) { uint8_t nr_arch_events = kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); @@ -596,6 +669,8 @@ static void test_intel_counters(void) for (k = 0; k <= (BIT(nr_fixed_counters) - 1); k++) test_fixed_counters(v, perf_caps[i], j, k); } + + test_intel_ovf_pmi(v, perf_caps[i]); } } } From patchwork Tue Nov 21 11:54:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jinrong Liang X-Patchwork-Id: 13462908 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="JcyGLbpb" Received: from mail-pf1-x443.google.com (mail-pf1-x443.google.com [IPv6:2607:f8b0:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B74B1112; Tue, 21 Nov 2023 03:55:40 -0800 (PST) Received: by mail-pf1-x443.google.com with SMTP id d2e1a72fcca58-6bee11456baso4596584b3a.1; Tue, 21 Nov 2023 03:55:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700567740; x=1701172540; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; 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Tue, 21 Nov 2023 03:55:40 -0800 (PST) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id g10-20020a170902740a00b001cc1dff5b86sm7685431pll.244.2023.11.21.03.55.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 03:55:39 -0800 (PST) From: Jinrong Liang X-Google-Original-From: Jinrong Liang To: Sean Christopherson Cc: Paolo Bonzini , Like Xu , Jim Mattson , Aaron Lewis , Wanpeng Li , Jinrong Liang , Jinrong Liang , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/9] KVM: selftests: Test fixed counters overflow interrupt handling Date: Tue, 21 Nov 2023 19:54:51 +0800 Message-Id: <20231121115457.76269-4-cloudliang@tencent.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231121115457.76269-1-cloudliang@tencent.com> References: <20231121115457.76269-1-cloudliang@tencent.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Jinrong Liang Add tests to verify that fixed counters overflow interrupt handling works as expected. Signed-off-by: Jinrong Liang --- .../selftests/kvm/x86_64/pmu_counters_test.c | 32 +++++++++++++++++-- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c index 1b108e6718fc..efd8c61e1c16 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -551,9 +551,8 @@ static void test_pmi_init_x2apic(void) pmi_irq_called = false; } -static void guest_test_gp_counter_pmi(void) +static void guest_test_gp_counter_pmi(uint8_t guest_pmu_version) { - uint8_t guest_pmu_version = guest_get_pmu_version(); uint32_t base_msr = get_pmc_msr(); test_pmi_init_x2apic(); @@ -569,6 +568,33 @@ static void guest_test_gp_counter_pmi(void) guest_test_counters_pmi_workload(); GUEST_ASSERT(pmi_irq_called); +} + +static void guest_test_fixed_counter_pmi(uint8_t guest_pmu_version) +{ + if (guest_pmu_version < 2) + return; + + test_pmi_init_x2apic(); + + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0); + wrmsr(MSR_CORE_PERF_FIXED_CTR0, + (1ULL << this_cpu_property(X86_PROPERTY_PMU_FIXED_COUNTERS_BIT_WIDTH)) - 2); + wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, FIXED_PMC_CTRL(0, FIXED_PMC_ENABLE_PMI)); + + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, FIXED_PMC_GLOBAL_CTRL_ENABLE(0)); + guest_test_counters_pmi_workload(); + + GUEST_ASSERT(pmi_irq_called); +} + +static void guest_test_counters_pmi(void) +{ + uint8_t guest_pmu_version = guest_get_pmu_version(); + + guest_test_gp_counter_pmi(guest_pmu_version); + guest_test_fixed_counter_pmi(guest_pmu_version); + GUEST_DONE(); } @@ -580,7 +606,7 @@ static void test_intel_ovf_pmi(uint8_t pmu_version, uint64_t perf_capabilities) if (!pmu_version) return; - vm = intel_pmu_vm_create(&vcpu, guest_test_gp_counter_pmi, pmu_version, + vm = intel_pmu_vm_create(&vcpu, guest_test_counters_pmi, pmu_version, perf_capabilities); vm_install_exception_handler(vm, PMI_VECTOR, pmi_irq_handler); From patchwork Tue Nov 21 11:54:52 2023 Content-Type: text/plain; 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Tue, 21 Nov 2023 03:55:42 -0800 (PST) From: Jinrong Liang X-Google-Original-From: Jinrong Liang To: Sean Christopherson Cc: Paolo Bonzini , Like Xu , Jim Mattson , Aaron Lewis , Wanpeng Li , Jinrong Liang , Jinrong Liang , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/9] KVM: selftests: Add x86 feature and properties for AMD PMU in processor.h Date: Tue, 21 Nov 2023 19:54:52 +0800 Message-Id: <20231121115457.76269-5-cloudliang@tencent.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231121115457.76269-1-cloudliang@tencent.com> References: <20231121115457.76269-1-cloudliang@tencent.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Jinrong Liang Add x86 feature and properties for AMD PMU so that tests don't have to manually retrieve the correct CPUID leaf+register, and so that the resulting code is self-documenting. Signed-off-by: Jinrong Liang --- tools/testing/selftests/kvm/include/x86_64/processor.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools/testing/selftests/kvm/include/x86_64/processor.h index ba16d714b451..250ace4f14b8 100644 --- a/tools/testing/selftests/kvm/include/x86_64/processor.h +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h @@ -176,6 +176,7 @@ struct kvm_x86_cpu_feature { * Extended Leafs, a.k.a. AMD defined */ #define X86_FEATURE_SVM KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 2) +#define X86_FEATURE_PERFCTR_CORE KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 23) #define X86_FEATURE_NX KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 20) #define X86_FEATURE_GBPAGES KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 26) #define X86_FEATURE_RDTSCP KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 27) @@ -192,6 +193,7 @@ struct kvm_x86_cpu_feature { #define X86_FEATURE_VGIF KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 16) #define X86_FEATURE_SEV KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 1) #define X86_FEATURE_SEV_ES KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 3) +#define X86_FEATURE_PERFMON_V2 KVM_X86_CPU_FEATURE(0x80000022, 0, EAX, 0) /* * KVM defined paravirt features. @@ -276,6 +278,7 @@ struct kvm_x86_cpu_property { #define X86_PROPERTY_MAX_PHY_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 0, 7) #define X86_PROPERTY_MAX_VIRT_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 8, 15) #define X86_PROPERTY_PHYS_ADDR_REDUCTION KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 6, 11) +#define X86_PROPERTY_PMU_NR_CORE_COUNTERS KVM_X86_CPU_PROPERTY(0x80000022, 0, EBX, 0, 3) #define X86_PROPERTY_MAX_CENTAUR_LEAF KVM_X86_CPU_PROPERTY(0xC0000000, 0, EAX, 0, 31) From patchwork Tue Nov 21 11:54:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jinrong Liang X-Patchwork-Id: 13462910 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="QjzyWU5+" Received: from mail-pl1-x644.google.com (mail-pl1-x644.google.com [IPv6:2607:f8b0:4864:20::644]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E81B0116; Tue, 21 Nov 2023 03:55:45 -0800 (PST) Received: by mail-pl1-x644.google.com with SMTP id d9443c01a7336-1cc2fc281cdso37520715ad.0; Tue, 21 Nov 2023 03:55:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700567745; x=1701172545; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3a2UvIVQOk+mF3Xt68Og+a1lPhUsU3gq66oL0/Q5kAA=; b=QjzyWU5+MxfF4KYTSMxHf5c+ZuFlhh6pPNVn3/c6V7Qwqr7U03APmCXtJ28E7AnlGe p+PglQ343HBhq3OFRjc5c5tUu58uKuzFdQ16KLpPcr4ASCzdxiy3IDNlCsPQaq/cmKlS HJ5EeC6cdO9BnbIbWn9A3kyzpzGE7MpsTVHlPvV8/J6geEw9m+rJ2E2GvecvLKzFCVr5 nr8k+IbJM9JhzzDeGnZLGXZDkABBY7KGJtdipwj2bI+dyR4VeBwwQgbRdPITIqXxxZcg LWPGnCGq7cHj8WRFeFSouiveSQ7344IYpdwCi7q+N/rnzkejC6QQQdZS7F5F1qw29bYj 1qdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700567745; x=1701172545; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3a2UvIVQOk+mF3Xt68Og+a1lPhUsU3gq66oL0/Q5kAA=; b=iO+RnDPIYlqOgt66sWRP7jgE4g/dudvZG3zvFAlQDrZpt4L0wwmT82j4bYDPT6aBuS 2OPpCQDOOYNvezcfvUKYd4Rk+gmD0RwzqfuluL/tWG3a+qfdrTEU8BO2OqqlpiF5MJUg VtFjF0Vn62IrxdC3iRU7tDJc+kGCQqiiMIHmbK4tR93pY00BpXVMUlzvQH4WWQzWBs2C OiBlZzm1uGWtRYuCP7bdmJ98kUigMWgwWJBZTNHbcJ5KlcuVoMD30dxcvJvo2NWBVLiV T1jxuhJ/7Tdmv8Q0yLZCtjwEreE0sn+jpjRiHbCkDQHjX5q6Bz4j+3JflN64IDJEAfd8 uVcw== X-Gm-Message-State: AOJu0YxAXCrPsj7e3lAlYJtnn2Y+y8REtNpFPEHYjv7maBTScpm67WB5 wMm4FzMDG/B/AqaTiyPqE0I= X-Google-Smtp-Source: AGHT+IEvjwRCdgy6JMsMIrf6Jl2kRTZG+1NXXxiUW0DHGSnPybpc3msHxuLOBkKWBSZ20tIb83ANqg== X-Received: by 2002:a17:902:db02:b0:1cf:5cb5:95bf with SMTP id m2-20020a170902db0200b001cf5cb595bfmr6363181plx.45.1700567745403; Tue, 21 Nov 2023 03:55:45 -0800 (PST) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id g10-20020a170902740a00b001cc1dff5b86sm7685431pll.244.2023.11.21.03.55.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 03:55:45 -0800 (PST) From: Jinrong Liang X-Google-Original-From: Jinrong Liang To: Sean Christopherson Cc: Paolo Bonzini , Like Xu , Jim Mattson , Aaron Lewis , Wanpeng Li , Jinrong Liang , Jinrong Liang , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/9] KVM: selftests: Test AMD PMU performance counters basic functions Date: Tue, 21 Nov 2023 19:54:53 +0800 Message-Id: <20231121115457.76269-6-cloudliang@tencent.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231121115457.76269-1-cloudliang@tencent.com> References: <20231121115457.76269-1-cloudliang@tencent.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Jinrong Liang Add tests to check AMD PMU performance counters basic functions. Signed-off-by: Jinrong Liang --- .../selftests/kvm/x86_64/pmu_counters_test.c | 84 +++++++++++++++++-- 1 file changed, 75 insertions(+), 9 deletions(-) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c index efd8c61e1c16..3c4081a508b0 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -21,6 +21,8 @@ #define NUM_INSNS_RETIRED (NUM_BRANCHES + NUM_EXTRA_INSNS) #define PMI_VECTOR 0x20 +#define AMD64_NR_COUNTERS 4 +#define AMD64_NR_COUNTERS_CORE 6 static uint8_t kvm_pmu_version; static bool kvm_has_perf_caps; @@ -411,7 +413,6 @@ static void guest_rd_wr_counters(uint32_t base_msr, uint8_t nr_possible_counters rdpmc_idx = i; if (base_msr == MSR_CORE_PERF_FIXED_CTR0) rdpmc_idx |= INTEL_RDPMC_FIXED; - guest_test_rdpmc(rdpmc_idx, expect_success, expected_val); /* @@ -421,7 +422,6 @@ static void guest_rd_wr_counters(uint32_t base_msr, uint8_t nr_possible_counters */ GUEST_ASSERT(!expect_success || !pmu_has_fast_mode); rdpmc_idx |= INTEL_RDPMC_FAST; - guest_test_rdpmc(rdpmc_idx, false, -1ull); vector = wrmsr_safe(msr, 0); @@ -701,19 +701,85 @@ static void test_intel_counters(void) } } +static void set_amd_counters(uint8_t *nr_amd_ounters, uint64_t *ctrl_msr, + uint32_t *pmc_msr, uint8_t *flag) +{ + if (this_cpu_has(X86_FEATURE_PERFMON_V2)) { + *nr_amd_ounters = this_cpu_property(X86_PROPERTY_PMU_NR_CORE_COUNTERS); + *ctrl_msr = MSR_F15H_PERF_CTL0; + *pmc_msr = MSR_F15H_PERF_CTR0; + *flag = 2; + } else if (this_cpu_has(X86_FEATURE_PERFCTR_CORE)) { + *nr_amd_ounters = AMD64_NR_COUNTERS_CORE; + *ctrl_msr = MSR_F15H_PERF_CTL0; + *pmc_msr = MSR_F15H_PERF_CTR0; + *flag = 2; + } else { + *nr_amd_ounters = AMD64_NR_COUNTERS; + *ctrl_msr = MSR_K7_EVNTSEL0; + *pmc_msr = MSR_K7_PERFCTR0; + *flag = 1; + } +} + +static void guest_test_amd_counters(void) +{ + bool guest_pmu_is_perfmonv2 = this_cpu_has(X86_FEATURE_PERFMON_V2); + uint8_t nr_amd_counters, flag; + uint64_t ctrl_msr; + unsigned int i, j; + uint32_t pmc_msr; + + set_amd_counters(&nr_amd_counters, &ctrl_msr, &pmc_msr, &flag); + + for (i = 0; i < nr_amd_counters; i++) { + for (j = 0; j < NR_AMD_ZEN_EVENTS; j++) { + wrmsr(pmc_msr + i * flag, 0); + wrmsr(ctrl_msr + i * flag, ARCH_PERFMON_EVENTSEL_OS | + ARCH_PERFMON_EVENTSEL_ENABLE | amd_pmu_zen_events[j]); + + if (guest_pmu_is_perfmonv2) + wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, BIT_ULL(i)); + + __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES})); + + GUEST_ASSERT(rdmsr(pmc_msr + i * flag)); + } + } + + GUEST_DONE(); +} + +static void test_amd_zen_events(void) +{ + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + + vm = pmu_vm_create_with_one_vcpu(&vcpu, guest_test_amd_counters); + + run_vcpu(vcpu); + kvm_vm_free(vm); +} + int main(int argc, char *argv[]) { TEST_REQUIRE(kvm_is_pmu_enabled()); - TEST_REQUIRE(host_cpu_is_intel); - TEST_REQUIRE(kvm_cpu_has_p(X86_PROPERTY_PMU_VERSION)); - TEST_REQUIRE(kvm_cpu_property(X86_PROPERTY_PMU_VERSION) > 0); + if (host_cpu_is_intel) { + TEST_REQUIRE(kvm_cpu_has_p(X86_PROPERTY_PMU_VERSION)); + TEST_REQUIRE(kvm_cpu_property(X86_PROPERTY_PMU_VERSION) > 0); + TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_PDCM)); - kvm_pmu_version = kvm_cpu_property(X86_PROPERTY_PMU_VERSION); - kvm_has_perf_caps = kvm_cpu_has(X86_FEATURE_PDCM); - is_forced_emulation_enabled = kvm_is_forced_emulation_enabled(); + kvm_pmu_version = kvm_cpu_property(X86_PROPERTY_PMU_VERSION); + kvm_has_perf_caps = kvm_cpu_has(X86_FEATURE_PDCM); + is_forced_emulation_enabled = kvm_is_forced_emulation_enabled(); - test_intel_counters(); + test_intel_counters(); + } else if (host_cpu_is_amd) { + test_amd_zen_events(); + } else { + TEST_FAIL("Unknown CPU vendor"); + } return 0; } From patchwork Tue Nov 21 11:54:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jinrong Liang X-Patchwork-Id: 13462911 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="X1yef7wm" Received: from mail-pl1-x644.google.com (mail-pl1-x644.google.com [IPv6:2607:f8b0:4864:20::644]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 907E0112; 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Nor will KVM emulate more counters than it can support. Signed-off-by: Jinrong Liang --- .../selftests/kvm/x86_64/pmu_counters_test.c | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c index 3c4081a508b0..b1502a446a55 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -761,6 +761,64 @@ static void test_amd_zen_events(void) kvm_vm_free(vm); } +static void guest_wr_rd_amd_counters(uint32_t pmc_msr, bool expect_gp, + uint64_t test_val) +{ + uint8_t vector; + uint64_t val; + + vector = wrmsr_safe(pmc_msr, test_val); + GUEST_ASSERT_PMC_MSR_ACCESS(WRMSR, pmc_msr, expect_gp, vector); + + vector = rdmsr_safe(pmc_msr, &val); + GUEST_ASSERT_PMC_MSR_ACCESS(RDMSR, pmc_msr, expect_gp, vector); + + if (!expect_gp) + GUEST_ASSERT_EQ(val, test_val); +} + +static void guest_test_amd_counters_num(void) +{ + uint8_t i, flag, nr_amd_counters; + uint64_t ctrl_msr; + uint32_t pmc_msr; + bool expect_gp; + + set_amd_counters(&nr_amd_counters, &ctrl_msr, &pmc_msr, &flag); + + for (i = 0; i < nr_amd_counters * flag; i++) { + expect_gp = i >= nr_amd_counters; + + guest_wr_rd_amd_counters(pmc_msr + i * flag, expect_gp, 0xffff); + guest_wr_rd_amd_counters(ctrl_msr + i * flag, expect_gp, 0); + } + + GUEST_DONE(); +} + +static void test_amd_counters_num(void) +{ + bool kvm_pmu_is_perfmonv2 = kvm_cpu_has(X86_FEATURE_PERFMON_V2); + unsigned int i, nr_test = 1; + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + + if (kvm_pmu_is_perfmonv2) + nr_test = AMD64_NR_COUNTERS_CORE; + + for (i = 0; i <= nr_test; i++) { + vm = pmu_vm_create_with_one_vcpu(&vcpu, + guest_test_amd_counters_num); + + if (kvm_pmu_is_perfmonv2) + vcpu_set_cpuid_property(vcpu, + X86_PROPERTY_PMU_NR_CORE_COUNTERS, i); + + run_vcpu(vcpu); + kvm_vm_free(vm); + } +} + int main(int argc, char *argv[]) { TEST_REQUIRE(kvm_is_pmu_enabled()); @@ -777,6 +835,7 @@ int main(int argc, char *argv[]) test_intel_counters(); } else if (host_cpu_is_amd) { test_amd_zen_events(); + test_amd_counters_num(); } else { TEST_FAIL("Unknown CPU vendor"); } From patchwork Tue Nov 21 11:54:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jinrong Liang X-Patchwork-Id: 13462912 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="dBczypLP" Received: from mail-pl1-x641.google.com (mail-pl1-x641.google.com [IPv6:2607:f8b0:4864:20::641]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A1B5123; Tue, 21 Nov 2023 03:55:51 -0800 (PST) Received: by mail-pl1-x641.google.com with SMTP id d9443c01a7336-1cf62a3b249so13031055ad.0; Tue, 21 Nov 2023 03:55:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700567751; x=1701172551; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; 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Tue, 21 Nov 2023 03:55:50 -0800 (PST) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id g10-20020a170902740a00b001cc1dff5b86sm7685431pll.244.2023.11.21.03.55.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 03:55:50 -0800 (PST) From: Jinrong Liang X-Google-Original-From: Jinrong Liang To: Sean Christopherson Cc: Paolo Bonzini , Like Xu , Jim Mattson , Aaron Lewis , Wanpeng Li , Jinrong Liang , Jinrong Liang , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/9] KVM: selftests: Test consistency of PMU MSRs with AMD PMU version Date: Tue, 21 Nov 2023 19:54:55 +0800 Message-Id: <20231121115457.76269-8-cloudliang@tencent.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231121115457.76269-1-cloudliang@tencent.com> References: <20231121115457.76269-1-cloudliang@tencent.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Jinrong Liang Add AMD test case to check that KVM accurately accesses the MSRs supported by the AMD PMU version. Signed-off-by: Jinrong Liang --- .../selftests/kvm/x86_64/pmu_counters_test.c | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c index b1502a446a55..07cb9694e225 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -819,6 +819,50 @@ static void test_amd_counters_num(void) } } +static void guest_test_amd_pmu_version(void) +{ + bool expect_gp = !this_cpu_has(X86_FEATURE_PERFMON_V2); + uint8_t vector; + uint64_t val; + + guest_wr_rd_amd_counters(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, + expect_gp, 0); + guest_wr_rd_amd_counters(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, + expect_gp, 0); + + /* + * Attempt to write to MSR_AMD64_PERF_CNTR_GLOBAL_STATUS register, which + * will trigger a #GP exception. Because MSR_AMD64_PERF_CNTR_GLOBAL_STATUS + * is read-only. + */ + vector = wrmsr_safe(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, 0); + GUEST_ASSERT_PMC_MSR_ACCESS(WRMSR, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, + true, vector); + + vector = rdmsr_safe(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, &val); + GUEST_ASSERT_PMC_MSR_ACCESS(RDMSR, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, + expect_gp, vector); + + GUEST_DONE(); +} + +static void test_amd_pmu_version(void) +{ + bool kvm_pmu_is_perfmonv2 = kvm_cpu_has(X86_FEATURE_PERFMON_V2); + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + unsigned int i; + + for (i = 0; i <= kvm_pmu_is_perfmonv2; i++) { + vm = pmu_vm_create_with_one_vcpu(&vcpu, guest_test_amd_pmu_version); + + vcpu_set_or_clear_cpuid_feature(vcpu, X86_FEATURE_PERFMON_V2, i); + + run_vcpu(vcpu); + kvm_vm_free(vm); + } +} + int main(int argc, char *argv[]) { TEST_REQUIRE(kvm_is_pmu_enabled()); @@ -836,6 +880,7 @@ int main(int argc, char *argv[]) } else if (host_cpu_is_amd) { test_amd_zen_events(); test_amd_counters_num(); + test_amd_pmu_version(); } else { TEST_FAIL("Unknown CPU vendor"); } From patchwork Tue Nov 21 11:54:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jinrong Liang X-Patchwork-Id: 13462913 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Qm1AT+aP" Received: from mail-pl1-x641.google.com (mail-pl1-x641.google.com [IPv6:2607:f8b0:4864:20::641]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E1838123; Tue, 21 Nov 2023 03:55:53 -0800 (PST) Received: by mail-pl1-x641.google.com with SMTP id d9443c01a7336-1cf5901b4c8so21522915ad.1; Tue, 21 Nov 2023 03:55:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700567753; x=1701172553; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZtftiOzjpf70P5oevOX6XZZCHaAm7J3EtiuJv1/+VvA=; b=Qm1AT+aPqLX7p1TgcTgzbWKQ/pOBlQTM0zaHKYZ7UxcdmVQia044wKWQFtAAd037y7 ZMch7ujaVV5dP4J6DG7R744rjMP/BHDDK3LYOVXc/uYIkQJxWtQb2HUfWTCcRL+2Er+v 4tXLApM5mv9EzRecwxBxymxGbXSJfP8mmP4M3vNQeTKsFlfgmpLBmcYxyiRpcmDlraWw HXzk4WLf2L7lIb+IC1o1ciVivUYMcIrLp9/1XlenXuqakN/zU4E6CPHYdV5HHNwdXbDV ec3427YMtgY79JuCf18o5xSRxJLFFPxJbY/KYQMkMX7LCBzvgIgwQQLgQj4Slk1iaMRL CKYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700567753; x=1701172553; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZtftiOzjpf70P5oevOX6XZZCHaAm7J3EtiuJv1/+VvA=; b=qXiE5UpC8hcFw6iTsGUDaUbZNEsDTtMo6g7wxblFy3iUtf4aFFUtp/W3HhhN3o8pyq UeN3Sbh15giGyhuyPg6Fp249p5VJ0xsWwr8uI67BDofsHMkDwzd3HLw4XYp10GnKggMd h9wbc82AQI0TUnwjmVlu1qNUg4REkrahw+bU0OLSQiqh8pdVMhOMRj4wKEORDuGAg4WJ F5T03JyouJFw+4NB+Q6rUvxCfR/CdDBeT1Ul1UjSkP4mDqSv0LondGj2eDGWRtUU2AJR 7Q/ak6JpUtKpjU7Tl7axtHW+bSFGd1uCw8xEo58vBSG3cOHIB+XI+8uo4IKYORKb8l36 GHxg== X-Gm-Message-State: AOJu0YysVdUqSSiCBjlX8HM7k0kO5E8x7IHYOD+1Zr8/hGFfpkZSIYTm 9DWFWaeYlA4xePiiU/xfKCI= X-Google-Smtp-Source: AGHT+IE1b6bIYK6eqr41otZww4GK+zX5EHlGcethonC2GP2y7PIZJt3ciJynJJiNd0GEaVazWNbg5A== X-Received: by 2002:a17:903:2350:b0:1cf:6ce6:5f22 with SMTP id c16-20020a170903235000b001cf6ce65f22mr2426187plh.60.1700567753338; Tue, 21 Nov 2023 03:55:53 -0800 (PST) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id g10-20020a170902740a00b001cc1dff5b86sm7685431pll.244.2023.11.21.03.55.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 03:55:53 -0800 (PST) From: Jinrong Liang X-Google-Original-From: Jinrong Liang To: Sean Christopherson Cc: Paolo Bonzini , Like Xu , Jim Mattson , Aaron Lewis , Wanpeng Li , Jinrong Liang , Jinrong Liang , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 8/9] KVM: selftests: Test AMD Guest PerfCtrExtCore Date: Tue, 21 Nov 2023 19:54:56 +0800 Message-Id: <20231121115457.76269-9-cloudliang@tencent.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231121115457.76269-1-cloudliang@tencent.com> References: <20231121115457.76269-1-cloudliang@tencent.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Jinrong Liang Add test case for AMD Guest PerfCtrExtCore. Signed-off-by: Jinrong Liang --- .../selftests/kvm/x86_64/pmu_counters_test.c | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c index 07cb9694e225..ca5b352ea6ae 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -863,6 +863,36 @@ static void test_amd_pmu_version(void) } } +static void guest_test_perfctr_core(void) +{ + bool expect_gp = !this_cpu_has(X86_FEATURE_PERFCTR_CORE); + unsigned int i; + + for (i = 0; i < AMD64_NR_COUNTERS_CORE; i++) { + guest_wr_rd_amd_counters(MSR_F15H_PERF_CTR0 + i * 2, expect_gp, 0xffff); + guest_wr_rd_amd_counters(MSR_F15H_PERF_CTL0 + i * 2, expect_gp, 0); + } + + GUEST_DONE(); +} + +static void test_amd_perfctr_core(void) +{ + bool kvm_pmu_has_perfctr_core = kvm_cpu_has(X86_FEATURE_PERFCTR_CORE); + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + unsigned int i; + + for (i = 0; i <= kvm_pmu_has_perfctr_core; i++) { + vm = pmu_vm_create_with_one_vcpu(&vcpu, guest_test_perfctr_core); + + vcpu_set_or_clear_cpuid_feature(vcpu, X86_FEATURE_PERFCTR_CORE, i); + + run_vcpu(vcpu); + kvm_vm_free(vm); + } +} + int main(int argc, char *argv[]) { TEST_REQUIRE(kvm_is_pmu_enabled()); @@ -881,6 +911,7 @@ int main(int argc, char *argv[]) test_amd_zen_events(); test_amd_counters_num(); test_amd_pmu_version(); + test_amd_perfctr_core(); } else { TEST_FAIL("Unknown CPU vendor"); } From patchwork Tue Nov 21 11:54:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jinrong Liang X-Patchwork-Id: 13462914 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="IiVajqij" Received: from mail-pf1-x442.google.com (mail-pf1-x442.google.com [IPv6:2607:f8b0:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E4F5112; Tue, 21 Nov 2023 03:55:56 -0800 (PST) Received: by mail-pf1-x442.google.com with SMTP id d2e1a72fcca58-6c34e87b571so4378434b3a.3; Tue, 21 Nov 2023 03:55:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700567756; x=1701172556; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dOxT43FDAQ5Xr6ouV6ennVtlCzo8xO0nJHSFrJt6nz4=; b=IiVajqij9UsYMMk6Oje17e96U1r4I6l3nsFCYF0apFiNfDb2iGPB8Z2T51iV6tuV6R lHQJH+TnZGeDtqh69sVN/QD7yYSQQtd9gjAWK1Bwk4rVHrtwp0q44SOp28gyaAVLZ02V ThhbWwol0acelCHY3kkJRAujF/Al1QShCddgidYNn93Mnk9wRmMwercan+7IWtsSeH4U acxo33Brr3LF8y7h/8i6GxRvOZZf+X7huq0kCpfsB4zPoO95vNhZI98oAvD7cwmQ8C3b gTFOoxCFPznic2no255GoYRng9/uJFzpqHI8Z4VRDR5qzgJYLoqvjo0lQdpr+ZqR+oLd ZHPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700567756; x=1701172556; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dOxT43FDAQ5Xr6ouV6ennVtlCzo8xO0nJHSFrJt6nz4=; b=n5mzJhwkHc2yGjkP+mWq+vlS1TsblBsLccrML9z3TWtSegjwJm0Fipu0c2naPLnj07 eW8bhrgvDJpwM/2yUDh+nW2bv04wilWQjOEBKJ1M/p63aobJXLk+UMRymZRypReJ9gm0 bfQDThcmMZ9u3zNOUUQSqKewrbxjF+tG4Eo1D3OTULtpghH3NJCZ2Dz7xvc+savjujCb 3NTw3s+XXc+Uqu+aEMmFBY2sLNL8S1rG8ideQiXkLDHj8o3XES8yl7G2bqqoth3S/ExT ZAAPnEXUf1yRfR8tPKsMMWsDuFlCTCgEeMRmRP+kK+5s5xUHsnMnnG9L7ZiMqNyPyPkQ 9Gww== X-Gm-Message-State: AOJu0YzmVvKkHCUFrycpBMVltcT3tn4NbidBAxeLI5wpRZ3FbvEkWyvY rOrliIP7V7NurG4/gfGpHO4= X-Google-Smtp-Source: AGHT+IFghql4Rbf15JDxeEuYt95Vz/RngIzBoF2uPGTDd8wm25ZtSEbNG//EtMwT/wDjrcARhRrgBg== X-Received: by 2002:a05:6a20:9f89:b0:187:f549:e2e7 with SMTP id mm9-20020a056a209f8900b00187f549e2e7mr11003353pzb.7.1700567756010; Tue, 21 Nov 2023 03:55:56 -0800 (PST) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id g10-20020a170902740a00b001cc1dff5b86sm7685431pll.244.2023.11.21.03.55.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 03:55:55 -0800 (PST) From: Jinrong Liang X-Google-Original-From: Jinrong Liang To: Sean Christopherson Cc: Paolo Bonzini , Like Xu , Jim Mattson , Aaron Lewis , Wanpeng Li , Jinrong Liang , Jinrong Liang , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 9/9] KVM: selftests: Test AMD Guest PerfMonV2 Date: Tue, 21 Nov 2023 19:54:57 +0800 Message-Id: <20231121115457.76269-10-cloudliang@tencent.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231121115457.76269-1-cloudliang@tencent.com> References: <20231121115457.76269-1-cloudliang@tencent.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Jinrong Liang Add test case for AMD Guest PerfMonV2. Signed-off-by: Jinrong Liang --- .../selftests/kvm/x86_64/pmu_counters_test.c | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c index ca5b352ea6ae..aa44f2282996 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -722,6 +722,38 @@ static void set_amd_counters(uint8_t *nr_amd_ounters, uint64_t *ctrl_msr, } } +static void guest_test_amd_perfmonv2(void) +{ + unsigned int i; + + for (i = 0; i < AMD64_NR_COUNTERS_CORE; i++) { + wrmsr(MSR_F15H_PERF_CTL0 + i * 2, 0); + wrmsr(MSR_F15H_PERF_CTR0 + i * 2, ARCH_PERFMON_EVENTSEL_OS | + ARCH_PERFMON_EVENTSEL_ENABLE | AMD_ZEN_CORE_CYCLES); + + wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0); + __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES})); + GUEST_ASSERT(!_rdpmc(i)); + + wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, BIT_ULL(i)); + __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES})); + wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0); + GUEST_ASSERT(_rdpmc(i)); + + wrmsr(MSR_F15H_PERF_CTL0 + i * 2, (1ULL << 48) - 2); + wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, 0xff); + wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, BIT_ULL(i)); + __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES})); + wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0); + GUEST_ASSERT(rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS) & + BIT_ULL(i)); + + wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, BIT_ULL(i)); + GUEST_ASSERT(!(rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS) & + BIT_ULL(i))); + } +} + static void guest_test_amd_counters(void) { bool guest_pmu_is_perfmonv2 = this_cpu_has(X86_FEATURE_PERFMON_V2); @@ -747,6 +779,9 @@ static void guest_test_amd_counters(void) } } + if (guest_pmu_is_perfmonv2) + guest_test_amd_perfmonv2(); + GUEST_DONE(); }