From patchwork Tue Nov 21 14:30:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13463271 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ASCU4lH8" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB25190; Tue, 21 Nov 2023 06:31:23 -0800 (PST) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3ALE2DS0003250; Tue, 21 Nov 2023 14:31:14 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=gqI+CxuXvB2nck6peTPOubE2SjCZOAUdVyrGTve6okI=; b=ASCU4lH8yIdXTbYQu9gUAcScKEnrCLM4rRh1FRFoOo1Z2M/QeWvKhmfmMav1bLfbtwsp Bh2FqxWnZBtx7jdg/um26w+U9wHR1hbZJcyd+rt5bi+36DJkYHJXRRQ3oe9qHWm/Qj4f 8XwUPEYtKpEygUFHunwMKfh+HxCq9jsPkpFyvCfeDrl0K/BefShzrPNjL8uUcZov70FK BeI0B7yATUtbc/4fEthuVvE8BnGEkPznSqruY+VyVI1kgeEtxdJ1dlm/pf5MbCacGIjl QjpzNfmmqXGUlWBoLTMz1GN42ji+u1nHSWcMHiQDtokFWC7y6oqmAMjQcDOaOHxPid1P zg== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ugu548vpc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 21 Nov 2023 14:31:13 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3ALEVCrL007741 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 21 Nov 2023 14:31:12 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 21 Nov 2023 06:31:07 -0800 From: Kathiravan Thirumoorthy Date: Tue, 21 Nov 2023 20:00:43 +0530 Subject: [PATCH v2 1/9] clk: qcom: ipq5332: add const qualifier to the clk_init_data structure Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20231121-ipq5332-nsscc-v2-1-a7ff61beab72@quicinc.com> References: <20231121-ipq5332-nsscc-v2-0-a7ff61beab72@quicinc.com> In-Reply-To: <20231121-ipq5332-nsscc-v2-0-a7ff61beab72@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Catalin Marinas , Will Deacon CC: , , , , , , "Kathiravan Thirumoorthy" X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1700577061; l=7721; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=+0Hvf6odeN5BU615J2c1Ow0cnXHABxgNEO32lQZZoLs=; b=KfY7rf2rGZK5HvUMmizxYsSIwSMJYnC5mNJWiiMuF7R+EVmScAvyHr9w/HDHXXhqbA0uEv6wO Y6JZRsYsONaBll4VkGlCMcO4lFjgdmnZXzOq4lzlxoWc8qjYLJnHDcg X-Developer-Key: i=quic_kathirav@quicinc.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: kJM-JN6_YoKioih57Q8O9WWiQm-QurjI X-Proofpoint-ORIG-GUID: kJM-JN6_YoKioih57Q8O9WWiQm-QurjI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-21_05,2023-11-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 bulkscore=0 phishscore=0 impostorscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 mlxlogscore=900 adultscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311210113 There are few places where clk_init_data structure doesn't carry the const qualifier. Let's add the same. Signed-off-by: Kathiravan Thirumoorthy Acked-by: Konrad Dybcio --- Changes in V2: - New patch --- drivers/clk/qcom/gcc-ipq5332.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c index f98591148a97..66d5399798fe 100644 --- a/drivers/clk/qcom/gcc-ipq5332.c +++ b/drivers/clk/qcom/gcc-ipq5332.c @@ -65,7 +65,7 @@ static struct clk_alpha_pll gpll0_main = { static struct clk_fixed_factor gpll0_div2 = { .mult = 1, .div = 2, - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gpll0_div2", .parent_hws = (const struct clk_hw *[]) { &gpll0_main.clkr.hw }, @@ -78,7 +78,7 @@ static struct clk_alpha_pll_postdiv gpll0 = { .offset = 0x20000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], .width = 4, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "gpll0", .parent_hws = (const struct clk_hw *[]) { &gpll0_main.clkr.hw }, @@ -106,7 +106,7 @@ static struct clk_alpha_pll_postdiv gpll2 = { .offset = 0x21000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], .width = 4, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "gpll2_main", .parent_hws = (const struct clk_hw *[]) { &gpll2_main.clkr.hw }, @@ -145,7 +145,7 @@ static struct clk_alpha_pll_postdiv gpll4 = { .offset = 0x22000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], .width = 4, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "gpll4", .parent_hws = (const struct clk_hw *[]) { &gpll4_main.clkr.hw }, @@ -572,7 +572,7 @@ static struct clk_branch gcc_pcie3x1_0_rchg_clk = { .clkr = { .enable_reg = 0x2907c, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie3x1_0_rchg_clk", .parent_hws = (const struct clk_hw *[]) { &gcc_pcie3x1_0_rchg_clk_src.clkr.hw }, @@ -615,7 +615,7 @@ static struct clk_branch gcc_pcie3x1_1_rchg_clk = { .clkr = { .enable_reg = 0x2a078, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie3x1_1_rchg_clk", .parent_hws = (const struct clk_hw *[]) { &gcc_pcie3x1_1_rchg_clk_src.clkr.hw }, @@ -678,7 +678,7 @@ static struct clk_branch gcc_pcie3x2_rchg_clk = { .clkr = { .enable_reg = 0x28078, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie3x2_rchg_clk", .parent_hws = (const struct clk_hw *[]) { &gcc_pcie3x2_rchg_clk_src.clkr.hw }, @@ -711,7 +711,7 @@ static struct clk_rcg2 gcc_pcie_aux_clk_src = { static struct clk_regmap_phy_mux gcc_pcie3x2_pipe_clk_src = { .reg = 0x28064, .clkr = { - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie3x2_pipe_clk_src", .parent_data = &(const struct clk_parent_data) { .index = DT_PCIE_2LANE_PHY_PIPE_CLK, @@ -725,7 +725,7 @@ static struct clk_regmap_phy_mux gcc_pcie3x2_pipe_clk_src = { static struct clk_regmap_phy_mux gcc_pcie3x1_0_pipe_clk_src = { .reg = 0x29064, .clkr = { - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie3x1_0_pipe_clk_src", .parent_data = &(const struct clk_parent_data) { .index = DT_USB_PCIE_WRAPPER_PIPE_CLK, @@ -739,7 +739,7 @@ static struct clk_regmap_phy_mux gcc_pcie3x1_0_pipe_clk_src = { static struct clk_regmap_phy_mux gcc_pcie3x1_1_pipe_clk_src = { .reg = 0x2a064, .clkr = { - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie3x1_1_pipe_clk_src", .parent_data = &(const struct clk_parent_data) { .index = DT_PCIE_2LANE_PHY_PIPE_CLK_X1, @@ -826,7 +826,7 @@ static struct clk_rcg2 gcc_qdss_tsctr_clk_src = { static struct clk_fixed_factor gcc_qdss_tsctr_div2_clk_src = { .mult = 1, .div = 2, - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_qdss_tsctr_div2_clk_src", .parent_hws = (const struct clk_hw *[]) { &gcc_qdss_tsctr_clk_src.clkr.hw }, @@ -839,7 +839,7 @@ static struct clk_fixed_factor gcc_qdss_tsctr_div2_clk_src = { static struct clk_fixed_factor gcc_qdss_tsctr_div3_clk_src = { .mult = 1, .div = 3, - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_qdss_tsctr_div3_clk_src", .parent_hws = (const struct clk_hw *[]) { &gcc_qdss_tsctr_clk_src.clkr.hw }, @@ -851,7 +851,7 @@ static struct clk_fixed_factor gcc_qdss_tsctr_div3_clk_src = { static struct clk_fixed_factor gcc_qdss_tsctr_div4_clk_src = { .mult = 1, .div = 4, - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_qdss_tsctr_div4_clk_src", .parent_hws = (const struct clk_hw *[]) { &gcc_qdss_tsctr_clk_src.clkr.hw }, @@ -863,7 +863,7 @@ static struct clk_fixed_factor gcc_qdss_tsctr_div4_clk_src = { static struct clk_fixed_factor gcc_qdss_tsctr_div8_clk_src = { .mult = 1, .div = 8, - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_qdss_tsctr_div8_clk_src", .parent_hws = (const struct clk_hw *[]) { &gcc_qdss_tsctr_clk_src.clkr.hw }, @@ -875,7 +875,7 @@ static struct clk_fixed_factor gcc_qdss_tsctr_div8_clk_src = { static struct clk_fixed_factor gcc_qdss_tsctr_div16_clk_src = { .mult = 1, .div = 16, - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_qdss_tsctr_div16_clk_src", .parent_hws = (const struct clk_hw *[]) { &gcc_qdss_tsctr_clk_src.clkr.hw }, @@ -976,7 +976,7 @@ static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = { static struct clk_fixed_factor gcc_system_noc_bfdcd_div2_clk_src = { .mult = 1, .div = 2, - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_system_noc_bfdcd_div2_clk_src", .parent_hws = (const struct clk_hw *[]) { &gcc_system_noc_bfdcd_clk_src.clkr.hw }, @@ -1069,7 +1069,7 @@ static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = { static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = { .reg = 0x2c074, .clkr = { - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_usb0_pipe_clk_src", .parent_data = &(const struct clk_parent_data) { .index = DT_USB_PCIE_WRAPPER_PIPE_CLK, @@ -1111,7 +1111,7 @@ static struct clk_rcg2 gcc_xo_clk_src = { static struct clk_fixed_factor gcc_xo_div4_clk_src = { .mult = 1, .div = 4, - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_xo_div4_clk_src", .parent_hws = (const struct clk_hw *[]) { &gcc_xo_clk_src.clkr.hw }, @@ -2431,7 +2431,7 @@ static struct clk_branch gcc_qdss_etr_usb_clk = { static struct clk_fixed_factor gcc_eud_at_div_clk_src = { .mult = 1, .div = 6, - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_eud_at_div_clk_src", .parent_hws = (const struct clk_hw *[]) { &gcc_qdss_at_clk_src.clkr.hw }, From patchwork Tue Nov 21 14:30:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13463274 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="GifGQbaD" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2531E10C1; Tue, 21 Nov 2023 06:31:53 -0800 (PST) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3ALE2A1B027334; Tue, 21 Nov 2023 14:31:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=pX4kYZuSKB3Oi5Dly+zBivG9ZOIjfQbprA7z6Adw25w=; b=GifGQbaDxvrSdhwkJ0FsA/Ha/zl6SXaphqkltAu9/6NxvUHIb+uiCzvo9RKfxQFnARQ2 6ALN+fN9og7RQR5R0Sk593MjiFqX9rVN4vZZklo2b2rH7SVYTw1E7W3XIv0eSTMBw07G DoC4PMD5VRN87cU+Mv+6o9QI3bGtrc/hYIrXGyiavadep8HuKQkv+WMDnA68dOaWZlgK 5AnOK25BSH0b73KB4EJAzoLovnc8LHhBpkbxJ2ECo5xriMVGCkLSoXQBQO0MTTJtRtz/ X65AKlz0lA2AAif2EJkUVXH1bDwKpXFImgsT3g7nfAm4+i1hb767ZOUscKui95B/34M2 OA== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ugk6x203g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 21 Nov 2023 14:31:42 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3ALEVIe3008253 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 21 Nov 2023 14:31:18 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 21 Nov 2023 06:31:12 -0800 From: Kathiravan Thirumoorthy Date: Tue, 21 Nov 2023 20:00:44 +0530 Subject: [PATCH v2 2/9] clk: qcom: ipq5332: enable few nssnoc clocks in driver probe Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20231121-ipq5332-nsscc-v2-2-a7ff61beab72@quicinc.com> References: <20231121-ipq5332-nsscc-v2-0-a7ff61beab72@quicinc.com> In-Reply-To: <20231121-ipq5332-nsscc-v2-0-a7ff61beab72@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Catalin Marinas , Will Deacon CC: , , , , , , "Kathiravan Thirumoorthy" X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1700577061; l=4389; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=kl1ojrNH4P07mHLq+405njkVkiRs0X/2WQl+0MW28PQ=; b=5idx+LxiSMfT/ykbqCHtwuJq8Bpqmn1DU0gL9ugynCmmhuBuUm24JteyhYun45DrcHXWim+l5 uNyyP33SZ2bANnFaRWJAG7ZWVeZmyBiU82RI8iouHZJFnrTpkMXFkSM X-Developer-Key: i=quic_kathirav@quicinc.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: H_dRvlKN3IJTZoaZPN00_MYFsr6ZPG7i X-Proofpoint-ORIG-GUID: H_dRvlKN3IJTZoaZPN00_MYFsr6ZPG7i X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-21_07,2023-11-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 impostorscore=0 spamscore=0 clxscore=1015 adultscore=0 malwarescore=0 bulkscore=0 phishscore=0 priorityscore=1501 mlxlogscore=864 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311210114 gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk, gcc_nssnoc_nsscc_clk are enabled by default and it's RCG is properly configured by bootloader. Some of the NSS clocks needs these clocks to be enabled. To avoid these clocks being disabled by clock framework, drop these entries from the clock table and enable it in the driver probe itself. Signed-off-by: Kathiravan Thirumoorthy Acked-by: Konrad Dybcio --- Changes in V2: - enabled the clocks in driver probe --- drivers/clk/qcom/gcc-ipq5332.c | 70 ++++++++---------------------------------- 1 file changed, 12 insertions(+), 58 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c index 66d5399798fe..38a570b68813 100644 --- a/drivers/clk/qcom/gcc-ipq5332.c +++ b/drivers/clk/qcom/gcc-ipq5332.c @@ -1672,24 +1672,6 @@ static struct clk_branch gcc_nssnoc_atb_clk = { }, }; -static struct clk_branch gcc_nssnoc_nsscc_clk = { - .halt_reg = 0x17030, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x17030, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_nssnoc_nsscc_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_pcnoc_bfdcd_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_nssnoc_qosgen_ref_clk = { .halt_reg = 0x1701c, .halt_check = BRANCH_HALT, @@ -2585,42 +2567,6 @@ static struct clk_branch gcc_snoc_lpass_cfg_clk = { }, }; -static struct clk_branch gcc_snoc_nssnoc_1_clk = { - .halt_reg = 0x17090, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x17090, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_snoc_nssnoc_1_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_system_noc_bfdcd_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_snoc_nssnoc_clk = { - .halt_reg = 0x17084, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x17084, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_snoc_nssnoc_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_system_noc_bfdcd_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_snoc_pcie3_1lane_1_m_clk = { .halt_reg = 0x2e050, .halt_check = BRANCH_HALT, @@ -3330,7 +3276,6 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = { [GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr, [GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr, [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr, - [GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr, [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr, [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr, [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr, @@ -3398,8 +3343,6 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = { [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr, [GCC_SNOC_LPASS_CFG_CLK] = &gcc_snoc_lpass_cfg_clk.clkr, - [GCC_SNOC_NSSNOC_1_CLK] = &gcc_snoc_nssnoc_1_clk.clkr, - [GCC_SNOC_NSSNOC_CLK] = &gcc_snoc_nssnoc_clk.clkr, [GCC_SNOC_PCIE3_1LANE_1_M_CLK] = &gcc_snoc_pcie3_1lane_1_m_clk.clkr, [GCC_SNOC_PCIE3_1LANE_1_S_CLK] = &gcc_snoc_pcie3_1lane_1_s_clk.clkr, [GCC_SNOC_PCIE3_1LANE_M_CLK] = &gcc_snoc_pcie3_1lane_m_clk.clkr, @@ -3660,7 +3603,18 @@ static const struct qcom_cc_desc gcc_ipq5332_desc = { static int gcc_ipq5332_probe(struct platform_device *pdev) { - return qcom_cc_probe(pdev, &gcc_ipq5332_desc); + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gcc_ipq5332_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* Keep the critical clocks always-On */ + regmap_update_bits(regmap, 0x17030, BIT(0), BIT(0)); /* gcc_nssnoc_nsscc_clk */ + regmap_update_bits(regmap, 0x17084, BIT(0), BIT(0)); /* gcc_snoc_nssnoc_clk */ + regmap_update_bits(regmap, 0x17090, BIT(0), BIT(0)); /* gcc_snoc_nssnoc_1_clk */ + + return qcom_cc_really_probe(pdev, &gcc_ipq5332_desc, regmap); } static const struct of_device_id gcc_ipq5332_match_table[] = { From patchwork Tue Nov 21 14:30:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13463276 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="giPbUB03" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B91810CF; 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Tue, 21 Nov 2023 14:31:50 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3ALEVOvi027441 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 21 Nov 2023 14:31:24 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 21 Nov 2023 06:31:18 -0800 From: Kathiravan Thirumoorthy Date: Tue, 21 Nov 2023 20:00:45 +0530 Subject: [PATCH v2 3/9] dt-bindings: clock: ipq5332: drop the few nss clocks definition Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20231121-ipq5332-nsscc-v2-3-a7ff61beab72@quicinc.com> References: <20231121-ipq5332-nsscc-v2-0-a7ff61beab72@quicinc.com> In-Reply-To: <20231121-ipq5332-nsscc-v2-0-a7ff61beab72@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Catalin Marinas , Will Deacon CC: , , , , , , "Kathiravan Thirumoorthy" X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; 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So let's drop the binding definition as well. Signed-off-by: Kathiravan Thirumoorthy --- Changes in V2: - No changes --- include/dt-bindings/clock/qcom,ipq5332-gcc.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h index 8a405a0a96d0..4649026da332 100644 --- a/include/dt-bindings/clock/qcom,ipq5332-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h @@ -55,7 +55,6 @@ #define GCC_NSSCC_CLK 46 #define GCC_NSSCFG_CLK 47 #define GCC_NSSNOC_ATB_CLK 48 -#define GCC_NSSNOC_NSSCC_CLK 49 #define GCC_NSSNOC_QOSGEN_REF_CLK 50 #define GCC_NSSNOC_SNOC_1_CLK 51 #define GCC_NSSNOC_SNOC_CLK 52 @@ -124,8 +123,6 @@ #define GCC_SDCC1_APPS_CLK_SRC 115 #define GCC_SLEEP_CLK_SRC 116 #define GCC_SNOC_LPASS_CFG_CLK 117 -#define GCC_SNOC_NSSNOC_1_CLK 118 -#define GCC_SNOC_NSSNOC_CLK 119 #define GCC_SNOC_PCIE3_1LANE_1_M_CLK 120 #define GCC_SNOC_PCIE3_1LANE_1_S_CLK 121 #define GCC_SNOC_PCIE3_1LANE_M_CLK 122 From patchwork Tue Nov 21 14:30:46 2023 Content-Type: text/plain; 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Tue, 21 Nov 2023 14:31:30 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3ALEVTEr023988 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 21 Nov 2023 14:31:29 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 21 Nov 2023 06:31:24 -0800 From: Kathiravan Thirumoorthy Date: Tue, 21 Nov 2023 20:00:46 +0530 Subject: [PATCH v2 4/9] dt-bindings: clock: ipq5332: add definition for GPLL0_OUT_AUX clock Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20231121-ipq5332-nsscc-v2-4-a7ff61beab72@quicinc.com> References: <20231121-ipq5332-nsscc-v2-0-a7ff61beab72@quicinc.com> In-Reply-To: <20231121-ipq5332-nsscc-v2-0-a7ff61beab72@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Catalin Marinas , Will Deacon CC: , , , , , , "Kathiravan Thirumoorthy" , Krzysztof Kozlowski X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; 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Acked-by: Krzysztof Kozlowski Signed-off-by: Kathiravan Thirumoorthy --- Changes in V2: - Pick up the A-b tag --- include/dt-bindings/clock/qcom,ipq5332-gcc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h index 4649026da332..486b6cf2e916 100644 --- a/include/dt-bindings/clock/qcom,ipq5332-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h @@ -176,6 +176,7 @@ #define GCC_PCIE3X1_0_PIPE_CLK_SRC 170 #define GCC_PCIE3X1_1_PIPE_CLK_SRC 171 #define GCC_USB0_PIPE_CLK_SRC 172 +#define GPLL0_OUT_AUX 173 #define GCC_ADSS_BCR 0 #define GCC_ADSS_PWM_CLK_ARES 1 From patchwork Tue Nov 21 14:30:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13463273 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="b269fsoT" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31A1DD79; Tue, 21 Nov 2023 06:31:45 -0800 (PST) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3ALE2MtZ005243; Tue, 21 Nov 2023 14:31:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=niG+EyfHCN01Z8sNBFqEkO6QzcsEUUFCB/230CsBPu8=; b=b269fsoTk2PpvzeaGylBs0MB0R+u9SF+p140U/Bh+MGao1RKn4t2doiinMZeuOWwNjof S5McDaO7bNMVACDOj4Ji+zJJPWcFS+/Y6Vu7n4/lsV9RWZXFkiQQn9oxQSaLfFtPmkXt qEJsaZ9/b1p9y+pR4XrVuquFw8RQpJsyrzNuqEEpuFZAYWddKQMrgTYp0hS+mMIEa2pC zCgfC6rFytAxxPH/jlVd8gOXuQ0cmwUW5KiOG7G7IhcHFGpHFm/xjEFabFSC/LFs9YQU zQVDgHwrc4C69NKrcbpm0GFztqeWPGjyPov5v4jAKkwUaFJmoanI7sVYrisR4yuUWoXp yg== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ugrk21a6n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 21 Nov 2023 14:31:36 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3ALEVZSY008324 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 21 Nov 2023 14:31:35 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 21 Nov 2023 06:31:30 -0800 From: Kathiravan Thirumoorthy Date: Tue, 21 Nov 2023 20:00:47 +0530 Subject: [PATCH v2 5/9] clk: qcom: ipq5332: add gpll0_out_aux clock Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20231121-ipq5332-nsscc-v2-5-a7ff61beab72@quicinc.com> References: <20231121-ipq5332-nsscc-v2-0-a7ff61beab72@quicinc.com> In-Reply-To: <20231121-ipq5332-nsscc-v2-0-a7ff61beab72@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Catalin Marinas , Will Deacon CC: , , , , , , "Kathiravan Thirumoorthy" X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1700577061; l=1538; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=VPS7QatPhXsdmufQxuURcRkX0dln/LrLHtBhAb0H6pI=; b=QCZplDk3qyHlf6Y8xLpCLN3BdU+9Kyv7fG3pr6YUnA6l4l3GLfBlXPjes+Dgf+UkUhow2vJe4 ++nzrEPtc+rDm2wCVBNG7gFphnLV+ey8riC51z8jrfGGJINpkQHuUuX X-Developer-Key: i=quic_kathirav@quicinc.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: hUSw1XmV4-tw2IVL14PaJdqFyuCfzgQM X-Proofpoint-ORIG-GUID: hUSw1XmV4-tw2IVL14PaJdqFyuCfzgQM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-21_07,2023-11-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 phishscore=0 mlxscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311210114 Add support for gpll0_out_aux clock which acts as the parent for certain networking subsystem (NSS) clocks. Signed-off-by: Kathiravan Thirumoorthy Acked-by: Konrad Dybcio --- Changes in V2: - add the const qualifier to the struct initdata --- drivers/clk/qcom/gcc-ipq5332.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c index 38a570b68813..9a5f0c98f734 100644 --- a/drivers/clk/qcom/gcc-ipq5332.c +++ b/drivers/clk/qcom/gcc-ipq5332.c @@ -87,6 +87,19 @@ static struct clk_alpha_pll_postdiv gpll0 = { }, }; +static struct clk_alpha_pll_postdiv gpll0_out_aux = { + .offset = 0x20000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpll0_out_aux", + .parent_hws = (const struct clk_hw *[]) { + &gpll0_main.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, +}; + static struct clk_alpha_pll gpll2_main = { .offset = 0x21000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], @@ -3393,6 +3406,7 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = { [GCC_PCIE3X1_0_PIPE_CLK_SRC] = &gcc_pcie3x1_0_pipe_clk_src.clkr, [GCC_PCIE3X1_1_PIPE_CLK_SRC] = &gcc_pcie3x1_1_pipe_clk_src.clkr, [GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr, + [GPLL0_OUT_AUX] = &gpll0_out_aux.clkr, }; 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Tue, 21 Nov 2023 06:31:35 -0800 From: Kathiravan Thirumoorthy Date: Tue, 21 Nov 2023 20:00:48 +0530 Subject: [PATCH v2 6/9] dt-bindings: clock: add Qualcomm IPQ5332 NSSCC clock and reset definitions Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20231121-ipq5332-nsscc-v2-6-a7ff61beab72@quicinc.com> References: <20231121-ipq5332-nsscc-v2-0-a7ff61beab72@quicinc.com> In-Reply-To: <20231121-ipq5332-nsscc-v2-0-a7ff61beab72@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Catalin Marinas , Will Deacon CC: , , , , , , "Kathiravan Thirumoorthy" , Krzysztof Kozlowski X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1700577061; l=6077; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=TSmKmZiK3DLZt0Zbx5+7IbVFU37ciFfHI89bN4e1Mzw=; b=Tgl5yUbwa5g7hop+nVqj7R9YFcPFP2E/1n+QnJz+3N+644JcBPbKbskha2/34WzIi22dN4G0E NKKheWr9/n5D0yzvoPFya+qI0LyPDqV5330rFFFu24I7oPd5Hryio/O X-Developer-Key: i=quic_kathirav@quicinc.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: HPNWwj_8GhrDdv-vHHqVzf6nhA-PkyT7 X-Proofpoint-ORIG-GUID: HPNWwj_8GhrDdv-vHHqVzf6nhA-PkyT7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-21_05,2023-11-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 bulkscore=0 phishscore=0 impostorscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 mlxlogscore=999 adultscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311210113 Add NSSCC clock and reset definitions for Qualcomm IPQ5332. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan Thirumoorthy --- Changes in V2: - Pick up R-b tag --- .../bindings/clock/qcom,ipq5332-nsscc.yaml | 60 +++++++++++++++ include/dt-bindings/clock/qcom,ipq5332-nsscc.h | 86 ++++++++++++++++++++++ 2 files changed, 146 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-nsscc.yaml new file mode 100644 index 000000000000..59f8d1e99229 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-nsscc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq5332-nsscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ5332 + +maintainers: + - Bjorn Andersson + +description: | + Qualcomm networking sub system clock control module provides the clocks, + resets and power domains on IPQ5332 + + See also:: + include/dt-bindings/clock/qcom,ipq5332-nsscc.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,ipq5332-nsscc + + clocks: + items: + - description: Common PLL nss clock 200M source + - description: Common PLL nss clock 300M source + - description: GCC GPLL0 out aux clock source + - description: Uniphy0 NSS Rx clock source + - description: Uniphy0 NSS Tx clock source + - description: Uniphy1 NSS Rx clock source + - description: Uniphy1 NSS Tx clock source + - description: Board XO source + +required: + - compatible + - clocks + +unevaluatedProperties: false + +examples: + - | + clock-controller@39b00000 { + compatible = "qcom,ipq5332-nsscc"; + reg = <0x39b00000 0x80000>; + clocks = <&bias_pll_cc_clk>, + <&bias_pll_nss_noc_clk>, + <&gcc_gpll0_out_aux>, + <&uniphy 0>, + <&uniphy 1>, + <&uniphy 2>, + <&uniphy 3>, + <&xo_board_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,ipq5332-nsscc.h b/include/dt-bindings/clock/qcom,ipq5332-nsscc.h new file mode 100644 index 000000000000..c077cde7f57d --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5332-nsscc.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_NSS_CC_IPQ5332_H +#define _DT_BINDINGS_CLK_QCOM_NSS_CC_IPQ5332_H + +/* NSS_CC clocks */ +#define NSS_CC_CE_APB_CLK 0 +#define NSS_CC_CE_AXI_CLK 1 +#define NSS_CC_CE_CLK_SRC 2 +#define NSS_CC_CFG_CLK_SRC 3 +#define NSS_CC_DEBUG_CLK 4 +#define NSS_CC_EIP_BFDCD_CLK_SRC 5 +#define NSS_CC_EIP_CLK 6 +#define NSS_CC_NSS_CSR_CLK 7 +#define NSS_CC_NSSNOC_CE_APB_CLK 8 +#define NSS_CC_NSSNOC_CE_AXI_CLK 9 +#define NSS_CC_NSSNOC_EIP_CLK 10 +#define NSS_CC_NSSNOC_NSS_CSR_CLK 11 +#define NSS_CC_NSSNOC_PPE_CFG_CLK 12 +#define NSS_CC_NSSNOC_PPE_CLK 13 +#define NSS_CC_PORT1_MAC_CLK 14 +#define NSS_CC_PORT1_RX_CLK 15 +#define NSS_CC_PORT1_RX_CLK_SRC 16 +#define NSS_CC_PORT1_RX_DIV_CLK_SRC 17 +#define NSS_CC_PORT1_TX_CLK 18 +#define NSS_CC_PORT1_TX_CLK_SRC 19 +#define NSS_CC_PORT1_TX_DIV_CLK_SRC 20 +#define NSS_CC_PORT2_MAC_CLK 21 +#define NSS_CC_PORT2_RX_CLK 22 +#define NSS_CC_PORT2_RX_CLK_SRC 23 +#define NSS_CC_PORT2_RX_DIV_CLK_SRC 24 +#define NSS_CC_PORT2_TX_CLK 25 +#define NSS_CC_PORT2_TX_CLK_SRC 26 +#define NSS_CC_PORT2_TX_DIV_CLK_SRC 27 +#define NSS_CC_PPE_CLK_SRC 28 +#define NSS_CC_PPE_EDMA_CFG_CLK 29 +#define NSS_CC_PPE_EDMA_CLK 30 +#define NSS_CC_PPE_SWITCH_BTQ_CLK 31 +#define NSS_CC_PPE_SWITCH_CFG_CLK 32 +#define NSS_CC_PPE_SWITCH_CLK 33 +#define NSS_CC_PPE_SWITCH_IPE_CLK 34 +#define NSS_CC_UNIPHY_PORT1_RX_CLK 35 +#define NSS_CC_UNIPHY_PORT1_TX_CLK 36 +#define NSS_CC_UNIPHY_PORT2_RX_CLK 37 +#define NSS_CC_UNIPHY_PORT2_TX_CLK 38 +#define NSS_CC_XGMAC0_PTP_REF_CLK 39 +#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 40 +#define NSS_CC_XGMAC1_PTP_REF_CLK 41 +#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 42 + +#define NSS_CC_CE_APB_CLK_ARES 0 +#define NSS_CC_CE_AXI_CLK_ARES 1 +#define NSS_CC_DEBUG_CLK_ARES 2 +#define NSS_CC_EIP_CLK_ARES 3 +#define NSS_CC_NSS_CSR_CLK_ARES 4 +#define NSS_CC_NSSNOC_CE_APB_CLK_ARES 5 +#define NSS_CC_NSSNOC_CE_AXI_CLK_ARES 6 +#define NSS_CC_NSSNOC_EIP_CLK_ARES 7 +#define NSS_CC_NSSNOC_NSS_CSR_CLK_ARES 8 +#define NSS_CC_NSSNOC_PPE_CLK_ARES 9 +#define NSS_CC_NSSNOC_PPE_CFG_CLK_ARES 10 +#define NSS_CC_PORT1_MAC_CLK_ARES 11 +#define NSS_CC_PORT1_RX_CLK_ARES 12 +#define NSS_CC_PORT1_TX_CLK_ARES 13 +#define NSS_CC_PORT2_MAC_CLK_ARES 14 +#define NSS_CC_PORT2_RX_CLK_ARES 15 +#define NSS_CC_PORT2_TX_CLK_ARES 16 +#define NSS_CC_PPE_BCR 17 +#define NSS_CC_PPE_EDMA_CLK_ARES 18 +#define NSS_CC_PPE_EDMA_CFG_CLK_ARES 19 +#define NSS_CC_PPE_SWITCH_BTQ_CLK_ARES 20 +#define NSS_CC_PPE_SWITCH_CLK_ARES 21 +#define NSS_CC_PPE_SWITCH_CFG_CLK_ARES 22 +#define NSS_CC_PPE_SWITCH_IPE_CLK_ARES 23 +#define NSS_CC_UNIPHY_PORT1_RX_CLK_ARES 24 +#define NSS_CC_UNIPHY_PORT1_TX_CLK_ARES 25 +#define NSS_CC_UNIPHY_PORT2_RX_CLK_ARES 26 +#define NSS_CC_UNIPHY_PORT2_TX_CLK_ARES 27 +#define NSS_CC_XGMAC0_PTP_REF_CLK_ARES 28 +#define NSS_CC_XGMAC1_PTP_REF_CLK_ARES 29 + +#endif From patchwork Tue Nov 21 14:30:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13463277 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="mFVVQ6yW" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44D52D6C; Tue, 21 Nov 2023 06:32:01 -0800 (PST) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3ALE2Axl027314; Tue, 21 Nov 2023 14:31:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=+DAcdvZ831X2+FOYBQhCYfe7zAHCzdFya/MCeJsgGPA=; b=mFVVQ6yWZHb5y5FAdcKKQWeOFgVMYOMGkP75BBYIcCFPmoW5z4w+WqX/SZNuD60a98Dg iAtbwLmWZLJLPbI1VzRXRC5suDsFz9Bs8EY3+7PrNY90LE4EtCFp+LZ+MV6ldxSw2Qxm 6qS3GujZLcpWBBlEh7fOGzNUQnpOJYNKHSBGKLJiRXPTmZ+RHwSwgCOSxP3HUMAelKNG xko0q3WVe93FK3yydxBE+jCTtttvLB5OA4D7Z0kS756iK8/3st6zSD1BV37FRzahOr39 8n/dkwwZuozUo2J/XCjf6ubabm3U9s96LqtwwrZD5BHAt1ADOYTaFOLqqZrGd0nYUcLE pQ== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ugk6x204g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 21 Nov 2023 14:31:48 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3ALEVlsP027964 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 21 Nov 2023 14:31:47 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 21 Nov 2023 06:31:41 -0800 From: Kathiravan Thirumoorthy Date: Tue, 21 Nov 2023 20:00:49 +0530 Subject: [PATCH v2 7/9] clk: qcom: add NSS clock Controller driver for Qualcomm IPQ5332 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20231121-ipq5332-nsscc-v2-7-a7ff61beab72@quicinc.com> References: <20231121-ipq5332-nsscc-v2-0-a7ff61beab72@quicinc.com> In-Reply-To: <20231121-ipq5332-nsscc-v2-0-a7ff61beab72@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Catalin Marinas , Will Deacon CC: , , , , , , "Kathiravan Thirumoorthy" X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; 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Signed-off-by: Kathiravan Thirumoorthy --- Changes in V2: - For the port rx and tx clock source, use clk_rcg2_fm_ops instead of clk_rcg2_ops - added space between ){ wherever applicable --- drivers/clk/qcom/Kconfig | 7 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/nsscc-ipq5332.c | 1035 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 1043 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index ad1acd9b7426..2e3efcdef9fa 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -162,6 +162,13 @@ config IPQ_GCC_5332 Say Y if you want to use peripheral devices such as UART, SPI, i2c, USB, SD/eMMC, etc. +config IPQ_NSSCC_5332 + tristate "IPQ5332 NSS Clock Controller" + depends on ARM64 || COMPILE_TEST + depends on IPQ_GCC_5332 + help + Support for NSS clock controller on ipq5332 devices. + config IPQ_GCC_6018 tristate "IPQ6018 Global Clock Controller" help diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 17edd73f9839..3aab744ecc99 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o +obj-$(CONFIG_IPQ_NSSCC_5332) += nsscc-ipq5332.o obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o diff --git a/drivers/clk/qcom/nsscc-ipq5332.c b/drivers/clk/qcom/nsscc-ipq5332.c new file mode 100644 index 000000000000..b521e807931f --- /dev/null +++ b/drivers/clk/qcom/nsscc-ipq5332.c @@ -0,0 +1,1035 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "reset.h" + +enum { + DT_CMN_PLL_NSS_CLK_200M, + DT_CMN_PLL_NSS_CLK_300M, + DT_GCC_GPLL0_OUT_AUX, + DT_UNIPHY0_NSS_TX_CLK, + DT_UNIPHY0_NSS_RX_CLK, + DT_UNIPHY1_NSS_TX_CLK, + DT_UNIPHY1_NSS_RX_CLK, + DT_XO, +}; + +enum { + P_CMN_PLL_NSS_CLK_200M, + P_CMN_PLL_NSS_CLK_300M, + P_GCC_GPLL0_OUT_AUX, + P_UNIPHY0_NSS_TX_CLK, + P_UNIPHY0_NSS_RX_CLK, + P_UNIPHY1_NSS_TX_CLK, + P_UNIPHY1_NSS_RX_CLK, + P_XO, +}; + +static const struct parent_map nss_cc_parent_map_0[] = { + { P_XO, 0 }, + { P_GCC_GPLL0_OUT_AUX, 2 }, + { P_CMN_PLL_NSS_CLK_300M, 5 }, + { P_CMN_PLL_NSS_CLK_200M, 6 }, +}; + +static const struct clk_parent_data nss_cc_parent_data_0[] = { + { .index = DT_XO }, + { .index = DT_GCC_GPLL0_OUT_AUX }, + { .index = DT_CMN_PLL_NSS_CLK_300M }, + { .index = DT_CMN_PLL_NSS_CLK_200M }, +}; + +static const struct parent_map nss_cc_parent_map_1[] = { + { P_XO, 0 }, + { P_GCC_GPLL0_OUT_AUX, 2 }, + { P_UNIPHY0_NSS_RX_CLK, 3 }, + { P_UNIPHY0_NSS_TX_CLK, 4 }, + { P_CMN_PLL_NSS_CLK_300M, 5 }, + { P_CMN_PLL_NSS_CLK_200M, 6 }, +}; + +static const struct clk_parent_data nss_cc_parent_data_1[] = { + { .index = DT_XO }, + { .index = DT_GCC_GPLL0_OUT_AUX }, + { .index = DT_UNIPHY0_NSS_RX_CLK }, + { .index = DT_UNIPHY0_NSS_TX_CLK }, + { .index = DT_CMN_PLL_NSS_CLK_300M }, + { .index = DT_CMN_PLL_NSS_CLK_200M }, +}; + +static const struct parent_map nss_cc_parent_map_2[] = { + { P_XO, 0 }, + { P_GCC_GPLL0_OUT_AUX, 2 }, + { P_UNIPHY1_NSS_RX_CLK, 3 }, + { P_UNIPHY1_NSS_TX_CLK, 4 }, + { P_CMN_PLL_NSS_CLK_300M, 5 }, + { P_CMN_PLL_NSS_CLK_200M, 6 }, +}; + +static const struct clk_parent_data nss_cc_parent_data_2[] = { + { .index = DT_XO }, + { .index = DT_GCC_GPLL0_OUT_AUX }, + { .index = DT_UNIPHY1_NSS_RX_CLK }, + { .index = DT_UNIPHY1_NSS_TX_CLK }, + { .index = DT_CMN_PLL_NSS_CLK_300M }, + { .index = DT_CMN_PLL_NSS_CLK_200M }, +}; + +static const struct freq_tbl ftbl_nss_cc_ce_clk_src[] = { + F(24000000, P_XO, 1, 0, 0), + F(200000000, P_CMN_PLL_NSS_CLK_200M, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_ce_clk_src = { + .cmd_rcgr = 0x518, + .mnd_width = 0, + .hid_width = 5, + .parent_map = nss_cc_parent_map_0, + .freq_tbl = ftbl_nss_cc_ce_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_ce_clk_src", + .parent_data = nss_cc_parent_data_0, + .num_parents = ARRAY_SIZE(nss_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_nss_cc_cfg_clk_src[] = { + F(100000000, P_GCC_GPLL0_OUT_AUX, 8, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_cfg_clk_src = { + .cmd_rcgr = 0x5e0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = nss_cc_parent_map_0, + .freq_tbl = ftbl_nss_cc_cfg_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_cfg_clk_src", + .parent_data = nss_cc_parent_data_0, + .num_parents = ARRAY_SIZE(nss_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_nss_cc_eip_bfdcd_clk_src[] = { + F(300000000, P_CMN_PLL_NSS_CLK_300M, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_eip_bfdcd_clk_src = { + .cmd_rcgr = 0x57c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = nss_cc_parent_map_0, + .freq_tbl = ftbl_nss_cc_eip_bfdcd_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_eip_bfdcd_clk_src", + .parent_data = nss_cc_parent_data_0, + .num_parents = ARRAY_SIZE(nss_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = { + C(P_UNIPHY0_NSS_RX_CLK, 12.5, 0, 0), + C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_125[] = { + C(P_UNIPHY0_NSS_RX_CLK, 2.5, 0, 0), + C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = { + FMS(24000000, P_XO, 1, 0, 0), + FM(25000000, ftbl_nss_cc_port1_rx_clk_src_25), + FMS(78125000, P_UNIPHY0_NSS_RX_CLK, 4, 0, 0), + FM(125000000, ftbl_nss_cc_port1_rx_clk_src_125), + FMS(156250000, P_UNIPHY0_NSS_RX_CLK, 2, 0, 0), + FMS(312500000, P_UNIPHY0_NSS_RX_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_port1_rx_clk_src = { + .cmd_rcgr = 0x450, + .mnd_width = 0, + .hid_width = 5, + .parent_map = nss_cc_parent_map_1, + .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_port1_rx_clk_src", + .parent_data = nss_cc_parent_data_1, + .num_parents = ARRAY_SIZE(nss_cc_parent_data_1), + .ops = &clk_rcg2_fm_ops, + }, +}; + +static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_25[] = { + C(P_UNIPHY0_NSS_TX_CLK, 12.5, 0, 0), + C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_125[] = { + C(P_UNIPHY0_NSS_TX_CLK, 2.5, 0, 0), + C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_port1_tx_clk_src[] = { + FMS(24000000, P_XO, 1, 0, 0), + FM(25000000, ftbl_nss_cc_port1_tx_clk_src_25), + FMS(78125000, P_UNIPHY0_NSS_TX_CLK, 4, 0, 0), + FM(125000000, ftbl_nss_cc_port1_tx_clk_src_125), + FMS(156250000, P_UNIPHY0_NSS_TX_CLK, 2, 0, 0), + FMS(312500000, P_UNIPHY0_NSS_TX_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_port1_tx_clk_src = { + .cmd_rcgr = 0x45c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = nss_cc_parent_map_1, + .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_port1_tx_clk_src", + .parent_data = nss_cc_parent_data_1, + .num_parents = ARRAY_SIZE(nss_cc_parent_data_1), + .ops = &clk_rcg2_fm_ops, + }, +}; + +static const struct freq_conf ftbl_nss_cc_port2_rx_clk_src_25[] = { + C(P_UNIPHY1_NSS_RX_CLK, 12.5, 0, 0), + C(P_UNIPHY1_NSS_RX_CLK, 5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_port2_rx_clk_src_125[] = { + C(P_UNIPHY1_NSS_RX_CLK, 2.5, 0, 0), + C(P_UNIPHY1_NSS_RX_CLK, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_port2_rx_clk_src[] = { + FMS(24000000, P_XO, 1, 0, 0), + FM(25000000, ftbl_nss_cc_port2_rx_clk_src_25), + FMS(78125000, P_UNIPHY1_NSS_RX_CLK, 4, 0, 0), + FM(125000000, ftbl_nss_cc_port2_rx_clk_src_125), + FMS(156250000, P_UNIPHY1_NSS_RX_CLK, 2, 0, 0), + FMS(312500000, P_UNIPHY1_NSS_RX_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_port2_rx_clk_src = { + .cmd_rcgr = 0x468, + .mnd_width = 0, + .hid_width = 5, + .parent_map = nss_cc_parent_map_2, + .freq_multi_tbl = ftbl_nss_cc_port2_rx_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_port2_rx_clk_src", + .parent_data = nss_cc_parent_data_2, + .num_parents = ARRAY_SIZE(nss_cc_parent_data_2), + .ops = &clk_rcg2_fm_ops, + }, +}; + +static const struct freq_conf ftbl_nss_cc_port2_tx_clk_src_25[] = { + C(P_UNIPHY1_NSS_TX_CLK, 12.5, 0, 0), + C(P_UNIPHY1_NSS_TX_CLK, 5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_port2_tx_clk_src_125[] = { + C(P_UNIPHY1_NSS_TX_CLK, 2.5, 0, 0), + C(P_UNIPHY1_NSS_TX_CLK, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_port2_tx_clk_src[] = { + FMS(24000000, P_XO, 1, 0, 0), + FM(25000000, ftbl_nss_cc_port2_tx_clk_src_25), + FMS(78125000, P_UNIPHY1_NSS_TX_CLK, 4, 0, 0), + FM(125000000, ftbl_nss_cc_port2_tx_clk_src_125), + FMS(156250000, P_UNIPHY1_NSS_TX_CLK, 2, 0, 0), + FMS(312500000, P_UNIPHY1_NSS_TX_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_port2_tx_clk_src = { + .cmd_rcgr = 0x474, + .mnd_width = 0, + .hid_width = 5, + .parent_map = nss_cc_parent_map_2, + .freq_multi_tbl = ftbl_nss_cc_port2_tx_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_port2_tx_clk_src", + .parent_data = nss_cc_parent_data_2, + .num_parents = ARRAY_SIZE(nss_cc_parent_data_2), + .ops = &clk_rcg2_fm_ops, + }, +}; + +static struct clk_rcg2 nss_cc_ppe_clk_src = { + .cmd_rcgr = 0x3e8, + .mnd_width = 0, + .hid_width = 5, + .parent_map = nss_cc_parent_map_0, + .freq_tbl = ftbl_nss_cc_ce_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_ppe_clk_src", + .parent_data = nss_cc_parent_data_0, + .num_parents = ARRAY_SIZE(nss_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port1_rx_div_clk_src = { + .reg = 0x458, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_port1_rx_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_port1_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port1_tx_div_clk_src = { + .reg = 0x464, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_port1_tx_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_port1_tx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port2_rx_div_clk_src = { + .reg = 0x470, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_port2_rx_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_port2_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port2_tx_div_clk_src = { + .reg = 0x47c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_port2_tx_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_port2_tx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_xgmac0_ptp_ref_div_clk_src = { + .reg = 0x3f0, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_xgmac0_ptp_ref_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div nss_cc_xgmac1_ptp_ref_div_clk_src = { + .reg = 0x3f4, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_xgmac1_ptp_ref_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch nss_cc_ce_apb_clk = { + .halt_reg = 0x520, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x520, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_ce_apb_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_ce_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ce_axi_clk = { + .halt_reg = 0x524, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x524, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_ce_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_ce_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_debug_clk = { + .halt_reg = 0x644, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x644, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_debug_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_eip_clk = { + .halt_reg = 0x590, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x590, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_eip_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_eip_bfdcd_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nss_csr_clk = { + .halt_reg = 0x5e8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5e8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_nss_csr_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_cfg_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_ce_apb_clk = { + .halt_reg = 0x52c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x52c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_nssnoc_ce_apb_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_ce_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_ce_axi_clk = { + .halt_reg = 0x530, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x530, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_nssnoc_ce_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_ce_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_eip_clk = { + .halt_reg = 0x598, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x598, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_nssnoc_eip_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_eip_bfdcd_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_nss_csr_clk = { + .halt_reg = 0x5ec, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5ec, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_nssnoc_nss_csr_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_cfg_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_ppe_cfg_clk = { + .halt_reg = 0x424, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x424, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_nssnoc_ppe_cfg_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_ppe_clk = { + .halt_reg = 0x420, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x420, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_nssnoc_ppe_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port1_mac_clk = { + .halt_reg = 0x428, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x428, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_port1_mac_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port1_rx_clk = { + .halt_reg = 0x480, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x480, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_port1_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_port1_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port1_tx_clk = { + .halt_reg = 0x488, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x488, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_port1_tx_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_port1_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port2_mac_clk = { + .halt_reg = 0x430, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x430, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_port2_mac_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port2_rx_clk = { + .halt_reg = 0x490, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x490, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_port2_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_port2_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port2_tx_clk = { + .halt_reg = 0x498, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x498, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_port2_tx_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_port2_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_edma_cfg_clk = { + .halt_reg = 0x41c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x41c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_ppe_edma_cfg_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_edma_clk = { + .halt_reg = 0x414, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x414, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_ppe_edma_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_switch_btq_clk = { + .halt_reg = 0x400, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x400, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_ppe_switch_btq_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_switch_cfg_clk = { + .halt_reg = 0x410, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x410, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_ppe_switch_cfg_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_switch_clk = { + .halt_reg = 0x408, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x408, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_ppe_switch_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_switch_ipe_clk = { + .halt_reg = 0x3f8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3f8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_ppe_switch_ipe_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port1_rx_clk = { + .halt_reg = 0x4b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4b4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_uniphy_port1_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_port1_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port1_tx_clk = { + .halt_reg = 0x4b8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4b8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_uniphy_port1_tx_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_port1_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port2_rx_clk = { + .halt_reg = 0x4bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4bc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_uniphy_port2_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_port2_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port2_tx_clk = { + .halt_reg = 0x4c0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4c0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_uniphy_port2_tx_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_port2_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_xgmac0_ptp_ref_clk = { + .halt_reg = 0x438, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x438, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_xgmac0_ptp_ref_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_xgmac1_ptp_ref_clk = { + .halt_reg = 0x43c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x43c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_xgmac1_ptp_ref_clk", + .parent_hws = (const struct clk_hw*[]) { + &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *nss_cc_ipq5332_clocks[] = { + [NSS_CC_CE_APB_CLK] = &nss_cc_ce_apb_clk.clkr, + [NSS_CC_CE_AXI_CLK] = &nss_cc_ce_axi_clk.clkr, + [NSS_CC_CE_CLK_SRC] = &nss_cc_ce_clk_src.clkr, + [NSS_CC_CFG_CLK_SRC] = &nss_cc_cfg_clk_src.clkr, + [NSS_CC_DEBUG_CLK] = &nss_cc_debug_clk.clkr, + [NSS_CC_EIP_BFDCD_CLK_SRC] = &nss_cc_eip_bfdcd_clk_src.clkr, + [NSS_CC_EIP_CLK] = &nss_cc_eip_clk.clkr, + [NSS_CC_NSS_CSR_CLK] = &nss_cc_nss_csr_clk.clkr, + [NSS_CC_NSSNOC_CE_APB_CLK] = &nss_cc_nssnoc_ce_apb_clk.clkr, + [NSS_CC_NSSNOC_CE_AXI_CLK] = &nss_cc_nssnoc_ce_axi_clk.clkr, + [NSS_CC_NSSNOC_EIP_CLK] = &nss_cc_nssnoc_eip_clk.clkr, + [NSS_CC_NSSNOC_NSS_CSR_CLK] = &nss_cc_nssnoc_nss_csr_clk.clkr, + [NSS_CC_NSSNOC_PPE_CFG_CLK] = &nss_cc_nssnoc_ppe_cfg_clk.clkr, + [NSS_CC_NSSNOC_PPE_CLK] = &nss_cc_nssnoc_ppe_clk.clkr, + [NSS_CC_PORT1_MAC_CLK] = &nss_cc_port1_mac_clk.clkr, + [NSS_CC_PORT1_RX_CLK] = &nss_cc_port1_rx_clk.clkr, + [NSS_CC_PORT1_RX_CLK_SRC] = &nss_cc_port1_rx_clk_src.clkr, + [NSS_CC_PORT1_RX_DIV_CLK_SRC] = &nss_cc_port1_rx_div_clk_src.clkr, + [NSS_CC_PORT1_TX_CLK] = &nss_cc_port1_tx_clk.clkr, + [NSS_CC_PORT1_TX_CLK_SRC] = &nss_cc_port1_tx_clk_src.clkr, + [NSS_CC_PORT1_TX_DIV_CLK_SRC] = &nss_cc_port1_tx_div_clk_src.clkr, + [NSS_CC_PORT2_MAC_CLK] = &nss_cc_port2_mac_clk.clkr, + [NSS_CC_PORT2_RX_CLK] = &nss_cc_port2_rx_clk.clkr, + [NSS_CC_PORT2_RX_CLK_SRC] = &nss_cc_port2_rx_clk_src.clkr, + [NSS_CC_PORT2_RX_DIV_CLK_SRC] = &nss_cc_port2_rx_div_clk_src.clkr, + [NSS_CC_PORT2_TX_CLK] = &nss_cc_port2_tx_clk.clkr, + [NSS_CC_PORT2_TX_CLK_SRC] = &nss_cc_port2_tx_clk_src.clkr, + [NSS_CC_PORT2_TX_DIV_CLK_SRC] = &nss_cc_port2_tx_div_clk_src.clkr, + [NSS_CC_PPE_CLK_SRC] = &nss_cc_ppe_clk_src.clkr, + [NSS_CC_PPE_EDMA_CFG_CLK] = &nss_cc_ppe_edma_cfg_clk.clkr, + [NSS_CC_PPE_EDMA_CLK] = &nss_cc_ppe_edma_clk.clkr, + [NSS_CC_PPE_SWITCH_BTQ_CLK] = &nss_cc_ppe_switch_btq_clk.clkr, + [NSS_CC_PPE_SWITCH_CFG_CLK] = &nss_cc_ppe_switch_cfg_clk.clkr, + [NSS_CC_PPE_SWITCH_CLK] = &nss_cc_ppe_switch_clk.clkr, + [NSS_CC_PPE_SWITCH_IPE_CLK] = &nss_cc_ppe_switch_ipe_clk.clkr, + [NSS_CC_UNIPHY_PORT1_RX_CLK] = &nss_cc_uniphy_port1_rx_clk.clkr, + [NSS_CC_UNIPHY_PORT1_TX_CLK] = &nss_cc_uniphy_port1_tx_clk.clkr, + [NSS_CC_UNIPHY_PORT2_RX_CLK] = &nss_cc_uniphy_port2_rx_clk.clkr, + [NSS_CC_UNIPHY_PORT2_TX_CLK] = &nss_cc_uniphy_port2_tx_clk.clkr, + [NSS_CC_XGMAC0_PTP_REF_CLK] = &nss_cc_xgmac0_ptp_ref_clk.clkr, + [NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC] = &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr, + [NSS_CC_XGMAC1_PTP_REF_CLK] = &nss_cc_xgmac1_ptp_ref_clk.clkr, + [NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC] = &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr, +}; + +static const struct qcom_reset_map nss_cc_ipq5332_resets[] = { + [NSS_CC_CE_APB_CLK_ARES] = { 0x520, 2 }, + [NSS_CC_CE_AXI_CLK_ARES] = { 0x524, 2 }, + [NSS_CC_DEBUG_CLK_ARES] = { 0x644, 2 }, + [NSS_CC_EIP_CLK_ARES] = { 0x590, 2 }, + [NSS_CC_NSS_CSR_CLK_ARES] = { 0x5e8, 2 }, + [NSS_CC_NSSNOC_CE_APB_CLK_ARES] = { 0x52c, 2 }, + [NSS_CC_NSSNOC_CE_AXI_CLK_ARES] = { 0x530, 2 }, + [NSS_CC_NSSNOC_EIP_CLK_ARES] = { 0x598, 2 }, + [NSS_CC_NSSNOC_NSS_CSR_CLK_ARES] = { 0x5ec, 2 }, + [NSS_CC_NSSNOC_PPE_CLK_ARES] = { 0x420, 2 }, + [NSS_CC_NSSNOC_PPE_CFG_CLK_ARES] = { 0x424, 2 }, + [NSS_CC_PORT1_MAC_CLK_ARES] = { 0x428, 2 }, + [NSS_CC_PORT1_RX_CLK_ARES] = { 0x480, 2 }, + [NSS_CC_PORT1_TX_CLK_ARES] = { 0x488, 2 }, + [NSS_CC_PORT2_MAC_CLK_ARES] = { 0x430, 2 }, + [NSS_CC_PORT2_RX_CLK_ARES] = { 0x490, 2 }, + [NSS_CC_PORT2_TX_CLK_ARES] = { 0x498, 2 }, + [NSS_CC_PPE_BCR] = { 0x3e4 }, + [NSS_CC_PPE_EDMA_CLK_ARES] = { 0x414, 2 }, + [NSS_CC_PPE_EDMA_CFG_CLK_ARES] = { 0x41c, 2 }, + [NSS_CC_PPE_SWITCH_BTQ_CLK_ARES] = { 0x400, 2 }, + [NSS_CC_PPE_SWITCH_CLK_ARES] = { 0x408, 2 }, + [NSS_CC_PPE_SWITCH_CFG_CLK_ARES] = { 0x410, 2 }, + [NSS_CC_PPE_SWITCH_IPE_CLK_ARES] = { 0x3f8, 2 }, + [NSS_CC_UNIPHY_PORT1_RX_CLK_ARES] = { 0x4b4, 2 }, + [NSS_CC_UNIPHY_PORT1_TX_CLK_ARES] = { 0x4b8, 2 }, + [NSS_CC_UNIPHY_PORT2_RX_CLK_ARES] = { 0x4bc, 2 }, + [NSS_CC_UNIPHY_PORT2_TX_CLK_ARES] = { 0x4c0, 2 }, + [NSS_CC_XGMAC0_PTP_REF_CLK_ARES] = { 0x438, 2 }, + [NSS_CC_XGMAC1_PTP_REF_CLK_ARES] = { 0x43c, 2 }, +}; + +static const struct regmap_config nss_cc_ipq5332_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x800, + .fast_io = true, +}; + +static const struct qcom_cc_desc nss_cc_ipq5332_desc = { + .config = &nss_cc_ipq5332_regmap_config, + .clks = nss_cc_ipq5332_clocks, + .num_clks = ARRAY_SIZE(nss_cc_ipq5332_clocks), + .resets = nss_cc_ipq5332_resets, + .num_resets = ARRAY_SIZE(nss_cc_ipq5332_resets), +}; + +static const struct of_device_id nss_cc_ipq5332_match_table[] = { + { .compatible = "qcom,ipq5332-nsscc" }, + { } +}; +MODULE_DEVICE_TABLE(of, nss_cc_ipq5332_match_table); + +static int nss_cc_ipq5332_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &nss_cc_ipq5332_desc); +} + +static struct platform_driver nss_cc_ipq5332_driver = { + .probe = nss_cc_ipq5332_probe, + .driver = { + .name = "qcom,ipq5332-nsscc", + .of_match_table = nss_cc_ipq5332_match_table, + }, +}; +module_platform_driver(nss_cc_ipq5332_driver); + +MODULE_DESCRIPTION("QTI NSS_CC MIAMI Driver"); +MODULE_LICENSE("GPL"); From patchwork Tue Nov 21 14:30:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13463289 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="bN4DxuyY" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D74E1707; Tue, 21 Nov 2023 06:32:33 -0800 (PST) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3ALE2DBW003193; Tue, 21 Nov 2023 14:32:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=pVNEr0Q9vRdjhIb5bJsONpiWNzmfdgAMPP5B4cuQpCM=; b=bN4DxuyYJp74ZpjdUzf0WzciMcJLGCy2Dpjt/IKz1zDRDuToaEoy5PlcOEjvtacs3sQB mqThR9aWAAQr0cfoZ4YukMKWAOgvPEMuXd7qf0RhTFEwH8nREX1ikoojHAqthuRIZaAg YrNyysSOZzx7qWdBSJC11NDpVyWc3XC/6ICK0b/1PzP+sgbzop4Agiqbjm1anAGsPSlC lOVNWPI6ntTMD9nMlDfABogF9UNwowGK0q9Ph7GPaqDCP8Zmm36bEj7kk9cHS6TuQO5g Nqye65Qc1gdcTzQ66fm60a50p2KzHOWyTicic94PgYOvYoVtnLFP/d31ll3HuoFZVwfT 2Q== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ugu548vrc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); 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Signed-off-by: Kathiravan Thirumoorthy --- Changes in V2: - Update the node names with proper suffix --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 42e2e48b2bc3..5cbe72f03869 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -15,6 +15,18 @@ / { #size-cells = <2>; clocks { + cmn_pll_nss_200m_clk: cmn-pll-nss-200m-clk { + compatible = "fixed-clock"; + clock-frequency = <200000000>; + #clock-cells = <0>; + }; + + cmn_pll_nss_300m_clk: cmn-pll-nss-300m-clk { + compatible = "fixed-clock"; + clock-frequency = <300000000>; + #clock-cells = <0>; + }; + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -473,6 +485,22 @@ frame@b128000 { status = "disabled"; }; }; + + nsscc: clock-controller@39b00000{ + compatible = "qcom,ipq5332-nsscc"; + reg = <0x39b00000 0x80000>; + clocks = <&cmn_pll_nss_200m_clk>, + <&cmn_pll_nss_300m_clk>, + <&gcc GPLL0_OUT_AUX>, + <0>, + <0>, + <0>, + <0>, + <&xo_board>; + #clock-cells = <0x1>; + #reset-cells = <0x1>; + #power-domain-cells = <1>; + }; }; timer { From patchwork Tue Nov 21 14:30:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13463278 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="KBnYgtro" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBBC810C1; Tue, 21 Nov 2023 06:32:07 -0800 (PST) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3ALE1vW7001454; Tue, 21 Nov 2023 14:31:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; 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Tue, 21 Nov 2023 06:31:53 -0800 From: Kathiravan Thirumoorthy Date: Tue, 21 Nov 2023 20:00:51 +0530 Subject: [PATCH v2 9/9] arm64: defconfig: build NSS Clock Controller driver for Qualcomm IPQ5332 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20231121-ipq5332-nsscc-v2-9-a7ff61beab72@quicinc.com> References: <20231121-ipq5332-nsscc-v2-0-a7ff61beab72@quicinc.com> In-Reply-To: <20231121-ipq5332-nsscc-v2-0-a7ff61beab72@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Catalin Marinas , Will Deacon CC: , , , , , , "Kathiravan Thirumoorthy" X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1700577061; l=805; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=54GjomXoINQC2+jck1NY8lQcoGQ3H3dg5VLy6r9f7v8=; b=qtiSiG6/ytLPi4jSYosubQcrYCO/OjmO+6XTNRYmPucsoe41vg0IbI/fzwE8K3PLv+OS+SkKm 6qA6vBMLHK1B3n3m9/oLhyFhRYzSRgvNflBnuYQPnAXuFPoNcsmqviW X-Developer-Key: i=quic_kathirav@quicinc.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: efM3ZfnufRw-eUs0oOtmqjB7JaQES_8s X-Proofpoint-GUID: efM3ZfnufRw-eUs0oOtmqjB7JaQES_8s X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-21_07,2023-11-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 phishscore=0 bulkscore=0 clxscore=1015 mlxlogscore=851 mlxscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311210114 NSSCC driver is needed to enable the ethernet interfaces and not necessary for the bootup of the SoC, hence build it as a module. Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Krzysztof Kozlowski --- Changes in V2: - Repharse the commit message to indicate why driver should be built as m. --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index b60aa1f89343..c075202d255d 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1223,6 +1223,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_QCOM_CLK_RPMH=y CONFIG_IPQ_APSS_6018=y CONFIG_IPQ_GCC_5332=y +CONFIG_IPQ_NSSCC_5332=m CONFIG_IPQ_APSS_5018=y CONFIG_IPQ_GCC_5018=y CONFIG_IPQ_GCC_6018=y