From patchwork Wed Nov 22 05:30:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Manne, Nava kishore" X-Patchwork-Id: 13463982 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="AwyouEut" Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2060.outbound.protection.outlook.com [40.107.101.60]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8DC77D52; Tue, 21 Nov 2023 21:31:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Orqd/4qqg5Jlav9M8CWpdryhfdqz1yjSgNFgkQNmZOXjq8IOdO5xfcl4fW9LB+Q3makHp3MZcCfnAA/dTlPgP6/zNdtPk2nEiA2Nt+L46BL8sb7d7y9kVGNN9JI1/R6dEmHMo7pZchFx7CRiKFpoMZtd6oVpi6abhDVWNFd0Aovw6kE1p+tKKJrGxyWHvijxi3OWjABGwMEtKYNKt1Ufqez3RjWVe/5AvIihlkXGdK8Od6hdYB5bjraMOiQkfVz7ei+SfbGMrRaGSZpAnd65SrxwTb4Yn4i8M1nVvWYQkAvd6p7nsMn37Xam/UbBxwar0i0pAlZDrPrelrhv0PMYXQ== ARC-Message-Signature: i=1; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB4B.mail.protection.outlook.com (10.167.242.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7025.12 via Frontend Transport; Wed, 22 Nov 2023 05:31:06 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 21 Nov 2023 23:31:03 -0600 From: Nava kishore Manne To: , , , , , , , , , , Subject: [RFC 1/2] fpga: support loading from a pre-allocated buffer Date: Wed, 22 Nov 2023 11:00:34 +0530 Message-ID: <20231122053035.3758124-2-nava.kishore.manne@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231122053035.3758124-1-nava.kishore.manne@amd.com> References: <20231122053035.3758124-1-nava.kishore.manne@amd.com> Precedence: bulk X-Mailing-List: linux-fpga@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4B:EE_|MN0PR12MB6152:EE_ X-MS-Office365-Filtering-Correlation-Id: c32917b5-97a4-4cf8-7a89-08dbeb1c39a3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Nov 2023 05:31:06.1215 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c32917b5-97a4-4cf8-7a89-08dbeb1c39a3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6152 Some systems are memory constrained but they need to load very large Configuration files. The FPGA subsystem allows drivers to request this Configuration image be loaded from the filesystem, but this requires that the entire configuration data be loaded into kernel memory first before it's provided to the driver. This can lead to a situation where we map the configuration data twice, once to load the configuration data into kernel memory and once to copy the configuration data into the final resting place which is nothing but a dma-able continuous buffer. This creates needless memory pressure and delays due to multiple copies. Let's add a dmabuf handling support to the fpga manager framework that allows drivers to load the Configuration data directly from a pre-allocated buffer. This skips the intermediate step of allocating a buffer in kernel memory to hold the Configuration data. Signed-off-by: Nava kishore Manne --- drivers/fpga/fpga-mgr.c | 113 ++++++++++++++++++++++++++++++++++ include/linux/fpga/fpga-mgr.h | 10 +++ 2 files changed, 123 insertions(+) diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c index 06651389c592..23d2b4d45827 100644 --- a/drivers/fpga/fpga-mgr.c +++ b/drivers/fpga/fpga-mgr.c @@ -8,6 +8,8 @@ * With code from the mailing list: * Copyright (C) 2013 Xilinx, Inc. */ +#include +#include #include #include #include @@ -519,6 +521,39 @@ static int fpga_mgr_buf_load(struct fpga_manager *mgr, return rc; } +static int fpga_dmabuf_load(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + struct dma_buf_attachment *attach; + struct sg_table *sgt; + int ret; + + /* create attachment for dmabuf with the user device */ + attach = dma_buf_attach(mgr->dmabuf, &mgr->dev); + if (IS_ERR(attach)) { + pr_err("failed to attach dmabuf\n"); + ret = PTR_ERR(attach); + goto fail_put; + } + + sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); + if (IS_ERR(sgt)) { + ret = PTR_ERR(sgt); + goto fail_detach; + } + + info->sgt = sgt; + ret = fpga_mgr_buf_load_sg(mgr, info, info->sgt); + dma_buf_unmap_attachment(attach, sgt, DMA_BIDIRECTIONAL); + +fail_detach: + dma_buf_detach(mgr->dmabuf, attach); +fail_put: + dma_buf_put(mgr->dmabuf); + + return ret; +} + /** * fpga_mgr_firmware_load - request firmware and load to fpga * @mgr: fpga manager @@ -573,6 +608,8 @@ int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info) { info->header_size = mgr->mops->initial_header_size; + if (mgr->flags & FPGA_MGR_CONFIG_DMA_BUF) + return fpga_dmabuf_load(mgr, info); if (info->sgt) return fpga_mgr_buf_load_sg(mgr, info, info->sgt); if (info->buf && info->count) @@ -732,6 +769,64 @@ void fpga_mgr_put(struct fpga_manager *mgr) } EXPORT_SYMBOL_GPL(fpga_mgr_put); +static int fpga_dmabuf_fd_get(struct file *file, char __user *argp) +{ + struct fpga_manager *mgr = (struct fpga_manager *)(file->private_data); + int buffd; + + if (copy_from_user(&buffd, argp, sizeof(buffd))) + return -EFAULT; + + mgr->dmabuf = dma_buf_get(buffd); + if (IS_ERR_OR_NULL(mgr->dmabuf)) + return -EINVAL; + + mgr->flags = FPGA_MGR_CONFIG_DMA_BUF; + + return 0; +} + +static int fpga_device_open(struct inode *inode, struct file *file) +{ + struct miscdevice *miscdev = file->private_data; + struct fpga_manager *mgr = container_of(miscdev, + struct fpga_manager, miscdev); + + file->private_data = mgr; + + return 0; +} + +static int fpga_device_release(struct inode *inode, struct file *file) +{ + return 0; +} + +static long fpga_device_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + char __user *argp = (char __user *)arg; + int err; + + switch (cmd) { + case FPGA_IOCTL_LOAD_DMA_BUFF: + err = fpga_dmabuf_fd_get(file, argp); + break; + default: + err = -ENOTTY; + } + + return err; +} + +static const struct file_operations fpga_fops = { + .owner = THIS_MODULE, + .open = fpga_device_open, + .release = fpga_device_release, + .unlocked_ioctl = fpga_device_ioctl, + .compat_ioctl = fpga_device_ioctl, +}; + /** * fpga_mgr_lock - Lock FPGA manager for exclusive use * @mgr: fpga manager @@ -815,10 +910,28 @@ fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *in mgr->dev.of_node = parent->of_node; mgr->dev.id = id; + /* Make device dma capable by inheriting from parent's */ + set_dma_ops(&mgr->dev, get_dma_ops(parent)); + ret = dma_coerce_mask_and_coherent(&mgr->dev, dma_get_mask(parent)); + if (ret) { + dev_warn(parent, + "Failed to set DMA mask %llx. Trying to continue... %x\n", + dma_get_mask(parent), ret); + } + ret = dev_set_name(&mgr->dev, "fpga%d", id); if (ret) goto error_device; + mgr->miscdev.minor = MISC_DYNAMIC_MINOR; + mgr->miscdev.name = kobject_name(&mgr->dev.kobj); + mgr->miscdev.fops = &fpga_fops; + ret = misc_register(&mgr->miscdev); + if (ret) { + pr_err("fpga: failed to register misc device.\n"); + goto error_device; + } + /* * Initialize framework state by requesting low level driver read state * from device. FPGA may be in reset mode or may have been programmed diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h index 54f63459efd6..c5de19a9b4ed 100644 --- a/include/linux/fpga/fpga-mgr.h +++ b/include/linux/fpga/fpga-mgr.h @@ -9,6 +9,7 @@ #define _LINUX_FPGA_MGR_H #include +#include #include struct fpga_manager; @@ -77,6 +78,7 @@ enum fpga_mgr_states { #define FPGA_MGR_ENCRYPTED_BITSTREAM BIT(2) #define FPGA_MGR_BITSTREAM_LSB_FIRST BIT(3) #define FPGA_MGR_COMPRESSED_BITSTREAM BIT(4) +#define FPGA_MGR_CONFIG_DMA_BUF BIT(5) /** * struct fpga_image_info - information specific to an FPGA image @@ -197,7 +199,10 @@ struct fpga_manager_ops { * struct fpga_manager - fpga manager structure * @name: name of low level fpga manager * @dev: fpga manager device + * @flags: flags determines the type of Bitstream + * @dmabuf: shared dma buffer * @ref_mutex: only allows one reference to fpga manager + * @miscdev: information about character device node * @state: state of fpga manager * @compat_id: FPGA manager id for compatibility check. * @mops: pointer to struct of fpga manager ops @@ -206,7 +211,10 @@ struct fpga_manager_ops { struct fpga_manager { const char *name; struct device dev; + unsigned long flags; + struct dma_buf *dmabuf; struct mutex ref_mutex; + struct miscdevice miscdev; enum fpga_mgr_states state; struct fpga_compat_id *compat_id; const struct fpga_manager_ops *mops; @@ -244,4 +252,6 @@ struct fpga_manager * devm_fpga_mgr_register(struct device *parent, const char *name, const struct fpga_manager_ops *mops, void *priv); +#define FPGA_IOCTL_LOAD_DMA_BUFF _IOWR('R', 1, __u32) + #endif /*_LINUX_FPGA_MGR_H */ From patchwork Wed Nov 22 05:30:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Manne, Nava kishore" X-Patchwork-Id: 13463983 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="Om6VUEwT" Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2085.outbound.protection.outlook.com [40.107.96.85]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FB5C1BC; Tue, 21 Nov 2023 21:31:12 -0800 (PST) ARC-Seal: i=1; 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Wed, 22 Nov 2023 05:31:09 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB4B.mail.protection.outlook.com (10.167.242.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7025.12 via Frontend Transport; Wed, 22 Nov 2023 05:31:09 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 21 Nov 2023 23:31:07 -0600 From: Nava kishore Manne To: , , , , , , , , , , Subject: [RFC 2/2] fpga: versal: Use the scatterlist interface Date: Wed, 22 Nov 2023 11:00:35 +0530 Message-ID: <20231122053035.3758124-3-nava.kishore.manne@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231122053035.3758124-1-nava.kishore.manne@amd.com> References: <20231122053035.3758124-1-nava.kishore.manne@amd.com> Precedence: bulk X-Mailing-List: linux-fpga@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4B:EE_|SJ1PR12MB6121:EE_ X-MS-Office365-Filtering-Correlation-Id: c6e237e2-dc7b-424d-b4a5-08dbeb1c3b63 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Nov 2023 05:31:09.0590 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c6e237e2-dc7b-424d-b4a5-08dbeb1c3b63 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6121 Allows drivers to request the Configuration image be loaded from dma-able continuous buffer to avoid needless memory pressure and delays due to multiple copies. Signed-off-by: Nava kishore Manne --- drivers/fpga/versal-fpga.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c index 3710e8f01be2..bf4fb4426417 100644 --- a/drivers/fpga/versal-fpga.c +++ b/drivers/fpga/versal-fpga.c @@ -19,6 +19,18 @@ static int versal_fpga_ops_write_init(struct fpga_manager *mgr, return 0; } +static int versal_fpga_ops_write_sg(struct fpga_manager *mgr, + struct sg_table *sgt) +{ + dma_addr_t dma_addr; + int ret; + + dma_addr = sg_dma_address(sgt->sgl); + ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr); + + return ret; +} + static int versal_fpga_ops_write(struct fpga_manager *mgr, const char *buf, size_t size) { @@ -40,6 +52,7 @@ static int versal_fpga_ops_write(struct fpga_manager *mgr, static const struct fpga_manager_ops versal_fpga_ops = { .write_init = versal_fpga_ops_write_init, .write = versal_fpga_ops_write, + .write_sg = versal_fpga_ops_write_sg, }; static int versal_fpga_probe(struct platform_device *pdev)