From patchwork Wed Nov 22 08:46:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 13464238 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3CF4AC61D92 for ; Wed, 22 Nov 2023 08:49:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=yqWOz0mXip2eVKU7t81nRJpkoKY3MV42M9u+KkzCIos=; b=ndEuCEZ4QGfYPf thIag+0vm8fVr51oV86grvHqE33WuUjgzBung0KnFTmNmn9uXX1CNQLpLzOD1FQlM0iaaAgYudD+i 7m2G5gpY976yvDaRd0rJWVi+sne3pHC1hV32mfiOMIlqRauGdcwO5wtaMP3lzMIQIn2W/KRWSFVtq gpsY/okFiN0k1S/TsTSfrIocSRdRBROC6zLskTuvCw9sneaKSy9vbE5yrSvr1I6nOb/2ylWxbGoqh jeh/J82aQEosRc1t6cq9pHyUqIiT3aEEmM0tSHVZOxAURWgDiv6hKNPwO+4HA68sktkG1kb5z1bvN y6KOg24Bn8nuVYoZQzAA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r5ivK-0016RX-2p; Wed, 22 Nov 2023 08:49:30 +0000 Received: from szxga01-in.huawei.com ([45.249.212.187]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r5ivG-0016Pj-0K for linux-arm-kernel@lists.infradead.org; Wed, 22 Nov 2023 08:49:28 +0000 Received: from canpemm500009.china.huawei.com (unknown [172.30.72.57]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4SZvwG6XcQzsRFQ; Wed, 22 Nov 2023 16:45:50 +0800 (CST) Received: from localhost.localdomain (10.50.165.33) by canpemm500009.china.huawei.com (7.192.105.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 22 Nov 2023 16:49:20 +0800 From: Yicong Yang To: , , , , , , CC: , , , , , Subject: [PATCH 1/3] arm64/sysreg: Add PMSCR_EL12 and factor out the common fields Date: Wed, 22 Nov 2023 16:46:00 +0800 Message-ID: <20231122084602.53914-2-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20231122084602.53914-1-yangyicong@huawei.com> References: <20231122084602.53914-1-yangyicong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.50.165.33] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To canpemm500009.china.huawei.com (7.192.105.203) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231122_004926_458433_DD2F708C X-CRM114-Status: GOOD ( 13.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yicong Yang Add PMSCR_EL12 for accessing PMSCR_EL1 from EL2. Since PMSCR_EL12 and PMSCR_EL1 share the same definition of the fields, define a common PMSCR_EL1x for both. Update the field name used in the driver accordingly. Signed-off-by: Yicong Yang Reviewed-by: Mark Brown --- arch/arm64/tools/sysreg | 10 +++++++++- drivers/perf/arm_spe_pmu.c | 20 ++++++++++---------- 2 files changed, 19 insertions(+), 11 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 96cbeeab4eec..b64278e1ed54 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1800,7 +1800,7 @@ Sysreg FAR_EL1 3 0 6 0 0 Field 63:0 ADDR EndSysreg -Sysreg PMSCR_EL1 3 0 9 9 0 +SysregFields PMSCR_EL1x Res0 63:8 Field 7:6 PCT Field 5 TS @@ -1809,6 +1809,14 @@ Field 3 CX Res0 2 Field 1 E1SPE Field 0 E0SPE +EndSysregFields + +Sysreg PMSCR_EL1 3 0 9 9 0 +Fields PMSCR_EL1x +EndSysreg + +Sysreg PMSCR_EL12 3 5 9 9 0 +Fields PMSCR_EL1x EndSysreg Sysreg PMSNEVFR_EL1 3 0 9 9 1 diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index d2b0cbf0e0c4..05647cfff61d 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -172,13 +172,13 @@ static const struct attribute_group arm_spe_pmu_cap_group = { }; /* User ABI */ -#define ATTR_CFG_FLD_ts_enable_CFG config /* PMSCR_EL1.TS */ +#define ATTR_CFG_FLD_ts_enable_CFG config /* PMSCR_EL1x.TS */ #define ATTR_CFG_FLD_ts_enable_LO 0 #define ATTR_CFG_FLD_ts_enable_HI 0 -#define ATTR_CFG_FLD_pa_enable_CFG config /* PMSCR_EL1.PA */ +#define ATTR_CFG_FLD_pa_enable_CFG config /* PMSCR_EL1x.PA */ #define ATTR_CFG_FLD_pa_enable_LO 1 #define ATTR_CFG_FLD_pa_enable_HI 1 -#define ATTR_CFG_FLD_pct_enable_CFG config /* PMSCR_EL1.PCT */ +#define ATTR_CFG_FLD_pct_enable_CFG config /* PMSCR_EL1x.PCT */ #define ATTR_CFG_FLD_pct_enable_LO 2 #define ATTR_CFG_FLD_pct_enable_HI 2 #define ATTR_CFG_FLD_jitter_CFG config /* PMSIRR_EL1.RND */ @@ -303,18 +303,18 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *event) struct perf_event_attr *attr = &event->attr; u64 reg = 0; - reg |= FIELD_PREP(PMSCR_EL1_TS, ATTR_CFG_GET_FLD(attr, ts_enable)); - reg |= FIELD_PREP(PMSCR_EL1_PA, ATTR_CFG_GET_FLD(attr, pa_enable)); - reg |= FIELD_PREP(PMSCR_EL1_PCT, ATTR_CFG_GET_FLD(attr, pct_enable)); + reg |= FIELD_PREP(PMSCR_EL1x_TS, ATTR_CFG_GET_FLD(attr, ts_enable)); + reg |= FIELD_PREP(PMSCR_EL1x_PA, ATTR_CFG_GET_FLD(attr, pa_enable)); + reg |= FIELD_PREP(PMSCR_EL1x_PCT, ATTR_CFG_GET_FLD(attr, pct_enable)); if (!attr->exclude_user) - reg |= PMSCR_EL1_E0SPE; + reg |= PMSCR_EL1x_E0SPE; if (!attr->exclude_kernel) - reg |= PMSCR_EL1_E1SPE; + reg |= PMSCR_EL1x_E1SPE; if (get_spe_event_has_cx(event)) - reg |= PMSCR_EL1_CX; + reg |= PMSCR_EL1x_CX; return reg; } @@ -768,7 +768,7 @@ static int arm_spe_pmu_event_init(struct perf_event *event) set_spe_event_has_cx(event); reg = arm_spe_event_to_pmscr(event); if (!perfmon_capable() && - (reg & (PMSCR_EL1_PA | PMSCR_EL1_PCT))) + (reg & (PMSCR_EL1x_PA | PMSCR_EL1x_PCT))) return -EACCES; return 0; From patchwork Wed Nov 22 08:46:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 13464241 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99D3EC072A2 for ; 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Wed, 22 Nov 2023 08:49:38 +0000 Received: from szxga01-in.huawei.com ([45.249.212.187]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r5ivH-0016Pr-0A for linux-arm-kernel@lists.infradead.org; Wed, 22 Nov 2023 08:49:29 +0000 Received: from canpemm500009.china.huawei.com (unknown [172.30.72.54]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4SZvzr3w0SzvR37; Wed, 22 Nov 2023 16:48:56 +0800 (CST) Received: from localhost.localdomain (10.50.165.33) by canpemm500009.china.huawei.com (7.192.105.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 22 Nov 2023 16:49:20 +0800 From: Yicong Yang To: , , , , , , CC: , , , , , Subject: [PATCH 2/3] perf: arm_spe: Factor out PMSCR set/clear operations Date: Wed, 22 Nov 2023 16:46:01 +0800 Message-ID: <20231122084602.53914-3-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20231122084602.53914-1-yangyicong@huawei.com> References: <20231122084602.53914-1-yangyicong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.50.165.33] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To canpemm500009.china.huawei.com (7.192.105.203) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231122_004927_411335_8F94D86F X-CRM114-Status: GOOD ( 12.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yicong Yang Currently we convert the user settings to PMSCR config in arm_spe_event_to_pmscr() and set/clear the PMSCR register separately. It blocks further extension for filtering the exception level. So Factor out PMSCR set/clear operatons into separate function and only configure the ELx filtering when setting the register. Signed-off-by: Yicong Yang --- drivers/perf/arm_spe_pmu.c | 31 ++++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 05647cfff61d..09570d4d63cd 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -297,7 +297,7 @@ static const struct attribute_group *arm_spe_pmu_attr_groups[] = { NULL, }; -/* Convert between user ABI and register values */ +/* Convert between user ABI and register values, except the exception control */ static u64 arm_spe_event_to_pmscr(struct perf_event *event) { struct perf_event_attr *attr = &event->attr; @@ -307,16 +307,32 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *event) reg |= FIELD_PREP(PMSCR_EL1x_PA, ATTR_CFG_GET_FLD(attr, pa_enable)); reg |= FIELD_PREP(PMSCR_EL1x_PCT, ATTR_CFG_GET_FLD(attr, pct_enable)); + if (get_spe_event_has_cx(event)) + reg |= PMSCR_EL1x_CX; + + return reg; +} + +static void arm_spe_pmu_set_pmscr(struct perf_event *event) +{ + struct perf_event_attr *attr = &event->attr; + u64 reg = 0; + + reg = arm_spe_event_to_pmscr(event); if (!attr->exclude_user) reg |= PMSCR_EL1x_E0SPE; if (!attr->exclude_kernel) reg |= PMSCR_EL1x_E1SPE; - if (get_spe_event_has_cx(event)) - reg |= PMSCR_EL1x_CX; + isb(); + write_sysreg_s(reg, SYS_PMSCR_EL1); +} - return reg; +static void arm_spe_pmu_clr_pmscr(void) +{ + write_sysreg_s(0, SYS_PMSCR_EL1); + isb(); } static void arm_spe_event_sanitise_period(struct perf_event *event) @@ -566,8 +582,7 @@ static void arm_spe_perf_aux_output_end(struct perf_output_handle *handle) static void arm_spe_pmu_disable_and_drain_local(void) { /* Disable profiling at EL0 and EL1 */ - write_sysreg_s(0, SYS_PMSCR_EL1); - isb(); + arm_spe_pmu_clr_pmscr(); /* Drain any buffered data */ psb_csync(); @@ -808,9 +823,7 @@ static void arm_spe_pmu_start(struct perf_event *event, int flags) write_sysreg_s(reg, SYS_PMSICR_EL1); } - reg = arm_spe_event_to_pmscr(event); - isb(); - write_sysreg_s(reg, SYS_PMSCR_EL1); + arm_spe_pmu_set_pmscr(event); } static void arm_spe_pmu_stop(struct perf_event *event, int flags) From patchwork Wed Nov 22 08:46:02 2023 Content-Type: text/plain; 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Wed, 22 Nov 2023 16:49:20 +0800 From: Yicong Yang To: , , , , , , CC: , , , , , Subject: [PATCH 3/3] perf: arm_spe: Enable the profiling of EL0&1 translation regime Date: Wed, 22 Nov 2023 16:46:02 +0800 Message-ID: <20231122084602.53914-4-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20231122084602.53914-1-yangyicong@huawei.com> References: <20231122084602.53914-1-yangyicong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.50.165.33] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To canpemm500009.china.huawei.com (7.192.105.203) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231122_004929_884939_B2D40AAD X-CRM114-Status: GOOD ( 13.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yicong Yang On a VHE enabled host, the PMSCR_EL1 will be redirect to PMSCR_EL2 and we're actually enabling E0SPE and E2SPE in the driver. This means the data from EL0&1 translation regime of a VM will not be profiled. So this patch tries to add the support of profiling EL0 and EL1 of a VM. Users can filter data of different exception level by using the perf's exclude_* attributes. The exclude_* decision is referred to Documentation/arch/arm64/perf.rst and the implementation of arm_pmuv3. Signed-off-by: Yicong Yang --- drivers/perf/arm_spe_pmu.c | 37 ++++++++++++++++++++++++++++++------- 1 file changed, 30 insertions(+), 7 deletions(-) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 09570d4d63cd..a647d625f359 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -316,21 +316,44 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *event) static void arm_spe_pmu_set_pmscr(struct perf_event *event) { struct perf_event_attr *attr = &event->attr; - u64 reg = 0; + u64 pmscr_el1, pmscr_el12; - reg = arm_spe_event_to_pmscr(event); - if (!attr->exclude_user) - reg |= PMSCR_EL1x_E0SPE; + pmscr_el1 = pmscr_el12 = arm_spe_event_to_pmscr(event); + + /* + * Map the exclude_* descision to ELx according to + * Documentation/arch/arm64/perf.rst. + */ + if (is_kernel_in_hyp_mode()) { + if (!attr->exclude_kernel && !attr->exclude_host) + pmscr_el1 |= PMSCR_EL1x_E1SPE; - if (!attr->exclude_kernel) - reg |= PMSCR_EL1x_E1SPE; + if (!attr->exclude_kernel && !attr->exclude_guest) + pmscr_el12 |= PMSCR_EL1x_E1SPE; + + if (!attr->exclude_user && !attr->exclude_host) { + pmscr_el1 |= PMSCR_EL1x_E0SPE; + pmscr_el12 |= PMSCR_EL1x_E0SPE; + } + } else { + if (!attr->exclude_kernel) + pmscr_el1 |= PMSCR_EL1x_E1SPE; + + if (!attr->exclude_user) + pmscr_el1 |= PMSCR_EL1x_E0SPE; + } isb(); - write_sysreg_s(reg, SYS_PMSCR_EL1); + write_sysreg_s(pmscr_el1, SYS_PMSCR_EL1); + if (is_kernel_in_hyp_mode()) + write_sysreg_s(pmscr_el12, SYS_PMSCR_EL12); } static void arm_spe_pmu_clr_pmscr(void) { + if (is_kernel_in_hyp_mode()) + write_sysreg_s(0, SYS_PMSCR_EL12); + write_sysreg_s(0, SYS_PMSCR_EL1); isb(); }