From patchwork Thu Nov 23 14:02:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13466291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB2A7C61DF7 for ; Thu, 23 Nov 2023 14:08:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 333D610E75B; Thu, 23 Nov 2023 14:08:03 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id BCFDF10E75B for ; Thu, 23 Nov 2023 14:08:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700748480; x=1732284480; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zOc1Db8jybgJ8BxBbq79OMfSWmQYOYmGai28Q1spsdc=; b=cRDAaaLrMdsOPJtH+A79JWxriSd/SQ2GPg9leTkZCuO6BBiJaUK6vv1J NEFjlD6Ug+RDdlTA6Oh8kIwfcr+XAYNAb8XJNEfQNPOscRDfOSsT3tCBj hYnHgKTI2cZTpFT6zh+CP+H2pZzZvVdikI9vwuxhIH5DhApZKakisUCPV p1EqbdJ/bqUWOA3Wdh/++RFZ1f+6FF6d+l9Bhag7I1z2OsPRW/6HAQA2v kwmHlScJe32jPW3n31ROUEp6LkBRm5hGfLmm8hvEXZG5xVFkORO0jer6S V5HPFDS7uf1f/SWF6xxMH0B3DG6pOybPj4CWv46penDfkkJRUvzzMpFgG g==; X-IronPort-AV: E=McAfee;i="6600,9927,10902"; a="5418516" X-IronPort-AV: E=Sophos;i="6.04,221,1695711600"; d="scan'208";a="5418516" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2023 06:07:54 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10902"; a="767213029" X-IronPort-AV: E=Sophos;i="6.04,221,1695711600"; d="scan'208";a="767213029" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orsmga002.jf.intel.com with ESMTP; 23 Nov 2023 06:07:52 -0800 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Date: Thu, 23 Nov 2023 19:32:42 +0530 Message-Id: <20231123140244.4183869-2-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231123140244.4183869-1-mitulkumar.ajitkumar.golani@intel.com> References: <20231123140244.4183869-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/3] drm: Add Adaptive Sync SDP logging X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add structure representing Adaptive Sync Secondary Data Packet (AS SDP). Also, add Adaptive Sync SDP logging in drm_dp_helper.c to facilitate debugging. Signed-off-by: Mitul Golani --- drivers/gpu/drm/display/drm_dp_helper.c | 15 +++++++++++++ include/drm/display/drm_dp.h | 1 + include/drm/display/drm_dp_helper.h | 30 +++++++++++++++++++++++++ 3 files changed, 46 insertions(+) diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c index d72b6f9a352c..a205e14a6681 100644 --- a/drivers/gpu/drm/display/drm_dp_helper.c +++ b/drivers/gpu/drm/display/drm_dp_helper.c @@ -2917,6 +2917,21 @@ void drm_dp_vsc_sdp_log(const char *level, struct device *dev, } EXPORT_SYMBOL(drm_dp_vsc_sdp_log); +void drm_dp_as_sdp_log(const char *level, struct device *dev, + const struct drm_dp_as_sdp *async) +{ +#define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__) + DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC", + async->revision, async->length); + DP_SDP_LOG(" vmin: %d vmax: %d\n", async->vmin, async->vmax); + DP_SDP_LOG(" target_rr: %s\n", async->target_rr); + DP_SDP_LOG(" duration_incr_ms: %u\n", async->duration_incr_ms); + DP_SDP_LOG(" duration_decr_ms: %u\n", async->duration_decr_ms); + DP_SDP_LOG(" operation_mode: %u\n", async->operation_mode); +#undef DP_SDP_LOG +} +EXPORT_SYMBOL(drm_dp_as_sdp_log); + /** * drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON * @dpcd: DisplayPort configuration data diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 83d2039c018b..0575ab8ea088 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -1578,6 +1578,7 @@ enum drm_dp_phy { #define DP_SDP_PPS 0x10 /* DP 1.4 */ #define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */ #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */ +#define DP_SDP_ADAPTIVE_SYNC 0x22 /* DP 1.4 */ /* 0x80+ CEA-861 infoframe types */ #define DP_SDP_AUDIO_INFOFRAME_HB2 0x1b diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h index 863b2e7add29..63b6bef3f21d 100644 --- a/include/drm/display/drm_dp_helper.h +++ b/include/drm/display/drm_dp_helper.h @@ -98,6 +98,36 @@ struct drm_dp_vsc_sdp { enum dp_content_type content_type; }; +/** + * struct drm_dp_as_sdp - drm DP Adaptive Sync SDP + * + * This structure represents a DP AS SDP of drm + * It is based on DP 2.1 spec [Table 2-126: Adaptive-Sync SDP Header Bytes] and + * [Table 2-127: Adaptive-Sync SDP Payload for DB0 through DB8] + * + * @sdp_type: secondary-data packet type + * @length: number of valid data bytes + * @vmin: minimum vtotal + * @vmax: maximum vtotal + * @duration_incr_ms: Successive frame duration increase + * @duration_decr_ms: Successive frame duration decrease + * @operation_mode: Adaptive Sync Operation Mode + */ + +struct drm_dp_as_sdp { + unsigned char sdp_type; + unsigned char revision; + unsigned char length; + u16 vmin, vmax; + u16 target_rr; + u8 duration_incr_ms; + u8 duration_decr_ms; + u8 operation_mode; +}; + +void drm_dp_as_sdp_log(const char *level, struct device *dev, + const struct drm_dp_as_sdp *async); + void drm_dp_vsc_sdp_log(const char *level, struct device *dev, const struct drm_dp_vsc_sdp *vsc); From patchwork Thu Nov 23 14:02:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13466293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1A95FC61DF7 for ; Thu, 23 Nov 2023 14:08:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8378110E769; Thu, 23 Nov 2023 14:08:11 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id E1F7110E75B for ; Thu, 23 Nov 2023 14:08:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700748482; x=1732284482; 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23 Nov 2023 06:07:55 -0800 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Date: Thu, 23 Nov 2023 19:32:43 +0530 Message-Id: <20231123140244.4183869-3-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231123140244.4183869-1-mitulkumar.ajitkumar.golani@intel.com> References: <20231123140244.4183869-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/3] drm/i915/display/: Add Read/Write support for Adaptive Sync SDP X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add the necessary structures and functions to handle reading and unpacking Adaptive Sync Secondary Data Packets. Also add support to write and pack AS SDP. Signed-off-by: Mitul Golani --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 118 +++++++++++++++++- 2 files changed, 114 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 9a44350ba05d..7d87923f63af 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1325,6 +1325,7 @@ struct intel_crtc_state { union hdmi_infoframe hdmi; union hdmi_infoframe drm; struct drm_dp_vsc_sdp vsc; + struct drm_dp_as_sdp async; } infoframes; u8 eld[MAX_ELD_BYTES]; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 1422c2370269..39624746d612 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -94,6 +94,8 @@ #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) +#define AS_SDP_ENABLE REG_BIT(2) +#define AS_SDP_OP_MODE REG_GENMASK(1, 0) /* Constants for DP DSC configurations */ static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; @@ -4113,6 +4115,42 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, return false; } +static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *async, + struct dp_sdp *sdp, size_t size) +{ + size_t length = sizeof(struct dp_sdp); + + if (size < length) + return -ENOSPC; + + memset(sdp, 0, size); + + /* Prepare AS (Adaptive Sync) VSC Header */ + sdp->sdp_header.HB0 = 0; + sdp->sdp_header.HB1 = async->sdp_type; + sdp->sdp_header.HB2 = 0x02; + sdp->sdp_header.HB3 = async->length; + + /* Fill AS (Adaptive Sync) SDP Payload */ + if ((sdp->db[0] & 0x03) == 0) { + sdp->db[3] = 0; + sdp->db[4] &= 0xFC; + } + + sdp->db[1] = async->vmin & 0xFF; + sdp->db[2] = (async->vmin >> 8) & 0xF; + sdp->db[17] = (async->vmin >> 8) & 0xFF; + sdp->db[18] = async->vmax & 0xFF; + sdp->db[19] = (async->vmax >> 8) & 0xFF; + sdp->db[20] = async->target_rr & 0xFF; + sdp->db[21] = (async->target_rr >> 8) & 0xFF; + sdp->db[22] = async->duration_incr_ms; + sdp->db[23] = async->duration_decr_ms; + sdp->db[24] = async->operation_mode; + + return length; +} + static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, struct dp_sdp *sdp, size_t size) { @@ -4280,6 +4318,10 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder, &crtc_state->infoframes.drm.drm, &sdp, sizeof(sdp)); break; + case DP_SDP_ADAPTIVE_SYNC: + len = intel_dp_as_sdp_pack(&crtc_state->infoframes.async, &sdp, + sizeof(sdp)); + break; default: MISSING_CASE(type); return; @@ -4342,6 +4384,44 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); } +/* + * This function is to unpack AS SDP Packet + */ +static +int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *async, + const void *buffer, size_t size) +{ + const struct dp_sdp *sdp = buffer; + + if (size < sizeof(struct dp_sdp)) + return -EINVAL; + + memset(async, 0, sizeof(*async)); + + if (sdp->sdp_header.HB0 != 0) + return -EINVAL; + + if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC) + return -EINVAL; + + if (sdp->sdp_header.HB2 != 0x02) + return -EINVAL; + + if ((sdp->sdp_header.HB3 & 0x3F) != 9) + return -EINVAL; + + if (sdp->db[0] != (AS_SDP_ENABLE | AS_SDP_OP_MODE)) + return -EINVAL; + + async->vmin = ((u64)sdp->db[2] << 32) | (u64)sdp->db[1]; + async->vmax = 0; + async->target_rr = 0; + async->duration_incr_ms = 0; + async->duration_decr_ms = 0; + + return 0; +} + static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, const void *buffer, size_t size) { @@ -4412,12 +4492,35 @@ static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, return 0; } +/* + * This function to read registers to fetch packets + */ +static int +intel_read_dp_as_metadata_infoframe_sdp(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state, + struct drm_dp_as_sdp *async) +{ + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + unsigned int type = DP_SDP_ADAPTIVE_SYNC; + struct dp_sdp sdp = {}; + int ret; + + dig_port->read_infoframe(encoder, crtc_state, type, &sdp, + sizeof(sdp)); + + ret = intel_dp_as_sdp_unpack(async, &sdp, sizeof(sdp)); + if (ret) + drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP AS SDP\n"); + + return ret; +} + static int intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe, const void *buffer, size_t size) { int ret; - const struct dp_sdp *sdp = buffer; if (size < sizeof(struct dp_sdp)) @@ -4484,9 +4587,10 @@ static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder, drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n"); } -static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder, - struct intel_crtc_state *crtc_state, - struct hdmi_drm_infoframe *drm_infoframe) +static void +intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state, + struct hdmi_drm_infoframe *drm_infoframe) { struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -4495,7 +4599,7 @@ static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encod int ret; if ((crtc_state->infoframes.enable & - intel_hdmi_infoframe_enable(type)) == 0) + intel_hdmi_infoframe_enable(type)) == 0) return; dig_port->read_infoframe(encoder, crtc_state, type, &sdp, @@ -4522,6 +4626,10 @@ void intel_read_dp_sdp(struct intel_encoder *encoder, intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state, &crtc_state->infoframes.drm.drm); break; + case DP_SDP_ADAPTIVE_SYNC: + intel_read_dp_as_metadata_infoframe_sdp(encoder, crtc_state, + &crtc_state->infoframes.async); + break; default: MISSING_CASE(type); break; From patchwork Thu Nov 23 14:02:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13466292 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A2A27C5AD4C for ; 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X-IronPort-AV: E=McAfee;i="6600,9927,10902"; a="5418537" X-IronPort-AV: E=Sophos;i="6.04,221,1695711600"; d="scan'208";a="5418537" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2023 06:08:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10902"; a="767213097" X-IronPort-AV: E=Sophos;i="6.04,221,1695711600"; d="scan'208";a="767213097" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orsmga002.jf.intel.com with ESMTP; 23 Nov 2023 06:07:59 -0800 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Date: Thu, 23 Nov 2023 19:32:44 +0530 Message-Id: <20231123140244.4183869-4-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231123140244.4183869-1-mitulkumar.ajitkumar.golani@intel.com> References: <20231123140244.4183869-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/3] drm/i915/display/:Compute and enable daptive Sync SDP X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add necessary functions and register definitions to enable and compute AS SDP data. The new `intel_dp_compute_as_sdp` function computes AS SDP values based on the display configuration, ensuring proper handling of Variable Refresh Rate (VRR). Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_hdmi.c | 11 +++++++++-- drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ 3 files changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 39624746d612..b3eb2d342a99 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2629,6 +2629,26 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, &crtc_state->infoframes.vsc); } +static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state) +{ + struct drm_dp_as_sdp *async = &crtc_state->infoframes.async; + struct intel_connector *connector = intel_dp->attached_connector; + int vrefresh = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode); + + if (intel_vrr_is_in_range(connector, vrefresh)) + return; + + crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); + async->sdp_type = DP_SDP_ADAPTIVE_SYNC; + async->length = 0x9; + async->vmin = crtc_state->vrr.vmin; + async->vmax = crtc_state->vrr.vmax; + async->target_rr = 0; + async->operation_mode = 0x0; +} + void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state, @@ -2965,6 +2985,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, intel_psr_compute_config(intel_dp, pipe_config, conn_state); intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16); intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); + intel_dp_compute_as_sdp(intel_dp, pipe_config, conn_state); intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state); return 0; diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index ab18cfc19c0a..abea359985ce 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -136,6 +136,8 @@ static u32 hsw_infoframe_enable(unsigned int type) return VIDEO_DIP_ENABLE_GMP_HSW; case DP_SDP_VSC: return VIDEO_DIP_ENABLE_VSC_HSW; + case DP_SDP_ADAPTIVE_SYNC: + return VIDEO_DIP_ENABLE_AS_HSW; case DP_SDP_PPS: return VDIP_ENABLE_PPS; case HDMI_INFOFRAME_TYPE_AVI: @@ -163,6 +165,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv, return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); case DP_SDP_VSC: return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); + case DP_SDP_ADAPTIVE_SYNC: + return HSW_TVIDEO_DIP_ASYNC_DATA(cpu_transcoder, i); case DP_SDP_PPS: return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); case HDMI_INFOFRAME_TYPE_AVI: @@ -185,6 +189,8 @@ static int hsw_dip_data_size(struct drm_i915_private *dev_priv, switch (type) { case DP_SDP_VSC: return VIDEO_DIP_VSC_DATA_SIZE; + case DP_SDP_ADAPTIVE_SYNC: + return VIDEO_DIP_ASYNC_DATA_SIZE; case DP_SDP_PPS: return VIDEO_DIP_PPS_DATA_SIZE; case HDMI_PACKET_TYPE_GAMUT_METADATA: @@ -555,7 +561,8 @@ static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | - VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); + VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | + VIDEO_DIP_ENABLE_AS_HSW); if (DISPLAY_VER(dev_priv) >= 10) mask |= VIDEO_DIP_ENABLE_DRM_GLK; @@ -1209,7 +1216,7 @@ static void hsw_set_infoframes(struct intel_encoder *encoder, val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | - VIDEO_DIP_ENABLE_DRM_GLK); + VIDEO_DIP_ENABLE_DRM_GLK | VIDEO_DIP_ENABLE_AS_HSW); if (!enable) { intel_de_write(dev_priv, reg, val); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 27dc903f0553..81d64c428693 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2312,6 +2312,7 @@ * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte * of the infoframe structure specified by CEA-861. */ #define VIDEO_DIP_DATA_SIZE 32 +#define VIDEO_DIP_ASYNC_DATA_SIZE 32 #define VIDEO_DIP_GMP_DATA_SIZE 36 #define VIDEO_DIP_VSC_DATA_SIZE 36 #define VIDEO_DIP_PPS_DATA_SIZE 132 @@ -2344,6 +2345,7 @@ #define VSC_DIP_HW_DATA_SW_HEA (2 << 25) #define VSC_DIP_SW_HEA_DATA (3 << 25) #define VDIP_ENABLE_PPS (1 << 24) +#define VIDEO_DIP_ENABLE_AS_HSW REG_BIT(23) #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) @@ -5038,6 +5040,7 @@ #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 +#define _HSW_VIDEO_DIP_ASYNC_DATA_A 0x60484 #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 @@ -5052,6 +5055,7 @@ #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 +#define _HSW_VIDEO_DIP_ASYNC_DATA_B 0x61484 #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 @@ -5078,6 +5082,8 @@ #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) +#define HSW_TVIDEO_DIP_ASYNC_DATA(trans, i) _MMIO_TRANS2(trans,\ + _HSW_VIDEO_DIP_ASYNC_DATA_A + (i) * 4) #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)