From patchwork Fri Nov 24 01:45:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Xie X-Patchwork-Id: 13466870 X-Patchwork-Delegate: bhelgaas@google.com Authentication-Results: smtp.subspace.kernel.org; dkim=none Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E31B10C7; Thu, 23 Nov 2023 17:45:22 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id C27C924E245; Fri, 24 Nov 2023 09:45:14 +0800 (CST) Received: from EXMBX172.cuchost.com (172.16.6.92) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 24 Nov 2023 09:45:14 +0800 Received: from kevin-ThinkStation-P340.starfivetech.com (113.72.144.198) by EXMBX172.cuchost.com (172.16.6.92) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 24 Nov 2023 09:45:13 +0800 From: Kevin Xie To: Bjorn Helgaas CC: , , , , Subject: [PATCH v1] PCI: Add PCIE_CONFIG_REQUEST_WAIT_MS waiting time value Date: Fri, 24 Nov 2023 09:45:08 +0800 Message-ID: <20231124014508.43358-1-kevin.xie@starfivetech.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX172.cuchost.com (172.16.6.92) X-YovoleRuleAgent: yovoleflag Add the PCIE_CONFIG_REQUEST_WAIT_MS marco to define the minimum waiting time between sending the first configuration request to the device and exit from a conventional reset (or after link training completes). As described in the conventional reset rules of PCI specifications, there are two different use cases of the value: - With a downstream port that supports link speeds <= 5.0 GT/s, the waiting is following exit from a conventional reset. - With a downstream port that supports link speeds > 5.0 GT/s, the waiting is after link training completes. Signed-off-by: Kevin Xie Reviewed-by: Mason Huo --- drivers/pci/pci.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 5ecbcf041179..4ca8766e546e 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -22,6 +22,13 @@ */ #define PCIE_PME_TO_L2_TIMEOUT_US 10000 +/* + * PCIe r6.0, sec 6.6.1, + * Requires a minimum waiting of 100ms before sending a configuration + * request to the device. + */ +#define PCIE_CONFIG_REQUEST_WAIT_MS 100 + extern const unsigned char pcie_link_speed[]; extern bool pci_early_dump;