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([80.71.140.73]) by smtp.gmail.com with ESMTPSA id y125-20020a636483000000b005bd3d6e270dsm1356002pgb.68.2023.11.30.07.19.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Nov 2023 07:19:52 -0800 (PST) From: Emil Renner Berthing To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/8] riscv: errata: Add StarFive JH7100 errata Date: Thu, 30 Nov 2023 16:19:25 +0100 Message-Id: <20231130151932.729708-2-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231130151932.729708-1-emil.renner.berthing@canonical.com> References: <20231130151932.729708-1-emil.renner.berthing@canonical.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231130_071956_775628_289F8D07 X-CRM114-Status: GOOD ( 12.45 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Emil Renner Berthing , Conor Dooley , Conor Dooley , Rob Herring , Palmer Dabbelt , Krzysztof Kozlowski , Paul Walmsley , Geert Uytterhoeven Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This not really an errata, but since the JH7100 was made before the standard Zicbom extension it needs the DMA_GLOBAL_POOL and RISCV_NONSTANDARD_CACHE_OPS enabled to work correctly. Acked-by: Conor Dooley Signed-off-by: Emil Renner Berthing Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- arch/riscv/Kconfig.errata | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index e2c731cfed8c..692de149141f 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -53,6 +53,23 @@ config ERRATA_SIFIVE_CIP_1200 If you don't know what to do here, say "Y". +config ERRATA_STARFIVE_JH7100 + bool "StarFive JH7100 support" + depends on ARCH_STARFIVE && NONPORTABLE + select DMA_GLOBAL_POOL + select RISCV_DMA_NONCOHERENT + select RISCV_NONSTANDARD_CACHE_OPS + select SIFIVE_CCACHE + default n + help + The StarFive JH7100 was a test chip for the JH7110 and has + caches that are non-coherent with respect to peripheral DMAs. + It was designed before the Zicbom extension so needs non-standard + cache operations through the SiFive cache controller. + + Say "Y" if you want to support the BeagleV Starlight and/or + StarFive VisionFive V1 boards. + config ERRATA_THEAD bool "T-HEAD errata" depends on RISCV_ALTERNATIVE From patchwork Thu Nov 30 15:19:26 2023 Content-Type: text/plain; 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([80.71.140.73]) by smtp.gmail.com with ESMTPSA id y125-20020a636483000000b005bd3d6e270dsm1356002pgb.68.2023.11.30.07.19.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Nov 2023 07:19:59 -0800 (PST) From: Emil Renner Berthing To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/8] riscv: dts: starfive: Group tuples in interrupt properties Date: Thu, 30 Nov 2023 16:19:26 +0100 Message-Id: <20231130151932.729708-3-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231130151932.729708-1-emil.renner.berthing@canonical.com> References: <20231130151932.729708-1-emil.renner.berthing@canonical.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231130_072004_613129_ABABAF45 X-CRM114-Status: GOOD ( 11.49 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Emil Renner Berthing , Conor Dooley , Rob Herring , Palmer Dabbelt , Krzysztof Kozlowski , Paul Walmsley , Geert Uytterhoeven Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Geert Uytterhoeven To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. Fix this by grouping the tuples of "interrupts-extended" properties using angle brackets. Signed-off-by: Geert Uytterhoeven Signed-off-by: Emil Renner Berthing --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index e68cafe7545f..a40a8544b860 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -149,15 +149,15 @@ soc { clint: clint@2000000 { compatible = "starfive,jh7100-clint", "sifive,clint0"; reg = <0x0 0x2000000 0x0 0x10000>; - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>; }; plic: interrupt-controller@c000000 { compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0"; reg = <0x0 0xc000000 0x0 0x4000000>; - interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9 - &cpu1_intc 11 &cpu1_intc 9>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>; 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([80.71.140.73]) by smtp.gmail.com with ESMTPSA id y125-20020a636483000000b005bd3d6e270dsm1356002pgb.68.2023.11.30.07.20.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Nov 2023 07:20:06 -0800 (PST) From: Emil Renner Berthing To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/8] riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAs Date: Thu, 30 Nov 2023 16:19:27 +0100 Message-Id: <20231130151932.729708-4-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231130151932.729708-1-emil.renner.berthing@canonical.com> References: <20231130151932.729708-1-emil.renner.berthing@canonical.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231130_072017_040243_6E7CFE0B X-CRM114-Status: UNSURE ( 9.99 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Emil Renner Berthing , Conor Dooley , Rob Herring , Palmer Dabbelt , Krzysztof Kozlowski , Paul Walmsley , Geert Uytterhoeven Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Emil Renner Berthing The StarFive JH7100 SoC has non-coherent device DMAs, so mark the soc bus as such. Link: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Cache%20Coherence%20V1.0.pdf Signed-off-by: Emil Renner Berthing --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index a40a8544b860..7c1009428c1f 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -144,6 +144,7 @@ soc { interrupt-parent = <&plic>; #address-cells = <2>; #size-cells = <2>; + dma-noncoherent; ranges; clint: clint@2000000 { From patchwork Thu Nov 30 15:19:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Renner Berthing X-Patchwork-Id: 13474621 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D05D4C4167B for ; Thu, 30 Nov 2023 15:20:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=AgIDJPLfOvUt+wOeH9xVtUVcDzLggquANcZuzanuOiU=; b=N2ijxZlXkJ6UWo M/T9OSSL3ZjVxaoig582KFjRx1NqLYzRPeXOuvxjPxdzsVPNfvaA9w9r9XR6K+SmSphigvHRFXuTB vfDojRl+aDQ/AS8A1KubAoDiMqC4+X1auVk5nzuT0PIcyN6nAiQCaZGehPyWEoW9794jT+3Far4/Z /dK4qfOQW22I2yE4JdYLJI9kcP0UiKllA2Syqkb6zKULiiug35uoZzyvvzFzc/v5Vb/R4RVfL6ZGW Jb8TfIr2WaqS1uem7AuyxvuZ4pxKavjtzWkwjic2riHjEljLtZTK5WRAogrvgRfB02k8NvVKjRwcZ lkY8SDkSF6msGS+febBQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r8ipz-00BBhG-0D; Thu, 30 Nov 2023 15:20:23 +0000 Received: from smtp-relay-internal-0.canonical.com ([185.125.188.122]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r8ipv-00BBfa-33 for linux-riscv@lists.infradead.org; Thu, 30 Nov 2023 15:20:21 +0000 Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-0.canonical.com (Postfix) with ESMTPS id 9338C44441 for ; Thu, 30 Nov 2023 15:20:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1701357616; bh=DJHVa7mIKQwhZz/JHltxB0iKVUnDkFEjfRvqGAQUx+4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=d0EHTKtbWwl3Iy2AaSzN1Aos19ZHoqh8eqsCNEB7TiGPusOiNt2sDxW9PVjcshRNH j2CquydUBg1ulwavAKzj8bpIyXJhB4IjMGGAGgNC7hcRhrmCtygpr3YQ+8KedZAYhK O6ovQNPlWJC69G9uvTmiyUtN5N54YEiEXjmlDWeZOdBKVn0ZQ+3BkDZqtI0Af8drCZ +oPRwPZUNynzk/VGGZEZ9vF3vCPUHAzGLVAYjHfvYRWfCaXE/rot8b7KikI48tIB2C eKEPmYCIiq0ciQPjFazabLQgdFjlEZcVmCLSLBRSbWDYB4CexP6IIsMTjDZwL0zo42 FMSx8S3JBKeog== Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-5c5e6009b98so928536a12.1 for ; Thu, 30 Nov 2023 07:20:16 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701357615; x=1701962415; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DJHVa7mIKQwhZz/JHltxB0iKVUnDkFEjfRvqGAQUx+4=; b=u8AUADzL1hbxYf3JoHjkfLytEhPPCXMv7NwTOR2KUdnLE2BIxRbnKxASWkOZEPz6Yj 2pSEX5XPE6SEoKRUynKfBYlX98k/a1AHp9Xf4h/y5qQLns0pNFecBefR9atp4oZxIA7R h56497HpOjeJBrPOQjQm4LzzAlj9Y37Rw/hC69/vqGUuDq3CuZtJo/9MTw8Zr+89+A6x hNFRSXyzvjybkrRmjVSiNpPmdinGGVS/2KmLuS9lpkK1cxlsaIUJ401P+Wk4/P6fYPtf HqdQM0xGVzVvcRVbHeDbl96jZRPQCPu7agkzle9JyO+0vbECfB3QQbxQDAY9hM23ly34 E+3Q== X-Gm-Message-State: AOJu0YyDEZSrqECKh55KTSrGnK5XUPu1jhHpG7nUp/d4z3vHvAiQEZAP YIk3cfpwVlUL2QKepPTbMVmiVZHlGeNToPlGF09R4PYBhidS2SnlyvS+Uzd5AP2JIArOPiBjN37 gP7dC61pJerxPjG45JZuRYJXuMc206f7zG/Rfq/c+IvaLPUAxEhNY8w== X-Received: by 2002:a05:6a20:7f98:b0:188:290d:17dc with SMTP id d24-20020a056a207f9800b00188290d17dcmr23728142pzj.60.1701357614813; Thu, 30 Nov 2023 07:20:14 -0800 (PST) X-Google-Smtp-Source: AGHT+IE7Mu2nDLembDBF+YwfqitZTioRcWFBD0XGtNJbp2zbw7AJm8Uh5SE/GyfEnowTrFxztj1irA== X-Received: by 2002:a05:6a20:7f98:b0:188:290d:17dc with SMTP id d24-20020a056a207f9800b00188290d17dcmr23728123pzj.60.1701357614540; Thu, 30 Nov 2023 07:20:14 -0800 (PST) Received: from stitch.. ([80.71.140.73]) by smtp.gmail.com with ESMTPSA id y125-20020a636483000000b005bd3d6e270dsm1356002pgb.68.2023.11.30.07.20.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Nov 2023 07:20:14 -0800 (PST) From: Emil Renner Berthing To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/8] riscv: dts: starfive: Add JH7100 cache controller Date: Thu, 30 Nov 2023 16:19:28 +0100 Message-Id: <20231130151932.729708-5-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231130151932.729708-1-emil.renner.berthing@canonical.com> References: <20231130151932.729708-1-emil.renner.berthing@canonical.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231130_072020_112593_30760C3E X-CRM114-Status: GOOD ( 11.22 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Emil Renner Berthing , Conor Dooley , Rob Herring , Palmer Dabbelt , Krzysztof Kozlowski , Paul Walmsley , Geert Uytterhoeven Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The StarFive JH7100 SoC also features the SiFive L2 cache controller, so add the device tree nodes for it. Signed-off-by: Emil Renner Berthing --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 7c1009428c1f..0cafac437746 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -32,6 +32,7 @@ U74_0: cpu@0 { i-tlb-sets = <1>; i-tlb-size = <32>; mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", @@ -60,6 +61,7 @@ U74_1: cpu@1 { i-tlb-sets = <1>; i-tlb-size = <32>; mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", @@ -154,6 +156,17 @@ clint: clint@2000000 { <&cpu1_intc 3>, <&cpu1_intc 7>; }; + ccache: cache-controller@2010000 { + compatible = "starfive,jh7100-ccache", "sifive,ccache0", "cache"; + reg = <0x0 0x2010000 0x0 0x1000>; + interrupts = <128>, <130>, <131>, <129>; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <2097152>; + cache-unified; + }; + plic: interrupt-controller@c000000 { compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0"; reg = <0x0 0xc000000 0x0 0x4000000>; From patchwork Thu Nov 30 15:19:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Renner Berthing X-Patchwork-Id: 13474622 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EFDD4C10DC2 for ; Thu, 30 Nov 2023 15:20:32 +0000 (UTC) DKIM-Signature: v=1; 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([80.71.140.73]) by smtp.gmail.com with ESMTPSA id y125-20020a636483000000b005bd3d6e270dsm1356002pgb.68.2023.11.30.07.20.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Nov 2023 07:20:21 -0800 (PST) From: Emil Renner Berthing To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/8] riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boards Date: Thu, 30 Nov 2023 16:19:29 +0100 Message-Id: <20231130151932.729708-6-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231130151932.729708-1-emil.renner.berthing@canonical.com> References: <20231130151932.729708-1-emil.renner.berthing@canonical.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231130_072025_103466_9F26A2FC X-CRM114-Status: GOOD ( 13.69 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Emil Renner Berthing , Conor Dooley , Rob Herring , Palmer Dabbelt , Krzysztof Kozlowski , Paul Walmsley , Geert Uytterhoeven Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The StarFive JH7100 SoC has non-coherent device DMAs, but most drivers expect to be able to allocate coherent memory for DMA descriptors and such. However on the JH7100 DDR memory appears twice in the physical memory map, once cached and once uncached: 0x00_8000_0000 - 0x08_7fff_ffff : Off chip DDR memory, cached 0x10_0000_0000 - 0x17_ffff_ffff : Off chip DDR memory, uncached To use this uncached region we create a global DMA memory pool there and reserve the corresponding area in the cached region. However the uncached region is fully above the 32bit address limit, so add a dma-ranges map so the DMA address used for peripherals is still in the regular cached region below the limit. Link: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf Signed-off-by: Emil Renner Berthing --- .../boot/dts/starfive/jh7100-common.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi index b93ce351a90f..3af88e6970a3 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -39,6 +39,30 @@ led-ack { label = "ack"; }; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dma-reserved@fa000000 { + reg = <0x0 0xfa000000 0x0 0x1000000>; + no-map; + }; + + linux,dma@107a000000 { + compatible = "shared-dma-pool"; + reg = <0x10 0x7a000000 0x0 0x1000000>; + no-map; + linux,dma-default; + }; + }; + + soc { + dma-ranges = <0x00 0x80000000 0x00 0x80000000 0x00 0x7a000000>, + <0x00 0xfa000000 0x10 0x7a000000 0x00 0x01000000>, + <0x00 0xfb000000 0x00 0xfb000000 0x07 0x85000000>; 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([80.71.140.73]) by smtp.gmail.com with ESMTPSA id y125-20020a636483000000b005bd3d6e270dsm1356002pgb.68.2023.11.30.07.20.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Nov 2023 07:20:28 -0800 (PST) From: Emil Renner Berthing To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/8] riscv: dts: starfive: Add JH7100 MMC nodes Date: Thu, 30 Nov 2023 16:19:30 +0100 Message-Id: <20231130151932.729708-7-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231130151932.729708-1-emil.renner.berthing@canonical.com> References: <20231130151932.729708-1-emil.renner.berthing@canonical.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231130_072032_748015_ADEF4DFB X-CRM114-Status: GOOD ( 10.98 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Emil Renner Berthing , Conor Dooley , Rob Herring , Palmer Dabbelt , Krzysztof Kozlowski , Paul Walmsley , Geert Uytterhoeven Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add device tree nodes for the Synopsis MMC controllers on the StarFive JH7100 SoC. Signed-off-by: Emil Renner Berthing --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 0cafac437746..c216aaecac53 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -178,6 +178,32 @@ plic: interrupt-controller@c000000 { riscv,ndev = <133>; }; + sdio0: mmc@10000000 { + compatible = "snps,dw-mshc"; + reg = <0x0 0x10000000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_SDIO0_AHB>, + <&clkgen JH7100_CLK_SDIO0_CCLKINT_INV>; + clock-names = "biu", "ciu"; + interrupts = <4>; + data-addr = <0>; + fifo-depth = <32>; + fifo-watermark-aligned; + status = "disabled"; + }; + + sdio1: mmc@10010000 { + compatible = "snps,dw-mshc"; + reg = <0x0 0x10010000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_SDIO1_AHB>, + <&clkgen JH7100_CLK_SDIO1_CCLKINT_INV>; + clock-names = "biu", "ciu"; + interrupts = <5>; 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([80.71.140.73]) by smtp.gmail.com with ESMTPSA id y125-20020a636483000000b005bd3d6e270dsm1356002pgb.68.2023.11.30.07.20.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Nov 2023 07:20:35 -0800 (PST) From: Emil Renner Berthing To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 7/8] riscv: dts: starfive: Enable SD-card on JH7100 boards Date: Thu, 30 Nov 2023 16:19:31 +0100 Message-Id: <20231130151932.729708-8-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231130151932.729708-1-emil.renner.berthing@canonical.com> References: <20231130151932.729708-1-emil.renner.berthing@canonical.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231130_072039_736081_122CF164 X-CRM114-Status: GOOD ( 11.49 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Emil Renner Berthing , Conor Dooley , Rob Herring , Palmer Dabbelt , Krzysztof Kozlowski , Paul Walmsley , Geert Uytterhoeven Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add pinctrl and MMC device tree nodes for the SD-card on the BeagleV Starlight and StarFive VisionFive V1 boards. Signed-off-by: Emil Renner Berthing --- .../boot/dts/starfive/jh7100-common.dtsi | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi index 3af88e6970a3..adcdbbc4f57f 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -12,6 +12,7 @@ / { aliases { + mmc0 = &sdio0; serial0 = &uart3; }; @@ -108,6 +109,43 @@ GPO_I2C2_PAD_SDA_OEN, }; }; + sdio0_pins: sdio0-0 { + clk-pins { + pinmux = ; + bias-disable; + input-disable; + input-schmitt-disable; + }; + sdio-pins { + pinmux = , + , + , + , + , + ; + bias-pull-up; + input-enable; + input-schmitt-enable; + }; + }; + uart3_pins: uart3-0 { rx-pins { pinmux = ; }; +&sdio0 { + broken-cd; + bus-width = <4>; + cap-sd-highspeed; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_pins>; + status = "okay"; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; From patchwork Thu Nov 30 15:19:32 2023 Content-Type: text/plain; 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([80.71.140.73]) by smtp.gmail.com with ESMTPSA id y125-20020a636483000000b005bd3d6e270dsm1356002pgb.68.2023.11.30.07.20.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Nov 2023 07:20:43 -0800 (PST) From: Emil Renner Berthing To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 8/8] riscv: dts: starfive: Enable SDIO wifi on JH7100 boards Date: Thu, 30 Nov 2023 16:19:32 +0100 Message-Id: <20231130151932.729708-9-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231130151932.729708-1-emil.renner.berthing@canonical.com> References: <20231130151932.729708-1-emil.renner.berthing@canonical.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231130_072047_548580_CFB38A7E X-CRM114-Status: GOOD ( 11.60 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Emil Renner Berthing , Conor Dooley , Rob Herring , Palmer Dabbelt , Krzysztof Kozlowski , Paul Walmsley , Geert Uytterhoeven Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add pinctrl and MMC controller nodes for the Broadcom wifi controller on the BeagleV Starlight and StarFive VisionFive V1 boards. Signed-off-by: Emil Renner Berthing --- .../boot/dts/starfive/jh7100-common.dtsi | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi index adcdbbc4f57f..42fb61c36068 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -13,6 +13,7 @@ / { aliases { mmc0 = &sdio0; + mmc1 = &sdio1; serial0 = &uart3; }; @@ -64,6 +65,11 @@ soc { <0x00 0xfa000000 0x10 0x7a000000 0x00 0x01000000>, <0x00 0xfb000000 0x00 0xfb000000 0x07 0x85000000>; }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>; + }; }; &gpio { @@ -146,6 +152,41 @@ GPO_SDIO0_PAD_CDATA_OEN_BIT3, }; }; + sdio1_pins: sdio1-0 { + clk-pins { + pinmux = ; + bias-disable; + input-disable; + input-schmitt-disable; + }; + sdio-pins { + pinmux = , + , + , + , + ; + bias-pull-up; + input-enable; + input-schmitt-enable; + }; + }; + uart3_pins: uart3-0 { rx-pins { pinmux = ; + #size-cells = <0>; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + cap-power-off-card; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio1_pins>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>;