From patchwork Sun Dec 10 16:15:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiqian Chen X-Patchwork-Id: 13486453 X-Patchwork-Delegate: kw@linux.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="WugWokQl" Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2085.outbound.protection.outlook.com [40.107.237.85]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36DE1F9; Sun, 10 Dec 2023 08:15:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=MUWM0qutTMMeenq1MAyWuVl2Ac5ZfWwhPASMMvE2GSw+WDK+mVtuvTmI1FqK9Tv844TlloXulWGi0GM+Wbozm227Icaa8EarXa7EymGB59jS2uQRkhFMlYEYy2EznTURuH5mhoPv4KHuQay8Sz74nQrDaXltiUlUSsEkPfF4I0cywXVw8L8idCCnwVyKbua+Z7amVSSU2n4nmdcivo31jSW+r/VETyi8lv9aY0EfrS4IWK49UBv6gEdEtbM9myavz7Zgp4tDnWpWUHdC1ZMZBlvOmryqyvdTsCRIbip37uqBEBaGlgljPgJ17eMvRGwj4EVBWxhIf62gr8XUjx91pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=e0cVJClnKI0t+S5tf/NWGenaSQY7dTKBr3BxoBA+0yg=; b=UGztRtYOB+Q+UbXi1c1mBnPetxV6zNQBSEpx14ozt2mYiVEcHsNm6kXEgpYnoHP1ir1uB5FzMd6/H0ZdmhvPxt+3qPfPv2/8FdkMz+ihTc3E52daGSxTF2SePhEO+64i0Of0/QNKwNpBq3tKrf/UwDOFjfXA7yLg/zFcxiQ2VpKNvxKgK2QtXLLEqMhCSTEQ5syHHAvrEFSiY2S/C2LOeaQYIUd9iFmoFSZUzC5Dva1Q6hr/lTTr+4OC3jD5pRz/K78VhZknx2FYp72nKXpoPBvaiAt97UkMBNPQQoeBaJUPNsz7tQyVqo3toqmy4hv2EKHOkLdhdVQejx9ek9AxuA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=suse.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=e0cVJClnKI0t+S5tf/NWGenaSQY7dTKBr3BxoBA+0yg=; b=WugWokQlCzKNdd4LZfCYgc+CgdEVr30USTES9WYlFrNv0avtgUNI3BLKYEstMgOs8j3ZJi8rZetjo4RCoYmNy6/stV0D3ymRkhGwI93bHS84nrvy2Y9O6df739q6UtYQT82XKys/IfhlBDvPwcLMSqji9theFdFLwSeYF3IIIe4= Received: from CY5PR17CA0058.namprd17.prod.outlook.com (2603:10b6:930:12::20) by CH2PR12MB4216.namprd12.prod.outlook.com (2603:10b6:610:a8::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.32; Sun, 10 Dec 2023 16:15:45 +0000 Received: from CY4PEPF0000E9D3.namprd03.prod.outlook.com (2603:10b6:930:12:cafe::55) by CY5PR17CA0058.outlook.office365.com (2603:10b6:930:12::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.32 via Frontend Transport; Sun, 10 Dec 2023 16:15:44 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D3.mail.protection.outlook.com (10.167.241.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7091.18 via Frontend Transport; Sun, 10 Dec 2023 16:15:44 +0000 Received: from cjq-desktop.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Sun, 10 Dec 2023 10:15:38 -0600 From: Jiqian Chen To: Juergen Gross , Stefano Stabellini , Oleksandr Tyshchenko , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , "Thomas Gleixner" , Boris Ostrovsky , =?utf-8?q?Roger_Pau_Monn?= =?utf-8?q?=C3=A9?= CC: , , , , Alex Deucher , Christian Koenig , Stewart Hildebrand , Xenia Ragiadakou , Honglei Huang , "Julia Zhang" , Huang Rui , Jiqian Chen , Huang Rui Subject: [RFC KERNEL PATCH v3 1/3] xen/pci: Add xen_reset_device_state function Date: Mon, 11 Dec 2023 00:15:17 +0800 Message-ID: <20231210161519.1550860-2-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231210161519.1550860-1-Jiqian.Chen@amd.com> References: <20231210161519.1550860-1-Jiqian.Chen@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D3:EE_|CH2PR12MB4216:EE_ X-MS-Office365-Filtering-Correlation-Id: c1ff42dc-c1c3-4b41-b08a-08dbf99b42f3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sjxsHOhfjm4BdqjLcc6/A0HrcK0KDCJsgTUEjobA6Pvj1fuXPvL4dSftfmoeOMf2UhVA6hfZyw9uVwKZj4Vw2uOm0oaA5K+HCXjGTXIu4M2kX/mcvCF7Aq4B64EVGrGo3jcuEAAL8l2rbWzms14he+qH1D8ORQ0ZwCE+WpCEUxUxuMeMmn8iMd67jyx3k58xXMe7PDrm4rtnhfeRh+CmY7A2crE03Z8EsjCmmWqouYzyO8VxsJnR9RtQg6Ht2RKyOrU9pwyhGvkTKLy4X77UV6U4XGSk56m+ueiIl2kgtAscsusRP3O4emgXv9jsPmNuXNRnQR0Yr1Lg5pAdx/rmGy/sXFN8NAISB4d4fbReLDTLgXTo9R1tBTfz8EhcYdbegFcDV+7b8gAJ0wTZq9ENjRsWtllmkvMBl2QT0bgD0o9dmvjNT6B5SBMw85ldmFL4BNNQ8nNdCjswyvzo25JHaT19C4Z3xZOF8WAedafYzqZ7kiTPY296Gw6d56jpepby+mjgyas/uRvFE0kxLQ+d25jMxJ39zjkf6T/ezvjE0ksXT70NrcYSC2x637hrYThr7db489RheqQ9U2W8ckGKJSOYvKD6nSl8+vVZ9ZZ6lOqkKT0wGU8HMxAjC0beus8YD9Bj/kY8NaDokaXSK+hQG3bPmnkkysOMc59R6woEcbrM7VCxCPAmo1nSBlq+ZpAGNAotujG/dujiql/ieHqAGEXiFEMT2cRKo35gcuC58EykX7QHDXV1XPSUIsprn5KkyerRYfNecvW6Vc0Bhw4YNg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(39860400002)(376002)(396003)(346002)(230922051799003)(451199024)(1800799012)(186009)(82310400011)(64100799003)(46966006)(36840700001)(40470700004)(41300700001)(5660300002)(7416002)(2906002)(2616005)(1076003)(6666004)(7696005)(36756003)(478600001)(36860700001)(47076005)(81166007)(82740400003)(356005)(426003)(83380400001)(336012)(40480700001)(26005)(16526019)(8936002)(40460700003)(8676002)(4326008)(86362001)(54906003)(110136005)(316002)(70206006)(70586007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2023 16:15:44.0477 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c1ff42dc-c1c3-4b41-b08a-08dbf99b42f3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4216 When device on dom0 side has been reset, the vpci on Xen side won't get notification, so that the cached state in vpci is all out of date with the real device state. To solve that problem, add a new function to clear all vpci device state when device is reset on dom0 side. And call that function in pcistub_init_device. Because when using "pci-assignable-add" to assign a passthrough device in Xen, it will reset passthrough device and the vpci state will out of date, and then device will fail to restore bar state. Co-developed-by: Huang Rui Signed-off-by: Jiqian Chen --- drivers/xen/pci.c | 12 ++++++++++++ drivers/xen/xen-pciback/pci_stub.c | 4 ++++ include/xen/interface/physdev.h | 8 ++++++++ include/xen/pci.h | 6 ++++++ 4 files changed, 30 insertions(+) diff --git a/drivers/xen/pci.c b/drivers/xen/pci.c index 72d4e3f193af..e9b30bc09139 100644 --- a/drivers/xen/pci.c +++ b/drivers/xen/pci.c @@ -177,6 +177,18 @@ static int xen_remove_device(struct device *dev) return r; } +int xen_reset_device_state(const struct pci_dev *dev) +{ + struct physdev_pci_device device = { + .seg = pci_domain_nr(dev->bus), + .bus = dev->bus->number, + .devfn = dev->devfn + }; + + return HYPERVISOR_physdev_op(PHYSDEVOP_pci_device_state_reset, &device); +} +EXPORT_SYMBOL_GPL(xen_reset_device_state); + static int xen_pci_notifier(struct notifier_block *nb, unsigned long action, void *data) { diff --git a/drivers/xen/xen-pciback/pci_stub.c b/drivers/xen/xen-pciback/pci_stub.c index e34b623e4b41..24f599eaec14 100644 --- a/drivers/xen/xen-pciback/pci_stub.c +++ b/drivers/xen/xen-pciback/pci_stub.c @@ -421,6 +421,10 @@ static int pcistub_init_device(struct pci_dev *dev) else { dev_dbg(&dev->dev, "resetting (FLR, D3, etc) the device\n"); __pci_reset_function_locked(dev); + if (!xen_pv_domain()) + err = xen_reset_device_state(dev); + if (err) + goto config_release; pci_restore_state(dev); } /* Now disable the device (this also ensures some private device diff --git a/include/xen/interface/physdev.h b/include/xen/interface/physdev.h index a237af867873..bed53afc4c52 100644 --- a/include/xen/interface/physdev.h +++ b/include/xen/interface/physdev.h @@ -256,6 +256,14 @@ struct physdev_pci_device_add { */ #define PHYSDEVOP_prepare_msix 30 #define PHYSDEVOP_release_msix 31 +/* + * On PVH dom0, when device is reset, the vpci on Xen side + * won't get notification, so that the cached state in vpci is + * all out of date with the real device state. Use this to reset + * the vpci state of device. + */ +#define PHYSDEVOP_pci_device_state_reset 32 + struct physdev_pci_device { /* IN */ uint16_t seg; diff --git a/include/xen/pci.h b/include/xen/pci.h index b8337cf85fd1..b2e2e856efd6 100644 --- a/include/xen/pci.h +++ b/include/xen/pci.h @@ -4,10 +4,16 @@ #define __XEN_PCI_H__ #if defined(CONFIG_XEN_DOM0) +int xen_reset_device_state(const struct pci_dev *dev); int xen_find_device_domain_owner(struct pci_dev *dev); int xen_register_device_domain_owner(struct pci_dev *dev, uint16_t domain); int xen_unregister_device_domain_owner(struct pci_dev *dev); #else +static inline int xen_reset_device_state(const struct pci_dev *dev) +{ + return -1; +} + static inline int xen_find_device_domain_owner(struct pci_dev *dev) { return -1; From patchwork Sun Dec 10 16:15:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiqian Chen X-Patchwork-Id: 13486454 X-Patchwork-Delegate: kw@linux.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="MLxN6e6Z" Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2059.outbound.protection.outlook.com [40.107.94.59]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C7A8FA; Sun, 10 Dec 2023 08:15:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=PfqbCwPVUJ+Y86f4IlIm0klx9RE8h/+d22GupL4sfNeIlMVaJPd32JfEYRuKe/GTGSf3+Fxe+DFDX7t9hdQ9QvG6hDSS/wV5wcyBgzxKnKrMeInCpQHzUOQYUzyl+/s2QU0efsJUE30N/2V5DqJHlsNpBipmpSIBeECJYkP/9mUirCpSaIC0oLmXIYp7Cot3xSrsdlTsTlLkVB8B44PM6KZdCxJIVsdn58RaemTy0CuAm4+FtvbG5Q0kEdQ+Z0hK//u9jvf7JmYuv2WPVBbuRwV8n615bNmrYv/3VvZJ7DAlFvV5ZD0M7xaJzay/RaHaO483PpVBgfux/MmudpLTBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=7ZzpD1Q9U1FBd+Cui/rhmlxEnZC6P7a6CPX3YbcNCVg=; b=YTVhdXMFxxkOsdFJFvrtW8yKIdnTgZxCmdsH3DcnXCvBuprQupSxSEPTukTZr73YgjhI/HOe9j4LvZ8S+DURyX9eC0TZ2hG/YIIVM7MFiCqZhElXYbT3xMwxFaAGpngGuaA606+C7l/kzp5S2C8tiqhZBWTtfJa5QCQqO85GlD2c/6hFS4b9+FvJNsc7rbycAi+nMAx1VMB0A08EZXE1jPnvRyFoloBeDgM7j67RatwMFiGTZ1rOtLhrbC8O55beZ5JGIwkIeGEIZSKEvNoS+nUrNnZuFNrporYIOn38+hnzINonDzlVsYXNoR32R/iMDnip4a8iPVKh6PmGZ4mT4g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=suse.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=7ZzpD1Q9U1FBd+Cui/rhmlxEnZC6P7a6CPX3YbcNCVg=; b=MLxN6e6ZzFCUfT2P6aRtvwpUy1pg30VtMWaLy6eGM6p6+3wkKmj7FpeIJCc/fdclJPhjTKZczqloDxBbzaUSaAzZjqNM81i68sTMI4Pmtefztcl5Eghb0bevHxhr7jqci+ywoU0AH/ATt6Em3+sfJT3mQm2oKW6Um1YPp1/7tI8= Received: from CY8PR11CA0046.namprd11.prod.outlook.com (2603:10b6:930:4a::6) by IA1PR12MB7519.namprd12.prod.outlook.com (2603:10b6:208:418::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.32; Sun, 10 Dec 2023 16:15:50 +0000 Received: from CY4PEPF0000E9D2.namprd03.prod.outlook.com (2603:10b6:930:4a:cafe::e4) by CY8PR11CA0046.outlook.office365.com (2603:10b6:930:4a::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.32 via Frontend Transport; Sun, 10 Dec 2023 16:15:49 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D2.mail.protection.outlook.com (10.167.241.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7091.18 via Frontend Transport; Sun, 10 Dec 2023 16:15:49 +0000 Received: from cjq-desktop.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Sun, 10 Dec 2023 10:15:43 -0600 From: Jiqian Chen To: Juergen Gross , Stefano Stabellini , Oleksandr Tyshchenko , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , "Thomas Gleixner" , Boris Ostrovsky , =?utf-8?q?Roger_Pau_Monn?= =?utf-8?q?=C3=A9?= CC: , , , , Alex Deucher , Christian Koenig , Stewart Hildebrand , Xenia Ragiadakou , Honglei Huang , "Julia Zhang" , Huang Rui , Jiqian Chen , Huang Rui Subject: [RFC KERNEL PATCH v3 2/3] xen/pvh: Setup gsi and map pirq for passthrough device Date: Mon, 11 Dec 2023 00:15:18 +0800 Message-ID: <20231210161519.1550860-3-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231210161519.1550860-1-Jiqian.Chen@amd.com> References: <20231210161519.1550860-1-Jiqian.Chen@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D2:EE_|IA1PR12MB7519:EE_ X-MS-Office365-Filtering-Correlation-Id: ef4d8cc1-c0af-4dd5-99af-08dbf99b4644 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rLD43QNXwEf9iZU2ACpTh2OyKu1vfqhy8LHHGgJC1/egSOQpVjtONHY6dPyJF72SNm5RQBEZmtO/QPYDK/jo0bOSpcFx6HWn8IyJ+uzsvXLMhGDjeP44Kz0USFqsois5BsZZ8xxHXN7LeRzFItHkBNWP1ntmKBhrzSGQ589K3M7jDArvCIKuYCDRFyIqfsJtnwjlHWdMZA5sec4cuGgJT2oy9VOb7L/hM5TlWHL/I7McObsrSobpspL/9CNLffOCmHfIBYeioGEPjjGMooL9AYy5NhHrf2xuqKqPI6Ky9sbbBBxvT1Ldgq819WoEMh7MQfEJcVmgnyeBKiymOfhhx1K7nomgZpniCQGGO5s3Gjwgjn1VuZHcJoT1zyIFOVlQ9d5BWbohtU3hrZXP1yLp5MF3ozgjaAGvAf6k0aI+u03HPQIJQmm1Jp5vuG2kQrekwTmtyBvZbrN7Jy4oZ9T7WM/WSprdn7TzsS/dXFNJbrQlrX6QhF+/J0IRCATd1MuDEGPv04wgF0f19TCEdnhblwH56kxUoMpQUlFAC2ZJ7HY/0OUY96chLLDPs51wNiTKEdO+vT032s4tP71sWpRUDfkRgid6y5MgqTSAG2FA9upAuJkgR23bJwIzwnMmnQTkdTmfcgR/qH4KaQQMBOdf8gJQPZ4+PxEh/fHCjTu9LboW8vK1EqdzaGXNIOeyAAgFc8Unu2fMtX+xDeUFmu0VTLyh1/s0NkVJ1xSJ6Pk0bJhuNZ+qPCU4XiwDf19wx6n2fQdYemw5DBJhMQXbTGY0Tw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(376002)(346002)(396003)(136003)(230922051799003)(82310400011)(64100799003)(186009)(1800799012)(451199024)(46966006)(40470700004)(36840700001)(40460700003)(1076003)(26005)(16526019)(2616005)(336012)(426003)(7696005)(6666004)(36860700001)(83380400001)(47076005)(5660300002)(7416002)(41300700001)(2906002)(4326008)(478600001)(8676002)(8936002)(70206006)(70586007)(110136005)(316002)(54906003)(82740400003)(81166007)(86362001)(356005)(36756003)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2023 16:15:49.6111 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ef4d8cc1-c0af-4dd5-99af-08dbf99b4644 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7519 When dom0 is PVH, the gsi isn't be unmasked, that causes two problems. First, in PVH dom0, the gsis don't get registered, but the gsi of a passthrough device must be configured for it to be able to be mapped into a domU. When assign a device to passthrough, proactively setup the gsi of the device during that process. Second, for hvm guest, it allocates a pirq and irq for a passthrough device by using gsi, before that, the gsi must first have a mapping in dom0, see Xen code pci_add_dm_done->xc_domain_irq_permission, it calls into Xen and check whether dom0 has the mapping. But currently PVH dom0 uses the kernel local interrupt mechanism instead of the pirq. So if passthrough a device to guest on PVH dom0, it will fail at the permission checking. When assign a device to passthrough, proactively map priq for the gsi of the device during that process. Co-developed-by: Huang Rui Signed-off-by: Jiqian Chen --- arch/x86/xen/enlighten_pvh.c | 116 +++++++++++++++++++++++++++++ drivers/acpi/pci_irq.c | 2 +- drivers/xen/xen-pciback/pci_stub.c | 8 ++ include/linux/acpi.h | 1 + include/xen/acpi.h | 1 + 5 files changed, 127 insertions(+), 1 deletion(-) diff --git a/arch/x86/xen/enlighten_pvh.c b/arch/x86/xen/enlighten_pvh.c index ada3868c02c2..d74a221bfb81 100644 --- a/arch/x86/xen/enlighten_pvh.c +++ b/arch/x86/xen/enlighten_pvh.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include #include +#include #include @@ -25,6 +26,121 @@ bool __ro_after_init xen_pvh; EXPORT_SYMBOL_GPL(xen_pvh); +typedef struct gsi_info { + u32 gsi; + int trigger; + int polarity; + int pirq; +} gsi_info_t; + +struct acpi_prt_entry { + struct acpi_pci_id id; + u8 pin; + acpi_handle link; + u32 index; /* GSI, or link _CRS index */ +}; + +static int xen_pvh_get_gsi_info(struct pci_dev *dev, + gsi_info_t *gsi_info) +{ + int gsi; + u8 pin = 0; + struct acpi_prt_entry *entry; + int trigger = ACPI_LEVEL_SENSITIVE; + int polarity = acpi_irq_model == ACPI_IRQ_MODEL_GIC ? + ACPI_ACTIVE_HIGH : ACPI_ACTIVE_LOW; + + if (dev) + pin = dev->pin; + if (!dev || !pin || !gsi_info) + return -EINVAL; + + entry = acpi_pci_irq_lookup(dev, pin); + if (entry) { + if (entry->link) + gsi = acpi_pci_link_allocate_irq(entry->link, + entry->index, + &trigger, &polarity, + NULL); + else + gsi = entry->index; + } else + return -EINVAL; + + if (gsi < 0) + return -EINVAL; + + gsi_info->gsi = gsi; + gsi_info->trigger = trigger; + gsi_info->polarity = polarity; + + return 0; +} + +static int xen_pvh_setup_gsi(gsi_info_t *gsi_info) +{ + struct physdev_setup_gsi setup_gsi; + + if (!gsi_info) + return -EINVAL; + + setup_gsi.gsi = gsi_info->gsi; + setup_gsi.triggering = (gsi_info->trigger == ACPI_EDGE_SENSITIVE ? 0 : 1); + setup_gsi.polarity = (gsi_info->polarity == ACPI_ACTIVE_HIGH ? 0 : 1); + + return HYPERVISOR_physdev_op(PHYSDEVOP_setup_gsi, &setup_gsi); +} + +static int xen_pvh_map_pirq(gsi_info_t *gsi_info) +{ + struct physdev_map_pirq map_irq; + int ret; + + if (!gsi_info) + return -EINVAL; + + map_irq.domid = DOMID_SELF; + map_irq.type = MAP_PIRQ_TYPE_GSI; + map_irq.index = gsi_info->gsi; + map_irq.pirq = gsi_info->gsi; + + ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq); + gsi_info->pirq = map_irq.pirq; + + return ret; +} + +int xen_pvh_passthrough_gsi(struct pci_dev *dev) +{ + int ret; + gsi_info_t gsi_info; + + if (!dev) + return -EINVAL; + + ret = xen_pvh_get_gsi_info(dev, &gsi_info); + if (ret) { + xen_raw_printk("Fail to get gsi info!\n"); + return ret; + } + + ret = xen_pvh_setup_gsi(&gsi_info); + if (ret == -EEXIST) { + ret = 0; + xen_raw_printk("Already setup the GSI :%u\n", gsi_info.gsi); + } else if (ret) { + xen_raw_printk("Fail to setup gsi (%d)!\n", gsi_info.gsi); + return ret; + } + + ret = xen_pvh_map_pirq(&gsi_info); + if (ret) + xen_raw_printk("Fail to map pirq for gsi (%d)!\n", gsi_info.gsi); + + return ret; +} +EXPORT_SYMBOL_GPL(xen_pvh_passthrough_gsi); + void __init xen_pvh_init(struct boot_params *boot_params) { u32 msr; diff --git a/drivers/acpi/pci_irq.c b/drivers/acpi/pci_irq.c index ff30ceca2203..630fe0a34bc6 100644 --- a/drivers/acpi/pci_irq.c +++ b/drivers/acpi/pci_irq.c @@ -288,7 +288,7 @@ static int acpi_reroute_boot_interrupt(struct pci_dev *dev, } #endif /* CONFIG_X86_IO_APIC */ -static struct acpi_prt_entry *acpi_pci_irq_lookup(struct pci_dev *dev, int pin) +struct acpi_prt_entry *acpi_pci_irq_lookup(struct pci_dev *dev, int pin) { struct acpi_prt_entry *entry = NULL; struct pci_dev *bridge; diff --git a/drivers/xen/xen-pciback/pci_stub.c b/drivers/xen/xen-pciback/pci_stub.c index 24f599eaec14..c3aeefbf4ba1 100644 --- a/drivers/xen/xen-pciback/pci_stub.c +++ b/drivers/xen/xen-pciback/pci_stub.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -427,6 +428,13 @@ static int pcistub_init_device(struct pci_dev *dev) goto config_release; pci_restore_state(dev); } + + if (xen_initial_domain() && xen_pvh_domain()) { + err = xen_pvh_passthrough_gsi(dev); + if (err) + goto config_release; + } + /* Now disable the device (this also ensures some private device * data is setup before we export) */ diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 54189e0e5f41..a211bdcdd6ff 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -360,6 +360,7 @@ void acpi_unregister_gsi (u32 gsi); struct pci_dev; +struct acpi_prt_entry *acpi_pci_irq_lookup(struct pci_dev *dev, int pin); int acpi_pci_irq_enable (struct pci_dev *dev); void acpi_penalize_isa_irq(int irq, int active); bool acpi_isa_irq_available(int irq); diff --git a/include/xen/acpi.h b/include/xen/acpi.h index b1e11863144d..ce7f5554f88e 100644 --- a/include/xen/acpi.h +++ b/include/xen/acpi.h @@ -67,6 +67,7 @@ static inline void xen_acpi_sleep_register(void) acpi_suspend_lowlevel = xen_acpi_suspend_lowlevel; } } +int xen_pvh_passthrough_gsi(struct pci_dev *dev); #else static inline void xen_acpi_sleep_register(void) { From patchwork Sun Dec 10 16:15:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiqian Chen X-Patchwork-Id: 13486455 X-Patchwork-Delegate: kw@linux.com Authentication-Results: smtp.subspace.kernel.org; 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Sun, 10 Dec 2023 10:15:49 -0600 From: Jiqian Chen To: Juergen Gross , Stefano Stabellini , Oleksandr Tyshchenko , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , "Thomas Gleixner" , Boris Ostrovsky , =?utf-8?q?Roger_Pau_Monn?= =?utf-8?q?=C3=A9?= CC: , , , , Alex Deucher , Christian Koenig , Stewart Hildebrand , Xenia Ragiadakou , Honglei Huang , "Julia Zhang" , Huang Rui , Jiqian Chen , Huang Rui Subject: [RFC KERNEL PATCH v3 3/3] PCI/sysfs: Add gsi sysfs for pci_dev Date: Mon, 11 Dec 2023 00:15:19 +0800 Message-ID: <20231210161519.1550860-4-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231210161519.1550860-1-Jiqian.Chen@amd.com> References: <20231210161519.1550860-1-Jiqian.Chen@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D3:EE_|LV8PR12MB9418:EE_ X-MS-Office365-Filtering-Correlation-Id: cf2f23ec-1ba0-46b2-0375-08dbf99b58cd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7cfoB48RFii35Dpa6TXwr7UxlCzYNwfbaERgbGp/VozX/bPoP+7GQKkXxKnbh7P9c4S1i/ANYjSywduz00puSxzU78+U7XlSAKk5dTeMTgG6vGBlrZyMY8Zhz5AScY0Tn8eGITwcP9NUGEKY0dpoGCUhhQKc7oNWLYIxRHRRHOfh0eBJPe+Mr3jHEBhlH2BV9CQT7xlwgE2uKwv1DrHy12MjwsrGW3qvxpfnsZPlzvVJWMJF+I/tyoj5AO3kjb1QpO/8fJahQBfoRGED+kCF4IAQDdbao/hXKt5kX6DghX4l75ZISl0ev8OfnWE3b5mF6oRbd6O7qJZV8kx9FrsiQFK2Jyt1Kr3VlOH4CUBQimAHcDJOB/WHZ56GfF3fdNknTAxdQryfH1dTx9a/UF6VVps96GdlMl0tKIPT/1SPdWImr04VRcoS/5cmkg8nRAIm0M/glfUUIIoluQLd+u1niu4TO94nDm1GwU72vr3DbV2jd1m4zOV7qijvq3FJwN9U9EfL5CAd5XkvAQ4EB1S9aCNn+Y1ZqLmHKjFM7MBAyk2pJxkMmuZyx0XPWWQE4clL5ROBI4HDG8u9sey//vLNJfMglx0RdiSEDVWSMtZxQsr/gnkldZ6wEnHbDszaNz0gUsaWLH1VUu6DdOZp7u5j586pAZQbyUBpIFzo0Rs/zErO47zc/3NtUu3tLFhNtQ22mZ7yfRPuksJOpdU2C3mdiGuUCk1FQWqrA4Qq4CKnk+xfklxcmldrIiUQCEMbdekINtRHBLsjPXosJjj1c7GuHA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(346002)(39860400002)(136003)(376002)(230922051799003)(64100799003)(82310400011)(1800799012)(451199024)(186009)(40470700004)(46966006)(36840700001)(7416002)(6666004)(7696005)(2906002)(54906003)(70206006)(356005)(81166007)(86362001)(36756003)(316002)(8936002)(4326008)(8676002)(5660300002)(40480700001)(70586007)(110136005)(478600001)(40460700003)(41300700001)(36860700001)(82740400003)(47076005)(26005)(336012)(426003)(1076003)(2616005)(83380400001)(16526019)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2023 16:16:20.7041 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cf2f23ec-1ba0-46b2-0375-08dbf99b58cd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9418 There is a need for some scenarios to use gsi sysfs. For example, when xen passthrough a device to dumU, it will use gsi to map pirq, but currently userspace can't get gsi number. So, add gsi sysfs for that and for other potential scenarios. Co-developed-by: Huang Rui Signed-off-by: Jiqian Chen --- drivers/acpi/pci_irq.c | 1 + drivers/pci/pci-sysfs.c | 11 +++++++++++ include/linux/pci.h | 2 ++ 3 files changed, 14 insertions(+) diff --git a/drivers/acpi/pci_irq.c b/drivers/acpi/pci_irq.c index 630fe0a34bc6..739a58755df2 100644 --- a/drivers/acpi/pci_irq.c +++ b/drivers/acpi/pci_irq.c @@ -449,6 +449,7 @@ int acpi_pci_irq_enable(struct pci_dev *dev) kfree(entry); return 0; } + dev->gsi = gsi; rc = acpi_register_gsi(&dev->dev, gsi, triggering, polarity); if (rc < 0) { diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 2321fdfefd7d..c51df88d079e 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -71,6 +71,16 @@ static ssize_t irq_show(struct device *dev, } static DEVICE_ATTR_RO(irq); +static ssize_t gsi_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct pci_dev *pdev = to_pci_dev(dev); + + return sysfs_emit(buf, "%u\n", pdev->gsi); +} +static DEVICE_ATTR_RO(gsi); + static ssize_t broken_parity_status_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -596,6 +606,7 @@ static struct attribute *pci_dev_attrs[] = { &dev_attr_revision.attr, &dev_attr_class.attr, &dev_attr_irq.attr, + &dev_attr_gsi.attr, &dev_attr_local_cpus.attr, &dev_attr_local_cpulist.attr, &dev_attr_modalias.attr, diff --git a/include/linux/pci.h b/include/linux/pci.h index 60ca768bc867..7ef9060b239c 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -529,6 +529,8 @@ struct pci_dev { /* These methods index pci_reset_fn_methods[] */ u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */ + + unsigned int gsi; }; static inline struct pci_dev *pci_physfn(struct pci_dev *dev)