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bh=uc3EWjHx3Sz2v0LIz/ArvgoRts9u/Cd05lxvAz4CijU=; b=v6O4cOgteZ9JnoeQw0e348K/JSvHeprwjCirIRrR3nd1WCIV+94fQwHNQIAOY6QWUzZrJlana7gNt8KyE5PG0b6/Wq5SBI5MzRRrG5HnHAL90aiawUmBOzeHPFaDsBZfTgiAdkHHol+YWD7/4e+OX2dQEue2fM4i0kdndcfseJA= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Jiqian Chen To: Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , "Daniel P . Smith" , Wei Liu , Anthony PERARD , "Juergen Gross" , Stefano Stabellini , CC: Stewart Hildebrand , Alex Deucher , Xenia Ragiadakou , Stefano Stabellini , Huang Rui , Honglei Huang , Julia Zhang , Jiqian Chen , Huang Rui Subject: [RFC XEN PATCH v3 1/3] xen/vpci: Clear all vpci status of device Date: Mon, 11 Dec 2023 00:40:07 +0800 Message-ID: <20231210164009.1551147-2-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231210164009.1551147-1-Jiqian.Chen@amd.com> References: <20231210164009.1551147-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C7:EE_|BL1PR12MB5239:EE_ X-MS-Office365-Filtering-Correlation-Id: daa03549-08d2-4b98-3d6c-08dbf99eb9e0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Pzblmn7jTtL52swqfnHLNCvuw3XpUIDQ6EqG/AAJffymjkStyjY/Vfnvh0oJAJ3fHhOquzkkSjSMGUUjXQxzK4am+cLWrDn5lYYARWXSTEu3zAl/dDWNRinRUiPFtnh8hdLxL+F+5e48srhSaoGtomLvQEfYb/1xu8wQorZBEbaFi8bKPW1sWZVp7RYTWP93AiNum4eoc9sDKWIlfRWd8wEuMTVlDPsvDZLruHxT6DOml4f/0XKWTgJi7gB06lpn3Gru5Zv2LPZytVWgJaoJeJHguY1CBm6ZI6Bek8dX4exHljOX8e9v0DvNeHwL5EMjv6ZmCRDEP2r9mA/cBe82CdhwTzKM3xu0YIpvCjn4VPqU3PZey2Uq34uf+Gy/tkt5O7hu2yODqchVqqdIbSYC+LV3pdlhzQo+GayFxCeBx96uMf20GKHV5W8DegmBLrd5cY7Ml7J0TbhpB048gg/+QiSjMvrSeDnWiZisa61SYAbYsPkBmzmVdkZx0PEXO5VkOxVS5wOgkBiF3sEibXTEm3BhRynmkrs/EsSacAfLvyVBg0yO/wFKg39tTwYJgOW83bqoRyNUc9230ZuMWjBj6YmYkomM1dOvdw4MUrwKbRpup8i69/4quwXCxJDWTLYl7eTOKCA4rDerDyLoeQtkm6BrHI6g3bS5PUNDWcIDVPXqCqVUIzVhLyxL/PabM+wAmM+yqUNBpz50nYaqgQFumf1hp3d1p3luAo9gd9PD1hn5CZSEWHuTKYwhuQh0sKaEmN/oLqkoi+m1cUGtTfJbxw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(136003)(346002)(39860400002)(376002)(230922051799003)(64100799003)(82310400011)(451199024)(186009)(1800799012)(40470700004)(36840700001)(46966006)(2616005)(1076003)(36756003)(7696005)(6666004)(478600001)(70206006)(110136005)(316002)(54906003)(70586007)(8676002)(40460700003)(86362001)(4326008)(356005)(81166007)(82740400003)(36860700001)(47076005)(8936002)(40480700001)(26005)(336012)(426003)(83380400001)(16526019)(5660300002)(41300700001)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2023 16:40:32.1061 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: daa03549-08d2-4b98-3d6c-08dbf99eb9e0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5239 When a device has been reset on dom0 side, the vpci on Xen side won't get notification, so the cached state in vpci is all out of date compare with the real device state. To solve that problem, add a new hypercall to clear all vpci device state. When the state of device is reset on dom0 side, dom0 can call this hypercall to notify vpci. Co-developed-by: Huang Rui Signed-off-by: Jiqian Chen --- xen/arch/x86/hvm/hypercall.c | 1 + xen/drivers/pci/physdev.c | 35 +++++++++++++++++++++++++++++++++++ xen/drivers/vpci/vpci.c | 9 +++++++++ xen/include/public/physdev.h | 8 ++++++++ xen/include/xen/vpci.h | 6 ++++++ 5 files changed, 59 insertions(+) diff --git a/xen/arch/x86/hvm/hypercall.c b/xen/arch/x86/hvm/hypercall.c index eeb73e1aa5..6ad5b4d5f1 100644 --- a/xen/arch/x86/hvm/hypercall.c +++ b/xen/arch/x86/hvm/hypercall.c @@ -84,6 +84,7 @@ long hvm_physdev_op(int cmd, XEN_GUEST_HANDLE_PARAM(void) arg) case PHYSDEVOP_pci_mmcfg_reserved: case PHYSDEVOP_pci_device_add: case PHYSDEVOP_pci_device_remove: + case PHYSDEVOP_pci_device_state_reset: case PHYSDEVOP_dbgp_op: if ( !is_hardware_domain(currd) ) return -ENOSYS; diff --git a/xen/drivers/pci/physdev.c b/xen/drivers/pci/physdev.c index 42db3e6d13..6ee2edb86a 100644 --- a/xen/drivers/pci/physdev.c +++ b/xen/drivers/pci/physdev.c @@ -2,6 +2,7 @@ #include #include #include +#include #ifndef COMPAT typedef long ret_t; @@ -67,6 +68,40 @@ ret_t pci_physdev_op(int cmd, XEN_GUEST_HANDLE_PARAM(void) arg) break; } + case PHYSDEVOP_pci_device_state_reset: { + struct physdev_pci_device dev; + struct pci_dev *pdev; + + if ( !is_pci_passthrough_enabled() ) + return -EOPNOTSUPP; + + ret = -EFAULT; + if ( copy_from_guest(&dev, arg, 1) != 0 ) + break; + + ret = xsm_resource_setup_pci(XSM_PRIV, + (dev.seg << 16) | (dev.bus << 8) | + dev.devfn); + if ( ret ) + break; + + pcidevs_lock(); + pdev = pci_get_pdev(NULL, PCI_SBDF(dev.seg, dev.bus, dev.devfn)); + if ( !pdev ) + { + ret = -ENODEV; + pcidevs_unlock(); + break; + } + + ret = vpci_reset_device_state(pdev); + if ( ret ) + printk(XENLOG_ERR "PCI reset device %pp state failed\n", + &pdev->sbdf); + pcidevs_unlock(); + break; + } + default: ret = -ENOSYS; break; diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 72ef277c4f..3c64cb10cc 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -107,6 +107,15 @@ int vpci_add_handlers(struct pci_dev *pdev) return rc; } + +int vpci_reset_device_state(struct pci_dev *pdev) +{ + ASSERT(pcidevs_locked()); + + vpci_remove_device(pdev); + return vpci_add_handlers(pdev); +} + #endif /* __XEN__ */ static int vpci_register_cmp(const struct vpci_register *r1, diff --git a/xen/include/public/physdev.h b/xen/include/public/physdev.h index f0c0d4727c..92c2f28bca 100644 --- a/xen/include/public/physdev.h +++ b/xen/include/public/physdev.h @@ -296,6 +296,14 @@ DEFINE_XEN_GUEST_HANDLE(physdev_pci_device_add_t); */ #define PHYSDEVOP_prepare_msix 30 #define PHYSDEVOP_release_msix 31 +/* + * On PVH dom0, when device is reset, the vpci on Xen side + * won't get notification, so that the cached state in vpci is + * all out of date with the real device state. Use this to reset + * the vpci state of device. + */ +#define PHYSDEVOP_pci_device_state_reset 32 + struct physdev_pci_device { /* IN */ uint16_t seg; diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index d20c301a3d..d6377424f0 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -30,6 +30,7 @@ int __must_check vpci_add_handlers(struct pci_dev *pdev); /* Remove all handlers and free vpci related structures. */ void vpci_remove_device(struct pci_dev *pdev); +int vpci_reset_device_state(struct pci_dev *pdev); /* Add/remove a register handler. */ int __must_check vpci_add_register_mask(struct vpci *vpci, @@ -262,6 +263,11 @@ static inline int vpci_add_handlers(struct pci_dev *pdev) static inline void vpci_remove_device(struct pci_dev *pdev) { } +static inline int vpci_reset_device_state(struct pci_dev *pdev) +{ + return 0; +} + static inline void vpci_dump_msi(void) { } static inline uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg, From patchwork Sun Dec 10 16:40:08 2023 Content-Type: text/plain; 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bh=jjpP9b3zdAapc7bFnAf9Yxc26I+r5JBx8/ouifmxHE0=; b=tUo6/jvg4+b8GQNOPcU0uyR6bysLNm/ngznSrU93nLv2YFJuPbDpRYh1sY3dUdpDvvy0u0Qagy5YDFjpV+mQzpLm0mOJzJ071Sl6/rKquxxY5nA8sUNsxbElvKdUIrNcpLMVPDz3+2CqUdHzJk9S04Wou8WWXADrzCx98UEYTTU= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Jiqian Chen To: Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , "Daniel P . Smith" , Wei Liu , Anthony PERARD , "Juergen Gross" , Stefano Stabellini , CC: Stewart Hildebrand , Alex Deucher , Xenia Ragiadakou , Stefano Stabellini , Huang Rui , Honglei Huang , Julia Zhang , Jiqian Chen , Huang Rui Subject: [RFC XEN PATCH v3 2/3] x86/pvh: Add (un)map_pirq and setup_gsi for PVH dom0 Date: Mon, 11 Dec 2023 00:40:08 +0800 Message-ID: <20231210164009.1551147-3-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231210164009.1551147-1-Jiqian.Chen@amd.com> References: <20231210164009.1551147-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CC:EE_|CY5PR12MB6180:EE_ X-MS-Office365-Filtering-Correlation-Id: 89ccbc9d-b50c-4dca-3908-08dbf99ebc8d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: OETyUUkechQu1WlULDuDfcPaYtmaBz8/5yprSVaO515+2y3zobN4O/aQeVg4LPUpl9NxVM8cX9l/5grkhG+AQLzLQFcxGSt1npBXEKzVi24RUV0UOP/IeHm1821GTqQdLV4QHjjQbfLWXNqEoqCFhbAQ0yS8kLgKokcOMkxDipxcdrJscD8rQRbfmfA5hZnIv6wP3dGDUucFT0t7OxVZ19rIL7ldfqsB7d9gNGLQ0+2GtZ5ocmBoDEE9Yu4Z/xck4ZckwWvfqURB4l6xoeCYhwrPDGd5ZB67f9dDYTouNC1et0tpymVPYY465WOokwdDVeR/xhww5Lvoa6MooPeqjw9XG08XFxZtjEIJtwnk6nQv5hZgZNGB5wJF5eRYQVgZy9HrtIsYpUtGSymw7UcmfUE2B1B8boIoO03uRxkeW6t2OSGDxYvdbOW4LibihJQJH1+HKmBfsxCmuHQrQXVpKAQqSg6RA7DfIpNjOOR1EaozEkbXK8SjpV7l3mNjkJ+pKrX4D9cMA86mbgbMTEKyaAkfaMHg/9nPvmKNaFxRL16IxmxzNTwK8rzgFCP7oh6tweVPZ+60B7Ye3gn9G/6OjmZpUNw7MkZ0EkfWn+fzVlgk9s+8xdBJqSvw4mF8TliKT8xUYjEiI8VAg0ThPIuai9DhhKPMBuB2yzfknBpq2sU6vBN1jdZ9TipvE2KCUl3vWh5aZlGbESL5dg1XM7tQ9AFcBj34ynbAr/QVI8UUeFblrntDhGddcb4zrgVre4v9iLgWiJhCYwAQDdHFV/+0bA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(136003)(376002)(396003)(39860400002)(230922051799003)(1800799012)(186009)(64100799003)(82310400011)(451199024)(46966006)(40470700004)(36840700001)(478600001)(7696005)(16526019)(2616005)(6666004)(26005)(70586007)(70206006)(336012)(83380400001)(110136005)(8936002)(4326008)(2906002)(47076005)(8676002)(426003)(316002)(54906003)(36860700001)(5660300002)(86362001)(81166007)(40480700001)(356005)(82740400003)(41300700001)(36756003)(1076003)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2023 16:40:36.5952 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 89ccbc9d-b50c-4dca-3908-08dbf99ebc8d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6180 If run Xen with PVH dom0 and hvm domU, hvm will map a pirq for a passthrough device by using gsi, see xen_pt_realize->xc_physdev_map_pirq and pci_add_dm_done->xc_physdev_map_pirq. Then xc_physdev_map_pirq will call into Xen, but in hvm_physdev_op, PHYSDEVOP_map_pirq is not allowed because currd is PVH dom0 and PVH has no X86_EMU_USE_PIRQ flag, it will fail at has_pirq check. So, allow PHYSDEVOP_map_pirq when currd is dom0 no matter if dom0 has X86_EMU_USE_PIRQ flag and also allow PHYSDEVOP_unmap_pirq for the failed path to unmap pirq. What's more, in PVH dom0, the gsis don't get registered, but the gsi of a passthrough device must be configured for it to be able to be mapped into a hvm domU. So, add PHYSDEVOP_setup_gsi for PVH dom0, because PVH dom0 will setup gsi during assigning a device to passthrough. Co-developed-by: Huang Rui Signed-off-by: Jiqian Chen --- xen/arch/x86/hvm/hypercall.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/xen/arch/x86/hvm/hypercall.c b/xen/arch/x86/hvm/hypercall.c index 6ad5b4d5f1..621d789bd3 100644 --- a/xen/arch/x86/hvm/hypercall.c +++ b/xen/arch/x86/hvm/hypercall.c @@ -72,8 +72,11 @@ long hvm_physdev_op(int cmd, XEN_GUEST_HANDLE_PARAM(void) arg) switch ( cmd ) { + case PHYSDEVOP_setup_gsi: case PHYSDEVOP_map_pirq: case PHYSDEVOP_unmap_pirq: + if ( is_hardware_domain(currd) ) + break; case PHYSDEVOP_eoi: case PHYSDEVOP_irq_status_query: case PHYSDEVOP_get_free_pirq: From patchwork Sun Dec 10 16:40:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chen, Jiqian" X-Patchwork-Id: 13486467 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DD73BC4167B for ; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Jiqian Chen To: Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , "Daniel P . Smith" , Wei Liu , Anthony PERARD , "Juergen Gross" , Stefano Stabellini , CC: Stewart Hildebrand , Alex Deucher , Xenia Ragiadakou , Stefano Stabellini , Huang Rui , Honglei Huang , Julia Zhang , Jiqian Chen , Huang Rui Subject: [RFC XEN PATCH v3 3/3] libxl: Use gsi instead of irq for mapping pirq Date: Mon, 11 Dec 2023 00:40:09 +0800 Message-ID: <20231210164009.1551147-4-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231210164009.1551147-1-Jiqian.Chen@amd.com> References: <20231210164009.1551147-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C8:EE_|SA0PR12MB4559:EE_ X-MS-Office365-Filtering-Correlation-Id: 66335a6c-1a3c-429b-e1a3-08dbf99ebf35 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: XpLKbnMU7A+9gF59s8pIU3rykYXY5HbnsrnO8wouj6x0aXlPR3tOv9edy+Y0HgmteIvrREAAWSu96gfKudaWoo9Ck/URdEdoGOIPIE2jXJghYIUyp1IAyVmhJ60VxsRg0MseOjVXhSzWefqlXlZ3b+PIeY7nuyRuvidfl/RPUQMo4F8u/6OkLivxbxxkbxgtfKKS8ThSj1irR1GAkloqD6r2sRM6Z9yjW925gJZdFkaMrIrr7VVWBdpg7UlKvPFT9fZDKn2IrAHnMFdkePPHPwLJ6gQTkug0xOcQu4MEle0eP0UaeAXlNMrjnVF4rpHywlROEtvNGjngih6+PnkocT4dty3UHOQUgwfmaJdzB8VVHH3EgkG/wCH+oqw9NF2CuesR8XMcpLfJn18ZwN2nwsv5aicm7eFZfiljUClWjGwC+eQA6gmEzoAKKO+UJIvfkeHJmBeKXsAKklA/51IOZHXUkcMBNP1Pya6KmY+ZQQCbU2nliiSST8TXf9h7Cl4v5xIPBOoVMTY6uWWZSLWoh38iwFXh6dwdnbJZl5WVraN4lrr2tccPmKBE3IHsk0BRfPzJyfBrICpY/lb2lfaGirCHFSalyGA0J2+lNhgJeYQnYKexaw3L6w5Cutvyc7Eu1gVJ239yDia/wE4cb/b+3wpHnhdOiqFVCcqMopDkzyARriq+gCucqR53/CD7YuB7GIpPTF5tSC9WdXb8BLXHW7LgtrVyt7YoAd+gqsbTrcZHcXorWSaVjvFqxtPPjWJLSae07VjxnEVPdsaqpf3Bhw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(396003)(136003)(376002)(346002)(230922051799003)(451199024)(64100799003)(82310400011)(1800799012)(186009)(46966006)(40470700004)(36840700001)(40460700003)(36860700001)(5660300002)(1076003)(47076005)(336012)(26005)(2616005)(16526019)(36756003)(426003)(70586007)(70206006)(54906003)(40480700001)(2906002)(83380400001)(82740400003)(81166007)(41300700001)(356005)(478600001)(7696005)(86362001)(8676002)(8936002)(4326008)(110136005)(316002)(6666004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2023 16:40:41.0560 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 66335a6c-1a3c-429b-e1a3-08dbf99ebf35 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4559 In PVH dom0, it uses the linux local interrupt mechanism, when it allocs irq for a gsi, it is dynamic, and follow the principle of applying first, distributing first. And the irq number is alloced from small to large, but the applying gsi number is not, may gsi 38 comes before gsi 28, that causes the irq number is not equal with the gsi number. And when passthrough a device, xl wants to use gsi to map pirq, see pci_add_dm_done->xc_physdev_map_pirq, but the gsi number is got from file /sys/bus/pci/devices//irq in current code, so it will fail when mapping. So, use real gsi number read from gsi sysfs. Co-developed-by: Huang Rui Signed-off-by: Jiqian Chen --- tools/libs/light/libxl_pci.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/tools/libs/light/libxl_pci.c b/tools/libs/light/libxl_pci.c index 96cb4da079..9e75f0c263 100644 --- a/tools/libs/light/libxl_pci.c +++ b/tools/libs/light/libxl_pci.c @@ -1416,7 +1416,7 @@ static void pci_add_dm_done(libxl__egc *egc, char *sysfs_path; FILE *f; unsigned long long start, end, flags, size; - int irq, i; + int gsi, i; int r; uint32_t flag = XEN_DOMCTL_DEV_RDM_RELAXED; uint32_t domainid = domid; @@ -1439,7 +1439,7 @@ static void pci_add_dm_done(libxl__egc *egc, pci->bus, pci->dev, pci->func); f = fopen(sysfs_path, "r"); start = end = flags = size = 0; - irq = 0; + gsi = 0; if (f == NULL) { LOGED(ERROR, domainid, "Couldn't open %s", sysfs_path); @@ -1478,26 +1478,26 @@ static void pci_add_dm_done(libxl__egc *egc, fclose(f); if (!pci_supp_legacy_irq()) goto out_no_irq; - sysfs_path = GCSPRINTF(SYSFS_PCI_DEV"/"PCI_BDF"/irq", pci->domain, + sysfs_path = GCSPRINTF(SYSFS_PCI_DEV"/"PCI_BDF"/gsi", pci->domain, pci->bus, pci->dev, pci->func); f = fopen(sysfs_path, "r"); if (f == NULL) { LOGED(ERROR, domainid, "Couldn't open %s", sysfs_path); goto out_no_irq; } - if ((fscanf(f, "%u", &irq) == 1) && irq) { - r = xc_physdev_map_pirq(ctx->xch, domid, irq, &irq); + if ((fscanf(f, "%u", &gsi) == 1) && gsi) { + r = xc_physdev_map_pirq(ctx->xch, domid, gsi, &gsi); if (r < 0) { - LOGED(ERROR, domainid, "xc_physdev_map_pirq irq=%d (error=%d)", - irq, r); + LOGED(ERROR, domainid, "xc_physdev_map_pirq gsi=%d (error=%d)", + gsi, r); fclose(f); rc = ERROR_FAIL; goto out; } - r = xc_domain_irq_permission(ctx->xch, domid, irq, 1); + r = xc_domain_irq_permission(ctx->xch, domid, gsi, 1); if (r < 0) { LOGED(ERROR, domainid, - "xc_domain_irq_permission irq=%d (error=%d)", irq, r); + "xc_domain_irq_permission gsi=%d (error=%d)", gsi, r); fclose(f); rc = ERROR_FAIL; goto out;