From patchwork Mon Dec 11 09:15:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LeoLiu-oc X-Patchwork-Id: 13486886 Received: from mx2.zhaoxin.com (mx2.zhaoxin.com [203.110.167.99]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7EA04EB for ; Mon, 11 Dec 2023 01:16:00 -0800 (PST) X-ASG-Debug-ID: 1702286158-1eb14e538c2fb40001-0c9NHn Received: from ZXSHMBX1.zhaoxin.com (ZXSHMBX1.zhaoxin.com [10.28.252.163]) by mx2.zhaoxin.com with ESMTP id tlsxMCEnclsgaayR (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Mon, 11 Dec 2023 17:15:58 +0800 (CST) X-Barracuda-Envelope-From: LeoLiu-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.163 Received: from ZXBJMBX03.zhaoxin.com (10.29.252.7) by ZXSHMBX1.zhaoxin.com (10.28.252.163) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 11 Dec 2023 17:15:47 +0800 Received: from xin.lan (10.32.64.1) by ZXBJMBX03.zhaoxin.com (10.29.252.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 11 Dec 2023 17:15:44 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.163 From: LeoLiu-oc X-Barracuda-RBL-Trusted-Forwarder: 10.29.252.7 To: , , CC: , , , , LeoLiuoc Subject: [PATCH v2] PCI: Extend PCI root port device IDs for Zhaoxin platforms Date: Mon, 11 Dec 2023 17:15:43 +0800 X-ASG-Orig-Subj: [PATCH v2] PCI: Extend PCI root port device IDs for Zhaoxin platforms Message-ID: <20231211091543.735903-1-LeoLiu-oc@zhaoxin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231201120942.680075-1-LeoLiu-oc@zhaoxin.com> References: <20231201120942.680075-1-LeoLiu-oc@zhaoxin.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Barracuda-Connect: ZXSHMBX1.zhaoxin.com[10.28.252.163] X-Barracuda-Start-Time: 1702286158 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.36:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 1227 X-Barracuda-BRTS-Status: 0 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.117936 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- From: LeoLiuoc Add more PCI root port device IDs to the pci_quirk_zhaoxin_pcie_ports_acs() for some new Zhaoxin platforms. v1 -> v2: 1. Add a note to indicate future Zhaoxin devices will implement ACS Capability based on the PCIe Spec. 2. Includes DID of more Zhaoxin devices that have not yet implemented ACS Capability. Signed-off-by: LeoLiuoc --- drivers/pci/quirks.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index ea476252280a..f4546590d9e3 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4706,10 +4706,14 @@ static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) return -ENOTTY; + /* + * Future Zhaoxin Root Ports and Switch Downstream Ports will implement ACS + * capability in accordance with the PCIe Spec. + */ switch (dev->device) { case 0x0710 ... 0x071e: case 0x0721: - case 0x0723 ... 0x0732: + case 0x0723 ... 0x0752: return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); }