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b=Lv9zjOsIyayVtWYKTIBW4eeJTkICTs0ITa6b4F7KN6QHBgl5WRcNWje1CK3d5mRNYI6LAt+or56nVEbjXkYzpBKXkz47JHbpQyi99vF5QSJzdTi2b3bxnaxDeKHRwbBmZcauGD5AJ7lJWFAPBwbhGu0j9Zlf//w+qAwhJfsitss= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from VI1PR04MB4845.eurprd04.prod.outlook.com (2603:10a6:803:51::30) by AM9PR04MB7569.eurprd04.prod.outlook.com (2603:10a6:20b:2d8::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.33; Mon, 11 Dec 2023 21:59:26 +0000 Received: from VI1PR04MB4845.eurprd04.prod.outlook.com ([fe80::dfaa:e869:45eb:76e5]) by VI1PR04MB4845.eurprd04.prod.outlook.com ([fe80::dfaa:e869:45eb:76e5%6]) with mapi id 15.20.7068.031; Mon, 11 Dec 2023 21:59:26 +0000 From: Frank Li To: frank.li@nxp.com Cc: bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v3 01/13] PCI: imx6: Simplify clock handling by using HAS_CLK_* bitmask Date: Mon, 11 Dec 2023 16:58:30 -0500 Message-Id: <20231211215842.134823-2-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231211215842.134823-1-Frank.Li@nxp.com> References: <20231211215842.134823-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0009.namprd03.prod.outlook.com (2603:10b6:a03:33a::14) To VI1PR04MB4845.eurprd04.prod.outlook.com (2603:10a6:803:51::30) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR04MB4845:EE_|AM9PR04MB7569:EE_ X-MS-Office365-Filtering-Correlation-Id: 2adae40c-1c7c-4529-64a0-08dbfa946fda X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Fz4ObZDupr6bmWGs3vQGzDTdcfkQ1sI/ATHShFPUe02Xll3uYg/KYa43qH0kqQjcvLeDdVUx2dPARPzpLxMQUSi46freAhFy04stQdnX7kAUpHJR3s4LlUye96YvzdL7LSPGBfblF3glNBeg/U4kV0ftsErbU/PSTZybmWH31e1dYz8+qiNDw/qWPynTDVubiYsaSD5ciLs/SD3ACeO/MMZZXOHaWluvd9rKlsCLYMj64J1Y0THnvHBSnvx/nk07xa8vVvj8437NS2URNZJj2d0NO0nMXWnfhDZzLZF2usI05Vs3xfP+8LQRJp7ROPN7fZVC9wBeRJx1wI6QbIY5n3VBzNKaXvPp7wVkqxo/UtuUonwB5wJ3JyHZOZnnL0VBRUbY+/vbS2GvFK1yPWVdPipPWOpi7rbkd5c7vSulLms/aVwnC2Ti/4foApKWvsvMkoknNDrpGbe5peqqcdMwR4gDTMMbwAOax9TKgDJ1zwq8sQM7+4KfBUHk3tGbmpYa42E5FGXWhfmFfwM2oUMvtGY4DcURP5uZwPLJesRvkpn7r+yjrN7lW8pvOq5Ubv36MnqJtOFO4y0zxkxHFS4KOmVIyWjPgSiJWXke7D0VHlXhHpSYdJQdqBXFX2BTmzOOdbllBBXXKgmGGz3bSDcuw9h9mEycihRV4fzWQPnAzDwwmtwGZ7OmvSlMjkpmJtys1UZenmcGO40Rx+XEuxdfrJrDmXd0ziKtZs8WMJVeoYufOPkcBqJB6kjry+1QjvevH9+vinSMc1O419gmEjcUjOgzEjFfavcHfqBa/qSjF+hLRG4qQgSO2ybAeoktIxksmN0X3l0RGH+UGOseRkM8bPZ9eGA2v4aYnU1uHDYUOORvCNCwFY2k6DcwavHaUw8nIUGPiIZjCHQOs3i0HhtWj6VuWBmAO+cd4spifcxyXrOWEHnorYmIQ/7D2zs1wvPIS6QBYmFB3C7lukOcB3xyXy8PbjCr25s4h40Z6lJsOJsfZQTCOjbHyc5XBnrURBW7IK5GLrFStaGyJN54cEOrfWBs1wyDUeleCq9OqXwhI67IMiVOwgz4pglFTreAULy2rZzdyzJCZAibhq0SIHREFYiML+ZqEsHxT7UO1DQoMFWofPOQJw0cOuGzfcE87nbFUdeXbwL1uT7A69RkNx1eLlL6fz4J5/UKVRroJoiXrsfgd9WO43zeUtLdEDsek+XwVT3c2tnoTIxRxz8V9cwA8+XOR2GUmFIKerdHdFQ1RpDr9hYH/y/VfQ15p5Ec7f8PPHKgWaTLI9X42ad4U3TDtVLwqNUyREG5yCk8f6p2qP18p1HkcY8vqQmKRZQ2Y4HELfmsImX+aEz5hW2OcMkzG8N8nBLBvG8hfZtLhNykj33QRt9p16vRaHjK8gn1WMvaV2CWhadRwvH3GkC2QB3l7K87HIfDlj7HfgSjJEXs0CbYqLcgfs2U0kx0WFyF5nuwsHImAVXkbXX5cZb9G2uFgN5w541JUsFLVmyuYrsYBmOhPgilhEuXZoz0/i7cR6rLsaziuOgr5gFOtnZa6VsZwIiS+oOt0hX+6k9rqFrzvBUHB5+3uxZEs11z1NpP2MUP X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2adae40c-1c7c-4529-64a0-08dbfa946fda X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB4845.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Dec 2023 21:59:24.4624 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: esMg3kXDvfd2onBLRwOYFSn2ukRUvV+yYD9g0JVyQr1no4AjX9h9H3liRjnir9rHy3VXTxxPpQhHpOMVfSdxAg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR04MB7569 Refactors the clock handling logic in the imx6 PCI driver by adding HAS_CLK_* bitmask define for drvdata::flags . Simplifies the code and makes it more maintainable, as future additions of SOC support will only require straightforward changes. The drvdata::flags and a bitmask ensures a cleaner and more scalable switch-case structure for handling clocks. Signed-off-by: Frank Li --- Notes: Change from v1 to v3 - none drivers/pci/controller/dwc/pci-imx6.c | 84 +++++++++++++-------------- 1 file changed, 42 insertions(+), 42 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 74703362aeec7..8a9b527934f80 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -60,6 +60,10 @@ enum imx6_pcie_variants { #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) +#define IMX6_PCIE_FLAG_HAS_CLK_INBOUND_AXI BIT(3) +#define IMX6_PCIE_FLAG_HAS_CLK_AUX BIT(4) + +#define imx6_check_flag(pci, val) (pci->drvdata->flags & val) struct imx6_pcie_drvdata { enum imx6_pcie_variants variant; @@ -550,19 +554,23 @@ static int imx6_pcie_attach_pd(struct device *dev) static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) { - struct dw_pcie *pci = imx6_pcie->pci; - struct device *dev = pci->dev; unsigned int offset; int ret = 0; - switch (imx6_pcie->drvdata->variant) { - case IMX6SX: + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_CLK_INBOUND_AXI)) { ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi); - if (ret) { - dev_err(dev, "unable to enable pcie_axi clock\n"); - break; - } + if (ret) + return ret; + } + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_CLK_AUX)) { + ret = clk_prepare_enable(imx6_pcie->pcie_aux); + if (ret) + return ret; + } + + switch (imx6_pcie->drvdata->variant) { + case IMX6SX: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); break; @@ -589,12 +597,6 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) case IMX8MQ_EP: case IMX8MP: case IMX8MP_EP: - ret = clk_prepare_enable(imx6_pcie->pcie_aux); - if (ret) { - dev_err(dev, "unable to enable pcie_aux clock\n"); - break; - } - offset = imx6_pcie_grp_offset(imx6_pcie); /* * Set the over ride low and enabled @@ -614,10 +616,13 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie) { - switch (imx6_pcie->drvdata->variant) { - case IMX6SX: + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_CLK_INBOUND_AXI)) clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); - break; + + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_CLK_AUX)) + clk_disable_unprepare(imx6_pcie->pcie_aux); + + switch (imx6_pcie->drvdata->variant) { case IMX6QP: case IMX6Q: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, @@ -631,14 +636,6 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie) IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); break; - case IMX8MM: - case IMX8MM_EP: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MP: - case IMX8MP_EP: - clk_disable_unprepare(imx6_pcie->pcie_aux); - break; default: break; } @@ -1316,21 +1313,21 @@ static int imx6_pcie_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie), "pcie clock source missing or invalid\n"); - switch (imx6_pcie->drvdata->variant) { - case IMX6SX: - imx6_pcie->pcie_inbound_axi = devm_clk_get(dev, - "pcie_inbound_axi"); + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_CLK_INBOUND_AXI)) { + imx6_pcie->pcie_inbound_axi = devm_clk_get(dev, "pcie_inbound_axi"); if (IS_ERR(imx6_pcie->pcie_inbound_axi)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_inbound_axi), - "pcie_inbound_axi clock missing or invalid\n"); - break; - case IMX8MQ: - case IMX8MQ_EP: + dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_inbound_axi), + "pcie_inbound_axi clock missing or invalid\n"); + } + + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_CLK_AUX)) { imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux"); if (IS_ERR(imx6_pcie->pcie_aux)) return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), "pcie_aux clock source missing or invalid\n"); - fallthrough; + } + + switch (imx6_pcie->drvdata->variant) { case IMX7D: if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) imx6_pcie->controller_id = 1; @@ -1353,10 +1350,6 @@ static int imx6_pcie_probe(struct platform_device *pdev) case IMX8MM_EP: case IMX8MP: case IMX8MP_EP: - imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux"); - if (IS_ERR(imx6_pcie->pcie_aux)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), - "pcie_aux clock source missing or invalid\n"); imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); if (IS_ERR(imx6_pcie->apps_reset)) @@ -1482,7 +1475,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .variant = IMX6SX, .flags = IMX6_PCIE_FLAG_IMX6_PHY | IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | - IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX6_PCIE_FLAG_HAS_CLK_INBOUND_AXI, .gpr = "fsl,imx6q-iomuxc-gpr", }, [IMX6QP] = { @@ -1500,30 +1494,36 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MQ] = { .variant = IMX8MQ, + .flags = IMX6_PCIE_FLAG_HAS_CLK_AUX, .gpr = "fsl,imx8mq-iomuxc-gpr", }, [IMX8MM] = { .variant = IMX8MM, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX6_PCIE_FLAG_HAS_CLK_AUX, .gpr = "fsl,imx8mm-iomuxc-gpr", }, [IMX8MP] = { .variant = IMX8MP, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX6_PCIE_FLAG_HAS_CLK_AUX, .gpr = "fsl,imx8mp-iomuxc-gpr", }, [IMX8MQ_EP] = { .variant = IMX8MQ_EP, + .flags = IMX6_PCIE_FLAG_HAS_CLK_AUX, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mq-iomuxc-gpr", }, [IMX8MM_EP] = { .variant = IMX8MM_EP, + .flags = IMX6_PCIE_FLAG_HAS_CLK_AUX, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mm-iomuxc-gpr", }, [IMX8MP_EP] = { .variant = IMX8MP_EP, + .flags = IMX6_PCIE_FLAG_HAS_CLK_AUX, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mp-iomuxc-gpr", }, From patchwork Mon Dec 11 21:58:31 2023 Content-Type: text/plain; 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Received: from VI1PR04MB4845.eurprd04.prod.outlook.com (2603:10a6:803:51::30) by AM9PR04MB7569.eurprd04.prod.outlook.com (2603:10a6:20b:2d8::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.33; Mon, 11 Dec 2023 21:59:30 +0000 Received: from VI1PR04MB4845.eurprd04.prod.outlook.com ([fe80::dfaa:e869:45eb:76e5]) by VI1PR04MB4845.eurprd04.prod.outlook.com ([fe80::dfaa:e869:45eb:76e5%6]) with mapi id 15.20.7068.031; Mon, 11 Dec 2023 21:59:30 +0000 From: Frank Li To: frank.li@nxp.com Cc: bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v3 02/13] PCI: imx6: Simplify phy handling by using by using IMX6_PCIE_FLAG_HAS_PHY Date: Mon, 11 Dec 2023 16:58:31 -0500 Message-Id: <20231211215842.134823-3-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231211215842.134823-1-Frank.Li@nxp.com> References: <20231211215842.134823-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0009.namprd03.prod.outlook.com (2603:10b6:a03:33a::14) To VI1PR04MB4845.eurprd04.prod.outlook.com (2603:10a6:803:51::30) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR04MB4845:EE_|AM9PR04MB7569:EE_ X-MS-Office365-Filtering-Correlation-Id: c68c9b6a-2b42-4cc9-eecd-08dbfa947310 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +2rlerO0KAcT5Jqdy/jWviW7aWX614O8YBQvHrS1GfSroVhyE0sZqVbZCQOUgdUoQz9ASyEp9pf5/TfllBy8sYIkchrD9HdHJNq5dIZjrt+ZTALEOYQFFIJryZjlLMLTzqRMz4zpHNeNhraiQihjGbcA81EIBQbHKThH1MfIhZ1/SnBPdTcO6XS4lyp/Jf04ubReA+dgi6GVvQK4QAFcEkJCtrv33hMAaXPQf6NgWm4io2HGngd49aEEtHgac9a3lNLaChB8Mfke4Hsaqd+zwQehsHdkpmGV7ZR4Da3TvvC1OqdBEgXStfA64052eh6R5RxcC9sxWSJya9fUfuJGR+VCYvjTrOKC08gLqs8gux5uk+WnIn1Pvcx30c/zcCZzbAHQi4hC9gRc3NyXqEmhwTFVu4Nbad/I22IGL3TpyOXfyYnQOpx7AoI5Vl2NWb3FECEIyYNxWXKZOCNBpmFtpn26WrkbMT2LOUB/CPIGcN8jGUj8TS85cg4x0tI1pqyZ0wp1BJtPM8xvTXnx+Jj4NniFBqoCOPNBDKKHEJyBdXXYzEWeaBiBDoFNiWsjcRYjxakrXP6+/b9HIXLFJrAOvfr3Q6f25JWK4IkEjHW1typHGAPVbS6n0m1n6Z7jBBOaCFMQtyFaieQfVR/u30s+W4GHSJuoAlGXNIcSchxajQaGMTWuYQazx7zQDIZornUxyi7pq2v+F0ptpi49njgbrNVQqVLiNMFNYiwbydRNpqj+6mNi1euuM5OusrxmK4hzIpt6alA3Tu1SngSk5loyasmMM92paNjfLh7JD5JOQwCsLyqPhHxuTPHSwKUR1rRzMV02RXpYc8dVaSC6RRgCRv32269Y48xdoA9OQ3j6VH4RIHc2plS1EZix7gEOejSAFqCHxlOSHJSmFXwt2aTeVme6KS8ZU0BGA+BBSWoiBw2k4Nd3oN/kDLVFCqUywqaLtCtxFUqo0OYDLYrjshTQ6wrm/M/WnKnnA0Z09dJptQApFEq45K6XRGmAYzmU+m40xIGDNQ7NvQFFCNW09NffvaFFuj8mvyY612IdNMu2RKulmeP0T3I+YEP/vDVQcZTNBw4vGSJEDGmsBIuxSutKwDacCFL6Df3xX6NCjP7ODTES9e9VH/Cig4N9lj9J1R/A2ij1TaOZRCbUy7dm2oqPyQJRTEXAuV2CQeADH/VXqtciqtv4a9gGF0vNOwp12fuJ9mNVg1roH5zSWOdUnllbsxi5INUKgxyVsH/UPwUWE6BRBDq0Ue7RWhV2FL0z0wCHUYpL6NakUtDobP1JdQMjcoUdw2Zbw2WlNPOoBxFvuKZCvIGic2ayuFA0v2suqyj3fSqpFm7YkHXPNqH0JsnATZA3QHwDFvI/COzjrtCS+OFc2veosagEn4vL37wbRTcb/WW942zrpJoAb+wAmKI0y6y6F64GI/PJaFHMD1wb3/QvpM6YZ1fui4Olim4P7w2+qU75WsU3EW/KYsz0ZqOr9wxS1+0PKdhJSZbjgWYLgYroWNPQumVALzoW/8nBFplfJh0U7Vyjqmxpw6eDvjJ8IcH2PWs+XFlX8cEDxBim3L8zUy+5ve0cZ2esQT23Gns7 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c68c9b6a-2b42-4cc9-eecd-08dbfa947310 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB4845.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Dec 2023 21:59:30.0707 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: KHrMfRaACH7HqS3Zss6U9ehGPbFI1OzhWbuFExHmekz/Epv9AJxzAgu2XzMEbthSycb4sUMO+1XTv4dbUN9T1Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR04MB7569 Refactors the phy handling logic in the imx6 PCI driver by adding IMX6_PCIE_FLAG_HAS_PHY bitmask define for drvdata::flags. The drvdata::flags and a bitmask ensures a cleaner and more scalable switch-case structure for handling phy. Signed-off-by: Frank Li --- Notes: Change from v1 to v3: - none drivers/pci/controller/dwc/pci-imx6.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 8a9b527934f80..bcf52aa86462e 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -62,6 +62,7 @@ enum imx6_pcie_variants { #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) #define IMX6_PCIE_FLAG_HAS_CLK_INBOUND_AXI BIT(3) #define IMX6_PCIE_FLAG_HAS_CLK_AUX BIT(4) +#define IMX6_PCIE_FLAG_HAS_PHY BIT(5) #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) @@ -1327,6 +1328,13 @@ static int imx6_pcie_probe(struct platform_device *pdev) "pcie_aux clock source missing or invalid\n"); } + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY)) { + imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); + if (IS_ERR(imx6_pcie->phy)) + return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), + "failed to get pcie phy\n"); + } + switch (imx6_pcie->drvdata->variant) { case IMX7D: if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) @@ -1356,11 +1364,6 @@ static int imx6_pcie_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), "failed to get pcie apps reset control\n"); - imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); - if (IS_ERR(imx6_pcie->phy)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), - "failed to get pcie phy\n"); - break; default: break; @@ -1500,24 +1503,28 @@ static const struct imx6_pcie_drvdata drvdata[] = { [IMX8MM] = { .variant = IMX8MM, .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | - IMX6_PCIE_FLAG_HAS_CLK_AUX, + IMX6_PCIE_FLAG_HAS_CLK_AUX | + IMX6_PCIE_FLAG_HAS_PHY, .gpr = "fsl,imx8mm-iomuxc-gpr", }, [IMX8MP] = { .variant = IMX8MP, .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | - IMX6_PCIE_FLAG_HAS_CLK_AUX, + IMX6_PCIE_FLAG_HAS_CLK_AUX | + IMX6_PCIE_FLAG_HAS_PHY, .gpr = "fsl,imx8mp-iomuxc-gpr", }, [IMX8MQ_EP] = { .variant = IMX8MQ_EP, - .flags = IMX6_PCIE_FLAG_HAS_CLK_AUX, + .flags = IMX6_PCIE_FLAG_HAS_CLK_AUX | + IMX6_PCIE_FLAG_HAS_PHY, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mq-iomuxc-gpr", }, [IMX8MM_EP] = { .variant = IMX8MM_EP, - .flags = IMX6_PCIE_FLAG_HAS_CLK_AUX, + .flags = IMX6_PCIE_FLAG_HAS_CLK_AUX | + IMX6_PCIE_FLAG_HAS_PHY, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mm-iomuxc-gpr", }, From patchwork Mon Dec 11 21:58:32 2023 Content-Type: text/plain; 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Received: from VI1PR04MB4845.eurprd04.prod.outlook.com (2603:10a6:803:51::30) by AM9PR04MB7569.eurprd04.prod.outlook.com (2603:10a6:20b:2d8::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.33; Mon, 11 Dec 2023 21:59:35 +0000 Received: from VI1PR04MB4845.eurprd04.prod.outlook.com ([fe80::dfaa:e869:45eb:76e5]) by VI1PR04MB4845.eurprd04.prod.outlook.com ([fe80::dfaa:e869:45eb:76e5%6]) with mapi id 15.20.7068.031; Mon, 11 Dec 2023 21:59:35 +0000 From: Frank Li To: frank.li@nxp.com Cc: bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v3 03/13] PCI: imx6: Simplify reset handling by using by using *_FLAG_HAS_*_RESET Date: Mon, 11 Dec 2023 16:58:32 -0500 Message-Id: <20231211215842.134823-4-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231211215842.134823-1-Frank.Li@nxp.com> References: <20231211215842.134823-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0009.namprd03.prod.outlook.com (2603:10b6:a03:33a::14) To VI1PR04MB4845.eurprd04.prod.outlook.com (2603:10a6:803:51::30) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR04MB4845:EE_|AM9PR04MB7569:EE_ X-MS-Office365-Filtering-Correlation-Id: b62b6877-19e6-4d67-d988-08dbfa947668 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: cJXVSoEg/q+BVN41fbGwotB1sS/79DadJAAqmC6puT8jMbpIq7Ql84WsuqLZtt4f42qD1Bo4L0HWFtujaci7cKDGhjvh3EAK2lRvdSaHAGw65v6Dqp2yZUytaPRAiFUn38wcU57NMkUILdtqebcJLM1XRlvYYFn76S2VCJCzHuLR+UcbbwVmzChXqN+Dm9CZ91U+7pKoac5eHy1/dw9vj6YFJKteqNKEFLs82iWUt05CJ9cE2leKwcHcXx9FYfITqdXfYUARexdvJYLOMeXhREfu9E8eyTAhRXR4TkQ8i3og+1FFq+1/9Xz7nNEpE2bcGaqIwLEGHzYae7emOHbvBN04Xptb9zU0NVajRyAhLho5lu4sjkUgGFzvsBjTSELG7OB9WvelvdtRSwi1xkuIUJObQAiKusBXky9V+qcJyCFtTzR+/sbOM4zTDl8UaHAxUffug9wXDoMN5bHAz5t8b16iSq3adTlDHeMZCGlq+uekW/yvK8hIiw98KVDWxGRdf3cMZpLbDVChzKwEkK+SHDacYUkcDD9iLZkympyxF3KFswSjwqXN+mo7SwjYhU2+BsEjPMoohlb15d6ZabynANolxopGu6CWBmcfifX+h4IpiQP+rsV2hea5lQHpWrEqjkWihgPluljbrJsW4rdKcFovtzjIxnNHgY0jgiXBFaiOdK3/Bp6JxjfoyzXuTT0y0zixfpoVhP05KO3XuG6KFU4Msc0HhCtyOrShbvLJX6sStOBHzmPHB9Dt6vnIQ0720y0WWEfQ3pxizyQh5wB4h2SbcV9Sh7J0VUc9lBfIiNPN+O4WFRJvuIjv510LiBws1onrlhNbO/C49U3GI6Z0E5uDfCn8oKNfCvDH4MdoobMGXiF3gyZCPVIVko/p3Df7Sz4AVLw3ysdRpf7t1XOhd1o2DMnecrccmsBh88jwdRrq5hvJbXQS1GLKfzBMZJkqDhp8M2MbLqz6jLs/S1wSzhHLtJdlFJ7e2RZ0vpbll55fGPit7iF2GzvZcju870aYJ+Xy1SvM3a72DANe1s09mQAL4tfAsvPYu40dR8RClOJlvTBIW8/e++SjFvQW7XrmIkF7NAiyrxtuGXU8RuRhisY/INMdKyaWmGskKro6RKRM+U0MyXUetcO5BmHi8zBZsbF49/BLXDhudt0SS2Zgm+x4H6SMiEyDC7vd+bqovD/Jz2ESoHfEmCXQzguDUmRNPk0RXBzfL0oKWVDrDzbEmwFdFGNH1kMimNvqwnNS8FgDFzH6td1R+BIuRpmfIGbmvP96vrwHxLy0LrXQXWAsi4YnEbInqYThCKhlmF9p4Ny4UGsdOefbjlEJx+Rkja9SX1EFZX8xQ7IJC/7i8dKl5nHrttPHvDDjyNd958C7gOMd9PxP5jDycs+F3e/rSSJ1W7q0Nd5BJM1i284VzdjIHOgXXfDN+mHk3gN4PbF0JBvnXUpCokaQvPSkXTeG2f299gHxCI5UuxLTtq2CecAvL/0hAANLC0XxqZx1PKzMi00PtlHuj942bgLoUolSsOV6abTGlCgH/3geoIXDyaQymdPMs917AxDxXWi9U5iA2jQ+aPfUsYL58WmDA+0TN97x X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: b62b6877-19e6-4d67-d988-08dbfa947668 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB4845.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Dec 2023 21:59:35.6468 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ajd3eW5t6mLiqBEyojxZ6F7dXduCgaIawh97hOj1jdsEPmNBHSD/cFIq5EDd5kpQMJ+26SJaJOKLA8A56eqWEg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR04MB7569 Refactors the reset handling logic in the imx6 PCI driver by adding IMX6_PCIE_FLAG_HAS_*_RESET bitmask define for drvdata::flags. The drvdata::flags and a bitmask ensures a cleaner and more scalable switch-case structure for handling reset. Reviewed-by: Philipp Zabel Signed-off-by: Frank Li --- Notes: Change from v2 to v3: - add Philipp's Reviewed-by tag Change from v1 to v2: - remove condition check before reset_control_(de)assert() because it is none ops if a NULL pointer pass down. - still keep condition check at probe to help identify dts file mismatch problem. Change from v1 to v2: - remove condition check before reset_control_(de)assert() because it is none ops if a NULL pointer pass down. - still keep condition check at probe to help identify dts file mismatch problem. drivers/pci/controller/dwc/pci-imx6.c | 111 ++++++++++---------------- 1 file changed, 42 insertions(+), 69 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index bcf52aa86462e..509d459bdc5a1 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -63,6 +63,8 @@ enum imx6_pcie_variants { #define IMX6_PCIE_FLAG_HAS_CLK_INBOUND_AXI BIT(3) #define IMX6_PCIE_FLAG_HAS_CLK_AUX BIT(4) #define IMX6_PCIE_FLAG_HAS_PHY BIT(5) +#define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(6) +#define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(7) #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) @@ -696,18 +698,10 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) { + reset_control_assert(imx6_pcie->pciephy_reset); + reset_control_assert(imx6_pcie->apps_reset); + switch (imx6_pcie->drvdata->variant) { - case IMX7D: - case IMX8MQ: - case IMX8MQ_EP: - reset_control_assert(imx6_pcie->pciephy_reset); - fallthrough; - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - reset_control_assert(imx6_pcie->apps_reset); - break; case IMX6SX: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, @@ -728,6 +722,8 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); break; + default: + break; } /* Some boards don't have PCIe reset GPIO. */ @@ -741,14 +737,10 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) struct dw_pcie *pci = imx6_pcie->pci; struct device *dev = pci->dev; + reset_control_deassert(imx6_pcie->pciephy_reset); + switch (imx6_pcie->drvdata->variant) { - case IMX8MQ: - case IMX8MQ_EP: - reset_control_deassert(imx6_pcie->pciephy_reset); - break; case IMX7D: - reset_control_deassert(imx6_pcie->pciephy_reset); - /* Workaround for ERR010728, failure of PCI-e PLL VCO to * oscillate, especially when cold. This turns off "Duty-cycle * Corrector" and other mysterious undocumented things. @@ -780,11 +772,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) usleep_range(200, 500); break; - case IMX6Q: /* Nothing to do */ - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: + default: break; } @@ -831,16 +819,11 @@ static void imx6_pcie_ltssm_enable(struct device *dev) IMX6Q_GPR12_PCIE_CTL_2, IMX6Q_GPR12_PCIE_CTL_2); break; - case IMX7D: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - reset_control_deassert(imx6_pcie->apps_reset); + default: break; } + + reset_control_deassert(imx6_pcie->apps_reset); } static void imx6_pcie_ltssm_disable(struct device *dev) @@ -854,16 +837,11 @@ static void imx6_pcie_ltssm_disable(struct device *dev) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_PCIE_CTL_2, 0); break; - case IMX7D: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - reset_control_assert(imx6_pcie->apps_reset); + default: break; } + + reset_control_assert(imx6_pcie->apps_reset); } static int imx6_pcie_start_link(struct dw_pcie *pci) @@ -1335,36 +1313,24 @@ static int imx6_pcie_probe(struct platform_device *pdev) "failed to get pcie phy\n"); } - switch (imx6_pcie->drvdata->variant) { - case IMX7D: - if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) - imx6_pcie->controller_id = 1; - - imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, - "pciephy"); - if (IS_ERR(imx6_pcie->pciephy_reset)) { - dev_err(dev, "Failed to get PCIEPHY reset control\n"); - return PTR_ERR(imx6_pcie->pciephy_reset); - } - - imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, - "apps"); - if (IS_ERR(imx6_pcie->apps_reset)) { - dev_err(dev, "Failed to get PCIE APPS reset control\n"); - return PTR_ERR(imx6_pcie->apps_reset); - } - break; - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, - "apps"); + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_APP_RESET)) { + imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); if (IS_ERR(imx6_pcie->apps_reset)) return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), "failed to get pcie apps reset control\n"); + } - break; + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY_RESET)) { + imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); + if (IS_ERR(imx6_pcie->pciephy_reset)) + return dev_err_probe(dev, PTR_ERR(imx6_pcie->pciephy_reset), + "Failed to get PCIEPHY reset control\n"); + } + + switch (imx6_pcie->drvdata->variant) { + case IMX7D: + if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) + imx6_pcie->controller_id = 1; default: break; } @@ -1492,32 +1458,39 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX7D] = { .variant = IMX7D, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX6_PCIE_FLAG_HAS_APP_RESET | + IMX6_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx7d-iomuxc-gpr", }, [IMX8MQ] = { .variant = IMX8MQ, - .flags = IMX6_PCIE_FLAG_HAS_CLK_AUX, + .flags = IMX6_PCIE_FLAG_HAS_CLK_AUX | + IMX6_PCIE_FLAG_HAS_APP_RESET | + IMX6_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx8mq-iomuxc-gpr", }, [IMX8MM] = { .variant = IMX8MM, .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | IMX6_PCIE_FLAG_HAS_CLK_AUX | - IMX6_PCIE_FLAG_HAS_PHY, + IMX6_PCIE_FLAG_HAS_PHY | + IMX6_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mm-iomuxc-gpr", }, [IMX8MP] = { .variant = IMX8MP, .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | IMX6_PCIE_FLAG_HAS_CLK_AUX | - IMX6_PCIE_FLAG_HAS_PHY, + IMX6_PCIE_FLAG_HAS_PHY | + IMX6_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mp-iomuxc-gpr", }, [IMX8MQ_EP] = { .variant = IMX8MQ_EP, .flags = IMX6_PCIE_FLAG_HAS_CLK_AUX | - IMX6_PCIE_FLAG_HAS_PHY, + IMX6_PCIE_FLAG_HAS_PHY | + IMX6_PCIE_FLAG_HAS_PHY_RESET, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mq-iomuxc-gpr", }, From patchwork Mon Dec 11 21:58:33 2023 Content-Type: text/plain; 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Received: from VI1PR04MB4845.eurprd04.prod.outlook.com (2603:10a6:803:51::30) by AM9PR04MB7569.eurprd04.prod.outlook.com (2603:10a6:20b:2d8::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.33; Mon, 11 Dec 2023 21:59:41 +0000 Received: from VI1PR04MB4845.eurprd04.prod.outlook.com ([fe80::dfaa:e869:45eb:76e5]) by VI1PR04MB4845.eurprd04.prod.outlook.com ([fe80::dfaa:e869:45eb:76e5%6]) with mapi id 15.20.7068.031; Mon, 11 Dec 2023 21:59:41 +0000 From: Frank Li To: frank.li@nxp.com Cc: bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v3 04/13] PCI: imx6: Using "linux,pci-domain" as slot ID Date: Mon, 11 Dec 2023 16:58:33 -0500 Message-Id: <20231211215842.134823-5-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231211215842.134823-1-Frank.Li@nxp.com> References: <20231211215842.134823-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0009.namprd03.prod.outlook.com (2603:10b6:a03:33a::14) To VI1PR04MB4845.eurprd04.prod.outlook.com (2603:10a6:803:51::30) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR04MB4845:EE_|AM9PR04MB7569:EE_ X-MS-Office365-Filtering-Correlation-Id: 17711b2e-47d1-4d95-2715-08dbfa9479c3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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If there are more than 2 slots, compared logic will become complex. Signed-off-by: Frank Li --- Notes: Change from v2 to v3 - none Change from v1 to v2 - fix of_get_pci_domain_nr return value check logic drivers/pci/controller/dwc/pci-imx6.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 509d459bdc5a1..548034151ee1a 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -33,6 +33,7 @@ #include #include +#include "../../pci.h" #include "pcie-designware.h" #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9) @@ -1327,6 +1328,12 @@ static int imx6_pcie_probe(struct platform_device *pdev) "Failed to get PCIEPHY reset control\n"); } + /* Using linux,pci-domain as PCI slot id */ + imx6_pcie->controller_id = of_get_pci_domain_nr(node); + /* If there are not "linux,pci-domain" in dts file, means only 1 controller */ + if (imx6_pcie->controller_id < 0) + imx6_pcie->controller_id = 0; + switch (imx6_pcie->drvdata->variant) { case IMX7D: if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) From patchwork Mon Dec 11 21:58:34 2023 Content-Type: text/plain; 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Received: from VI1PR04MB4845.eurprd04.prod.outlook.com (2603:10a6:803:51::30) by AM9PR04MB7569.eurprd04.prod.outlook.com (2603:10a6:20b:2d8::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.33; Mon, 11 Dec 2023 21:59:47 +0000 Received: from VI1PR04MB4845.eurprd04.prod.outlook.com ([fe80::dfaa:e869:45eb:76e5]) by VI1PR04MB4845.eurprd04.prod.outlook.com ([fe80::dfaa:e869:45eb:76e5%6]) with mapi id 15.20.7068.031; Mon, 11 Dec 2023 21:59:47 +0000 From: Frank Li To: frank.li@nxp.com Cc: bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v3 05/13] PCI: imx6: Simplify ltssm_enable() by using ltssm_off and ltssm_mask Date: Mon, 11 Dec 2023 16:58:34 -0500 Message-Id: <20231211215842.134823-6-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231211215842.134823-1-Frank.Li@nxp.com> References: <20231211215842.134823-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0009.namprd03.prod.outlook.com (2603:10b6:a03:33a::14) To VI1PR04MB4845.eurprd04.prod.outlook.com (2603:10a6:803:51::30) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR04MB4845:EE_|AM9PR04MB7569:EE_ X-MS-Office365-Filtering-Correlation-Id: eb3afe69-0f7f-499a-35d8-08dbfa947d60 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Frank Li --- Notes: Change from v1 to v3 - none drivers/pci/controller/dwc/pci-imx6.c | 37 ++++++++++++--------------- 1 file changed, 16 insertions(+), 21 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 548034151ee1a..5bfb780e441fd 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -75,6 +75,8 @@ struct imx6_pcie_drvdata { u32 flags; int dbi_length; const char *gpr; + const u32 ltssm_off; + const u32 ltssm_mask; }; struct imx6_pcie { @@ -811,18 +813,11 @@ static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) static void imx6_pcie_ltssm_enable(struct device *dev) { struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); + const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; - switch (imx6_pcie->drvdata->variant) { - case IMX6Q: - case IMX6SX: - case IMX6QP: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6Q_GPR12_PCIE_CTL_2, - IMX6Q_GPR12_PCIE_CTL_2); - break; - default: - break; - } + if (drvdata->ltssm_mask) + regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, + drvdata->ltssm_mask); reset_control_deassert(imx6_pcie->apps_reset); } @@ -830,17 +825,11 @@ static void imx6_pcie_ltssm_enable(struct device *dev) static void imx6_pcie_ltssm_disable(struct device *dev) { struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); + const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; - switch (imx6_pcie->drvdata->variant) { - case IMX6Q: - case IMX6SX: - case IMX6QP: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6Q_GPR12_PCIE_CTL_2, 0); - break; - default: - break; - } + if (drvdata->ltssm_mask) + regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, + drvdata->ltssm_mask, 0); reset_control_assert(imx6_pcie->apps_reset); } @@ -1446,6 +1435,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, .dbi_length = 0x200, .gpr = "fsl,imx6q-iomuxc-gpr", + .ltssm_off = IOMUXC_GPR12, + .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, }, [IMX6SX] = { .variant = IMX6SX, @@ -1454,6 +1445,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | IMX6_PCIE_FLAG_HAS_CLK_INBOUND_AXI, .gpr = "fsl,imx6q-iomuxc-gpr", + .ltssm_off = IOMUXC_GPR12, + .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, }, [IMX6QP] = { .variant = IMX6QP, @@ -1462,6 +1455,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, .dbi_length = 0x200, .gpr = "fsl,imx6q-iomuxc-gpr", + .ltssm_off = IOMUXC_GPR12, + .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, }, [IMX7D] = { .variant = IMX7D, From patchwork Mon Dec 11 21:58:35 2023 Content-Type: text/plain; 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Signed-off-by: Frank Li --- Notes: Change from v2 to v3 - none Change from v1 to v2 - use ffs() to fixe build error. drivers/pci/controller/dwc/pci-imx6.c | 60 ++++++++++++++++++--------- 1 file changed, 40 insertions(+), 20 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 5bfb780e441fd..1fac6129eeb5f 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -69,6 +69,7 @@ enum imx6_pcie_variants { #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) +#define IMX6_PCIE_MAX_INSTANCES 2 struct imx6_pcie_drvdata { enum imx6_pcie_variants variant; enum dw_pcie_device_mode mode; @@ -77,6 +78,8 @@ struct imx6_pcie_drvdata { const char *gpr; const u32 ltssm_off; const u32 ltssm_mask; + const u32 mode_off[IMX6_PCIE_MAX_INSTANCES]; + const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES]; }; struct imx6_pcie { @@ -177,32 +180,25 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) { - unsigned int mask, val, mode; + const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; + unsigned int mask, val, mode, id; - if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) + if (drvdata->mode == DW_PCIE_EP_TYPE) mode = PCI_EXP_TYPE_ENDPOINT; else mode = PCI_EXP_TYPE_ROOT_PORT; - switch (imx6_pcie->drvdata->variant) { - case IMX8MQ: - case IMX8MQ_EP: - if (imx6_pcie->controller_id == 1) { - mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE; - val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, - mode); - } else { - mask = IMX6Q_GPR12_DEVICE_TYPE; - val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode); - } - break; - default: - mask = IMX6Q_GPR12_DEVICE_TYPE; - val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode); - break; - } + id = imx6_pcie->controller_id; + + /* If mode_mask[id] is zero, means each controller have its individual gpr */ + if (!drvdata->mode_mask[id]) + id = 0; + + mask = drvdata->mode_mask[id]; + /* FIELD_PREP mask have been constant */ + val = mode << (ffs(mask) - 1); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val); + regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val); } static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) @@ -1437,6 +1433,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .gpr = "fsl,imx6q-iomuxc-gpr", .ltssm_off = IOMUXC_GPR12, .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX6SX] = { .variant = IMX6SX, @@ -1447,6 +1445,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .gpr = "fsl,imx6q-iomuxc-gpr", .ltssm_off = IOMUXC_GPR12, .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX6QP] = { .variant = IMX6QP, @@ -1457,6 +1457,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .gpr = "fsl,imx6q-iomuxc-gpr", .ltssm_off = IOMUXC_GPR12, .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX7D] = { .variant = IMX7D, @@ -1464,6 +1466,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_HAS_APP_RESET | IMX6_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx7d-iomuxc-gpr", + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX8MQ] = { .variant = IMX8MQ, @@ -1471,6 +1475,10 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_HAS_APP_RESET | IMX6_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx8mq-iomuxc-gpr", + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .mode_off[1] = IOMUXC_GPR12, + .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, }, [IMX8MM] = { .variant = IMX8MM, @@ -1479,6 +1487,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_HAS_PHY | IMX6_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mm-iomuxc-gpr", + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX8MP] = { .variant = IMX8MP, @@ -1487,6 +1497,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_HAS_PHY | IMX6_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mp-iomuxc-gpr", + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX8MQ_EP] = { .variant = IMX8MQ_EP, @@ -1495,6 +1507,10 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_HAS_PHY_RESET, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mq-iomuxc-gpr", + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .mode_off[1] = IOMUXC_GPR12, + .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, }, [IMX8MM_EP] = { .variant = IMX8MM_EP, @@ -1502,12 +1518,16 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_HAS_PHY, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mm-iomuxc-gpr", + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX8MP_EP] = { .variant = IMX8MP_EP, .flags = IMX6_PCIE_FLAG_HAS_CLK_AUX, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mp-iomuxc-gpr", + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, }; 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b=YcLJ8U0fAZpdzwgApJ4RrNEiv+ZdSgFZV1bbc9lpQMbyfyfL2+1ppXEyT4s1lkuGfI4g2zFRTcAL7o92jlNoKmF9LusPAon0yIx4IA2WW4cmMcrvcL5mHEhJTcXnWAEJ/2E39uq/KFM8mHgAQVNVqPpV5reytHuwLZ9AeCxTK84= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from VI1PR04MB4845.eurprd04.prod.outlook.com (2603:10a6:803:51::30) by AM9PR04MB7569.eurprd04.prod.outlook.com (2603:10a6:20b:2d8::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.33; Mon, 11 Dec 2023 21:59:58 +0000 Received: from VI1PR04MB4845.eurprd04.prod.outlook.com ([fe80::dfaa:e869:45eb:76e5]) by VI1PR04MB4845.eurprd04.prod.outlook.com ([fe80::dfaa:e869:45eb:76e5%6]) with mapi id 15.20.7068.031; Mon, 11 Dec 2023 21:59:58 +0000 From: Frank Li To: frank.li@nxp.com Cc: bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v3 07/13] PCI: imx6: Simplify switch-case logic by involve init_phy callback Date: Mon, 11 Dec 2023 16:58:36 -0500 Message-Id: <20231211215842.134823-8-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231211215842.134823-1-Frank.Li@nxp.com> References: <20231211215842.134823-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0009.namprd03.prod.outlook.com (2603:10b6:a03:33a::14) To VI1PR04MB4845.eurprd04.prod.outlook.com (2603:10a6:803:51::30) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR04MB4845:EE_|AM9PR04MB7569:EE_ X-MS-Office365-Filtering-Correlation-Id: f2bf809f-f7ab-4d65-96b1-08dbfa9483fa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 135 ++++++++++++++------------ 1 file changed, 71 insertions(+), 64 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 1fac6129eeb5f..4e55b629d4efb 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -70,6 +70,9 @@ enum imx6_pcie_variants { #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) #define IMX6_PCIE_MAX_INSTANCES 2 + +struct imx6_pcie; + struct imx6_pcie_drvdata { enum imx6_pcie_variants variant; enum dw_pcie_device_mode mode; @@ -80,6 +83,7 @@ struct imx6_pcie_drvdata { const u32 ltssm_mask; const u32 mode_off[IMX6_PCIE_MAX_INSTANCES]; const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES]; + int (*init_phy)(struct imx6_pcie *pcie); }; struct imx6_pcie { @@ -326,76 +330,69 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) return 0; } -static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) +static int imx8mq_pcie_init_phy(struct imx6_pcie *imx6_pcie) { - switch (imx6_pcie->drvdata->variant) { - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - /* - * The PHY initialization had been done in the PHY - * driver, break here directly. - */ - break; - case IMX8MQ: - case IMX8MQ_EP: - /* - * TODO: Currently this code assumes external - * oscillator is being used - */ + /* + * TODO: Currently this code assumes external + * oscillator is being used + */ + regmap_update_bits(imx6_pcie->iomuxc_gpr, + imx6_pcie_grp_offset(imx6_pcie), + IMX8MQ_GPR_PCIE_REF_USE_PAD, + IMX8MQ_GPR_PCIE_REF_USE_PAD); + /* + * Regarding the datasheet, the PCIE_VPH is suggested + * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the + * VREG_BYPASS should be cleared to zero. + */ + if (imx6_pcie->vph && regulator_get_voltage(imx6_pcie->vph) > 3000000) regmap_update_bits(imx6_pcie->iomuxc_gpr, imx6_pcie_grp_offset(imx6_pcie), - IMX8MQ_GPR_PCIE_REF_USE_PAD, - IMX8MQ_GPR_PCIE_REF_USE_PAD); - /* - * Regarding the datasheet, the PCIE_VPH is suggested - * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the - * VREG_BYPASS should be cleared to zero. - */ - if (imx6_pcie->vph && - regulator_get_voltage(imx6_pcie->vph) > 3000000) - regmap_update_bits(imx6_pcie->iomuxc_gpr, - imx6_pcie_grp_offset(imx6_pcie), - IMX8MQ_GPR_PCIE_VREG_BYPASS, - 0); - break; - case IMX7D: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX8MQ_GPR_PCIE_VREG_BYPASS, + 0); + + return 0; +} + +static int imx7d_pcie_init_phy(struct imx6_pcie *imx6_pcie) +{ + return regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); - break; - case IMX6SX: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_RX_EQ_MASK, - IMX6SX_GPR12_PCIE_RX_EQ_2); - fallthrough; - default: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, +} + +static int imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) +{ + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); - /* configure constant input signal to the pcie ctrl and phy */ - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6Q_GPR12_LOS_LEVEL, 9 << 4); - - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, - IMX6Q_GPR8_TX_DEEMPH_GEN1, - imx6_pcie->tx_deemph_gen1 << 0); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, - IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, - imx6_pcie->tx_deemph_gen2_3p5db << 6); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, - IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, - imx6_pcie->tx_deemph_gen2_6db << 12); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, - IMX6Q_GPR8_TX_SWING_FULL, - imx6_pcie->tx_swing_full << 18); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, - IMX6Q_GPR8_TX_SWING_LOW, - imx6_pcie->tx_swing_low << 25); - break; - } + /* configure constant input signal to the pcie ctrl and phy */ + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX6Q_GPR12_LOS_LEVEL, 9 << 4); + + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + IMX6Q_GPR8_TX_DEEMPH_GEN1, + imx6_pcie->tx_deemph_gen1 << 0); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, + imx6_pcie->tx_deemph_gen2_3p5db << 6); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, + imx6_pcie->tx_deemph_gen2_6db << 12); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + IMX6Q_GPR8_TX_SWING_FULL, + imx6_pcie->tx_swing_full << 18); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + IMX6Q_GPR8_TX_SWING_LOW, + imx6_pcie->tx_swing_low << 25); + return 0; +} - imx6_pcie_configure_type(imx6_pcie); +static int imx6sx_pcie_init_phy(struct imx6_pcie *imx6_pcie) +{ + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX6SX_GPR12_PCIE_RX_EQ_MASK, IMX6SX_GPR12_PCIE_RX_EQ_2); + + return imx6_pcie_init_phy(imx6_pcie); } static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) @@ -939,7 +936,11 @@ static int imx6_pcie_host_init(struct dw_pcie_rp *pp) } imx6_pcie_assert_core_reset(imx6_pcie); - imx6_pcie_init_phy(imx6_pcie); + + if (imx6_pcie->drvdata->init_phy) + imx6_pcie->drvdata->init_phy(imx6_pcie); + + imx6_pcie_configure_type(imx6_pcie); ret = imx6_pcie_clk_enable(imx6_pcie); if (ret) { @@ -1435,6 +1436,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .init_phy = imx6_pcie_init_phy, }, [IMX6SX] = { .variant = IMX6SX, @@ -1447,6 +1449,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .init_phy = imx6sx_pcie_init_phy, }, [IMX6QP] = { .variant = IMX6QP, @@ -1459,6 +1462,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .init_phy = imx6_pcie_init_phy, }, [IMX7D] = { .variant = IMX7D, @@ -1468,6 +1472,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .gpr = "fsl,imx7d-iomuxc-gpr", .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .init_phy = imx7d_pcie_init_phy, }, [IMX8MQ] = { .variant = IMX8MQ, @@ -1479,6 +1484,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .mode_off[1] = IOMUXC_GPR12, .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, + .init_phy = imx8mq_pcie_init_phy, }, [IMX8MM] = { .variant = IMX8MM, @@ -1511,6 +1517,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .mode_off[1] = IOMUXC_GPR12, .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, + .init_phy = imx8mq_pcie_init_phy, }, [IMX8MM_EP] = { .variant = IMX8MM_EP, From patchwork Mon Dec 11 21:58:37 2023 Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 7HY82mVhLBj3fCSbUy0wtwhGAghOIIrLeY1/bQymzwAMynojsKs94N66Abk02O9sPLUoZIjTFq5H3ARpgQgEh5QdEgaFbTApQuFeOgUJTyVKfJS9PL0go7o3Zl92Xchg+HaSATnhU9fU1MW5zyZng5r+Mz3wFDa0NmAj3kYe7RFDXsWhAElYlby6WbMKeVCNCgkSPWwbEaTUyIdGLLc3XYcixEQrxXWrHQHD6axrpm/3iHpjEzwrF8pogO80qwfKCCbTjXHhamRvUl6+A4GFspYwMhV8qCVKXrMa4lglPil7KreJJCnDl52pB00eNTcl0FaLv5pCLVO+mn+XRmR1m9n5Fy5YdRQ3uyKkVfJY6im1BNdzvxI4oG3jZ8nbwSq/Hf9nbVJcMaKp2S9hyUlD4fgCVkSXBL4bzXUsxoENUfMpLZMIqXISxTqFPsI0pS++eD787EL4+qfgXiux8RIZQw7WPqtoonIasPj52ksf8511u+F9858/VI0GLzKLxgnvvzUKX2WKLOsoBe1J4qqS/DyixOaAu2Fwe5e8Xq9LhIKpsL1DwhEuxfd7aMa5wbr5HSz3zwX7ZDfqaeKJtqMwNOO1MqrGtclSnToYt1uT27/WRgq14dz1oSHD2II0U7q0eRoRz2YF8LNALHujOjcbuy/r7fVvtaHCKjILvq/JMuz1nTH3fJijy5h5PkvlnLER1Vwd6VRekigXtos5WM7GAA0C/Me0ikjXtTTCuhSOn5lbvjlkrhK9r3+AoAcA9nw//wW2CKRQ0eeQlqFi+scGUEElEemCP7F8v1c9EiXopMkhmB3G1J6GS48tw1JTfrl1cT0j2b89uHSXfpsfIwLe9bAvoYFbeB2DGV+2ou89RAVoMVJKFtFNrY00fxlH6co6Qt2LPYfVlyMt8mxR3DBtFeTIFgmogSfUDPt6oy9xLShI9Pj6arNwP/xk6m3qN7h4YxgqQ0PM7IkFPu0A0Hbkf4gxKyQGsR5JzbqB4yeQVrHQGc5QA8J8JMg3qmHCnT2Bi8KADVz84XjJQLknmqkSBmYa9NUftl3vBrWHJPoefflawjzh7cDQBAVHpkA+huWsqKWUl0k4HxfNlebq56aVXM7upDH+NvJVKwNPhs/+0GxFLTvROFzyYcrjHpeAHBX8/DzdtBFzvDxmfkgXAIq1VZrBZsL0HCos2WWdIMY2TlyWLpfYjKLeLXYEEznXAvaTfaOSJgTbpWlNxdgSof3WsSJhOfyyEIqq5PhtTsRe2KKYZYKeL39+qLkTxqGoDk0uu4uj0WDT/0zev7kQ3646bscJVeHY+2Z26ysOXUXGvA+LZRTdBMBVYIS0L8+93yeXnPhqwHTYpJ+Pb4WUrgPkDmP2tJsT03FzH1ESrDSATqIPgxPmnGB3pxmii4h9ByIDgv+XsVB/CkfYMm4Eis8nQAC+MbdL+Nw9t5bYH5hGcTkTuvsGDIvbOc3Wc406E3O9lhdq7vjivHNpgPGF2Yesher9lgop3L7s61UnT2UrJfr7cbGsR5YqgjzBryO2MkAe/QNTunZChlwUbiMkAMDiYujtUbkziTxwrOENBhan39R701WGU7r5OlgnoXBfZfxl X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0e4b017f-5cb9-438d-aa2b-08dbfa94873a X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB4845.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Dec 2023 22:00:03.5976 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: yvrQwmFnQoH7ocQ8rGu5qjUyhBCLCJpX0KguezTdHA9iRw7W7JUYMp/lNndVjzH0+XEsTcsBCWt2MzKIJmhcfw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR04MB7569 From: Richard Zhu Add i.MX95 PCIe "fsl,imx95-pcie" compatible string. Add "atu" and "serdes" to reg-names. Signed-off-by: Richard Zhu --- Notes: Change from v2 to v3 - Remove krzy's ACK tag - Add condition check for imx95, which required more reg-names then old platform, so need Krzy review again, Change from v1 to v2 - add Krzy's ACK tag .../bindings/pci/fsl,imx6q-pcie.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 81bbb8728f0f9..b8fcf8258f031 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -29,6 +29,7 @@ properties: - fsl,imx8mq-pcie - fsl,imx8mm-pcie - fsl,imx8mp-pcie + - fsl,imx95-pcie reg: items: @@ -90,6 +91,22 @@ required: allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml# + - if: + properties: + compatible: + enum: + - fsl,imx95-pcie + then: + properties: + reg: + minItems: 4 + reg-names: + items: + - const: dbi + - const: serdes + - const: atu + - const: config + - if: properties: compatible: @@ -111,6 +128,7 @@ allOf: compatible: enum: - fsl,imx8mq-pcie + - fsl,imx95-pcie then: properties: clocks: From patchwork Mon Dec 11 21:58:38 2023 Content-Type: text/plain; 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Received: from VI1PR04MB4845.eurprd04.prod.outlook.com (2603:10a6:803:51::30) by AM9PR04MB7569.eurprd04.prod.outlook.com (2603:10a6:20b:2d8::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.33; Mon, 11 Dec 2023 22:00:08 +0000 Received: from VI1PR04MB4845.eurprd04.prod.outlook.com ([fe80::dfaa:e869:45eb:76e5]) by VI1PR04MB4845.eurprd04.prod.outlook.com ([fe80::dfaa:e869:45eb:76e5%6]) with mapi id 15.20.7068.031; Mon, 11 Dec 2023 22:00:08 +0000 From: Frank Li To: frank.li@nxp.com Cc: bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v3 09/13] PCI: imx6: Add iMX95 PCIe support Date: Mon, 11 Dec 2023 16:58:38 -0500 Message-Id: <20231211215842.134823-10-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231211215842.134823-1-Frank.Li@nxp.com> References: <20231211215842.134823-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0009.namprd03.prod.outlook.com (2603:10b6:a03:33a::14) To VI1PR04MB4845.eurprd04.prod.outlook.com (2603:10a6:803:51::30) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR04MB4845:EE_|AM9PR04MB7569:EE_ X-MS-Office365-Filtering-Correlation-Id: c32d5818-c808-4533-83d8-08dbfa948a60 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Frank Li --- Notes: Change from v1 to v3 - none drivers/pci/controller/dwc/pci-imx6.c | 89 +++++++++++++++++++++++++-- 1 file changed, 84 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 4e55b629d4efb..99022efe27334 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -43,6 +43,25 @@ #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8) #define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000 +#define IMX95_PCIE_PHY_GEN_CTRL 0x0 +#define IMX95_PCIE_REF_USE_PAD BIT(17) + +#define IMX95_PCIE_PHY_MPLLA_CTRL 0x10 +#define IMX95_PCIE_PHY_MPLL_STATE BIT(30) + +#define IMX95_PCIE_SS_RW_REG_0 0xf0 +#define IMX95_PCIE_REF_CLKEN BIT(23) +#define IMX95_PCIE_PHY_CR_PARA_SEL BIT(9) + +#define IMX95_PE0_GEN_CTRL_1 0x1050 +#define IMX95_PCIE_DEVICE_TYPE GENMASK(3, 0) + +#define IMX95_PE0_GEN_CTRL_3 0x1058 +#define IMX95_PCIE_LTSSM_EN BIT(0) + +#define IMX95_PE0_PM_STS 0x1064 +#define IMX95_PCIE_PM_LINKST_IN_L2 BIT(14) + #define to_imx6_pcie(x) dev_get_drvdata((x)->dev) enum imx6_pcie_variants { @@ -53,6 +72,7 @@ enum imx6_pcie_variants { IMX8MQ, IMX8MM, IMX8MP, + IMX95, IMX8MQ_EP, IMX8MM_EP, IMX8MP_EP, @@ -66,6 +86,7 @@ enum imx6_pcie_variants { #define IMX6_PCIE_FLAG_HAS_PHY BIT(5) #define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(6) #define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(7) +#define IMX6_PCIE_FLAG_HAS_SERDES BIT(8) #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) @@ -182,6 +203,24 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; } +static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie) +{ + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX95_PCIE_SS_RW_REG_0, + IMX95_PCIE_PHY_CR_PARA_SEL, + IMX95_PCIE_PHY_CR_PARA_SEL); + + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX95_PCIE_PHY_GEN_CTRL, + IMX95_PCIE_REF_USE_PAD, 0); + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX95_PCIE_SS_RW_REG_0, + IMX95_PCIE_REF_CLKEN, + IMX95_PCIE_REF_CLKEN); + + return 0; +} + static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) { const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; @@ -589,6 +628,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); break; case IMX7D: + case IMX95: break; case IMX8MM: case IMX8MM_EP: @@ -732,10 +772,19 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) { struct dw_pcie *pci = imx6_pcie->pci; struct device *dev = pci->dev; + u32 val; reset_control_deassert(imx6_pcie->pciephy_reset); switch (imx6_pcie->drvdata->variant) { + case IMX95: + /* Polling the MPLL_STATE */ + if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr, + IMX95_PCIE_PHY_MPLLA_CTRL, val, + val & IMX95_PCIE_PHY_MPLL_STATE, + 10, 10000)) + dev_err(dev, "PCIe PLL lock timeout\n"); + break; case IMX7D: /* Workaround for ERR010728, failure of PCI-e PLL VCO to * oscillate, especially when cold. This turns off "Duty-cycle @@ -1343,12 +1392,32 @@ static int imx6_pcie_probe(struct platform_device *pdev) return PTR_ERR(imx6_pcie->turnoff_reset); } + if (imx6_pcie->drvdata->gpr) { /* Grab GPR config register range */ - imx6_pcie->iomuxc_gpr = - syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr); - if (IS_ERR(imx6_pcie->iomuxc_gpr)) { - dev_err(dev, "unable to find iomuxc registers\n"); - return PTR_ERR(imx6_pcie->iomuxc_gpr); + imx6_pcie->iomuxc_gpr = + syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr); + if (IS_ERR(imx6_pcie->iomuxc_gpr)) + return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr), + "unable to find iomuxc registers\n"); + } + + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_SERDES)) { + void __iomem *off = devm_platform_ioremap_resource_byname(pdev, "serdes"); + + if (IS_ERR(off)) + return dev_err_probe(dev, PTR_ERR(off), + "unable to find serdes registers\n"); + + static struct regmap_config regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + }; + + imx6_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, ®map_config); + if (IS_ERR(imx6_pcie->iomuxc_gpr)) + return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr), + "unable to find iomuxc registers\n"); } /* Grab PCIe PHY Tx Settings */ @@ -1506,6 +1575,15 @@ static const struct imx6_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, + [IMX95] = { + .variant = IMX95, + .flags = IMX6_PCIE_FLAG_HAS_CLK_AUX | IMX6_PCIE_FLAG_HAS_SERDES, + .ltssm_off = IMX95_PE0_GEN_CTRL_3, + .ltssm_mask = IMX95_PCIE_LTSSM_EN, + .mode_off[0] = IMX95_PE0_GEN_CTRL_1, + .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, + .init_phy = imx95_pcie_init_phy, + }, [IMX8MQ_EP] = { .variant = IMX8MQ_EP, .flags = IMX6_PCIE_FLAG_HAS_CLK_AUX | @@ -1546,6 +1624,7 @@ static const struct of_device_id imx6_pcie_of_match[] = { { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], }, { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], }, { .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], }, + { .compatible = "fsl,imx95-pcie", .data = &drvdata[IMX95], }, { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, From patchwork Mon Dec 11 21:58:39 2023 Content-Type: text/plain; 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Received: from VI1PR04MB4845.eurprd04.prod.outlook.com (2603:10a6:803:51::30) by AM9PR04MB7569.eurprd04.prod.outlook.com (2603:10a6:20b:2d8::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.33; Mon, 11 Dec 2023 22:00:14 +0000 Received: from VI1PR04MB4845.eurprd04.prod.outlook.com ([fe80::dfaa:e869:45eb:76e5]) by VI1PR04MB4845.eurprd04.prod.outlook.com ([fe80::dfaa:e869:45eb:76e5%6]) with mapi id 15.20.7068.031; Mon, 11 Dec 2023 22:00:14 +0000 From: Frank Li To: frank.li@nxp.com Cc: bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v3 10/13] PCI: imx6: Clean up get addr_space code Date: Mon, 11 Dec 2023 16:58:39 -0500 Message-Id: <20231211215842.134823-11-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231211215842.134823-1-Frank.Li@nxp.com> References: <20231211215842.134823-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0009.namprd03.prod.outlook.com (2603:10b6:a03:33a::14) To VI1PR04MB4845.eurprd04.prod.outlook.com (2603:10a6:803:51::30) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR04MB4845:EE_|AM9PR04MB7569:EE_ X-MS-Office365-Filtering-Correlation-Id: 1568c97e-dd86-4ad1-be57-08dbfa948da7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Jm2cUxnir1W/HaRcKKXDYx89XQDEHt3QSdI+Ih9JL0VUnNuiOkqNBX+AhJdPQE/NyPBzb2P4l/JzczZV9PdjWPXsTUDJr24/mLYnzoTIfEZCnkszS+VLbhLUNGZBb2CccxhjyqL7o05d2TFWBYJs6iyr/le6LhQwnTEi3T+Kn/TpZecE1h5zU0J/6ZSW5w19rTCezg4a0x7bOgk5hfOByBfboNbVy71BxdDp1fYM0iEStTnpfQHI7bJ7kb291W9I6rObIsotWoWYQE1W8nxibs5rbwYMH/ms+Vk9G3Vpe0u10hpggCwvP7IOMfTGamWlN9QJftCdHCAoFavPD++qxBxK1eaN+LizC5rqx+m0L+V3pZfBnyu7ZNfYEa87ZUquL80bQ+ncoxz55W5AKAg+SAjTh+U793na1gx8HjjYtWsZX6u4CngmBP8h0Sd9L2z2rJyLnG5ERIJm02E3GE1i+kQOeq2oJSskhq/QGOCzq1TFCHHVXJxRw/pJKz7Cp0Q+s+sqx3xJUIDx6JvMizeWk3pL1Q8tR7ESDNihLCL/i2sfvX8slKCEoqpneAy87pyaqvWWYZ2SKlUdANl6PhdtLMGPOU4DDJu4CJudCgfFfrsJUuuHw0Wu+YEHWVW7YwQRy0jWOILaBrOdztnCMKvHMgPUC9gGdoYWUH9vcMbcFGZs82NrRoiU0qydpi4mCorZPRZTCeHnqHocu0qwHnlD8mnlEMNxbNUF+L3TeHqe31m4nytkaTbpdA0bCCXI2tfKByHKGtz6oNDeSU+mAB3C/DPGj1qp0xBC1QYWxaPIPVuBq5JZK/lxQihNDDoct8yn+rEyR2Eeh2/Q8rKFPu22i/20qCehQChtDGylMJXrSUj3AKfi4j5D4NXhoqJ3yumRMUKihJjdh8BoLz7EmgO13XS6Ct/EgGpUIdLckShat/lBK2p3yqN4gDCM1fGrA2F2WnQN/OmX5NtSUcqcsU+7utALSG3nUQ7I+SqZcaZ5M2VfQiYalhI5Pe5BIj4hgAi+M++RQ2z6N9Jxk1muGRCBPKKXgmOk1GhHyFoxDV26lCejCphVNDJ/rrYsuNRljlAUIKc1xlaIJaDTdCxstetTrw5E7Kx42TqWlB/zhW9AsFMWF1v6cmdTC7/4mOAI9vjfrLHYes+mPAEMVw9FdCPc4LbAAB0lKmVSpCDX/IwShKwkUesWvNYF505VgRy4pvY21pO/da5Pbxg6inLiqEDtCP+B9XqXhYneuEVOWD1gtyRu7rGvQvPDhNOtCBXpOuDnMf3T2QfROdGUSdL04Vd/w4vgN5KJYb1QO7AghfJdOrt2gx0WKD/JfQOnlLfTMvXF5qCs4kIz3CGK+nuQ3hSIK+ZoQLf5sycMwTNyqClyCWpLckGJMPQBG0qW2LHhQF6RMw6O5i6Gqh6XMICKtSvgaybe0pCv28TTdNOYa3YifWPDgLCKOdo5DD6nYPcqD/M/Bd0UbR7hEX/BWOJkXt28vK3Xq4V2OJ83bvSL7G04GNx9OGGpT9RF6Y0ul9oGTSCEp0ThzTN7demHHnFgzShAGdZlnIaDA3shAqyMywOzxD9kVMdYpCttheYKhK3zRnXj X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1568c97e-dd86-4ad1-be57-08dbfa948da7 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB4845.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Dec 2023 22:00:14.5335 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: AwpIhNzJa4sG/ZNzpI9pEJstewcQiJH6ybOcWyKs7SC6mXFqWJnyYFs4LR/HXK/6r+prann2UJoRGY6A3ty5+A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR04MB7569 The common dw_pcie_ep_init() already do the same thing. Needn't platform driver do it again. Signed-off-by: Frank Li --- Notes: Change from v1 to v3 - new patches drivers/pci/controller/dwc/pci-imx6.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 99022efe27334..eb4e954e3a167 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1116,7 +1116,6 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, int ret; unsigned int pcie_dbi2_offset; struct dw_pcie_ep *ep; - struct resource *res; struct dw_pcie *pci = imx6_pcie->pci; struct dw_pcie_rp *pp = &pci->pp; struct device *dev = pci->dev; @@ -1135,14 +1134,8 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, pcie_dbi2_offset = SZ_4K; break; } - pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); - if (!res) - return -EINVAL; - ep->phys_base = res->start; - ep->addr_size = resource_size(res); - ep->page_size = SZ_64K; + pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset; ret = dw_pcie_ep_init(ep); if (ret) { From patchwork Mon Dec 11 21:58:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13488130 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="ss2Xytcw" Received: from EUR02-VI1-obe.outbound.protection.outlook.com (mail-vi1eur02on2083.outbound.protection.outlook.com [40.107.241.83]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9CC6198; Mon, 11 Dec 2023 14:00:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=mMwohfa6DxTuveYABOuRfjrbzmXBUGtj484bf6ezpWB+C6OQ7GMlyiThz4V4axPHgapAkDHIPdVvI+xknLSP9cJaoxQ1eUDG9qjilq/BTUmSmzvB0cAjfZMIwLnnyyIFn3Fgwh6IQeKTajeUznM9TSMUMI3qCSoe4O2/ZuUjy+TGbTDmb0d3EY7DrNM7sJaxemuLtnKzcO0gfwoB233fH+yJSJv7KW/kxNvlzMZKAZ5gWHRp9LhQcbTvFmyUXgrdUJwPANcIIIMNfy+EQZM2n4LvEws8pQF1XigP+wj67l+pckx/n+/F29m8DSvuWSGtQrVkFvKV5Al7SiqO6LM7jA== ARC-Message-Signature: i=1; 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b=ss2Xytcwlwutp0Ei0MEYKRIHH8hijq+VzBYJXC4E99y1WWLkGPxvg78cifKgvLiz1eO82cShaAhBDYq7gskoA69Jiy0/qaC/2exkIzeIBD2grgSgPKIoT3xkfNS1eKap+88hjPuHU29uXFVNWe7opKDq21tP1VxExXq3+A5kyzU= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from VI1PR04MB4845.eurprd04.prod.outlook.com (2603:10a6:803:51::30) by AM9PR04MB7569.eurprd04.prod.outlook.com (2603:10a6:20b:2d8::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.33; Mon, 11 Dec 2023 22:00:19 +0000 Received: from VI1PR04MB4845.eurprd04.prod.outlook.com ([fe80::dfaa:e869:45eb:76e5]) by VI1PR04MB4845.eurprd04.prod.outlook.com ([fe80::dfaa:e869:45eb:76e5%6]) with mapi id 15.20.7068.031; Mon, 11 Dec 2023 22:00:19 +0000 From: Frank Li To: frank.li@nxp.com Cc: bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v3 11/13] PCI: imx6: Add epc_features in imx6_pcie_drvdata Date: Mon, 11 Dec 2023 16:58:40 -0500 Message-Id: <20231211215842.134823-12-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231211215842.134823-1-Frank.Li@nxp.com> References: <20231211215842.134823-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0009.namprd03.prod.outlook.com (2603:10b6:a03:33a::14) To VI1PR04MB4845.eurprd04.prod.outlook.com (2603:10a6:803:51::30) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR04MB4845:EE_|AM9PR04MB7569:EE_ X-MS-Office365-Filtering-Correlation-Id: 41636d05-49b4-407b-6f94-08dbfa9490e5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sPGK5T44FVd+ySVZ256cT1eQZBestxU13kBmNkL3DWqK84Paq/TE6FcW+aEdgpURshHATKvcVX+5ufq2GieIvhYkPBvzt+n1j19OEk9RuZgPJxhFqmrutvKQlaDC8DQS6QSECms4783WdydukuReGJQzilRF8B8o1OlGpXB3H/RvzgWTUFEW++dy11CEk+b57yt9M+NLvsjcF3I9vtzPTss0rQowwWUbQu/lfxfU920SGOI6eqEUfdDmxN4skz+Oxrom0zTNNln43skikCafLlkE8tQK8RU5zXfhCuaeTRaF8pTpaO/TvMagSd6Rq20vLyaN9cY6tj5PuaQWdA/unDGGBncxUno5XyOlHcYOnKaqRBorju9QK5xc5OoOTgcMYScgNpqx20UMFwfCTu7s2AHeXlC/rH9XZO/BrtILVgOcHbOmKtLO5XDcmWeY1suoMovVvenPdQBGpL9xX6fV8e1lOQIcX3P0z3582j6NEOxaKByClWdrWEWWhcR4HHvEiUD1L1QjJ6DRcyTG+WTm7PtelTnPVqxqlohmneAxk19Hz6jp0q8RAqVXXoTJP94/XIXZEolx7MIDzfAEU2uJXKNzVvXPGmP0ZVTpVW6dRZz1OdT1nY8+wpsjz7C3gous0Ab/DGXV0JGUA81S1CmW3MnF74B10aL/zD/x3bDMZfdDJxHy4WfOLgF3phBo/Pfv1HTKToHQqKR89DX+bdVVVjDFZ10sy9UKdJXGXJhRSfGkMkHEU6uAORBfDg2NO+rNpOiOanz5EVROeMF5XWBb8kvh1WYUmDud0i3C0xFuDVaguiwTB0ht50Gp9PwQPBhwFR6Ai9+NKXod9I/PHXeRbn9EOogIVdBK34YCH22vl+Snc07ZbTT5+BXbpuZCTFzsliH4Wp452z9fGsdh81W80UMFOqwPMusv9BpOBSddjNqyqZgGKIjk1JCRmcE5e8dnNShvYAEUM6K+VfiUX92y4XIBsP5ArwjQND8vcHMdRTFBH+z0FT9OtHwFqHSG9s4grs9sb0g9VVfQrkjeU9aoWv/A2oQZaU1Rko+PtSVf+ugGrEQ23tnQjO8shOALUCSBR1DUUFIKBz/DCijn1f2OppVfEymgr1WTPBLa62RXMG3+xXgfRL24MfmCPHzp1S71oVE4k9Ce4d5hbLlrfCAts6uEz17sNWLqYbtRZOIHtiIBrC0MN/JvRHI0TIIxUSDFW6eqzVn6DLPxLBJaNl6nMkq2W65srkHWe/6ZteiGLXNJRJX6MiMusOnLPygmYj+SVF/kigvikkR84ul5NbTjybAtriI/j4rtEaUbQkFuXx6COwdsQkRNXR4sijK9kouIdQhzK6JwFuIKOZlx48CJZ8qM/qlG54+IJ156dJY35N/qp/z06DwF/3zplviDlQMDkGrMrKf4zw3t/DKnJ90bb54WmNem6K1MuuHsGRLUYu7OZxJONEq28fHwFw+ZIlKp3c3kvjjAKEWKF6RVvF+KLxH5CUkjp06k77pYHeY4HJd511K6VHbTVET6TVys/Ca504RFpT7/drOvOw5CPMAHnrZIO+Bs3GoNYr+7n9IjO7r0wbP+JZCkVwT8Kh6cl0OJ X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 41636d05-49b4-407b-6f94-08dbfa9490e5 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB4845.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Dec 2023 22:00:19.8155 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: B+gnfKIlfBRi53UZ951vShf2NK2xi3SKqVNCN3kSuYzyrphFsDeuGaVfACCnugQ2mkr3viCSJYgu2ryXERxtJA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR04MB7569 The i.MX EP exhibits variations in epc_features among different EP configurations. This introduces the addition of epc_features in imx6_pcie_drvdata to accommodate these differences. It's important to note that there are no functional changes in this commit; instead, it lays the groundwork for supporting i.MX95 EP functions. Signed-off-by: Frank Li --- Notes: Change from v1 to v3 - new patch at v3 drivers/pci/controller/dwc/pci-imx6.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index eb4e954e3a167..8fe66d3e947a6 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -104,6 +104,7 @@ struct imx6_pcie_drvdata { const u32 ltssm_mask; const u32 mode_off[IMX6_PCIE_MAX_INSTANCES]; const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES]; + const struct pci_epc_features *epc_features; int (*init_phy)(struct imx6_pcie *pcie); }; @@ -1101,7 +1102,10 @@ static const struct pci_epc_features imx8m_pcie_epc_features = { static const struct pci_epc_features* imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) { - return &imx8m_pcie_epc_features; + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); + + return imx6_pcie->drvdata->epc_features; } static const struct dw_pcie_ep_ops pcie_ep_ops = { @@ -1588,6 +1592,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .mode_off[1] = IOMUXC_GPR12, .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, + .epc_features = &imx8m_pcie_epc_features, .init_phy = imx8mq_pcie_init_phy, }, [IMX8MM_EP] = { @@ -1598,6 +1603,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .gpr = "fsl,imx8mm-iomuxc-gpr", .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .epc_features = &imx8m_pcie_epc_features, }, [IMX8MP_EP] = { .variant = IMX8MP_EP, @@ -1606,6 +1612,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .gpr = "fsl,imx8mp-iomuxc-gpr", .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .epc_features = &imx8m_pcie_epc_features, }, }; From patchwork Mon Dec 11 21:58:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13488131 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Authentication-Results: smtp.subspace.kernel.org; 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Add reg-name: "atu", "dbi2", "dma" and "serdes". Signed-off-by: Frank Li Acked-by: Conor Dooley --- Notes: Change from v1 to v3 - new patches at v3 .../bindings/pci/fsl,imx6q-pcie-ep.yaml | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml index ee155ed5f1811..36d8f117fdfb3 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml @@ -22,6 +22,7 @@ properties: - fsl,imx8mm-pcie-ep - fsl,imx8mq-pcie-ep - fsl,imx8mp-pcie-ep + - fsl,imx95-pcie-ep reg: minItems: 2 @@ -62,11 +63,30 @@ required: allOf: - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml# + - if: + properties: + compatible: + enum: + - fsl,imx95-pcie-ep + then: + properties: + reg: + minItems: 6 + reg-names: + items: + - const: dbi + - const: atu + - const: dbi2 + - const: serdes + - const: dma + - const: addr_space + - if: properties: compatible: enum: - fsl,imx8mq-pcie-ep + - fsl,imx95-pcie-ep then: properties: clocks: From patchwork Mon Dec 11 21:58:42 2023 Content-Type: text/plain; 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Internal bus bridge for PCI support 64bit dma address in iMX95. So set call dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)). Signed-off-by: Frank Li --- Notes: Change from v1 to v3 - new patches at v3 drivers/pci/controller/dwc/pci-imx6.c | 44 +++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 8fe66d3e947a6..31df682432e24 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -76,6 +76,7 @@ enum imx6_pcie_variants { IMX8MQ_EP, IMX8MM_EP, IMX8MP_EP, + IMX95_EP, }; #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) @@ -87,6 +88,7 @@ enum imx6_pcie_variants { #define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(6) #define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(7) #define IMX6_PCIE_FLAG_HAS_SERDES BIT(8) +#define IMX6_PCIE_FLAG_SUPPORT_64BIT BIT(9) #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) @@ -630,6 +632,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) break; case IMX7D: case IMX95: + case IMX95_EP: break; case IMX8MM: case IMX8MM_EP: @@ -1099,6 +1102,23 @@ static const struct pci_epc_features imx8m_pcie_epc_features = { .align = SZ_64K, }; +/* + * BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme + * ================================================================================================ + * BAR0 | Enable | 64-bit | 1 MB | Programmable Size + * BAR1 | Disable | 32-bit | 64 KB | Fixed Size + * | (BAR0 is 64-bit) | if BAR0 is 32-bit | | As Bar0 is 64bit + * BAR2 | Enable | 32-bit | 1 MB | Programmable Size + * BAR3 | Enable | 32-bit | 64 KB | Programmable Size + * BAR4 | Enable | 32-bit | 1M | Programmable Size + * BAR5 | Enable | 32-bit | 64 KB | Programmable Size + */ +static const struct pci_epc_features imx95_pcie_epc_features = { + .msi_capable = false, + .bar_fixed_size[1] = SZ_64K, + .align = SZ_64K, +}; + static const struct pci_epc_features* imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) { @@ -1141,6 +1161,14 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset; + /* + * db2 information should fetch from dtb file. dw_pcie_ep_init() can get dbi_base2 from + * "dbi2" if pci->dbi_base2 is NULL. All code related pcie_dbi2_offset should be removed + * after all dts added "dbi2" reg. + */ + if (imx6_pcie->drvdata->variant == IMX95_EP) + pci->dbi_base2 = NULL; + ret = dw_pcie_ep_init(ep); if (ret) { dev_err(dev, "failed to initialize endpoint\n"); @@ -1417,6 +1445,9 @@ static int imx6_pcie_probe(struct platform_device *pdev) "unable to find iomuxc registers\n"); } + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); + /* Grab PCIe PHY Tx Settings */ if (of_property_read_u32(node, "fsl,tx-deemph-gen1", &imx6_pcie->tx_deemph_gen1)) @@ -1614,6 +1645,18 @@ static const struct imx6_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .epc_features = &imx8m_pcie_epc_features, }, + [IMX95_EP] = { + .variant = IMX95_EP, + .flags = IMX6_PCIE_FLAG_HAS_CLK_AUX | IMX6_PCIE_FLAG_HAS_SERDES | + IMX6_PCIE_FLAG_SUPPORT_64BIT, + .ltssm_off = IMX95_PE0_GEN_CTRL_3, + .ltssm_mask = IMX95_PCIE_LTSSM_EN, + .mode_off[0] = IMX95_PE0_GEN_CTRL_1, + .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, + .init_phy = imx95_pcie_init_phy, + .epc_features = &imx95_pcie_epc_features, + .mode = DW_PCIE_EP_TYPE, + }, }; static const struct of_device_id imx6_pcie_of_match[] = { @@ -1628,6 +1671,7 @@ static const struct of_device_id imx6_pcie_of_match[] = { { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, + { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], }, {}, };