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([178.197.202.123]) by smtp.gmail.com with ESMTPSA id p16-20020a5d48d0000000b0033616ea5a0fsm7906913wrs.45.2023.12.12.06.12.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 06:12:00 -0800 (PST) From: Stefan Eichenberger To: maxime.chevallier@bootlin.com, mw@semihalf.com, linux@armlinux.org.uk, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v2] net: mvpp2: add support for mii Date: Tue, 12 Dec 2023 15:12:00 +0100 Message-Id: <20231212141200.62579-1-eichest@gmail.com> X-Mailer: git-send-email 2.40.1 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Currently, mvpp2 only supports RGMII. This commit adds support for MII. The description in Marvell's functional specification seems to be wrong. To enable MII, we need to set GENCONF_CTRL0_PORT3_RGMII, while for RGMII we need to clear it. This is also how U-Boot handles it. Signed-off-by: Stefan Eichenberger Reviewed-by: Maxime Chevallier Reviewed-by: Marcin Wojtas Reviewed-by: Russell King (Oracle) --- v2: - Remove PHY_INTERFACE_MODE_100BASEX from supported_interfaces (Maxime) --- .../net/ethernet/marvell/mvpp2/mvpp2_main.c | 21 ++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c index 93137606869e..c5f72a1ef928 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c @@ -1513,10 +1513,21 @@ static void mvpp22_gop_init_rgmii(struct mvpp2_port *port) regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); - if (port->gop_id == 2) + if (port->gop_id == 2) { val |= GENCONF_CTRL0_PORT2_RGMII; - else if (port->gop_id == 3) + } else if (port->gop_id == 3) { val |= GENCONF_CTRL0_PORT3_RGMII_MII; + + /* According to the specification, GENCONF_CTRL0_PORT3_RGMII + * should be set to 1 for RGMII and 0 for MII. However, tests + * show that it is the other way around. This is also what + * U-Boot does for mvpp2, so it is assumed to be correct. + */ + if (port->phy_interface == PHY_INTERFACE_MODE_MII) + val |= GENCONF_CTRL0_PORT3_RGMII; + else + val &= ~GENCONF_CTRL0_PORT3_RGMII; + } regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); } @@ -1615,6 +1626,7 @@ static int mvpp22_gop_init(struct mvpp2_port *port, phy_interface_t interface) return 0; switch (interface) { + case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII_RXID: @@ -6948,8 +6960,11 @@ static int mvpp2_port_probe(struct platform_device *pdev, MAC_10000FD; } - if (mvpp2_port_supports_rgmii(port)) + if (mvpp2_port_supports_rgmii(port)) { phy_interface_set_rgmii(port->phylink_config.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_MII, + port->phylink_config.supported_interfaces); + } if (comphy) { /* If a COMPHY is present, we can support any of the