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Fri, 15 Feb 2019 18:07:22 +0000 From: Abel Vesa To: Rob Herring , Mark Rutland , Shawn Guo , Sascha Hauer , Lucas Stach , Angus Ainslie Subject: [PATCH v2 1/3] arm64: dts: imx8mq: Add the clocks and the latencies for the A53 cores Thread-Topic: [PATCH v2 1/3] arm64: dts: imx8mq: Add the clocks and the latencies for the A53 cores Thread-Index: AQHUxVlMOnMGYj2UEkGIzXXdUVdTXw== Date: Fri, 15 Feb 2019 18:07:22 +0000 Message-ID: <1550254032-16451-2-git-send-email-abel.vesa@nxp.com> References: <1550254032-16451-1-git-send-email-abel.vesa@nxp.com> In-Reply-To: <1550254032-16451-1-git-send-email-abel.vesa@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM6PR0502CA0043.eurprd05.prod.outlook.com (2603:10a6:20b:56::20) To AM0PR04MB5779.eurprd04.prod.outlook.com (2603:10a6:208:131::23) x-originating-ip: [95.76.156.53] authentication-results: spf=none (sender IP is ) smtp.mailfrom=abel.vesa@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.7.4 x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 27cef4af-9b29-4796-d058-08d693706e84 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 9155bd4..1a89062 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -87,6 +87,8 @@ device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; }; @@ -95,6 +97,8 @@ device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; }; @@ -103,6 +107,8 @@ device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; }; @@ -111,6 +117,8 @@ device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; }; From patchwork Fri Feb 15 18:07:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 10815661 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BFCA4139A for ; Fri, 15 Feb 2019 18:07:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AD7A32F824 for ; Fri, 15 Feb 2019 18:07:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9E9422F92F; Fri, 15 Feb 2019 18:07:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAD_ENC_HEADER,BAYES_00, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 294112F824 for ; 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Fri, 15 Feb 2019 18:07:23 +0000 From: Abel Vesa To: Rob Herring , Mark Rutland , Shawn Guo , Sascha Hauer , Lucas Stach , Angus Ainslie Subject: [PATCH v2 2/3] arm64: dts: imx8mq: Add the buck vdd_arm regulator Thread-Topic: [PATCH v2 2/3] arm64: dts: imx8mq: Add the buck vdd_arm regulator Thread-Index: AQHUxVlMid01fUo1802jjVCZ5QXkdg== Date: Fri, 15 Feb 2019 18:07:23 +0000 Message-ID: <1550254032-16451-3-git-send-email-abel.vesa@nxp.com> References: <1550254032-16451-1-git-send-email-abel.vesa@nxp.com> In-Reply-To: <1550254032-16451-1-git-send-email-abel.vesa@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM6PR0502CA0043.eurprd05.prod.outlook.com (2603:10a6:20b:56::20) To AM0PR04MB5779.eurprd04.prod.outlook.com (2603:10a6:208:131::23) x-originating-ip: [95.76.156.53] authentication-results: spf=none (sender IP is ) smtp.mailfrom=abel.vesa@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.7.4 x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 8ae8c690-eaf9-43fa-d425-08d693706f1b x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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When set the gpio is set to high the regulator output is set to 0.9V. When the gpio is set to low the regulator output is set to 1V. Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 36 ++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 54737bf..e5da3dd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -31,6 +31,35 @@ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + buck2_reg: buck2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_buck2>; + compatible = "regulator-gpio"; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1000000>; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + states = <1000000 0x0 + 900000 0x1>; + enable-active-high; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; }; &fec1 { @@ -203,6 +232,13 @@ }; &iomuxc { + pinctrl_buck2: vddarmgrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 + >; + + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 From patchwork Fri Feb 15 18:07:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 10815663 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 90D2A922 for ; Fri, 15 Feb 2019 18:08:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7A11E2F824 for ; Fri, 15 Feb 2019 18:08:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 69FF52F92F; Fri, 15 Feb 2019 18:08:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAD_ENC_HEADER,BAYES_00, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E64382F824 for ; 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Fri, 15 Feb 2019 18:07:24 +0000 From: Abel Vesa To: Rob Herring , Mark Rutland , Shawn Guo , Sascha Hauer , Lucas Stach , Angus Ainslie Subject: [PATCH v2 3/3] arm64: dts: imx8mq: Add the opp table and cores opp properties Thread-Topic: [PATCH v2 3/3] arm64: dts: imx8mq: Add the opp table and cores opp properties Thread-Index: AQHUxVlNIq31A6OcskGGyy1wv+2NnQ== Date: Fri, 15 Feb 2019 18:07:24 +0000 Message-ID: <1550254032-16451-4-git-send-email-abel.vesa@nxp.com> References: <1550254032-16451-1-git-send-email-abel.vesa@nxp.com> In-Reply-To: <1550254032-16451-1-git-send-email-abel.vesa@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM6PR0502CA0043.eurprd05.prod.outlook.com (2603:10a6:20b:56::20) To AM0PR04MB5779.eurprd04.prod.outlook.com (2603:10a6:208:131::23) x-originating-ip: [95.76.156.53] authentication-results: spf=none (sender IP is ) smtp.mailfrom=abel.vesa@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.7.4 x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 08f99247-b403-46cf-8468-08d693706fbf x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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According to the datasheet: https://www.nxp.com/docs/en/data-sheet/IMX8MDQLQIEC.pdf section 3.1.3 Operating ranges. The 0.8GHz opp runs in nominal mode with the regulator set to 0.9V. The 1GHz runs in overdrive mode with the regulator set to 1V. Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 1a89062..ebdec9e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -91,6 +91,7 @@ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_0_opp_table>; }; A53_1: cpu@1 { @@ -101,6 +102,7 @@ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_0_opp_table>; }; A53_2: cpu@2 { @@ -111,6 +113,7 @@ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_0_opp_table>; }; A53_3: cpu@3 { @@ -121,6 +124,7 @@ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_0_opp_table>; }; A53_L2: l2-cache0 { @@ -666,6 +670,25 @@ status = "disabled"; }; + + a53_0_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <900000>; + clock-latency-ns = <150000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */