From patchwork Thu Dec 14 09:48:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 13492668 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="OKnX+WKN" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 441D711A; Thu, 14 Dec 2023 01:48:47 -0800 (PST) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE5uPrq000888; Thu, 14 Dec 2023 09:48:33 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=xFzkCDqolDHuGop0ghdEPVtTSSDKjiEFcdJpsmCuDfI=; b=OK nX+WKNn9E9GWJRwZ8+SQ0OwpAJH0r1IofwbYfMJEWZPbRIEowDfzr9TS3RYxxqoU Zo+4+5UEq5WbN4jc6SX/I119B/dzYaTHAsg1lcbEffg+2uYoO4Li6VJP3MCFH+X5 PPhr3CBUxhkQgDl/iz7nlO+j7QSZ5zmeCjUal/GH52gQbdHMf1qcnw79fN8O8nbM L3VNfsuRduhAWe78yAAfor2BegH6O6ClFfx1QCGRkSleP+DXwYwGuJXOm0e2ylCj hjxI6zA4ZQnEDeeBzFVVZJp1fOJZ2bnMsSnBIh0P8Ax64/t/H2g0QrXKy85Pr9Wn 9LCEp8J9S7KPNO63j/7w== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uyq9t0yaf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:48:33 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE9mWxU000756 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:48:32 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:48:27 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v7 01/14] net: phy: introduce core support for phy-mode = "10g-qxgmii" Date: Thu, 14 Dec 2023 17:48:00 +0800 Message-ID: <20231214094813.24690-2-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214094813.24690-1-quic_luoj@quicinc.com> References: <20231214094813.24690-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: mRC-5l0o1gY7iX8XrLRYTKmeJvyCyIGC X-Proofpoint-GUID: mRC-5l0o1gY7iX8XrLRYTKmeJvyCyIGC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 mlxlogscore=999 suspectscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140065 X-Patchwork-Delegate: kuba@kernel.org From: Vladimir Oltean 10G-QXGMII is a MAC-to-PHY interface defined by the USXGMII multiport specification. It uses the same signaling as USXGMII, but it multiplexes 4 ports over the link, resulting in a maximum speed of 2.5G per port. Some in-tree SoCs like the NXP LS1028A use "usxgmii" when they mean either the single-port USXGMII or the quad-port 10G-QXGMII variant, and they could get away just fine with that thus far. But there is a need to distinguish between the 2 as far as SerDes drivers are concerned. Signed-off-by: Vladimir Oltean Signed-off-by: Luo Jie Reviewed-by: Andrew Lunn Reviewed-by: Russell King (Oracle) --- Documentation/networking/phy.rst | 6 ++++++ drivers/net/phy/phy-core.c | 1 + drivers/net/phy/phylink.c | 11 +++++++++-- include/linux/phy.h | 4 ++++ include/linux/phylink.h | 2 ++ 5 files changed, 22 insertions(+), 2 deletions(-) diff --git a/Documentation/networking/phy.rst b/Documentation/networking/phy.rst index 1283240d7620..f64641417c54 100644 --- a/Documentation/networking/phy.rst +++ b/Documentation/networking/phy.rst @@ -327,6 +327,12 @@ Some of the interface modes are described below: This is the Penta SGMII mode, it is similar to QSGMII but it combines 5 SGMII lines into a single link compared to 4 on QSGMII. +``PHY_INTERFACE_MODE_10G_QXGMII`` + Represents the 10G-QXGMII PHY-MAC interface as defined by the Cisco USXGMII + Multiport Copper Interface document. It supports 4 ports over a 10.3125 GHz + SerDes lane, each port having speeds of 2.5G / 1G / 100M / 10M achieved + through symbol replication. The PCS expects the standard USXGMII code word. + Pause frames / flow control =========================== diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c index 966c93cbe616..1cd58723d6d0 100644 --- a/drivers/net/phy/phy-core.c +++ b/drivers/net/phy/phy-core.c @@ -141,6 +141,7 @@ int phy_interface_num_ports(phy_interface_t interface) return 1; case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_QUSGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: return 4; case PHY_INTERFACE_MODE_PSGMII: return 5; diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 48d3bd3e9fc7..938faac14930 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -231,6 +231,7 @@ static int phylink_interface_max_speed(phy_interface_t interface) return SPEED_1000; case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_10G_QXGMII: return SPEED_2500; case PHY_INTERFACE_MODE_5GBASER: @@ -500,7 +501,11 @@ static unsigned long phylink_get_capabilities(phy_interface_t interface, switch (interface) { case PHY_INTERFACE_MODE_USXGMII: - caps |= MAC_10000FD | MAC_5000FD | MAC_2500FD; + caps |= MAC_10000FD | MAC_5000FD; + fallthrough; + + case PHY_INTERFACE_MODE_10G_QXGMII: + caps |= MAC_2500FD; fallthrough; case PHY_INTERFACE_MODE_RGMII_TXID: @@ -941,6 +946,7 @@ static int phylink_parse_mode(struct phylink *pl, phylink_set(pl->supported, 25000baseSR_Full); fallthrough; case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: case PHY_INTERFACE_MODE_10GKR: case PHY_INTERFACE_MODE_10GBASER: phylink_set(pl->supported, 10baseT_Half); @@ -1837,7 +1843,8 @@ static int phylink_validate_phy(struct phylink *pl, struct phy_device *phy, if (phy->is_c45 && state->rate_matching == RATE_MATCH_NONE && state->interface != PHY_INTERFACE_MODE_RXAUI && state->interface != PHY_INTERFACE_MODE_XAUI && - state->interface != PHY_INTERFACE_MODE_USXGMII) + state->interface != PHY_INTERFACE_MODE_USXGMII && + state->interface != PHY_INTERFACE_MODE_10G_QXGMII) state->interface = PHY_INTERFACE_MODE_NA; return phylink_validate(pl, supported, state); diff --git a/include/linux/phy.h b/include/linux/phy.h index 6e7ebcc50b85..7697d94ac330 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -125,6 +125,7 @@ extern const int phy_10gbit_features_array[1]; * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN * @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII * @PHY_INTERFACE_MODE_1000BASEKX: 1000Base-KX - with Clause 73 AN + * @PHY_INTERFACE_MODE_10G_QXGMII: 10G-QXGMII - 4 ports over 10G USXGMII * @PHY_INTERFACE_MODE_MAX: Book keeping * * Describes the interface between the MAC and PHY. @@ -165,6 +166,7 @@ typedef enum { PHY_INTERFACE_MODE_10GKR, PHY_INTERFACE_MODE_QUSGMII, PHY_INTERFACE_MODE_1000BASEKX, + PHY_INTERFACE_MODE_10G_QXGMII, PHY_INTERFACE_MODE_MAX, } phy_interface_t; @@ -286,6 +288,8 @@ static inline const char *phy_modes(phy_interface_t interface) return "100base-x"; case PHY_INTERFACE_MODE_QUSGMII: return "qusgmii"; + case PHY_INTERFACE_MODE_10G_QXGMII: + return "10g-qxgmii"; default: return "unknown"; } diff --git a/include/linux/phylink.h b/include/linux/phylink.h index 875439ab45de..92bd2726cc8a 100644 --- a/include/linux/phylink.h +++ b/include/linux/phylink.h @@ -128,6 +128,7 @@ static inline unsigned int phylink_pcs_neg_mode(unsigned int mode, case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_QUSGMII: case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: /* These protocols are designed for use with a PHY which * communicates its negotiation result back to the MAC via * inband communication. Note: there exist PHYs that run @@ -680,6 +681,7 @@ static inline int phylink_get_link_timer_ns(phy_interface_t interface) case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: return 1600000; case PHY_INTERFACE_MODE_1000BASEX: From patchwork Thu Dec 14 09:48:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 13492671 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="IpT5kdUc" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9E8811B; Thu, 14 Dec 2023 01:48:55 -0800 (PST) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE9O7db002347; Thu, 14 Dec 2023 09:48:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=fJ0kPUacM0+GFovGU/9ppRTUtY56F7LcUFW0ZWXHPxY=; b=Ip T5kdUcTjzRKtB042rLloskSmNT1/8iMic/ELc9RgBJIXlhOEzPHzDrXDPRtlFVaS frLnBEBqnNZYrx72rS5L1PTnoMWIeu6lAFlfNn91zTeBASiIflD4f0OBZZdFRSq0 eElxqgUYHARyxFaSG54RYyl11D8FshC790e6F7iBNON4jibPiD0y7IFuNSzkw0hG HxmJRLVrJVhr+EI5tl2n86lS/IDrSy5Be4qSnqcuYQFZqKArVegEjMM6PCJt1v4B q0kjaVhMuLoMUwokJ6klqyF98eyhCtnMKKgoq2Avseu47m9LuO7WPWtJo40OWPsl T6sxTC9hkGyEICbMIBPw== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uyq66gy4d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:48:37 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE9maQj008023 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:48:36 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:48:31 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , , Conor Dooley Subject: [PATCH v7 02/14] dt-bindings: net: ethernet-controller: add 10g-qxgmii mode Date: Thu, 14 Dec 2023 17:48:01 +0800 Message-ID: <20231214094813.24690-3-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214094813.24690-1-quic_luoj@quicinc.com> References: <20231214094813.24690-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: rxAfb3TMjuynHNCPv9dv7PyGijuKEUSj X-Proofpoint-ORIG-GUID: rxAfb3TMjuynHNCPv9dv7PyGijuKEUSj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 bulkscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 phishscore=0 malwarescore=0 mlxlogscore=970 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140065 X-Patchwork-Delegate: kuba@kernel.org From: Vladimir Oltean Add the new interface mode 10g-qxgmii, which is similar to usxgmii but extend to 4 channels to support maximum of 4 ports with the link speed 10M/100M/1G/2.5G. Signed-off-by: Vladimir Oltean Signed-off-by: Luo Jie Acked-by: Conor Dooley Reviewed-by: Andrew Lunn --- Documentation/devicetree/bindings/net/ethernet-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index d14d123ad7a0..0ef6103c5fd8 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -104,6 +104,7 @@ properties: - usxgmii - 10gbase-r - 25gbase-r + - 10g-qxgmii phy-mode: $ref: "#/properties/phy-connection-type" From patchwork Thu Dec 14 09:48:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 13492670 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Sjo6Lk4r" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B335118; Thu, 14 Dec 2023 01:48:55 -0800 (PST) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE5d0lK018068; Thu, 14 Dec 2023 09:48:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=gZ/G1pFW0dLa+8o+dWcun5klmauXu0uQjqsi4LtQX7Q=; b=Sj o6Lk4rsYuaoUSPimAUc94NrhgZqDwq+IEaFD3OG49W3DoEetkpMHS6Q1hMZCouaS aEc3fCd5RgI1XCop9qS1rRnRMXkRvtL9vr1MRJlijnKBo6JVl8ZMgcBn6H3E5UZ/ ZZb3/X7uLgaOlwjpIXhMFl5iEWlUZyBTOldodMW4dWXOmKHHOD448TDcAMAoJyYm sAmC/0Taf9FPJcaOWVa7WfitsstVbN0HCRWcqE89T1vxFeFQ8PVMoHa02Cd8UoTx DsFA4w8RBmu8/9gwhjO8OQ+ZI4Tf/WwDeLU9otxE8MBhKqKTgseTX+6SMuEdhUX4 af2sFsa0QoUl9I3uCL2Q== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uynre130q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:48:41 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE9me0E008508 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:48:40 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:48:36 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v7 03/14] net: phy: at803x: add QCA8084 ethernet phy support Date: Thu, 14 Dec 2023 17:48:02 +0800 Message-ID: <20231214094813.24690-4-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214094813.24690-1-quic_luoj@quicinc.com> References: <20231214094813.24690-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: RhP1EfKtgo2pdt8Zq9Sf4r5t1XhGbXFR X-Proofpoint-GUID: RhP1EfKtgo2pdt8Zq9Sf4r5t1XhGbXFR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=965 suspectscore=0 impostorscore=0 phishscore=0 bulkscore=0 spamscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140065 X-Patchwork-Delegate: kuba@kernel.org Add qca8084 PHY support, which is four-port PHY with maximum link capability 2.5G, the features of each port is almost same as QCA8081 and slave seed config is not needed. Three kind of interface modes supported by qca8084. PHY_INTERFACE_MODE_10G_QXGMII, PHY_INTERFACE_MODE_2500BASEX and PHY_INTERFACE_MODE_SGMII. The PCS(serdes) and clock are also needed to be configured to bringup qca8084 PHY, which will be added in the pcs driver. The additional CDT configurations used for qca8084. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 49 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 37fb033e1c29..8dfdf2ff56a5 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -176,6 +176,7 @@ #define AT8030_PHY_ID_MASK 0xffffffef #define QCA8081_PHY_ID 0x004dd101 +#define QCA8084_PHY_ID 0x004dd180 #define QCA8327_A_PHY_ID 0x004dd033 #define QCA8327_B_PHY_ID 0x004dd034 @@ -1760,6 +1761,9 @@ static bool qca808x_is_prefer_master(struct phy_device *phydev) static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev) { + if (phydev_id_compare(phydev, QCA8084_PHY_ID)) + return false; + return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); } @@ -1824,6 +1828,23 @@ static int qca808x_read_status(struct phy_device *phydev) return ret; if (phydev->link) { + /* There are two PCSs available for QCA8084, which support the + * following interface modes. + * + * 1. PHY_INTERFACE_MODE_10G_QXGMII utilizes PCS1 for all + * available 4 ports, which is for all link speeds. + * + * 2. PHY_INTERFACE_MODE_2500BASEX utilizes PCS0 for the + * fourth port, which is only for the link speed 2500M same + * as QCA8081. + * + * 3. PHY_INTERFACE_MODE_SGMII utilizes PCS0 for the fourth + * port, which is for the link speed 10M, 100M and 1000M same + * as QCA8081. + */ + if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII) + return 0; + if (phydev->speed == SPEED_2500) phydev->interface = PHY_INTERFACE_MODE_2500BASEX; else @@ -1958,6 +1979,14 @@ static int qca808x_cable_test_start(struct phy_device *phydev) phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); + if (phydev_id_compare(phydev, QCA8084_PHY_ID)) { + /* Adjust the positive and negative pulse thereshold of CDT */ + phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8075, 0xa060); + + /* Disable the near echo bypass */ + phy_modify_mmd(phydev, MDIO_MMD_PCS, 0x807f, BIT(15), 0); + } + return 0; } @@ -2227,6 +2256,25 @@ static struct phy_driver at803x_driver[] = { .cable_test_start = qca808x_cable_test_start, .cable_test_get_status = qca808x_cable_test_get_status, .link_change_notify = qca808x_link_change_notify, +}, { + /* Qualcomm QCA8084 */ + PHY_ID_MATCH_MODEL(QCA8084_PHY_ID), + .name = "Qualcomm QCA8084", + .flags = PHY_POLL_CABLE_TEST, + .config_intr = at803x_config_intr, + .handle_interrupt = at803x_handle_interrupt, + .get_tunable = at803x_get_tunable, + .set_tunable = at803x_set_tunable, + .set_wol = at803x_set_wol, + .get_wol = at803x_get_wol, + .get_features = qca808x_get_features, + .config_aneg = at803x_config_aneg, + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_status = qca808x_read_status, + .soft_reset = qca808x_soft_reset, + .cable_test_start = qca808x_cable_test_start, + .cable_test_get_status = qca808x_cable_test_get_status, }, }; module_phy_driver(at803x_driver); @@ -2242,6 +2290,7 @@ static struct mdio_device_id __maybe_unused atheros_tbl[] = { { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, + { PHY_ID_MATCH_MODEL(QCA8084_PHY_ID) }, { } }; From patchwork Thu Dec 14 09:48:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 13492672 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="TMTAO+3R" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6CCE115; Thu, 14 Dec 2023 01:48:59 -0800 (PST) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE9MNtf021355; Thu, 14 Dec 2023 09:48:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=0bVysHhmiIwOWR5neHsBpe+iBusVLfMfldDRhFy7W/U=; b=TM TAO+3R5ieHFgpyIiLyw7VEToa4jK6LoQ1BDDP3ArMFqnkeAa7uUUDiqhR5DGB88A F3drXwBMUxFM+3utW5pH4mzSa3NoJQ007UVsi3MsFOZPL52ZsBLqIm3NykhgbUJu RNTwlMfTKk2pzDc7owTJxjbHimtLY79+ZTYB7QGsEng1ITEoFnEnvv/ga6Z+VYDK PUig9PZRV24AxfPiZvza03jAqnxquprY/cTlHkXhY9tr3SJE7qAfnXGIZDhVwlsS 4Gw12ZA3Bao6kpS/mEgSOAg8ajjJ9P3B3r26UHnN5tCEoJU2pEI7WhnThZwQNviU n8ri4zV7W8EwYUw+DFoQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uyp0p92uq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:48:46 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE9mjmj006323 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:48:45 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:48:40 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v7 04/14] net: phy: at803x: add the function phydev_id_is_qca808x Date: Thu, 14 Dec 2023 17:48:03 +0800 Message-ID: <20231214094813.24690-5-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214094813.24690-1-quic_luoj@quicinc.com> References: <20231214094813.24690-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: BGPm8VSDTEI6Fp5UWSGCowun_Q7j8vPW X-Proofpoint-GUID: BGPm8VSDTEI6Fp5UWSGCowun_Q7j8vPW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 phishscore=0 impostorscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140065 X-Patchwork-Delegate: kuba@kernel.org The function phydev_id_is_qca808x is applicable to the PHY qca8081 and qca8084. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 8dfdf2ff56a5..143f0d2e36a6 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -1165,6 +1165,12 @@ static void at803x_link_change_notify(struct phy_device *phydev) } } +static bool phydev_id_is_qca808x(struct phy_device *phydev) +{ + return phydev_id_compare(phydev, QCA8081_PHY_ID) || + phydev_id_compare(phydev, QCA8084_PHY_ID); +} + static int at803x_read_specific_status(struct phy_device *phydev) { int ss; @@ -1184,8 +1190,8 @@ static int at803x_read_specific_status(struct phy_device *phydev) if (sfc < 0) return sfc; - /* qca8081 takes the different bits for speed value from at803x */ - if (phydev->drv->phy_id == QCA8081_PHY_ID) + /* qca808x takes the different bits for speed value from at803x */ + if (phydev_id_is_qca808x(phydev)) speed = FIELD_GET(QCA808X_SS_SPEED_MASK, ss); else speed = FIELD_GET(AT803X_SS_SPEED_MASK, ss); @@ -1316,7 +1322,7 @@ static int at803x_config_aneg(struct phy_device *phydev) */ ret = 0; - if (phydev->drv->phy_id == QCA8081_PHY_ID) { + if (phydev_id_is_qca808x(phydev)) { int phy_ctrl = 0; /* The reg MII_BMCR also needs to be configured for force mode, the @@ -1470,8 +1476,8 @@ static int at803x_cdt_start(struct phy_device *phydev, int pair) { u16 cdt; - /* qca8081 takes the different bit 15 to enable CDT test */ - if (phydev->drv->phy_id == QCA8081_PHY_ID) + /* qca808x takes the different bit 15 to enable CDT test */ + if (phydev_id_is_qca808x(phydev)) cdt = QCA808X_CDT_ENABLE_TEST | QCA808X_CDT_LENGTH_UNIT | QCA808X_CDT_INTER_CHECK_DIS; @@ -1487,7 +1493,7 @@ static int at803x_cdt_wait_for_completion(struct phy_device *phydev) int val, ret; u16 cdt_en; - if (phydev->drv->phy_id == QCA8081_PHY_ID) + if (phydev_id_is_qca808x(phydev)) cdt_en = QCA808X_CDT_ENABLE_TEST; else cdt_en = AT803X_CDT_ENABLE_TEST; From patchwork Thu Dec 14 09:48:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 13492673 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Q+6Kucqe" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3DDAA118; Thu, 14 Dec 2023 01:49:04 -0800 (PST) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE8k2hR017630; Thu, 14 Dec 2023 09:48:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=g1/PSi7VGkjdeLX+7/20eelyP/TKgqeOerVb/AB4m5E=; b=Q+ 6Kucqe6Hyr1jN9o+GdfITFsebJQfe4JJcWN/rbWE930l+NT+nsBWplPb6pljGKHW bS1Aw3AZKsfxkg6y1yFucFRLNMDOLlfXENFeN7mAa8FTt1ZlTN30lYKVofCYAMVc O8Yb+4czgyFpEk9/KptwgLOuA19NM8W5ndqTjnFCEQj2Qg/BP5+B4pYmqwd0ky12 z/xxplvMLZr+0Fli5lPXC3HMwwNPtmmzkVArdnxmNdR+ku1rptOYhz8dQ2iKlVSL t2vUzhMjadeCajCwlUJQed+E9pUc6f3oSOtjuhCQhii+WZTID1Vf3fHbqa+Vxr9O W1Q6XiEmixoNxhzoOWGA== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uytn68jwu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:48:50 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE9mn8e016536 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:48:49 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:48:45 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v7 05/14] net: phy: at803x: Add qca8084_config_init function Date: Thu, 14 Dec 2023 17:48:04 +0800 Message-ID: <20231214094813.24690-6-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214094813.24690-1-quic_luoj@quicinc.com> References: <20231214094813.24690-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: QRAe3tA68AcDDTlUQBoC24ioP5h0tAK_ X-Proofpoint-ORIG-GUID: QRAe3tA68AcDDTlUQBoC24ioP5h0tAK_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 phishscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 bulkscore=0 impostorscore=0 adultscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140065 X-Patchwork-Delegate: kuba@kernel.org Configure MSE detect threshold and ADC clock edge invert. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 143f0d2e36a6..ba5d069ad351 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -280,6 +280,15 @@ #define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072 #define QCA8081_PHY_FIFO_RSTN BIT(11) +/* QCA8084 ADC clock edge */ +#define QCA8084_ADC_CLK_SEL 0x8b80 +#define QCA8084_ADC_CLK_SEL_ACLK GENMASK(7, 4) +#define QCA8084_ADC_CLK_SEL_ACLK_FALL 0xf +#define QCA8084_ADC_CLK_SEL_ACLK_RISE 0x0 + +#define QCA8084_MSE_THRESHOLD 0x800a +#define QCA8084_MSE_THRESHOLD_2P5G_VAL 0x51c6 + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -2085,6 +2094,26 @@ static void qca808x_link_change_notify(struct phy_device *phydev) QCA8081_PHY_FIFO_RSTN, phydev->link ? QCA8081_PHY_FIFO_RSTN : 0); } +static int qca8084_config_init(struct phy_device *phydev) +{ + int ret; + + /* Invert ADC clock edge */ + ret = at803x_debug_reg_mask(phydev, QCA8084_ADC_CLK_SEL, + QCA8084_ADC_CLK_SEL_ACLK, + FIELD_PREP(QCA8084_ADC_CLK_SEL_ACLK, + QCA8084_ADC_CLK_SEL_ACLK_FALL)); + if (ret < 0) + return ret; + + /* Adjust MSE threshold value to avoid link issue with + * some link partner. + */ + return phy_write_mmd(phydev, MDIO_MMD_PMAPMD, + QCA8084_MSE_THRESHOLD, + QCA8084_MSE_THRESHOLD_2P5G_VAL); +} + static struct phy_driver at803x_driver[] = { { /* Qualcomm Atheros AR8035 */ @@ -2281,6 +2310,7 @@ static struct phy_driver at803x_driver[] = { .soft_reset = qca808x_soft_reset, .cable_test_start = qca808x_cable_test_start, .cable_test_get_status = qca808x_cable_test_get_status, + .config_init = qca8084_config_init, }, }; module_phy_driver(at803x_driver); From patchwork Thu Dec 14 09:48:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 13492674 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="lKQWqLP5" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD0D0186; Thu, 14 Dec 2023 01:49:08 -0800 (PST) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE6F5uM020469; Thu, 14 Dec 2023 09:48:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=y0D0iHXYA2UwA5V/ss5IJKv+axl//qAJpDzVbQOftAs=; b=lK QWqLP5DkWjGLtg7TE6eN4Eqk3w5YjE559rz+3mOhnrhVUrAk+qIdYL49KtCPNtss H+/CtO/7lB54QsClBR+SpKWriZAbhbONAVwh+fkPxo12M2biixljcoRVBk3fW7Jq w/wW5IFB63H6IXLTzIXpuK1yDEBQ/zH7u3uFdS4T74k5Mspx1uTwsACNBKa9Lj4e wz/rRlK7ySl6wajTNAYXbJW0+BJIJkfzeMN+x6vjtQGZYy7RfssDZ0gA0/DKIiYA HhQDCAcGl3V2Ekw0CsIV+t2SP1dXwaiXXuve+motCBczXl+//FigH7JtL6jNVc1V rGQfdoENvQMLSMY0mUYA== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uyqgt0x6v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:48:55 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE9msk8016564 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:48:54 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:48:49 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v7 06/14] net: phy: at803x: add qca8084_link_change_notify Date: Thu, 14 Dec 2023 17:48:05 +0800 Message-ID: <20231214094813.24690-7-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214094813.24690-1-quic_luoj@quicinc.com> References: <20231214094813.24690-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: JS8OlbMNkJnE_wXl87Cfi-nGgSakcntL X-Proofpoint-ORIG-GUID: JS8OlbMNkJnE_wXl87Cfi-nGgSakcntL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 mlxlogscore=999 mlxscore=0 clxscore=1015 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140065 X-Patchwork-Delegate: kuba@kernel.org When the link is changed, qca8084 needs to do the fifo reset and adjust the IPG level for the qusgmii link speed 1000M. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 41 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index ba5d069ad351..b6b41b1a4352 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -289,6 +289,13 @@ #define QCA8084_MSE_THRESHOLD 0x800a #define QCA8084_MSE_THRESHOLD_2P5G_VAL 0x51c6 +#define QCA8084_FIFO_CONTROL 0x19 +#define QCA8084_FIFO_MAC_2_PHY BIT(1) +#define QCA8084_FIFO_PHY_2_MAC BIT(0) + +#define QCA8084_MMD7_IPG_OP 0x901d +#define QCA8084_IPG_10_TO_11_EN BIT(0) + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -2114,6 +2121,39 @@ static int qca8084_config_init(struct phy_device *phydev) QCA8084_MSE_THRESHOLD_2P5G_VAL); } +static void qca8084_link_change_notify(struct phy_device *phydev) +{ + int ret; + + ret = phy_modify(phydev, QCA8084_FIFO_CONTROL, + QCA8084_FIFO_MAC_2_PHY | QCA8084_FIFO_PHY_2_MAC, + 0); + if (ret) + return; + + /* If the PHY works on PHY_INTERFACE_MODE_10G_QXGMII mode, the fifo + * needs to be kept as reset state in link down status. + */ + if (phydev->interface != PHY_INTERFACE_MODE_10G_QXGMII || + phydev->link) { + msleep(50); + ret = phy_modify(phydev, QCA8084_FIFO_CONTROL, + QCA8084_FIFO_MAC_2_PHY | + QCA8084_FIFO_PHY_2_MAC, + QCA8084_FIFO_MAC_2_PHY | + QCA8084_FIFO_PHY_2_MAC); + if (ret) + return; + } + + /* Enable IPG 10 to 11 tuning on link speed 1000M of QUSGMII mode. */ + if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII) + phy_modify_mmd(phydev, MDIO_MMD_AN, QCA8084_MMD7_IPG_OP, + QCA8084_IPG_10_TO_11_EN, + phydev->speed == SPEED_1000 ? + QCA8084_IPG_10_TO_11_EN : 0); +} + static struct phy_driver at803x_driver[] = { { /* Qualcomm Atheros AR8035 */ @@ -2311,6 +2351,7 @@ static struct phy_driver at803x_driver[] = { .cable_test_start = qca808x_cable_test_start, .cable_test_get_status = qca808x_cable_test_get_status, .config_init = qca8084_config_init, + .link_change_notify = qca8084_link_change_notify, }, }; module_phy_driver(at803x_driver); From patchwork Thu Dec 14 09:48:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 13492675 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="hOlAVQCO" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C56E1AA; Thu, 14 Dec 2023 01:49:14 -0800 (PST) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE5VDxc031722; Thu, 14 Dec 2023 09:49:00 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=t69PPg+jCem4K6Eo0WgGA6QNG+KxgQaYrvmj24AWmE8=; b=hO lAVQCOeP0+EFAlSzjzj63U3VKPaLC+rgRgf6hehkLrPxbNPKAlWBKRSmL4sWf4fA qLtquyAMT1/eD3X5jhVK2zxK03B9ToLujcoUmRzM0TMw/yJ65BJBO8JKFi3ycTQL C1FIbZ7rN/jw2EzkLmaP+mCWvhMGLE+E7GEqgvrep8SJwWnqltoFMFSiEmXCwWPK zZ7lYVBt5oPtTIHJuRBrIBiMR4QLfpGrBSRxtiPVns2NeISRqTrs1ThcJTxetIaf cc4mV3K3pWks1RNDgNVCGHfmAXNopoGVkRIsD69Y5QZUTz4jCtgaMxCVLbQgjcDc M9NTc2QHdaHa0rSoBrKA== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uyqgt0x70-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:48:59 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE9mx25024099 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:48:59 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:48:54 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v7 07/14] net: phy: at803x: add the possible_interfaces Date: Thu, 14 Dec 2023 17:48:06 +0800 Message-ID: <20231214094813.24690-8-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214094813.24690-1-quic_luoj@quicinc.com> References: <20231214094813.24690-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: enyKgFTJ0Q4_IgOjsAA-INSrHrCZby5p X-Proofpoint-ORIG-GUID: enyKgFTJ0Q4_IgOjsAA-INSrHrCZby5p X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 mlxlogscore=954 mlxscore=0 clxscore=1015 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140065 X-Patchwork-Delegate: kuba@kernel.org When qca808x works on the interface mode sgmii or 2500base-x, the interface mode can be switched according to the PHY link speed. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index b6b41b1a4352..c186ef8e798f 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -2101,10 +2101,22 @@ static void qca808x_link_change_notify(struct phy_device *phydev) QCA8081_PHY_FIFO_RSTN, phydev->link ? QCA8081_PHY_FIFO_RSTN : 0); } +static void qca808x_fill_possible_interfaces(struct phy_device *phydev) +{ + unsigned long *possible = phydev->possible_interfaces; + + if (phydev->interface != PHY_INTERFACE_MODE_10G_QXGMII) { + __set_bit(PHY_INTERFACE_MODE_2500BASEX, possible); + __set_bit(PHY_INTERFACE_MODE_SGMII, possible); + } +} + static int qca8084_config_init(struct phy_device *phydev) { int ret; + qca808x_fill_possible_interfaces(phydev); + /* Invert ADC clock edge */ ret = at803x_debug_reg_mask(phydev, QCA8084_ADC_CLK_SEL, QCA8084_ADC_CLK_SEL_ACLK, From patchwork Thu Dec 14 09:48:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 13492676 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="DbfTmDbs" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36051D50; Thu, 14 Dec 2023 01:49:17 -0800 (PST) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE9bdrf019740; Thu, 14 Dec 2023 09:49:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=hpvMBuARU64hMyagAI+sVm+34y+gMIefztSa1JH/fjY=; b=Db fTmDbsP65AALl2nqOe9GU6Jbw6o+Jdb9fqiTxJANH4nsu9h8X+nAJ6UEEfy8lChQ DRSsWBTHXIfIr+SKfVLShtoVUmuB66nk4v2WRZoxsWShJ7+FcW0LEdpPRaBOY1fW Y/yHXH0XZGaO9h3s8r+p/nmmOAWgVRgPeJMXXxpMPG3qbBY9wn1NYDIQ6ncsuUFo 0jGeubj95Q3vdGFJIUfTOgdIWam+N3oRT0URULwruberLa/Rqf6zOce6sA5OI0VI emcEX+BxYaKKq0HdSNgUL3/qq939+Qz5yz0Eb6rOwAmRmkxFqVT3kmeWwNWukQLA Z1m9y5+QwVuN9o1ALSGA== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uynja94qj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:49:04 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE9n3N2016687 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:49:03 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:48:59 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v7 08/14] net: phy: at803x: add qca8084 switch registe access Date: Thu, 14 Dec 2023 17:48:07 +0800 Message-ID: <20231214094813.24690-9-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214094813.24690-1-quic_luoj@quicinc.com> References: <20231214094813.24690-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: aGsADAo4H8C-Ks1W9KkGLFrJyk7dtA-k X-Proofpoint-ORIG-GUID: aGsADAo4H8C-Ks1W9KkGLFrJyk7dtA-k X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 impostorscore=0 spamscore=0 priorityscore=1501 mlxlogscore=999 mlxscore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 suspectscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140065 X-Patchwork-Delegate: kuba@kernel.org For qca8084 chip, there are GCC, TLMM and security control modules besides the PHY, these moudles are accessed with 32 bits value, which has the special MDIO sequences to read or write this 32bit register. There are initial configurations configured to make qca8084 PHY probeable, and the MDIO address of qca8084 can be programmed for the PHY device and PCS device. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 86 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index c186ef8e798f..016e40e32982 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -296,6 +296,13 @@ #define QCA8084_MMD7_IPG_OP 0x901d #define QCA8084_IPG_10_TO_11_EN BIT(0) +/* QCA8084 includes secure control module, which supports customizing the + * MDIO address of PHY device and PCS device, the register of secure control + * is accessed by MDIO bus with the special MDIO sequences. + */ +#define QCA8084_HIGH_ADDR_PREFIX 0x18 +#define QCA8084_LOW_ADDR_PREFIX 0x10 + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -408,6 +415,85 @@ static int at803x_read_page(struct phy_device *phydev) return AT803X_PAGE_FIBER; } +static void qca8084_split_addr(u32 regaddr, u16 *r1, u16 *r2, + u16 *page, u16 *sw_addr) +{ + *r1 = regaddr & 0x1c; + + regaddr >>= 5; + *r2 = regaddr & 0x7; + + regaddr >>= 3; + *page = regaddr & 0xffff; + + regaddr >>= 16; + *sw_addr = regaddr & 0xff; +} + +static int __qca8084_set_page(struct mii_bus *bus, u16 sw_addr, u16 page) +{ + return __mdiobus_write(bus, QCA8084_HIGH_ADDR_PREFIX | (sw_addr >> 5), + sw_addr & 0x1f, page); +} + +static int __qca8084_mii_read(struct mii_bus *bus, u16 addr, u16 reg, u32 *val) +{ + int ret, data; + + ret = __mdiobus_read(bus, addr, reg); + if (ret >= 0) { + data = ret; + + ret = __mdiobus_read(bus, addr, reg | BIT(1)); + if (ret >= 0) + *val = data | ret << 16; + } + + return ret < 0 ? ret : 0; +} + +static int __qca8084_mii_write(struct mii_bus *bus, u16 addr, u16 reg, u32 val) +{ + int ret; + + ret = __mdiobus_write(bus, addr, reg, lower_16_bits(val)); + if (!ret) + ret = __mdiobus_write(bus, addr, reg | BIT(1), upper_16_bits(val)); + + return ret; +} + +static int qca8084_mii_modify(struct phy_device *phydev, u32 regaddr, + u32 clear, u32 set) +{ + struct mii_bus *bus; + u16 reg, addr, page, sw_addr; + u32 val; + int ret; + + bus = phydev->mdio.bus; + mutex_lock(&bus->mdio_lock); + + qca8084_split_addr(regaddr, ®, &addr, &page, &sw_addr); + ret = __qca8084_set_page(bus, sw_addr, page); + if (ret < 0) + goto qca8084_mii_modify_exit; + + ret = __qca8084_mii_read(bus, QCA8084_LOW_ADDR_PREFIX | addr, + reg, &val); + if (ret < 0) + goto qca8084_mii_modify_exit; + + val &= ~clear; + val |= set; + ret = __qca8084_mii_write(bus, QCA8084_LOW_ADDR_PREFIX | addr, + reg, val); + +qca8084_mii_modify_exit: + mutex_unlock(&bus->mdio_lock); + return ret; +}; + static int at803x_enable_rx_delay(struct phy_device *phydev) { return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0, From patchwork Thu Dec 14 09:48:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 13492677 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="avuB8VK+" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A319B10E2; Thu, 14 Dec 2023 01:49:22 -0800 (PST) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE5ebtr021783; Thu, 14 Dec 2023 09:49:09 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=Pv0bj9BwrtvC5bjKTWWscgwoj6oQ0HJW9ayhPrX1rpc=; b=av uB8VK+rZji8jFbuHXmSyXY5nWcKQdgZrYa3fhsrTJZfI5x18N29SlgGQPWry9Tw/ HgErdP463iQgVtyHKxZ3pVS203iiTYg6R1wCGCRKIh4gsTjkV9J7rvx8nfzELmQ8 tGUIxgg85Az4IxKQnII5pLwWkkRjCY8FLQnwOS6rRFsGES5xzQI8LL2ukmQlv9Rw Xd736LirDR3DUh8lw4w/1D93XXbGAbIpfqPn3AZ31Fwfy1hcBy9SjySyk9L6LDPN qjyee+H2eyi7VVh2WySVYW4oIcn26UUSEmRS5Hx+g1VMLrs/+wyrO010u5+vRtfL uw1fDA46r4F2SAGtpCsg== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uynre131p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:49:09 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE9n8WY001600 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:49:08 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:49:03 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v7 09/14] net: phy: at803x: set MDIO address of qca8084 PHY Date: Thu, 14 Dec 2023 17:48:08 +0800 Message-ID: <20231214094813.24690-10-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214094813.24690-1-quic_luoj@quicinc.com> References: <20231214094813.24690-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: B344eEj8kRyMFwBGLtS16jb4hoxAoER7 X-Proofpoint-GUID: B344eEj8kRyMFwBGLtS16jb4hoxAoER7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=999 suspectscore=0 impostorscore=0 phishscore=0 bulkscore=0 spamscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140065 X-Patchwork-Delegate: kuba@kernel.org Program the MDIO address of qca8084 PHY and PCS device in the PHY probe function. The MDIO address of qca8084 device is configured according to the property "qcom,phy-addr-fixup" of phy node, which defines the MDIO address for 4 PHYs and 3 PCSes, each MDIO address occupies 5 bits in the config register. The MDIO address of qca8084 should be configured correctly before doing the clock initialization in the PHY probe function, so the property "reg" can't be used to configure the MDIO address of phy device one by one, the clock initialization will be configured with all 4 PHY devices in one PHY probe function. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 61 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 016e40e32982..a00c5950683c 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -303,6 +303,18 @@ #define QCA8084_HIGH_ADDR_PREFIX 0x18 #define QCA8084_LOW_ADDR_PREFIX 0x10 +#define QCA8084_PCS_CFG 0xc90f014 +#define QCA8084_PCS_ADDR0_MASK GENMASK(4, 0) +#define QCA8084_PCS_ADDR1_MASK GENMASK(9, 5) +#define QCA8084_PCS_ADDR2_MASK GENMASK(14, 10) + +#define QCA8084_EPHY_CFG 0xc90f018 +#define QCA8084_EPHY_ADDR0_MASK GENMASK(4, 0) +#define QCA8084_EPHY_ADDR1_MASK GENMASK(9, 5) +#define QCA8084_EPHY_ADDR2_MASK GENMASK(14, 10) +#define QCA8084_EPHY_ADDR3_MASK GENMASK(19, 15) +#define QCA8084_EPHY_LDO_EN GENMASK(21, 20) + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -955,6 +967,51 @@ static int at803x_parse_dt(struct phy_device *phydev) return 0; } +static int qca8084_parse_and_set_phyaddr(struct phy_device *phydev) +{ + struct device_node *node; + u32 addr[7]; + int ret; + + node = phydev->mdio.dev.of_node; + + /* The property "qcom,phy-addr-fixup" is only defined in one + * PHY device tree node. + */ + ret = of_property_read_u32_array(node, "qcom,phy-addr-fixup", + addr, ARRAY_SIZE(addr)); + if (ret) + return ret == -EINVAL ? 0 : ret; + + /* There are 4 PHYs and 3 PCSes on qca8084 chip, each device address + * occupies 5 bits of the config register to customize the MDIO address. + */ + ret = qca8084_mii_modify(phydev, QCA8084_EPHY_CFG, + QCA8084_EPHY_ADDR0_MASK | + QCA8084_EPHY_ADDR1_MASK | + QCA8084_EPHY_ADDR2_MASK | + QCA8084_EPHY_ADDR3_MASK, + FIELD_PREP(QCA8084_EPHY_ADDR0_MASK, addr[0]) | + FIELD_PREP(QCA8084_EPHY_ADDR1_MASK, addr[1]) | + FIELD_PREP(QCA8084_EPHY_ADDR2_MASK, addr[2]) | + FIELD_PREP(QCA8084_EPHY_ADDR3_MASK, addr[3])); + if (ret) + return ret; + + return qca8084_mii_modify(phydev, QCA8084_PCS_CFG, + QCA8084_PCS_ADDR0_MASK | + QCA8084_PCS_ADDR1_MASK | + QCA8084_PCS_ADDR2_MASK, + FIELD_PREP(QCA8084_PCS_ADDR0_MASK, addr[4]) | + FIELD_PREP(QCA8084_PCS_ADDR1_MASK, addr[5]) | + FIELD_PREP(QCA8084_PCS_ADDR2_MASK, addr[6])); +} + +static int qca8084_probe(struct phy_device *phydev) +{ + return qca8084_parse_and_set_phyaddr(phydev); +} + static int at803x_probe(struct phy_device *phydev) { struct device *dev = &phydev->mdio.dev; @@ -967,6 +1024,9 @@ static int at803x_probe(struct phy_device *phydev) phydev->priv = priv; + if (phydev_id_compare(phydev, QCA8084_PHY_ID)) + return qca8084_probe(phydev); + ret = at803x_parse_dt(phydev); if (ret) return ret; @@ -2434,6 +2494,7 @@ static struct phy_driver at803x_driver[] = { PHY_ID_MATCH_MODEL(QCA8084_PHY_ID), .name = "Qualcomm QCA8084", .flags = PHY_POLL_CABLE_TEST, + .probe = at803x_probe, .config_intr = at803x_config_intr, .handle_interrupt = at803x_handle_interrupt, .get_tunable = at803x_get_tunable, From patchwork Thu Dec 14 09:48:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 13492678 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="gXzbEMq0" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D84CB171D; Thu, 14 Dec 2023 01:49:27 -0800 (PST) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE8SjSS011003; Thu, 14 Dec 2023 09:49:13 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=s+ow7T+OuUMlBNecjU0aO/QVMPc5Mr6UNh605j+9AnI=; b=gX zbEMq0+xr6UQdvcCfF+ylpw3PCRuDMXNdPWeA4AuWQclAzduepNc8oqPcRtsTmIc ohHCMvN8dKg6KuMMMvz+x3T2CCyZFIc0tAYfwHNoW/Y6qGsR6I2MNgze97PJ2M0z +bmZc//4V8e+ahazTfpgJibrBQQi7brWPk3n9x/yL0arnuJTty3tyYXIoPO7pidD 5xDGWlYEQCg7aGG8DQDzRpmTjzHChtmkJZxlsIaZgdGqvk4Pl0BoEVoIo/IxX3PP 0/CWRp+1KsMXYB0yL98fWh1nuPM5UY1q2HhzBhNZs9tMRsaqmGa3QWVMBU1Nlgw+ X346Bs6botVzTRXCZArA== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uyp0p92w3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:49:13 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE9nCep008859 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:49:12 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:49:08 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v7 10/14] net: phy: at803x: parse qca8084 clocks and resets Date: Thu, 14 Dec 2023 17:48:09 +0800 Message-ID: <20231214094813.24690-11-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214094813.24690-1-quic_luoj@quicinc.com> References: <20231214094813.24690-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: p5TAOuoHTDqpWvnniRSjaspXoQ2u5gLa X-Proofpoint-GUID: p5TAOuoHTDqpWvnniRSjaspXoQ2u5gLa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 phishscore=0 impostorscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140065 X-Patchwork-Delegate: kuba@kernel.org These clock and reset IDs are needed to bring up qca8084, after the initializations with these clocks and resets, the PHY function can be accessed correctly such as reading the capabilities of PHY. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 89 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index a00c5950683c..6a7a7111ff68 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -21,6 +21,8 @@ #include #include #include +#include +#include #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 #define AT803X_SFC_ASSERT_CRS BIT(11) @@ -337,6 +339,31 @@ static struct at803x_hw_stat at803x_hw_stats[] = { { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, }; +enum { + SRDS0_SYS_CLK, + SRDS1_SYS_CLK, + GEPHY0_SYS_CLK, + GEPHY1_SYS_CLK, + GEPHY2_SYS_CLK, + GEPHY3_SYS_CLK, + QCA8084_CLK_CNT +}; + +enum { + SRDS0_SYS_RESET, + SRDS1_SYS_RESET, + GEPHY0_SYS_RESET, + GEPHY1_SYS_RESET, + GEPHY2_SYS_RESET, + GEPHY3_SYS_RESET, + GEPHY0_RESET, + GEPHY1_RESET, + GEPHY2_RESET, + GEPHY3_RESET, + GEPHY_DSP_RESET, + QCA8084_RESET_CNT, +}; + struct at803x_priv { int flags; u16 clk_25m_reg; @@ -348,6 +375,8 @@ struct at803x_priv { struct regulator_dev *vddio_rdev; struct regulator_dev *vddh_rdev; u64 stats[ARRAY_SIZE(at803x_hw_stats)]; + struct clk *clk[QCA8084_CLK_CNT]; + struct reset_control *reset[QCA8084_RESET_CNT]; }; struct at803x_context { @@ -359,6 +388,29 @@ struct at803x_context { u16 led_control; }; +static const char *const qca8084_clock_name[QCA8084_CLK_CNT] = { + "srds0_sys", + "srds1_sys", + "gephy0_sys", + "gephy1_sys", + "gephy2_sys", + "gephy3_sys", +}; + +static const char *const qca8084_reset_name[QCA8084_RESET_CNT] = { + "srds0_sys", + "srds1_sys", + "gephy0_sys", + "gephy1_sys", + "gephy2_sys", + "gephy3_sys", + "gephy0_soft", + "gephy1_soft", + "gephy2_soft", + "gephy3_soft", + "gephy_dsp", +}; + static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data) { int ret; @@ -1007,8 +1059,45 @@ static int qca8084_parse_and_set_phyaddr(struct phy_device *phydev) FIELD_PREP(QCA8084_PCS_ADDR2_MASK, addr[6])); } +static int qca8084_parse_dt(struct phy_device *phydev) +{ + struct at803x_priv *priv; + int i; + + priv = phydev->priv; + for (i = 0; i < QCA8084_CLK_CNT; i++) { + priv->clk[i] = devm_clk_get_optional(&phydev->mdio.dev, + qca8084_clock_name[i]); + if (IS_ERR(priv->clk[i])) { + phydev_err(phydev, "failed to get the clock ID %s!\n", + qca8084_clock_name[i]); + + return PTR_ERR(priv->clk[i]); + } + } + + for (i = 0; i < QCA8084_RESET_CNT; i++) { + priv->reset[i] = devm_reset_control_get_optional_exclusive(&phydev->mdio.dev, + qca8084_reset_name[i]); + if (IS_ERR(priv->reset[i])) { + phydev_err(phydev, "failed to get the reset ID %s!\n", + qca8084_reset_name[i]); + + return PTR_ERR(priv->reset[i]); + } + } + + return 0; +} + static int qca8084_probe(struct phy_device *phydev) { + int ret; + + ret = qca8084_parse_dt(phydev); + if (ret) + return ret; + return qca8084_parse_and_set_phyaddr(phydev); } From patchwork Thu Dec 14 09:48:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 13492679 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="HwUP/3IY" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 74E281994; Thu, 14 Dec 2023 01:49:31 -0800 (PST) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE8SPg7014660; Thu, 14 Dec 2023 09:49:18 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=MRC8Z48TOdwwqp4jcexel6jg2C4JQxWltiNljtKZ+2w=; b=Hw UP/3IYfG4iZQhyseKDYkuhKqEEGEqA7i++NIGURiu+96L0Glbp11sMfZy6rA9Heh J1+eC1aXSS9uYsf3g6LxebAZjvWq529dP6m0tBxcJwZVCQSWiP68Cvkl+F8gCHat RMckNvrKJCNuqxeIMW7t3yh2Z72+8L/9KhLPCoLFg2mnP+5dSVPRkMtA+FYMI3z5 vzYqzcbhJ4Q7jMCyiLbauQuBCKpA3ONJrGu0Vx93Q8k8h7fb4uOQAUmp51NlK4HG XnvjlNcoG8x1mP/hf2/j0DlCE5Bl3WOCc4hiUc/dWs3wQBXh/HK1TPnllOvSNosf SieUtNlRcNQIi7B3s6Bw== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uytn68jxx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:49:17 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE9nHTL024433 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:49:17 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:49:12 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v7 11/14] net: phy: at803x: add qca808x initial config sequence Date: Thu, 14 Dec 2023 17:48:10 +0800 Message-ID: <20231214094813.24690-12-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214094813.24690-1-quic_luoj@quicinc.com> References: <20231214094813.24690-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: WwWodg1rUzi9iUBdMCKl9kvLIYZ0l01Q X-Proofpoint-ORIG-GUID: WwWodg1rUzi9iUBdMCKl9kvLIYZ0l01Q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 phishscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 bulkscore=0 impostorscore=0 adultscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140065 X-Patchwork-Delegate: kuba@kernel.org After GPIO reset, these Ethernet clock sequence needs to be configured before reading the features of PHY, the Ethernet system clock works on 25MHZ. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 84 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 83 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 6a7a7111ff68..204f5ca6001c 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -1090,6 +1090,84 @@ static int qca8084_parse_dt(struct phy_device *phydev) return 0; } +static int qca8084_clock_config(struct phy_device *phydev) +{ + struct at803x_priv *priv; + int ret = 0; + + /* The ethernet clock IDs are only defined in one PHY device + * tree node, and these ethernet clocks only needs to be configured + * one time, which work on the clock rate 25MHZ. + */ + priv = phydev->priv; + if (!priv->clk[SRDS0_SYS_CLK]) + return 0; + + ret = clk_set_rate(priv->clk[SRDS0_SYS_CLK], 25000000); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[SRDS0_SYS_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[SRDS1_SYS_CLK]); + if (ret) + return ret; + + /* Reset PCS system clocks */ + reset_control_assert(priv->reset[SRDS0_SYS_RESET]); + reset_control_assert(priv->reset[SRDS1_SYS_RESET]); + fsleep(20000); + + reset_control_deassert(priv->reset[SRDS0_SYS_RESET]); + reset_control_deassert(priv->reset[SRDS1_SYS_RESET]); + + ret = clk_prepare_enable(priv->clk[GEPHY0_SYS_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[GEPHY1_SYS_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[GEPHY2_SYS_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[GEPHY3_SYS_CLK]); + if (ret) + return ret; + + /* Reset ethernet system clocks */ + reset_control_assert(priv->reset[GEPHY0_SYS_RESET]); + reset_control_assert(priv->reset[GEPHY1_SYS_RESET]); + reset_control_assert(priv->reset[GEPHY2_SYS_RESET]); + reset_control_assert(priv->reset[GEPHY3_SYS_RESET]); + fsleep(20000); + + reset_control_deassert(priv->reset[GEPHY0_SYS_RESET]); + reset_control_deassert(priv->reset[GEPHY1_SYS_RESET]); + reset_control_deassert(priv->reset[GEPHY2_SYS_RESET]); + reset_control_deassert(priv->reset[GEPHY3_SYS_RESET]); + + /* Release ethernet DSP reset */ + reset_control_deassert(priv->reset[GEPHY0_RESET]); + reset_control_deassert(priv->reset[GEPHY1_RESET]); + reset_control_deassert(priv->reset[GEPHY2_RESET]); + reset_control_deassert(priv->reset[GEPHY3_RESET]); + reset_control_deassert(priv->reset[GEPHY_DSP_RESET]); + + /* Enable efuse loading into analog circuit */ + ret = qca8084_mii_modify(phydev, QCA8084_EPHY_CFG, + QCA8084_EPHY_LDO_EN, 0); + if (ret) + return ret; + + fsleep(10000); + return 0; +} + static int qca8084_probe(struct phy_device *phydev) { int ret; @@ -1098,7 +1176,11 @@ static int qca8084_probe(struct phy_device *phydev) if (ret) return ret; - return qca8084_parse_and_set_phyaddr(phydev); + ret = qca8084_parse_and_set_phyaddr(phydev); + if (ret) + return ret; + + return qca8084_clock_config(phydev); } static int at803x_probe(struct phy_device *phydev) From patchwork Thu Dec 14 09:48:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 13492680 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="jq5c+gON" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15FBF19B1; Thu, 14 Dec 2023 01:49:35 -0800 (PST) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE4qC9p028409; Thu, 14 Dec 2023 09:49:22 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=UPSQOuBh14dqy+VE2CjEh9qgLnMj8uBsrhetcQjZ3IU=; b=jq 5c+gON2jdEBM5olU312eYmoqhMK35j6nmuOxZChmejvRbSuvn7FInxLILw+DirSs yw4jY/ic+NmvoIU+CHPvXFSPEQxkvl5vyrH+Ai/t+O6Qp254T/y63wSGdrK72Jk7 66G/WmFaiuCZcZdfiM+zBxXlB5Cu3chInu1TLC3AzQG4MQx7o/WLkUecLUsi4WfZ Lk8q02PwuHM5LhBkqHNVhzVP3JMeA8h0T87irlzO2ccBr1YS7GOFl9aJa849nYgg wgUj7ARq01gFT63rdQNRN+zuoewo5QMGxCtK5U+D3Hn1mdmaLKN5KkHe03JJQI/w GFdmQRc0dPFZF+0D6Ccg== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uytn68jy3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:49:22 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE9nLw6007213 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:49:21 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:49:17 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v7 12/14] net: phy: at803x: configure qca8084 common clocks Date: Thu, 14 Dec 2023 17:48:11 +0800 Message-ID: <20231214094813.24690-13-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214094813.24690-1-quic_luoj@quicinc.com> References: <20231214094813.24690-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: xl1nKYK7jXxhSbPAdIJ-EWH0Wf5GjBxP X-Proofpoint-ORIG-GUID: xl1nKYK7jXxhSbPAdIJ-EWH0Wf5GjBxP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 phishscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 bulkscore=0 impostorscore=0 adultscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140065 X-Patchwork-Delegate: kuba@kernel.org After initial clock sequence, the clock source 312.5MHZ is available, the common clocks based on clock source 312.5MHZ needs to be configured, which includes APB bridge clock tree with rate 312.5MHZ, AHB clock tree with 104.17MHZ. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 69 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 68 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 204f5ca6001c..4499d78891d2 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -340,6 +340,14 @@ static struct at803x_hw_stat at803x_hw_stats[] = { }; enum { + APB_BRIDGE_CLK, + AHB_CLK, + SEC_CTRL_AHB_CLK, + TLMM_CLK, + TLMM_AHB_CLK, + CNOC_AHB_CLK, + MDIO_AHB_CLK, + MDIO_MASTER_AHB_CLK, SRDS0_SYS_CLK, SRDS1_SYS_CLK, GEPHY0_SYS_CLK, @@ -389,6 +397,14 @@ struct at803x_context { }; static const char *const qca8084_clock_name[QCA8084_CLK_CNT] = { + "apb_bridge", + "ahb", + "sec_ctrl_ahb", + "tlmm", + "tlmm_ahb", + "cnoc_ahb", + "mdio_ahb", + "mdio_master_ahb", "srds0_sys", "srds1_sys", "gephy0_sys", @@ -1168,6 +1184,53 @@ static int qca8084_clock_config(struct phy_device *phydev) return 0; } +static int qca8084_common_clock_init(struct phy_device *phydev) +{ + struct at803x_priv *priv; + int ret = 0; + + priv = phydev->priv; + /* Enable APB bridge tree clock */ + ret = clk_set_rate(priv->clk[APB_BRIDGE_CLK], 312500000); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[APB_BRIDGE_CLK]); + if (ret) + return ret; + + /* Enable AHB tree clocks */ + ret = clk_set_rate(priv->clk[AHB_CLK], 104170000); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[AHB_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[SEC_CTRL_AHB_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[TLMM_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[TLMM_AHB_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[CNOC_AHB_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[MDIO_AHB_CLK]); + if (ret) + return ret; + + return clk_prepare_enable(priv->clk[MDIO_MASTER_AHB_CLK]); +} + static int qca8084_probe(struct phy_device *phydev) { int ret; @@ -1180,7 +1243,11 @@ static int qca8084_probe(struct phy_device *phydev) if (ret) return ret; - return qca8084_clock_config(phydev); + ret = qca8084_clock_config(phydev); + if (ret) + return ret; + + return qca8084_common_clock_init(phydev); } static int at803x_probe(struct phy_device *phydev) From patchwork Thu Dec 14 09:48:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 13492681 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="pUqDr1IA" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 194F31BCD; Thu, 14 Dec 2023 01:49:39 -0800 (PST) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE9Q7hb029781; Thu, 14 Dec 2023 09:49:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=B1iNr8ZoSL+9Nsxcj5DA5N199o4zb2A3hGCzRlJGaGY=; b=pU qDr1IAs4uZrFHYTL27NM3OUYM3gyIXR8ZKA3wuNVjZqJr3nUvtYhkoJwiX8v9Y59 ExADBYObOiIyjQsKfF5AbdWTCUqWSnnD13WphIZzNsHP0oQBWWeXbjwb8S0WAiPq Rb49NIkB5cQj1GXZD89bkroAvXIBsb/hO2/1xQPT+h4wqn4r1ZuSmLsEIdc6+D6L XraXgJxZ5xgadAB1vQfAc/NsVWrPriw+1on2Tb22DXFOqSFtk1h5WmU8GMAonWlc H5NOM5kNYHxff2yYAkTUXlN57dlaVITJ/0Z4AbJz7AsW9dn4UQUTULvnkWzsLxJk k27pEMtv54bjjT7Ke1Xg== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uyp0p92wr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:49:26 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE9nPBq007224 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:49:25 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:49:21 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v7 13/14] net: phy: at803x: configure qca8084 work mode Date: Thu, 14 Dec 2023 17:48:12 +0800 Message-ID: <20231214094813.24690-14-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214094813.24690-1-quic_luoj@quicinc.com> References: <20231214094813.24690-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: JJmBKfLAsNLue1oyIUYX3IljNaKN31xX X-Proofpoint-GUID: JJmBKfLAsNLue1oyIUYX3IljNaKN31xX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 phishscore=0 impostorscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140065 X-Patchwork-Delegate: kuba@kernel.org There are four kind of work modes supported by qca8084. 1. Quad PHYs work on 10g-qxgmii. 2. PHY1, PHY2, PHY3 wors on 10g-qxgmii, PHY4 works on sgmii. 3. Quad PHYs connected with internal MACs by GMII, which works on switch mode. 4. PHY1, PHY2, PHY3 connected with internal MACs by GMII, PHY4 works on sgmii. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 53 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 52 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 4499d78891d2..6bc80704949a 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -317,6 +317,13 @@ #define QCA8084_EPHY_ADDR3_MASK GENMASK(19, 15) #define QCA8084_EPHY_LDO_EN GENMASK(21, 20) +#define QCA8084_WORK_MODE_CFG 0xc90f030 +#define QCA8084_WORK_MODE_MASK GENMASK(5, 0) +#define QCA8084_WORK_MODE_QXGMII (BIT(5) | GENMASK(3, 0)) +#define QCA8084_WORK_MODE_QXGMII_PORT4_SGMII (BIT(5) | GENMASK(2, 0)) +#define QCA8084_WORK_MODE_SWITCH BIT(4) +#define QCA8084_WORK_MODE_SWITCH_PORT4_SGMII BIT(5) + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -1231,6 +1238,46 @@ static int qca8084_common_clock_init(struct phy_device *phydev) return clk_prepare_enable(priv->clk[MDIO_MASTER_AHB_CLK]); } +static int qca8084_parse_and_set_work_mode(struct phy_device *phydev) +{ + struct device_node *node; + struct at803x_priv *priv; + u32 value, work_mode; + int ret; + + node = phydev->mdio.dev.of_node; + priv = phydev->priv; + + /* The property "qcom,phy-work-mode" is only defined in one + * PHY device tree node. + */ + ret = of_property_read_u32(node, "qcom,phy-work-mode", &value); + if (ret) + return ret == -EINVAL ? 0 : ret; + + switch (value) { + case 0: + work_mode = QCA8084_WORK_MODE_QXGMII; + break; + case 1: + work_mode = QCA8084_WORK_MODE_QXGMII_PORT4_SGMII; + break; + case 2: + work_mode = QCA8084_WORK_MODE_SWITCH; + break; + case 3: + work_mode = QCA8084_WORK_MODE_SWITCH_PORT4_SGMII; + break; + default: + phydev_err(phydev, "invalid qcom,phy-work-mode %d\n", value); + return -EINVAL; + } + + return qca8084_mii_modify(phydev, QCA8084_WORK_MODE_CFG, + QCA8084_WORK_MODE_MASK, + FIELD_PREP(QCA8084_WORK_MODE_MASK, work_mode)); +} + static int qca8084_probe(struct phy_device *phydev) { int ret; @@ -1247,7 +1294,11 @@ static int qca8084_probe(struct phy_device *phydev) if (ret) return ret; - return qca8084_common_clock_init(phydev); + ret = qca8084_common_clock_init(phydev); + if (ret) + return ret; + + return qca8084_parse_and_set_work_mode(phydev); } static int at803x_probe(struct phy_device *phydev) From patchwork Thu Dec 14 09:48:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 13492682 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="oVT6c+VE" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DF221BE9; Thu, 14 Dec 2023 01:49:45 -0800 (PST) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE9TS2r023593; Thu, 14 Dec 2023 09:49:31 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=AhES8Y7x+ZpiqbfFpeHU+5rxqGlvKWJu/Mp3zVbaca0=; b=oV T6c+VELcBW5dn2GehNL+ov3U8He2zOEx868Wb++REhMB4udMHO29plxxxK9ONaCh j1XmbFGvWNQFjgiRg5iTb66jmgVK0iM6mdK7HhZ57VwfATbH6605w3CJw+XAAv9e Y7s8TrA29yzaM6YvY5su3h+WLcpuiZNronEioEW4ugxAiBU+2HxO7YQZvwpAcW29 Eoo4dgaFESc8haqenFChVlxby/YP0tiAFLDUCFN0X+4GlBg0nPJIClRImhI8/r0C JFHiN5OuFPzWeBCgelrWMDHgtG/TBlsZUwGyUon22Fx3hPBWo/7vZH2W1Dj1BhVd JyUkEvk5/Wu954pyNEOw== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uysrprq1k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:49:31 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE9nUYf024558 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:49:30 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:49:25 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v7 14/14] dt-bindings: net: ar803x: add qca8084 PHY propetry Date: Thu, 14 Dec 2023 17:48:13 +0800 Message-ID: <20231214094813.24690-15-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214094813.24690-1-quic_luoj@quicinc.com> References: <20231214094813.24690-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: mMfo319Ha1GenamwBq7cOMRZqSIvWQa9 X-Proofpoint-GUID: mMfo319Ha1GenamwBq7cOMRZqSIvWQa9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 mlxscore=0 bulkscore=0 mlxlogscore=765 priorityscore=1501 impostorscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140065 X-Patchwork-Delegate: kuba@kernel.org The following properties are added for qca8084 PHY. 1. add the compatible string "ethernet-phy-id004d.d180" since the PHY device is not accessible during MDIO bus register. 2. add property "qcom,phy-addr-fixup" for customizing MDIO address. 3. add property "qcom,phy-work-mode" for specifying qca8084 PHY work mode. 4. add the initial clocks and resets. Signed-off-by: Luo Jie --- .../devicetree/bindings/net/qca,ar803x.yaml | 158 +++++++++++++++++- 1 file changed, 155 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/net/qca,ar803x.yaml b/Documentation/devicetree/bindings/net/qca,ar803x.yaml index 3acd09f0da86..febff039a44f 100644 --- a/Documentation/devicetree/bindings/net/qca,ar803x.yaml +++ b/Documentation/devicetree/bindings/net/qca,ar803x.yaml @@ -14,9 +14,6 @@ maintainers: description: | Bindings for Qualcomm Atheros AR803x PHYs -allOf: - - $ref: ethernet-phy.yaml# - properties: qca,clk-out-frequency: description: Clock output frequency in Hertz. @@ -85,6 +82,161 @@ properties: $ref: /schemas/regulator/regulator.yaml unevaluatedProperties: false + qcom,phy-addr-fixup: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + MDIO address for 4 PHY devices and 3 PCS devices + + qcom,phy-work-mode: + description: PHY device work mode. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + clocks: + items: + - description: APB bridge clock + - description: AHB clock + - description: Security control clock + - description: TLMM clock + - description: TLMM AHB clock + - description: CNOC AHB clock + - description: MDIO AHB clock + - description: MDIO master AHB clock + - description: PCS0 system clock + - description: PCS1 system clock + - description: EPHY0 system clock + - description: EPHY1 system clock + - description: EPHY2 system clock + - description: EPHY3 system clock + description: PHY initial common clock configs + + clock-names: + items: + - const: apb_bridge + - const: ahb + - const: sec_ctrl_ahb + - const: tlmm + - const: tlmm_ahb + - const: cnoc_ahb + - const: mdio_ahb + - const: mdio_master_ahb + - const: srds0_sys + - const: srds1_sys + - const: gephy0_sys + - const: gephy1_sys + - const: gephy2_sys + - const: gephy3_sys + + resets: + items: + - description: PCS0 system reset + - description: PCS1 system reset + - description: EPHY0 system reset + - description: EPHY1 system reset + - description: EPHY2 system reset + - description: EPHY3 system reset + - description: EPHY0 software reset + - description: EPHY1 software reset + - description: EPHY2 software reset + - description: EPHY3 software reset + - description: Ethernet DSP reset + description: PHY initial common reset configs + + reset-names: + items: + - const: srds0_sys + - const: srds1_sys + - const: gephy0_sys + - const: gephy1_sys + - const: gephy2_sys + - const: gephy3_sys + - const: gephy0_soft + - const: gephy1_soft + - const: gephy2_soft + - const: gephy3_soft + - const: gephy_dsp + +allOf: + - $ref: ethernet-phy.yaml# + + - if: + properties: + compatible: + contains: + enum: + - ethernet-phy-id004d.d180 + then: + properties: + clocks: + items: + - description: APB bridge clock + - description: AHB clock + - description: Security control clock + - description: TLMM clock + - description: TLMM AHB clock + - description: CNOC AHB clock + - description: MDIO AHB clock + - description: MDIO master AHB clock + - description: PCS0 system clock + - description: PCS1 system clock + - description: EPHY0 system clock + - description: EPHY1 system clock + - description: EPHY2 system clock + - description: EPHY3 system clock + clock-names: + items: + - const: apb_bridge + - const: ahb + - const: sec_ctrl_ahb + - const: tlmm + - const: tlmm_ahb + - const: cnoc_ahb + - const: mdio_ahb + - const: mdio_master_ahb + - const: srds0_sys + - const: srds1_sys + - const: gephy0_sys + - const: gephy1_sys + - const: gephy2_sys + - const: gephy3_sys + resets: + items: + - description: PCS0 system reset + - description: PCS1 system reset + - description: EPHY0 system reset + - description: EPHY1 system reset + - description: EPHY2 system reset + - description: EPHY3 system reset + - description: EPHY0 software reset + - description: EPHY1 software reset + - description: EPHY2 software reset + - description: EPHY3 software reset + - description: Ethernet DSP reset + reset-names: + items: + - const: srds0_sys + - const: srds1_sys + - const: gephy0_sys + - const: gephy1_sys + - const: gephy2_sys + - const: gephy3_sys + - const: gephy0_soft + - const: gephy1_soft + - const: gephy2_soft + - const: gephy3_soft + - const: gephy_dsp + required: + - qcom,phy-addr-fixup + - qcom,phy-work-mode + - clocks + - clock-names + - resets + - reset-names + else: + properties: + qcom,phy-addr-fixup: false + qcom,phy-work-mode: false + unevaluatedProperties: false examples: