From patchwork Thu Dec 14 22:29:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 13493761 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CF236C4332F for ; Thu, 14 Dec 2023 22:29:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Thu, 14 Dec 2023 14:29:18 -0800 (PST) Received: from [127.0.1.1] ([85.235.12.238]) by smtp.gmail.com with ESMTPSA id g19-20020ac25393000000b0050bc56dd0acsm1989956lfh.184.2023.12.14.14.29.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 14:29:18 -0800 (PST) From: Linus Walleij Date: Thu, 14 Dec 2023 23:29:12 +0100 Subject: [PATCH 1/3] ARM: dts: ux500-href: Push AB8500 inclusion to the top MIME-Version: 1.0 Message-Id: <20231214-ux500-no-turnoff-lowbatt-v1-1-9dcff0783d62@linaro.org> References: <20231214-ux500-no-turnoff-lowbatt-v1-0-9dcff0783d62@linaro.org> In-Reply-To: <20231214-ux500-no-turnoff-lowbatt-v1-0-9dcff0783d62@linaro.org> To: linux-arm-kernel@lists.infradead.org Cc: Linus Walleij X-Mailer: b4 0.12.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231214_142921_491662_352CD90F X-CRM114-Status: GOOD ( 11.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On the hardware reference designs, include the AB8500 definitions on the top level in the DTS files, this is to make it possible to use the AB8505 in the HREF520. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/st/ste-href520-tvk.dts | 1 + arch/arm/boot/dts/st/ste-hrefprev60-stuib.dts | 1 + arch/arm/boot/dts/st/ste-hrefprev60-tvk.dts | 1 + arch/arm/boot/dts/st/ste-hrefv60plus-stuib.dts | 1 + arch/arm/boot/dts/st/ste-hrefv60plus-tvk.dts | 1 + arch/arm/boot/dts/st/ste-hrefv60plus.dtsi | 1 - 6 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/ste-href520-tvk.dts b/arch/arm/boot/dts/st/ste-href520-tvk.dts index 7f661f8f13ad..930058a8e0d1 100644 --- a/arch/arm/boot/dts/st/ste-href520-tvk.dts +++ b/arch/arm/boot/dts/st/ste-href520-tvk.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "ste-db8520.dtsi" +#include "ste-href-ab8500.dtsi" #include "ste-hrefv60plus.dtsi" #include "ste-href-tvk1281618-r3.dtsi" diff --git a/arch/arm/boot/dts/st/ste-hrefprev60-stuib.dts b/arch/arm/boot/dts/st/ste-hrefprev60-stuib.dts index a29e345a43d3..b142bb2d38d8 100644 --- a/arch/arm/boot/dts/st/ste-hrefprev60-stuib.dts +++ b/arch/arm/boot/dts/st/ste-hrefprev60-stuib.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "ste-db8500.dtsi" +#include "ste-href-ab8500.dtsi" #include "ste-hrefprev60.dtsi" #include "ste-href-stuib.dtsi" diff --git a/arch/arm/boot/dts/st/ste-hrefprev60-tvk.dts b/arch/arm/boot/dts/st/ste-hrefprev60-tvk.dts index 1968bd143114..5da1ff41b00e 100644 --- a/arch/arm/boot/dts/st/ste-hrefprev60-tvk.dts +++ b/arch/arm/boot/dts/st/ste-hrefprev60-tvk.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "ste-db8500.dtsi" +#include "ste-href-ab8500.dtsi" #include "ste-hrefprev60.dtsi" #include "ste-href-tvk1281618-r2.dtsi" diff --git a/arch/arm/boot/dts/st/ste-hrefv60plus-stuib.dts b/arch/arm/boot/dts/st/ste-hrefv60plus-stuib.dts index 7a5b6aa1db5b..c4abe24a7cd0 100644 --- a/arch/arm/boot/dts/st/ste-hrefv60plus-stuib.dts +++ b/arch/arm/boot/dts/st/ste-hrefv60plus-stuib.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "ste-db8500.dtsi" +#include "ste-href-ab8500.dtsi" #include "ste-hrefv60plus.dtsi" #include "ste-href-stuib.dtsi" diff --git a/arch/arm/boot/dts/st/ste-hrefv60plus-tvk.dts b/arch/arm/boot/dts/st/ste-hrefv60plus-tvk.dts index d5af3f375161..f55e8de2b516 100644 --- a/arch/arm/boot/dts/st/ste-hrefv60plus-tvk.dts +++ b/arch/arm/boot/dts/st/ste-hrefv60plus-tvk.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "ste-db8500.dtsi" +#include "ste-href-ab8500.dtsi" #include "ste-hrefv60plus.dtsi" #include "ste-href-tvk1281618-r2.dtsi" diff --git a/arch/arm/boot/dts/st/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/st/ste-hrefv60plus.dtsi index e66fa59c2de6..94927f048151 100644 --- a/arch/arm/boot/dts/st/ste-hrefv60plus.dtsi +++ b/arch/arm/boot/dts/st/ste-hrefv60plus.dtsi @@ -3,7 +3,6 @@ * Copyright 2012 ST-Ericsson AB */ -#include "ste-href-ab8500.dtsi" #include "ste-href.dtsi" / { From patchwork Thu Dec 14 22:29:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 13493762 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6C232C4332F for ; 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Thu, 14 Dec 2023 14:29:19 -0800 (PST) Received: from [127.0.1.1] ([85.235.12.238]) by smtp.gmail.com with ESMTPSA id g19-20020ac25393000000b0050bc56dd0acsm1989956lfh.184.2023.12.14.14.29.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 14:29:18 -0800 (PST) From: Linus Walleij Date: Thu, 14 Dec 2023 23:29:13 +0100 Subject: [PATCH 2/3] ARM: dts: ux500-href: Push AB8500 config out MIME-Version: 1.0 Message-Id: <20231214-ux500-no-turnoff-lowbatt-v1-2-9dcff0783d62@linaro.org> References: <20231214-ux500-no-turnoff-lowbatt-v1-0-9dcff0783d62@linaro.org> In-Reply-To: <20231214-ux500-no-turnoff-lowbatt-v1-0-9dcff0783d62@linaro.org> To: linux-arm-kernel@lists.infradead.org Cc: Linus Walleij X-Mailer: b4 0.12.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231214_142922_567350_6AFF7A23 X-CRM114-Status: GOOD ( 11.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Push out some AB8500 setup of regulators and phy out to the per-AB850x variant file ste-href-ab8500.dtsi so it becomes self-contained for each AB850x chip. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/st/ste-href-ab8500.dtsi | 48 +++++++++++++++++++++++++++ arch/arm/boot/dts/st/ste-href.dtsi | 55 ------------------------------- 2 files changed, 48 insertions(+), 55 deletions(-) diff --git a/arch/arm/boot/dts/st/ste-href-ab8500.dtsi b/arch/arm/boot/dts/st/ste-href-ab8500.dtsi index e1de9d389a01..5eeb44c5e932 100644 --- a/arch/arm/boot/dts/st/ste-href-ab8500.dtsi +++ b/arch/arm/boot/dts/st/ste-href-ab8500.dtsi @@ -9,6 +9,54 @@ / { soc { prcmu@80157000 { ab8500 { + phy { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usb_a_1_default>; + pinctrl-1 = <&usb_a_1_sleep>; + }; + + regulator { + ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { + regulator-name = "V-DISPLAY"; + }; + + ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { + regulator-name = "V-eMMC1"; + }; + + ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { + regulator-name = "V-MMC-SD"; + }; + + ab8500_ldo_intcore_reg: ab8500_ldo_intcore { + regulator-name = "V-INTCORE"; + }; + + ab8500_ldo_tvout_reg: ab8500_ldo_tvout { + regulator-name = "V-TVOUT"; + }; + + ab8500_ldo_audio_reg: ab8500_ldo_audio { + regulator-name = "V-AUD"; + }; + + ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { + regulator-name = "V-AMIC1"; + }; + + ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { + regulator-name = "V-AMIC2"; + }; + + ab8500_ldo_dmic_reg: ab8500_ldo_dmic { + regulator-name = "V-DMIC"; + }; + + ab8500_ldo_ana_reg: ab8500_ldo_ana { + regulator-name = "V-CSI/DSI"; + }; + }; + gpio { /* Hog a few default settings */ pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/st/ste-href.dtsi b/arch/arm/boot/dts/st/ste-href.dtsi index 13b11dbeba1c..fbf0309e108f 100644 --- a/arch/arm/boot/dts/st/ste-href.dtsi +++ b/arch/arm/boot/dts/st/ste-href.dtsi @@ -242,61 +242,6 @@ msp3: msp@80125000 { status = "okay"; }; - prcmu@80157000 { - ab8500 { - gpio { - }; - - phy { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usb_a_1_default>; - pinctrl-1 = <&usb_a_1_sleep>; - }; - - regulator { - ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { - regulator-name = "V-DISPLAY"; - }; - - ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { - regulator-name = "V-eMMC1"; - }; - - ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { - regulator-name = "V-MMC-SD"; - }; - - ab8500_ldo_intcore_reg: ab8500_ldo_intcore { - regulator-name = "V-INTCORE"; - }; - - ab8500_ldo_tvout_reg: ab8500_ldo_tvout { - regulator-name = "V-TVOUT"; - }; - - ab8500_ldo_audio_reg: ab8500_ldo_audio { - regulator-name = "V-AUD"; - }; - - ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { - regulator-name = "V-AMIC1"; - }; - - ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { - regulator-name = "V-AMIC2"; - }; - - ab8500_ldo_dmic_reg: ab8500_ldo_dmic { - regulator-name = "V-DMIC"; - }; - - ab8500_ldo_ana_reg: ab8500_ldo_ana { - regulator-name = "V-CSI/DSI"; - }; - }; - }; - }; - pinctrl { sdi0 { sdi0_default_mode: sdi0_default { From patchwork Thu Dec 14 22:29:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 13493763 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59CD6C4332F for ; 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Thu, 14 Dec 2023 14:29:20 -0800 (PST) Received: from [127.0.1.1] ([85.235.12.238]) by smtp.gmail.com with ESMTPSA id g19-20020ac25393000000b0050bc56dd0acsm1989956lfh.184.2023.12.14.14.29.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 14:29:20 -0800 (PST) From: Linus Walleij Date: Thu, 14 Dec 2023 23:29:14 +0100 Subject: [PATCH 3/3] ARM: dts: ux500-href: Switch HREF520 to AB8505 MIME-Version: 1.0 Message-Id: <20231214-ux500-no-turnoff-lowbatt-v1-3-9dcff0783d62@linaro.org> References: <20231214-ux500-no-turnoff-lowbatt-v1-0-9dcff0783d62@linaro.org> In-Reply-To: <20231214-ux500-no-turnoff-lowbatt-v1-0-9dcff0783d62@linaro.org> To: linux-arm-kernel@lists.infradead.org Cc: Linus Walleij X-Mailer: b4 0.12.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231214_142923_294983_CDB90D9D X-CRM114-Status: GOOD ( 16.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org After noticing a tendency to misbehave and randomly power down: switch the HREF520 AB8500 to the AB8505, which is what it has mounted. After this the board works better. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/st/ste-href-ab8505.dtsi | 490 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/st/ste-href520-tvk.dts | 2 +- 2 files changed, 491 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/ste-href-ab8505.dtsi b/arch/arm/boot/dts/st/ste-href-ab8505.dtsi new file mode 100644 index 000000000000..268db68ccf87 --- /dev/null +++ b/arch/arm/boot/dts/st/ste-href-ab8505.dtsi @@ -0,0 +1,490 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2023 Linus Walleij + */ + +#include "ste-ab8505.dtsi" + +/ { + soc { + prcmu@80157000 { + ab8505 { + phy { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usb_a_1_default>; + pinctrl-1 = <&usb_a_1_sleep>; + }; + + regulator { + ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { + regulator-name = "V-DISPLAY"; + }; + + ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { + regulator-name = "V-eMMC1"; + }; + + ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { + regulator-name = "V-MMC-SD"; + }; + + ab8500_ldo_intcore_reg: ab8500_ldo_intcore { + regulator-name = "V-INTCORE"; + }; + + ab8500_ldo_tvout_reg: ab8500_ldo_tvout { + regulator-name = "V-TVOUT"; + }; + + ab8500_ldo_audio_reg: ab8500_ldo_audio { + regulator-name = "V-AUD"; + }; + + ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { + regulator-name = "V-AMIC1"; + }; + + ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { + regulator-name = "V-AMIC2"; + }; + + ab8500_ldo_dmic_reg: ab8500_ldo_dmic { + regulator-name = "V-DMIC"; + }; + + ab8500_ldo_ana_reg: ab8500_ldo_ana { + regulator-name = "V-CSI/DSI"; + }; + }; + + gpio { + /* Hog a few default settings */ + pinctrl-names = "default"; + pinctrl-0 = <&gpio2_default_mode>, + <&gpio4_default_mode>, + <&gpio10_default_mode>, + <&gpio11_default_mode>, + <&gpio12_default_mode>, + <&gpio13_default_mode>, + <&gpio16_default_mode>, + <&gpio24_default_mode>, + <&gpio25_default_mode>, + <&gpio36_default_mode>, + <&gpio37_default_mode>, + <&gpio38_default_mode>, + <&gpio39_default_mode>, + <&gpio42_default_mode>, + <&gpio26_default_mode>, + <&gpio35_default_mode>, + <&ycbcr_default_mode>, + <&pwm_default_mode>, + <&adi1_default_mode>, + <&usbuicc_default_mode>, + <&dmic_default_mode>, + <&extcpena_default_mode>, + <&modsclsda_default_mode>; + + /* + * Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42 + * are muxed in as GPIO, and configured as INPUT PULL DOWN + */ + gpio2 { + gpio2_default_mode: gpio2_default { + default_mux { + function = "gpio"; + groups = "gpio2_a_1"; + }; + default_cfg { + pins = "GPIO2_T9"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio4 { + gpio4_default_mode: gpio4_default { + default_mux { + function = "gpio"; + groups = "gpio4_a_1"; + }; + default_cfg { + pins = "GPIO4_W2"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio10 { + gpio10_default_mode: gpio10_default { + default_mux { + function = "gpio"; + groups = "gpio10_d_1"; + }; + default_cfg { + pins = "GPIO10_U17"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio11 { + gpio11_default_mode: gpio11_default { + default_mux { + function = "gpio"; + groups = "gpio11_d_1"; + }; + default_cfg { + pins = "GPIO11_AA18"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio12 { + gpio12_default_mode: gpio12_default { + default_mux { + function = "gpio"; + groups = "gpio12_d_1"; + }; + default_cfg { + pins = "GPIO12_U16"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio13 { + gpio13_default_mode: gpio13_default { + default_mux { + function = "gpio"; + groups = "gpio13_d_1"; + }; + default_cfg { + pins = "GPIO13_W17"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio16 { + gpio16_default_mode: gpio16_default { + default_mux { + function = "gpio"; + groups = "gpio16_a_1"; + }; + default_cfg { + pins = "GPIO16_F15"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio24 { + gpio24_default_mode: gpio24_default { + default_mux { + function = "gpio"; + groups = "gpio24_a_1"; + }; + default_cfg { + pins = "GPIO24_T14"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio25 { + gpio25_default_mode: gpio25_default { + default_mux { + function = "gpio"; + groups = "gpio25_a_1"; + }; + default_cfg { + pins = "GPIO25_R16"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio36 { + gpio36_default_mode: gpio36_default { + default_mux { + function = "gpio"; + groups = "gpio36_a_1"; + }; + default_cfg { + pins = "GPIO36_A17"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio37 { + gpio37_default_mode: gpio37_default { + default_mux { + function = "gpio"; + groups = "gpio37_a_1"; + }; + default_cfg { + pins = "GPIO37_E15"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio38 { + gpio38_default_mode: gpio38_default { + default_mux { + function = "gpio"; + groups = "gpio38_a_1"; + }; + default_cfg { + pins = "GPIO38_C17"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio39 { + gpio39_default_mode: gpio39_default { + default_mux { + function = "gpio"; + groups = "gpio39_a_1"; + }; + default_cfg { + pins = "GPIO39_E16"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio42 { + gpio42_default_mode: gpio42_default { + default_mux { + function = "gpio"; + groups = "gpio42_a_1"; + }; + default_cfg { + pins = "GPIO42_U2"; + input-enable; + bias-pull-down; + }; + }; + }; + /* + * Pins 26 and 35 muxed in as GPIO, and configured as OUTPUT LOW + */ + gpio26 { + gpio26_default_mode: gpio26_default { + default_mux { + function = "gpio"; + groups = "gpio26_d_1"; + }; + default_cfg { + pins = "GPIO26_M16"; + output-low; + }; + }; + }; + gpio35 { + gpio35_default_mode: gpio35_default { + default_mux { + function = "gpio"; + groups = "gpio35_d_1"; + }; + default_cfg { + pins = "GPIO35_W15"; + output-low; + }; + }; + }; + /* + * This sets up the YCBCR connector pins, i.e. analog video out. + * Set as input with no bias. + */ + ycbcr { + ycbcr_default_mode: ycbcr_default { + default_mux { + function = "ycbcr"; + groups = "ycbcr0123_d_1"; + }; + default_cfg { + pins = "GPIO6_Y18", + "GPIO7_AA20", + "GPIO8_W18", + "GPIO9_AA19"; + input-enable; + bias-disable; + }; + }; + }; + /* This sets up the PWM pins 14 and 15 */ + pwm { + pwm_default_mode: pwm_default { + default_mux { + function = "pwmout"; + groups = "pwmout1_d_1", "pwmout2_d_1"; + }; + default_cfg { + pins = "GPIO14_F14", + "GPIO15_B17"; + input-enable; + bias-pull-down; + }; + }; + }; + /* This sets up audio interface 1 */ + adi1 { + adi1_default_mode: adi1_default { + default_mux { + function = "adi1"; + groups = "adi1_d_1"; + }; + default_cfg { + pins = "GPIO17_P5", + "GPIO18_R5", + "GPIO19_U5", + "GPIO20_T5"; + input-enable; + bias-pull-down; + }; + }; + }; + /* This sets up the USB UICC pins */ + usbuicc { + usbuicc_default_mode: usbuicc_default { + default_mux { + function = "usbuicc"; + groups = "usbuicc_d_1"; + }; + default_cfg { + pins = "GPIO21_H19", + "GPIO22_G20", + "GPIO23_G19"; + input-enable; + bias-pull-down; + }; + }; + }; + /* This sets up the microphone pins */ + dmic { + dmic_default_mode: dmic_default { + default_mux { + function = "dmic"; + groups = "dmic12_d_1", + "dmic34_d_1", + "dmic56_d_1"; + }; + default_cfg { + pins = "GPIO27_J6", + "GPIO28_K6", + "GPIO29_G6", + "GPIO30_H6", + "GPIO31_F5", + "GPIO32_G5"; + input-enable; + bias-pull-down; + }; + }; + }; + extcpena { + extcpena_default_mode: extcpena_default { + default_mux { + function = "extcpena"; + groups = "extcpena_d_1"; + }; + default_cfg { + pins = "GPIO34_R17"; + input-enable; + bias-pull-down; + }; + }; + }; + /* Modem I2C setup (SCL and SDA pins) */ + modsclsda { + modsclsda_default_mode: modsclsda_default { + default_mux { + function = "modsclsda"; + groups = "modsclsda_d_1"; + }; + default_cfg { + pins = "GPIO40_T19", + "GPIO41_U19"; + input-enable; + bias-pull-down; + }; + }; + }; + /* + * Clock output pins associated with regulators. + */ + sysclkreq2 { + sysclkreq2_default_mode: sysclkreq2_default { + default_mux { + function = "sysclkreq"; + groups = "sysclkreq2_d_1"; + }; + default_cfg { + pins = "GPIO1_T10"; + input-enable; + bias-disable; + }; + }; + sysclkreq2_sleep_mode: sysclkreq2_sleep { + default_mux { + function = "gpio"; + groups = "gpio1_a_1"; + }; + default_cfg { + pins = "GPIO1_T10"; + input-enable; + bias-pull-down; + }; + }; + }; + sysclkreq4 { + sysclkreq4_default_mode: sysclkreq4_default { + default_mux { + function = "sysclkreq"; + groups = "sysclkreq4_d_1"; + }; + default_cfg { + pins = "GPIO3_U9"; + input-enable; + bias-disable; + }; + }; + sysclkreq4_sleep_mode: sysclkreq4_sleep { + default_mux { + function = "gpio"; + groups = "gpio3_a_1"; + }; + default_cfg { + pins = "GPIO3_U9"; + input-enable; + bias-pull-down; + }; + }; + }; + }; + /* + * Charging is not working on the HREF unless an actual battery is + * mounted, most HREFs have a DC cable in to the "battery power" + * which means this will only be cofusing. So do not enable charging + * of the HREFs. + */ + ab8500_fg { + status = "disabled"; + }; + ab8500_btemp { + status = "disabled"; + }; + ab8500_charger { + status = "disabled"; + }; + ab8500_chargalg { + status = "disabled"; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-href520-tvk.dts b/arch/arm/boot/dts/st/ste-href520-tvk.dts index 930058a8e0d1..5677df43c3ac 100644 --- a/arch/arm/boot/dts/st/ste-href520-tvk.dts +++ b/arch/arm/boot/dts/st/ste-href520-tvk.dts @@ -5,7 +5,7 @@ /dts-v1/; #include "ste-db8520.dtsi" -#include "ste-href-ab8500.dtsi" +#include "ste-href-ab8505.dtsi" #include "ste-hrefv60plus.dtsi" #include "ste-href-tvk1281618-r3.dtsi"