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b=NIOa12n7f/NcgJefzOwtqUDTTvgvAIAHDl4h83il28x1WXbJZynyF5JR7kPFcCl7uGbxWFdqygXFGrDQFl6LObnU4M+08CZRvPwdGpz6rvdyVOFv5eJyciwy6Xwv58TsiDSpSqXmiKWFOhBrRRqcwIYDD1G5ZN/l0E3NGixuIsE= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by PAXPR04MB8174.eurprd04.prod.outlook.com (2603:10a6:102:1c4::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7091.36; Sun, 17 Dec 2023 05:12:40 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%7]) with mapi id 15.20.7091.034; Sun, 17 Dec 2023 05:12:40 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org Cc: Frank.li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v4 01/15] PCI: imx6: Simplify clock handling by using bulk_clk_*() function Date: Sun, 17 Dec 2023 00:11:56 -0500 Message-Id: <20231217051210.754832-2-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231217051210.754832-1-Frank.Li@nxp.com> References: <20231217051210.754832-1-Frank.Li@nxp.com> X-ClientProxiedBy: BYAPR04CA0007.namprd04.prod.outlook.com (2603:10b6:a03:40::20) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|PAXPR04MB8174:EE_ X-MS-Office365-Filtering-Correlation-Id: d7428790-92c9-4d9a-b92f-08dbfebecaf5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: B857CR2NBQKsHkQ8KDW9Cq3Jo3WWVwfHwbv1AYffEiH+MHxhvcmoteUnWlAK1RMbzihDDZtRzHRCCxKF06HYyBDd5awV0fxNolsFVxL8hbQYLIDlfDWCt3Vnd9wMrFfQ2/KUsTdR5XhWbeF5TsFQtEybCVkPGKojhKgLkyQnKND8nOSC0vVFQ0hsKWNezKWDIYOxWBhw/B+xmLiSD6Z82Qrcn2H46LrSxXxmLebkxcziFN1LmyR0O8k/b926Y2ey9Ie2vdaAixs3dzFOn+HXQJHVqDzMBxAWRUZN0ElZerDdsbcahj/pOI6kKRTfPUU6r1eRGuCldYMtaulSEjvdhIZrP9Xass0rxKuK48nnA5bfgH4/WsggP/xfy1LGA3ogtCupaNYwZGC3aNMjjb1KRpqnJcQno/YO3pRAJyrL5I6g4EMb36pVRV/jOBgnD+W3qVG3kxPyjhJB+CqhJx2EEjxS7xyLK1mifKohvGlkp+ecMbylnNg1/0waEusmDtIADFlNJQwzWsi7lwFIu5hGO3OjI/6bp5mumo4BLvozFgITSHuC6zLHeKMdjfmHuBb//ULacANpskF2BM5vE/GdmRLceDlTKjkeWzWdpzCFJObdvn784BwoLVCOu2iPIPrCls4IlQ9xUmi5cDPeJ7I8kG/U9d/NdPadNtDQNq77+JlvL0ttR0nOx4aoNLILX0fG+DgdA2MQwDS0JLdU1aYRml7m7621fgH66Ycc8jLjp6I0QQ2vW9Bi+RhbysFyaml3I//n6y709Cofi6HxjmxxkH1Q/8u9cinOSUkCDWsSTe/+zJLKZmdVrrACXWzYt8OtwnV2NsIIdWWjiRm98jLfg/hUh9d3jy3SozlJ6Qxw+wY5cPDgUCkuyOgMQxIvgcey6VqUnpgwcPYsvcX9wn/Igx4YN4A5bsmuxznzmDfkbR6S6Mhy3WAssGBZpsbOeWbNluNbWOuH8IRhJqQ2HCAFlg21oTS+g12bx7zitfrdfzPb5W+wScm4o66Ld/nj94QJkZi90q9ULAK3SVwAEcfTNMqBeN733KJ65WblGymFw8cYML9BYsRXkODSPtiS9UmbkWdYOsNCRvoLspiSrIpdlqeXTpG4F4/OsPLoz4p7TmTkV4tHoPwwqacg5xKwwTjZoPhEH6Du8taNp3Xvxqq5p+ritN1OumBlHXpVHuWk96hgpngxdanQLWbKrCB2pVtIApapBlWbMGxXQtBaTOA9V9QmKCBtDLQnIqrwBwkgGBwO7vO2lC+Y6Ujkl6HPEXLHtLKP6NGjAVNscUhjlCWy2f7Zg6hGE77Ns0nqcl7+CC2P2p0Ucw8d6/td3Li7s7JptM2yPXNgfWv9q5eLrij+htGzO7ApVi7+qbT8Fkt0yJms6avqrNkBgekmSX8hMjELqNHki0RYw13jOTKi1kA9MIdFpNt8VlDyt++tanPeNQr0bGwFrEiIZD2F21QuljyLClHFZxiVgASylrhv28lGIa3U6z9Xcf5C2SEnXc8cy/0pwRMvOpv4j98vf9lIJXxacPSLKDnh7hPxiGjJkm58TpMRgni4a1XQOmcRN/LYgl8= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: d7428790-92c9-4d9a-b92f-08dbfebecaf5 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Dec 2023 05:12:40.8523 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: WNStehkinXDRkKe7bHU2lVFvP40aLcvBpD3z6S5qMl0fdR58RKT27LsIQbDlXJwUhpThsSBKfJ6MmHdOqfsAsQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8174 Refactors the clock handling logic in the imx6 PCI driver by adding clk_names[] define in drvdata . Simplifies the code and makes it more maintainable, as future additions of SOC support will only require straightforward changes. Signed-off-by: Frank Li --- Notes: Change from v3 to v4 - using clk_bulk_*() API Change from v1 to v3 - none drivers/pci/controller/dwc/pci-imx6.c | 128 ++++++++------------------ 1 file changed, 38 insertions(+), 90 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 74703362aeec7..2086214345e9a 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -61,12 +61,15 @@ enum imx6_pcie_variants { #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) +#define IMX6_PCIE_MAX_CLKS 6 + struct imx6_pcie_drvdata { enum imx6_pcie_variants variant; enum dw_pcie_device_mode mode; u32 flags; int dbi_length; const char *gpr; + const char *clk_names[IMX6_PCIE_MAX_CLKS]; }; struct imx6_pcie { @@ -74,11 +77,8 @@ struct imx6_pcie { int reset_gpio; bool gpio_active_high; bool link_is_up; - struct clk *pcie_bus; - struct clk *pcie_phy; - struct clk *pcie_inbound_axi; - struct clk *pcie; - struct clk *pcie_aux; + struct clk_bulk_data clks[IMX6_PCIE_MAX_CLKS]; + u32 clks_cnt; struct regmap *iomuxc_gpr; u16 msi_ctrl; u32 controller_id; @@ -407,13 +407,18 @@ static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) { - unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy); + unsigned long phy_rate = 0; int mult, div; u16 val; + int i; if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) return 0; + for (i = 0; i < imx6_pcie->clks_cnt; i++) + if (strncmp(imx6_pcie->clks[i].id, "pcie_phy", 8) == 0) + phy_rate = clk_get_rate(imx6_pcie->clks[i].clk); + switch (phy_rate) { case 125000000: /* @@ -550,19 +555,11 @@ static int imx6_pcie_attach_pd(struct device *dev) static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) { - struct dw_pcie *pci = imx6_pcie->pci; - struct device *dev = pci->dev; unsigned int offset; int ret = 0; switch (imx6_pcie->drvdata->variant) { case IMX6SX: - ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi); - if (ret) { - dev_err(dev, "unable to enable pcie_axi clock\n"); - break; - } - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); break; @@ -589,12 +586,6 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) case IMX8MQ_EP: case IMX8MP: case IMX8MP_EP: - ret = clk_prepare_enable(imx6_pcie->pcie_aux); - if (ret) { - dev_err(dev, "unable to enable pcie_aux clock\n"); - break; - } - offset = imx6_pcie_grp_offset(imx6_pcie); /* * Set the over ride low and enabled @@ -615,9 +606,6 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie) { switch (imx6_pcie->drvdata->variant) { - case IMX6SX: - clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); - break; case IMX6QP: case IMX6Q: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, @@ -631,14 +619,6 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie) IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); break; - case IMX8MM: - case IMX8MM_EP: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MP: - case IMX8MP_EP: - clk_disable_unprepare(imx6_pcie->pcie_aux); - break; default: break; } @@ -650,23 +630,9 @@ static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) struct device *dev = pci->dev; int ret; - ret = clk_prepare_enable(imx6_pcie->pcie_phy); - if (ret) { - dev_err(dev, "unable to enable pcie_phy clock\n"); + ret = clk_bulk_prepare_enable(imx6_pcie->clks_cnt, imx6_pcie->clks); + if (ret) return ret; - } - - ret = clk_prepare_enable(imx6_pcie->pcie_bus); - if (ret) { - dev_err(dev, "unable to enable pcie_bus clock\n"); - goto err_pcie_bus; - } - - ret = clk_prepare_enable(imx6_pcie->pcie); - if (ret) { - dev_err(dev, "unable to enable pcie clock\n"); - goto err_pcie; - } ret = imx6_pcie_enable_ref_clk(imx6_pcie); if (ret) { @@ -679,11 +645,7 @@ static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) return 0; err_ref_clk: - clk_disable_unprepare(imx6_pcie->pcie); -err_pcie: - clk_disable_unprepare(imx6_pcie->pcie_bus); -err_pcie_bus: - clk_disable_unprepare(imx6_pcie->pcie_phy); + clk_bulk_disable_unprepare(imx6_pcie->clks_cnt, imx6_pcie->clks); return ret; } @@ -691,9 +653,7 @@ static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) { imx6_pcie_disable_ref_clk(imx6_pcie); - clk_disable_unprepare(imx6_pcie->pcie); - clk_disable_unprepare(imx6_pcie->pcie_bus); - clk_disable_unprepare(imx6_pcie->pcie_phy); + clk_bulk_disable_unprepare(imx6_pcie->clks_cnt, imx6_pcie->clks); } static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) @@ -1305,32 +1265,19 @@ static int imx6_pcie_probe(struct platform_device *pdev) return imx6_pcie->reset_gpio; } - /* Fetch clocks */ - imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus"); - if (IS_ERR(imx6_pcie->pcie_bus)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_bus), - "pcie_bus clock source missing or invalid\n"); + while (imx6_pcie->drvdata->clk_names[imx6_pcie->clks_cnt]) { + int i = imx6_pcie->clks_cnt; - imx6_pcie->pcie = devm_clk_get(dev, "pcie"); - if (IS_ERR(imx6_pcie->pcie)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie), - "pcie clock source missing or invalid\n"); + imx6_pcie->clks[i].id = imx6_pcie->drvdata->clk_names[i]; + imx6_pcie->clks_cnt++; + } + + /* Fetch clocks */ + ret = devm_clk_bulk_get(dev, imx6_pcie->clks_cnt, imx6_pcie->clks); + if (ret) + return ret; switch (imx6_pcie->drvdata->variant) { - case IMX6SX: - imx6_pcie->pcie_inbound_axi = devm_clk_get(dev, - "pcie_inbound_axi"); - if (IS_ERR(imx6_pcie->pcie_inbound_axi)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_inbound_axi), - "pcie_inbound_axi clock missing or invalid\n"); - break; - case IMX8MQ: - case IMX8MQ_EP: - imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux"); - if (IS_ERR(imx6_pcie->pcie_aux)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), - "pcie_aux clock source missing or invalid\n"); - fallthrough; case IMX7D: if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) imx6_pcie->controller_id = 1; @@ -1353,10 +1300,6 @@ static int imx6_pcie_probe(struct platform_device *pdev) case IMX8MM_EP: case IMX8MP: case IMX8MP_EP: - imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux"); - if (IS_ERR(imx6_pcie->pcie_aux)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), - "pcie_aux clock source missing or invalid\n"); imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); if (IS_ERR(imx6_pcie->apps_reset)) @@ -1372,14 +1315,6 @@ static int imx6_pcie_probe(struct platform_device *pdev) default: break; } - /* Don't fetch the pcie_phy clock, if it has abstract PHY driver */ - if (imx6_pcie->phy == NULL) { - imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy"); - if (IS_ERR(imx6_pcie->pcie_phy)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy), - "pcie_phy clock source missing or invalid\n"); - } - /* Grab turnoff reset */ imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); @@ -1470,6 +1405,9 @@ static void imx6_pcie_shutdown(struct platform_device *pdev) imx6_pcie_assert_core_reset(imx6_pcie); } +#define IMX6_CLKS_COMMON "pcie_bus", "pcie" +#define IMX6_CLKS_NO_PHYDRV IMX6_CLKS_COMMON, "pcie_phy" + static const struct imx6_pcie_drvdata drvdata[] = { [IMX6Q] = { .variant = IMX6Q, @@ -1477,6 +1415,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, .dbi_length = 0x200, .gpr = "fsl,imx6q-iomuxc-gpr", + .clk_names = {IMX6_CLKS_NO_PHYDRV}, }, [IMX6SX] = { .variant = IMX6SX, @@ -1484,6 +1423,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr = "fsl,imx6q-iomuxc-gpr", + .clk_names = {IMX6_CLKS_NO_PHYDRV, "pcie_inbound_axi"}, }, [IMX6QP] = { .variant = IMX6QP, @@ -1492,40 +1432,48 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, .dbi_length = 0x200, .gpr = "fsl,imx6q-iomuxc-gpr", + .clk_names = {IMX6_CLKS_NO_PHYDRV}, }, [IMX7D] = { .variant = IMX7D, .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr = "fsl,imx7d-iomuxc-gpr", + .clk_names = {IMX6_CLKS_NO_PHYDRV}, }, [IMX8MQ] = { .variant = IMX8MQ, .gpr = "fsl,imx8mq-iomuxc-gpr", + .clk_names = {IMX6_CLKS_NO_PHYDRV, "pcie_aux"}, }, [IMX8MM] = { .variant = IMX8MM, .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr = "fsl,imx8mm-iomuxc-gpr", + .clk_names = {IMX6_CLKS_COMMON, "pcie_aux"}, }, [IMX8MP] = { .variant = IMX8MP, .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr = "fsl,imx8mp-iomuxc-gpr", + .clk_names = {IMX6_CLKS_COMMON, "pcie_aux"}, }, [IMX8MQ_EP] = { .variant = IMX8MQ_EP, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mq-iomuxc-gpr", + .clk_names = {IMX6_CLKS_NO_PHYDRV, "pcie_aux"}, }, [IMX8MM_EP] = { .variant = IMX8MM_EP, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mm-iomuxc-gpr", + .clk_names = {IMX6_CLKS_COMMON, "pcie_aux"}, }, [IMX8MP_EP] = { .variant = IMX8MP_EP, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mp-iomuxc-gpr", + .clk_names = {IMX6_CLKS_COMMON, "pcie_aux"}, }, }; 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b=g/ade2iCpOFtMD7tSdwk4YsyTZJZGmRPokke0B2+Tqh1akIbJxNdo03doAjyqYhEV5uQSM8omMaNsyCbo0WEcXEWLIyh+cD91Jc1W53aiXvY8RfaU5lBSOGStkrs88YwXjxvtcaUTXOuN5PFzCJxRW5kQtLPs7yyCVs3vOoHB9A= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by PAXPR04MB8174.eurprd04.prod.outlook.com (2603:10a6:102:1c4::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7091.36; Sun, 17 Dec 2023 05:12:45 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%7]) with mapi id 15.20.7091.034; Sun, 17 Dec 2023 05:12:45 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org Cc: Frank.li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v4 02/15] PCI: imx6: Simplify phy handling by using by using IMX6_PCIE_FLAG_HAS_PHY Date: Sun, 17 Dec 2023 00:11:57 -0500 Message-Id: <20231217051210.754832-3-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231217051210.754832-1-Frank.Li@nxp.com> References: <20231217051210.754832-1-Frank.Li@nxp.com> X-ClientProxiedBy: BYAPR04CA0007.namprd04.prod.outlook.com (2603:10b6:a03:40::20) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|PAXPR04MB8174:EE_ X-MS-Office365-Filtering-Correlation-Id: d75b788b-a14b-47e4-1db0-08dbfebece06 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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The drvdata::flags and a bitmask ensures a cleaner and more scalable switch-case structure for handling phy. Signed-off-by: Frank Li --- Notes: Change from v1 to v3: - none drivers/pci/controller/dwc/pci-imx6.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 2086214345e9a..91ba26a4b4c3d 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -60,6 +60,9 @@ enum imx6_pcie_variants { #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) +#define IMX6_PCIE_FLAG_HAS_PHY BIT(3) + +#define imx6_check_flag(pci, val) (pci->drvdata->flags & val) #define IMX6_PCIE_MAX_CLKS 6 @@ -1277,6 +1280,13 @@ static int imx6_pcie_probe(struct platform_device *pdev) if (ret) return ret; + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY)) { + imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); + if (IS_ERR(imx6_pcie->phy)) + return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), + "failed to get pcie phy\n"); + } + switch (imx6_pcie->drvdata->variant) { case IMX7D: if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) @@ -1306,11 +1316,6 @@ static int imx6_pcie_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), "failed to get pcie apps reset control\n"); - imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); - if (IS_ERR(imx6_pcie->phy)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), - "failed to get pcie phy\n"); - break; default: break; @@ -1447,13 +1452,15 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MM] = { .variant = IMX8MM, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX6_PCIE_FLAG_HAS_PHY, .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = {IMX6_CLKS_COMMON, "pcie_aux"}, }, [IMX8MP] = { .variant = IMX8MP, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX6_PCIE_FLAG_HAS_PHY, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = {IMX6_CLKS_COMMON, "pcie_aux"}, }, @@ -1465,12 +1472,14 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MM_EP] = { .variant = IMX8MM_EP, + .flags = IMX6_PCIE_FLAG_HAS_PHY, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = {IMX6_CLKS_COMMON, "pcie_aux"}, }, [IMX8MP_EP] = { .variant = IMX8MP_EP, + .flags = IMX6_PCIE_FLAG_HAS_PHY, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = {IMX6_CLKS_COMMON, "pcie_aux"}, From patchwork Sun Dec 17 05:11:58 2023 Content-Type: text/plain; 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b=JRHNoUAoUXtcdoUFAxXRVGCHBThiK4kqIDZFJOEr/kmFQUbZ/93aY3r95w1Ar7rX4hF2VamkYAeuHBFDXTXek8nqa2iM9WIvCPv9XSM/t48JrgZZ4nadhtXKpt51eMWtGaMNcIy3J3LtF68cxJM90tKSqi92AoXhsCS3iyQM2aY= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by PAXPR04MB8174.eurprd04.prod.outlook.com (2603:10a6:102:1c4::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7091.36; Sun, 17 Dec 2023 05:12:50 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%7]) with mapi id 15.20.7091.034; Sun, 17 Dec 2023 05:12:50 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org Cc: Frank.li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v4 03/15] PCI: imx6: Simplify reset handling by using by using *_FLAG_HAS_*_RESET Date: Sun, 17 Dec 2023 00:11:58 -0500 Message-Id: <20231217051210.754832-4-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231217051210.754832-1-Frank.Li@nxp.com> References: <20231217051210.754832-1-Frank.Li@nxp.com> X-ClientProxiedBy: BYAPR04CA0007.namprd04.prod.outlook.com (2603:10b6:a03:40::20) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|PAXPR04MB8174:EE_ X-MS-Office365-Filtering-Correlation-Id: b38736bc-4fd2-43b8-0d18-08dbfebed101 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Bjj4qTPeITTMaGgX5UufndUxXpo5VUuKyzsWQ3A2sxgklRVqSS9i2aBvyHUgMmScQcsSV63gosbjmF6WWMuA/PMBHxAKn969xfijwftgce8vgOffX9nYj8X0hGRy0LHy0AeNTegf09uMw7J9XneAGH1JnJRm72LrFJqcO4iWXtOuHvekAVJQX9WSlrAje/T9ROx7e73rRI06dffFDp5AmLpGCCtEdbJ08ANS04gEnsT+3lG6Bw194qax8InRilv9Gn3/2eb6UVbDdI7zHLCuIcKBvd7Ygefht3aPErnNBoKL8KV7YUrZ5x3S5qdWgHDNtXQlQ2UqqutQLTBmtzjGXNugWZ1AU1Pq/fj1JvnLfsfqdLtwkDlO3eprpnLMSAm+wbnr/dpZEgcWXT34AYshLscxGBwjI/vBptt+NBYUlZR6l96uCdwWUcUoxNvMgssGbOu/6VHVUQiRxiSCHOY3j75ysBe6RZN2TPdCazuDH6bpHfDFnrtD0ELnFYz2NtXOACL9+Qj6rlZxV77eXeJ4LNqjGBqdqsiCfPiJTZeAGsH0SE/WpcVSr2XsaLB5o6Q8ktfK9mUpm8FNwyL8gq6j5Fgvc85AAacIGWVMtBvkwz4wQm3ttXBiM1cius5hxUXj6ug5vpbnIkX36GfoiWyxPRXCmBKcStpS7JMLFpLqRijn7TgZF1spOoHG4qpP/CL+cR8RXXBBBdtL+H/Mxj6sAMdE+ZvRM7lQ1QWnXGv0M59xRGlr/8YWSueG9b8zQG9mMTC6r2mcQDxnsQ5BjMvdq+TBb3PKJ6jtBSCf6gTZGn34uouqV8s2qaLdkVu7fdSAIvcplg9OwQrTu2jmJ0j266MwV4pGJT6RkaF5Nh/i/n6UpY4s9opxNGP2IFFC7IMuySKuIA65joUlKtKVpAN2upk+AHamKdS3cxyCOmKgKH9j7p8+lXIGVHNv8h7K6O2WAfi1pyBbgQ4mFsz0cxG+CXWWpOQHRM3x0xL/LPGYcHvDGIvg9u1eIqLPFgrbt9Bnhar7jwliygKgoPCTMc1R9H2WeSl5Ag9hEM/st/so2eIdcUDUsqBhJApYPwTRn/MYMpX19x/89T306w54syWZu/34/aN0uZiH3HLFoPBIYIruJJOcydzBlwBxtoOQoMBNsCn3EA1xjKf2TJQhnLDW03zaWWOiaG76ZQ0nai7BxQBEpalZRoeOzHmBhdfX1jxGCIFdFNXmNdKoxZhr59d1THE1VstWqXXJ4hNUMUiwLZQbFJdN0phjm/eB+UmTqCG/qHlaUd2z16752selIBZEsSCE5ioMm6DRXoOEh5CBgssLvkfkK41Am8uNtXVay6386dXifkwPZMVaGfNvhHewH1J8zJoWfg6eQrHMchcLdy0No6tHfvm5F5/VaoNcfskKnEEJ+yAh9VZE/5KTfLkpOTE4Ve74Mj5v6yoGP2BhZGL21ZxJAROw5A1voKMfq8Eh4JUWv1R8EiC+FWkLx610FAj8ftt6yGchmtTdXNp+SQeDg4DcLK36u8Jb6uPYkooG87w6dxgekugKWNqDQg4sFbhEu7GQwR2uZSgAd/0q2TQ= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: b38736bc-4fd2-43b8-0d18-08dbfebed101 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Dec 2023 05:12:50.8330 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +X+aGZ9RU/8LX1luRRGbhitDUAsDR9q1/IdUH34+OT5pjddZ26KIRmu6DsjMu1zeMVK8JcYlNuZFkRNNKRHiCw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8174 Refactors the reset handling logic in the imx6 PCI driver by adding IMX6_PCIE_FLAG_HAS_*_RESET bitmask define for drvdata::flags. The drvdata::flags and a bitmask ensures a cleaner and more scalable switch-case structure for handling reset. Reviewed-by: Philipp Zabel Signed-off-by: Frank Li Reviewed-by: Manivannan Sadhasivam --- Notes: Change from v2 to v3: - add Philipp's Reviewed-by tag Change from v1 to v2: - remove condition check before reset_control_(de)assert() because it is none ops if a NULL pointer pass down. - still keep condition check at probe to help identify dts file mismatch problem. Change from v1 to v2: - remove condition check before reset_control_(de)assert() because it is none ops if a NULL pointer pass down. - still keep condition check at probe to help identify dts file mismatch problem. drivers/pci/controller/dwc/pci-imx6.c | 108 ++++++++++---------------- 1 file changed, 41 insertions(+), 67 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 91ba26a4b4c3d..c1fb38a2ebeb6 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -61,6 +61,8 @@ enum imx6_pcie_variants { #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) #define IMX6_PCIE_FLAG_HAS_PHY BIT(3) +#define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4) +#define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5) #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) @@ -661,18 +663,10 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) { + reset_control_assert(imx6_pcie->pciephy_reset); + reset_control_assert(imx6_pcie->apps_reset); + switch (imx6_pcie->drvdata->variant) { - case IMX7D: - case IMX8MQ: - case IMX8MQ_EP: - reset_control_assert(imx6_pcie->pciephy_reset); - fallthrough; - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - reset_control_assert(imx6_pcie->apps_reset); - break; case IMX6SX: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, @@ -693,6 +687,8 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); break; + default: + break; } /* Some boards don't have PCIe reset GPIO. */ @@ -706,14 +702,10 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) struct dw_pcie *pci = imx6_pcie->pci; struct device *dev = pci->dev; + reset_control_deassert(imx6_pcie->pciephy_reset); + switch (imx6_pcie->drvdata->variant) { - case IMX8MQ: - case IMX8MQ_EP: - reset_control_deassert(imx6_pcie->pciephy_reset); - break; case IMX7D: - reset_control_deassert(imx6_pcie->pciephy_reset); - /* Workaround for ERR010728, failure of PCI-e PLL VCO to * oscillate, especially when cold. This turns off "Duty-cycle * Corrector" and other mysterious undocumented things. @@ -745,11 +737,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) usleep_range(200, 500); break; - case IMX6Q: /* Nothing to do */ - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: + default: break; } @@ -796,16 +784,11 @@ static void imx6_pcie_ltssm_enable(struct device *dev) IMX6Q_GPR12_PCIE_CTL_2, IMX6Q_GPR12_PCIE_CTL_2); break; - case IMX7D: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - reset_control_deassert(imx6_pcie->apps_reset); + default: break; } + + reset_control_deassert(imx6_pcie->apps_reset); } static void imx6_pcie_ltssm_disable(struct device *dev) @@ -819,16 +802,11 @@ static void imx6_pcie_ltssm_disable(struct device *dev) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_PCIE_CTL_2, 0); break; - case IMX7D: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - reset_control_assert(imx6_pcie->apps_reset); + default: break; } + + reset_control_assert(imx6_pcie->apps_reset); } static int imx6_pcie_start_link(struct dw_pcie *pci) @@ -1287,36 +1265,24 @@ static int imx6_pcie_probe(struct platform_device *pdev) "failed to get pcie phy\n"); } - switch (imx6_pcie->drvdata->variant) { - case IMX7D: - if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) - imx6_pcie->controller_id = 1; - - imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, - "pciephy"); - if (IS_ERR(imx6_pcie->pciephy_reset)) { - dev_err(dev, "Failed to get PCIEPHY reset control\n"); - return PTR_ERR(imx6_pcie->pciephy_reset); - } - - imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, - "apps"); - if (IS_ERR(imx6_pcie->apps_reset)) { - dev_err(dev, "Failed to get PCIE APPS reset control\n"); - return PTR_ERR(imx6_pcie->apps_reset); - } - break; - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, - "apps"); + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_APP_RESET)) { + imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); if (IS_ERR(imx6_pcie->apps_reset)) return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), "failed to get pcie apps reset control\n"); + } - break; + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY_RESET)) { + imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); + if (IS_ERR(imx6_pcie->pciephy_reset)) + return dev_err_probe(dev, PTR_ERR(imx6_pcie->pciephy_reset), + "Failed to get PCIEPHY reset control\n"); + } + + switch (imx6_pcie->drvdata->variant) { + case IMX7D: + if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) + imx6_pcie->controller_id = 1; default: break; } @@ -1441,31 +1407,39 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX7D] = { .variant = IMX7D, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX6_PCIE_FLAG_HAS_APP_RESET | + IMX6_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx7d-iomuxc-gpr", .clk_names = {IMX6_CLKS_NO_PHYDRV}, }, [IMX8MQ] = { .variant = IMX8MQ, + .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | + IMX6_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = {IMX6_CLKS_NO_PHYDRV, "pcie_aux"}, }, [IMX8MM] = { .variant = IMX8MM, .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | - IMX6_PCIE_FLAG_HAS_PHY, + IMX6_PCIE_FLAG_HAS_PHY | + IMX6_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = {IMX6_CLKS_COMMON, "pcie_aux"}, }, [IMX8MP] = { .variant = IMX8MP, .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | - IMX6_PCIE_FLAG_HAS_PHY, + IMX6_PCIE_FLAG_HAS_PHY | + IMX6_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = {IMX6_CLKS_COMMON, "pcie_aux"}, }, [IMX8MQ_EP] = { .variant = IMX8MQ_EP, + .flags = IMX6_PCIE_FLAG_HAS_PHY | + IMX6_PCIE_FLAG_HAS_PHY_RESET, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = {IMX6_CLKS_NO_PHYDRV, "pcie_aux"}, From patchwork Sun Dec 17 05:11:59 2023 Content-Type: text/plain; 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b=kRjZZ8ZAFZ65ScBB1s/y2LuqIfHD6zSn33nuFiUs4iVYyoI1LByq/6cWgmDHh+Ruc92p4f0YPjdrqJm9xt5Tl+SHmhMXrtqUj9nL6eFjUnvr+LG9ws106FOBSh0ziS2MT+MPfZpHIUqXY4xO+SVnynrrrxIGlTSKqueP+QKDSxg= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by PAXPR04MB8174.eurprd04.prod.outlook.com (2603:10a6:102:1c4::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7091.36; Sun, 17 Dec 2023 05:12:56 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%7]) with mapi id 15.20.7091.034; Sun, 17 Dec 2023 05:12:56 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org Cc: Frank.li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v4 04/15] PCI: imx6: Using "linux,pci-domain" as slot ID Date: Sun, 17 Dec 2023 00:11:59 -0500 Message-Id: <20231217051210.754832-5-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231217051210.754832-1-Frank.Li@nxp.com> References: <20231217051210.754832-1-Frank.Li@nxp.com> X-ClientProxiedBy: BYAPR04CA0007.namprd04.prod.outlook.com (2603:10b6:a03:40::20) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|PAXPR04MB8174:EE_ X-MS-Office365-Filtering-Correlation-Id: 033c5254-2f27-4389-fcb5-08dbfebed3fb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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If there are more than 2 slots, compared logic will become complex. "linux,pci-domain" already exist at dts since first commit: commit (9e65987b9584d arm64: dts: imx8mp: Add iMX8MP PCIe support). So it is safe to remove compare basic address code: ... if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) imx6_pcie->controller_id = 1; ... Signed-off-by: Frank Li --- Notes: Change from v3 to v4 - remove compare basic address logic Change from v2 to v3 - none Change from v1 to v2 - fix of_get_pci_domain_nr return value check logic drivers/pci/controller/dwc/pci-imx6.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index c1fb38a2ebeb6..7145947e21d92 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -33,6 +33,7 @@ #include #include +#include "../../pci.h" #include "pcie-designware.h" #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9) @@ -40,7 +41,6 @@ #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11) #define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12) #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8) -#define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev) @@ -1279,13 +1279,11 @@ static int imx6_pcie_probe(struct platform_device *pdev) "Failed to get PCIEPHY reset control\n"); } - switch (imx6_pcie->drvdata->variant) { - case IMX7D: - if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) - imx6_pcie->controller_id = 1; - default: - break; - } + /* Using linux,pci-domain as PCI slot id */ + imx6_pcie->controller_id = of_get_pci_domain_nr(node); + /* If there are not "linux,pci-domain" in dts file, means only 1 controller */ + if (imx6_pcie->controller_id < 0) + imx6_pcie->controller_id = 0; /* Grab turnoff reset */ imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); From patchwork Sun Dec 17 05:12:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13495747 Received: from EUR02-AM0-obe.outbound.protection.outlook.com (mail-am0eur02on2074.outbound.protection.outlook.com [40.107.247.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F4615CB5; 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Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by PAXPR04MB8174.eurprd04.prod.outlook.com (2603:10a6:102:1c4::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7091.36; Sun, 17 Dec 2023 05:13:01 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%7]) with mapi id 15.20.7091.034; Sun, 17 Dec 2023 05:13:01 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org Cc: Frank.li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v4 05/15] PCI: imx6: Simplify ltssm_enable() by using ltssm_off and ltssm_mask Date: Sun, 17 Dec 2023 00:12:00 -0500 Message-Id: <20231217051210.754832-6-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231217051210.754832-1-Frank.Li@nxp.com> References: <20231217051210.754832-1-Frank.Li@nxp.com> X-ClientProxiedBy: BYAPR04CA0007.namprd04.prod.outlook.com (2603:10b6:a03:40::20) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|PAXPR04MB8174:EE_ X-MS-Office365-Filtering-Correlation-Id: fd9dc01f-d1b1-4ea6-c3cf-08dbfebed70e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Frank Li --- Notes: Change from v1 to v3 - none drivers/pci/controller/dwc/pci-imx6.c | 37 ++++++++++++--------------- 1 file changed, 16 insertions(+), 21 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 7145947e21d92..79d892836a24d 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -75,6 +75,8 @@ struct imx6_pcie_drvdata { int dbi_length; const char *gpr; const char *clk_names[IMX6_PCIE_MAX_CLKS]; + const u32 ltssm_off; + const u32 ltssm_mask; }; struct imx6_pcie { @@ -775,18 +777,11 @@ static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) static void imx6_pcie_ltssm_enable(struct device *dev) { struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); + const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; - switch (imx6_pcie->drvdata->variant) { - case IMX6Q: - case IMX6SX: - case IMX6QP: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6Q_GPR12_PCIE_CTL_2, - IMX6Q_GPR12_PCIE_CTL_2); - break; - default: - break; - } + if (drvdata->ltssm_mask) + regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, + drvdata->ltssm_mask); reset_control_deassert(imx6_pcie->apps_reset); } @@ -794,17 +789,11 @@ static void imx6_pcie_ltssm_enable(struct device *dev) static void imx6_pcie_ltssm_disable(struct device *dev) { struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); + const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; - switch (imx6_pcie->drvdata->variant) { - case IMX6Q: - case IMX6SX: - case IMX6QP: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6Q_GPR12_PCIE_CTL_2, 0); - break; - default: - break; - } + if (drvdata->ltssm_mask) + regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, + drvdata->ltssm_mask, 0); reset_control_assert(imx6_pcie->apps_reset); } @@ -1385,6 +1374,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .dbi_length = 0x200, .gpr = "fsl,imx6q-iomuxc-gpr", .clk_names = {IMX6_CLKS_NO_PHYDRV}, + .ltssm_off = IOMUXC_GPR12, + .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, }, [IMX6SX] = { .variant = IMX6SX, @@ -1393,6 +1384,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr = "fsl,imx6q-iomuxc-gpr", .clk_names = {IMX6_CLKS_NO_PHYDRV, "pcie_inbound_axi"}, + .ltssm_off = IOMUXC_GPR12, + .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, }, [IMX6QP] = { .variant = IMX6QP, @@ -1402,6 +1395,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .dbi_length = 0x200, .gpr = "fsl,imx6q-iomuxc-gpr", .clk_names = {IMX6_CLKS_NO_PHYDRV}, + .ltssm_off = IOMUXC_GPR12, + .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, }, [IMX7D] = { .variant = IMX7D, From patchwork Sun Dec 17 05:12:01 2023 Content-Type: text/plain; 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b=rBP3h62cOarlVBu414trgzAtTZ47FHUpULANnNlylEjgp5uoj7qTVSmM0JK8PUeWB1vFnMlSb2NJNUIbsf9XHwdxfzBX1P9m3akxN22mwM+/8r3sEnRL2W6lt/ij/neR1As+vInzGEWvECP8C20JQ6Sm5EWyXcjl0DYITjN568E= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by PAXPR04MB8174.eurprd04.prod.outlook.com (2603:10a6:102:1c4::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7091.36; Sun, 17 Dec 2023 05:13:06 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%7]) with mapi id 15.20.7091.034; Sun, 17 Dec 2023 05:13:06 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org Cc: Frank.li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v4 06/15] PCI: imx6: Simplify configure_type() by using mode_off and mode_mask Date: Sun, 17 Dec 2023 00:12:01 -0500 Message-Id: <20231217051210.754832-7-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231217051210.754832-1-Frank.Li@nxp.com> References: <20231217051210.754832-1-Frank.Li@nxp.com> X-ClientProxiedBy: BYAPR04CA0007.namprd04.prod.outlook.com (2603:10b6:a03:40::20) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|PAXPR04MB8174:EE_ X-MS-Office365-Filtering-Correlation-Id: 2b3cff2f-d75c-4b5e-5122-08dbfebeda07 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Frank Li --- Notes: Change from v2 to v3 - none Change from v1 to v2 - use ffs() to fixe build error. drivers/pci/controller/dwc/pci-imx6.c | 60 ++++++++++++++++++--------- 1 file changed, 40 insertions(+), 20 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 79d892836a24d..49b98593326f9 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -68,6 +68,7 @@ enum imx6_pcie_variants { #define IMX6_PCIE_MAX_CLKS 6 +#define IMX6_PCIE_MAX_INSTANCES 2 struct imx6_pcie_drvdata { enum imx6_pcie_variants variant; enum dw_pcie_device_mode mode; @@ -77,6 +78,8 @@ struct imx6_pcie_drvdata { const char *clk_names[IMX6_PCIE_MAX_CLKS]; const u32 ltssm_off; const u32 ltssm_mask; + const u32 mode_off[IMX6_PCIE_MAX_INSTANCES]; + const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES]; }; struct imx6_pcie { @@ -174,32 +177,25 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) { - unsigned int mask, val, mode; + const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; + unsigned int mask, val, mode, id; - if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) + if (drvdata->mode == DW_PCIE_EP_TYPE) mode = PCI_EXP_TYPE_ENDPOINT; else mode = PCI_EXP_TYPE_ROOT_PORT; - switch (imx6_pcie->drvdata->variant) { - case IMX8MQ: - case IMX8MQ_EP: - if (imx6_pcie->controller_id == 1) { - mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE; - val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, - mode); - } else { - mask = IMX6Q_GPR12_DEVICE_TYPE; - val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode); - } - break; - default: - mask = IMX6Q_GPR12_DEVICE_TYPE; - val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode); - break; - } + id = imx6_pcie->controller_id; + + /* If mode_mask[id] is zero, means each controller have its individual gpr */ + if (!drvdata->mode_mask[id]) + id = 0; + + mask = drvdata->mode_mask[id]; + /* FIELD_PREP mask have been constant */ + val = mode << (ffs(mask) - 1); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val); + regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val); } static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) @@ -1376,6 +1372,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .clk_names = {IMX6_CLKS_NO_PHYDRV}, .ltssm_off = IOMUXC_GPR12, .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX6SX] = { .variant = IMX6SX, @@ -1386,6 +1384,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .clk_names = {IMX6_CLKS_NO_PHYDRV, "pcie_inbound_axi"}, .ltssm_off = IOMUXC_GPR12, .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX6QP] = { .variant = IMX6QP, @@ -1397,6 +1397,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .clk_names = {IMX6_CLKS_NO_PHYDRV}, .ltssm_off = IOMUXC_GPR12, .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX7D] = { .variant = IMX7D, @@ -1405,6 +1407,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx7d-iomuxc-gpr", .clk_names = {IMX6_CLKS_NO_PHYDRV}, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX8MQ] = { .variant = IMX8MQ, @@ -1412,6 +1416,10 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = {IMX6_CLKS_NO_PHYDRV, "pcie_aux"}, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .mode_off[1] = IOMUXC_GPR12, + .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, }, [IMX8MM] = { .variant = IMX8MM, @@ -1420,6 +1428,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = {IMX6_CLKS_COMMON, "pcie_aux"}, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX8MP] = { .variant = IMX8MP, @@ -1428,6 +1438,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = {IMX6_CLKS_COMMON, "pcie_aux"}, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX8MQ_EP] = { .variant = IMX8MQ_EP, @@ -1436,6 +1448,10 @@ static const struct imx6_pcie_drvdata drvdata[] = { .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = {IMX6_CLKS_NO_PHYDRV, "pcie_aux"}, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .mode_off[1] = IOMUXC_GPR12, + .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, }, [IMX8MM_EP] = { .variant = IMX8MM_EP, @@ -1443,6 +1459,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = {IMX6_CLKS_COMMON, "pcie_aux"}, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX8MP_EP] = { .variant = IMX8MP_EP, @@ -1450,6 +1468,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = {IMX6_CLKS_COMMON, "pcie_aux"}, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, }; 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b=eI/m5MbzQmCzi02F9vgWQgG67Qo7KyVkQb2+cwwPICIEew9JKVcJZ4tZwc52FayplAL5LEckYMTP+fWthHt51TWB7LzHM/kZM+4qbfmkHe1brtQS1peGXG/WLtrN5nZdXYaid5leJSf+AIFFj70uVPkBQxZrQG9kZxnF+2elNYo= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by PAXPR04MB8174.eurprd04.prod.outlook.com (2603:10a6:102:1c4::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7091.36; Sun, 17 Dec 2023 05:13:11 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%7]) with mapi id 15.20.7091.034; Sun, 17 Dec 2023 05:13:11 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org Cc: Frank.li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v4 07/15] PCI: imx6: Simplify switch-case logic by involve init_phy callback Date: Sun, 17 Dec 2023 00:12:02 -0500 Message-Id: <20231217051210.754832-8-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231217051210.754832-1-Frank.Li@nxp.com> References: <20231217051210.754832-1-Frank.Li@nxp.com> X-ClientProxiedBy: BYAPR04CA0007.namprd04.prod.outlook.com (2603:10b6:a03:40::20) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|PAXPR04MB8174:EE_ X-MS-Office365-Filtering-Correlation-Id: efcce15b-430d-46a3-053d-08dbfebedd07 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Frank Li --- Notes: change from v1 to v4: - none drivers/pci/controller/dwc/pci-imx6.c | 135 ++++++++++++++------------ 1 file changed, 71 insertions(+), 64 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 49b98593326f9..02da650aa55ee 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -69,6 +69,9 @@ enum imx6_pcie_variants { #define IMX6_PCIE_MAX_CLKS 6 #define IMX6_PCIE_MAX_INSTANCES 2 + +struct imx6_pcie; + struct imx6_pcie_drvdata { enum imx6_pcie_variants variant; enum dw_pcie_device_mode mode; @@ -80,6 +83,7 @@ struct imx6_pcie_drvdata { const u32 ltssm_mask; const u32 mode_off[IMX6_PCIE_MAX_INSTANCES]; const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES]; + int (*init_phy)(struct imx6_pcie *pcie); }; struct imx6_pcie { @@ -323,76 +327,69 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) return 0; } -static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) +static int imx8mq_pcie_init_phy(struct imx6_pcie *imx6_pcie) { - switch (imx6_pcie->drvdata->variant) { - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - /* - * The PHY initialization had been done in the PHY - * driver, break here directly. - */ - break; - case IMX8MQ: - case IMX8MQ_EP: - /* - * TODO: Currently this code assumes external - * oscillator is being used - */ + /* + * TODO: Currently this code assumes external + * oscillator is being used + */ + regmap_update_bits(imx6_pcie->iomuxc_gpr, + imx6_pcie_grp_offset(imx6_pcie), + IMX8MQ_GPR_PCIE_REF_USE_PAD, + IMX8MQ_GPR_PCIE_REF_USE_PAD); + /* + * Regarding the datasheet, the PCIE_VPH is suggested + * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the + * VREG_BYPASS should be cleared to zero. + */ + if (imx6_pcie->vph && regulator_get_voltage(imx6_pcie->vph) > 3000000) regmap_update_bits(imx6_pcie->iomuxc_gpr, imx6_pcie_grp_offset(imx6_pcie), - IMX8MQ_GPR_PCIE_REF_USE_PAD, - IMX8MQ_GPR_PCIE_REF_USE_PAD); - /* - * Regarding the datasheet, the PCIE_VPH is suggested - * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the - * VREG_BYPASS should be cleared to zero. - */ - if (imx6_pcie->vph && - regulator_get_voltage(imx6_pcie->vph) > 3000000) - regmap_update_bits(imx6_pcie->iomuxc_gpr, - imx6_pcie_grp_offset(imx6_pcie), - IMX8MQ_GPR_PCIE_VREG_BYPASS, - 0); - break; - case IMX7D: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX8MQ_GPR_PCIE_VREG_BYPASS, + 0); + + return 0; +} + +static int imx7d_pcie_init_phy(struct imx6_pcie *imx6_pcie) +{ + return regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); - break; - case IMX6SX: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_RX_EQ_MASK, - IMX6SX_GPR12_PCIE_RX_EQ_2); - fallthrough; - default: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, +} + +static int imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) +{ + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); - /* configure constant input signal to the pcie ctrl and phy */ - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6Q_GPR12_LOS_LEVEL, 9 << 4); - - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, - IMX6Q_GPR8_TX_DEEMPH_GEN1, - imx6_pcie->tx_deemph_gen1 << 0); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, - IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, - imx6_pcie->tx_deemph_gen2_3p5db << 6); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, - IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, - imx6_pcie->tx_deemph_gen2_6db << 12); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, - IMX6Q_GPR8_TX_SWING_FULL, - imx6_pcie->tx_swing_full << 18); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, - IMX6Q_GPR8_TX_SWING_LOW, - imx6_pcie->tx_swing_low << 25); - break; - } + /* configure constant input signal to the pcie ctrl and phy */ + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX6Q_GPR12_LOS_LEVEL, 9 << 4); + + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + IMX6Q_GPR8_TX_DEEMPH_GEN1, + imx6_pcie->tx_deemph_gen1 << 0); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, + imx6_pcie->tx_deemph_gen2_3p5db << 6); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, + imx6_pcie->tx_deemph_gen2_6db << 12); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + IMX6Q_GPR8_TX_SWING_FULL, + imx6_pcie->tx_swing_full << 18); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + IMX6Q_GPR8_TX_SWING_LOW, + imx6_pcie->tx_swing_low << 25); + return 0; +} - imx6_pcie_configure_type(imx6_pcie); +static int imx6sx_pcie_init_phy(struct imx6_pcie *imx6_pcie) +{ + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX6SX_GPR12_PCIE_RX_EQ_MASK, IMX6SX_GPR12_PCIE_RX_EQ_2); + + return imx6_pcie_init_phy(imx6_pcie); } static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) @@ -903,7 +900,11 @@ static int imx6_pcie_host_init(struct dw_pcie_rp *pp) } imx6_pcie_assert_core_reset(imx6_pcie); - imx6_pcie_init_phy(imx6_pcie); + + if (imx6_pcie->drvdata->init_phy) + imx6_pcie->drvdata->init_phy(imx6_pcie); + + imx6_pcie_configure_type(imx6_pcie); ret = imx6_pcie_clk_enable(imx6_pcie); if (ret) { @@ -1374,6 +1375,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .init_phy = imx6_pcie_init_phy, }, [IMX6SX] = { .variant = IMX6SX, @@ -1386,6 +1388,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .init_phy = imx6sx_pcie_init_phy, }, [IMX6QP] = { .variant = IMX6QP, @@ -1399,6 +1402,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .init_phy = imx6_pcie_init_phy, }, [IMX7D] = { .variant = IMX7D, @@ -1409,6 +1413,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .clk_names = {IMX6_CLKS_NO_PHYDRV}, .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .init_phy = imx7d_pcie_init_phy, }, [IMX8MQ] = { .variant = IMX8MQ, @@ -1420,6 +1425,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .mode_off[1] = IOMUXC_GPR12, .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, + .init_phy = imx8mq_pcie_init_phy, }, [IMX8MM] = { .variant = IMX8MM, @@ -1452,6 +1458,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .mode_off[1] = IOMUXC_GPR12, .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, + .init_phy = imx8mq_pcie_init_phy, }, [IMX8MM_EP] = { .variant = IMX8MM_EP, From patchwork Sun Dec 17 05:12:03 2023 Content-Type: text/plain; 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So needn't irrationality check again for clock's miniItems and maxItems. Signed-off-by: Frank Li --- Notes: Change from v1 to v4 - new patch at v4 .../bindings/pci/fsl,imx6q-pcie-common.yaml | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml index d91b639ae7ae7..0c50487a3866d 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml @@ -150,22 +150,6 @@ allOf: - {} - const: pcie_phy - const: pcie_aux - - if: - properties: - compatible: - not: - contains: - enum: - - fsl,imx6sx-pcie - - fsl,imx8mq-pcie - - fsl,imx6sx-pcie-ep - - fsl,imx8mq-pcie-ep - then: - properties: - clocks: - maxItems: 3 - clock-names: - maxItems: 3 - if: properties: From patchwork Sun Dec 17 05:12:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13495751 Received: from EUR02-AM0-obe.outbound.protection.outlook.com (mail-am0eur02on2056.outbound.protection.outlook.com [40.107.247.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0F26DDB2; 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Needn't duplciate here. Signed-off-by: Frank Li Acked-by: Rob Herring --- Notes: Change from v1 to v4: - new patch at v4 .../devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 81bbb8728f0f9..f20d4f0e3cb6c 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -30,16 +30,6 @@ properties: - fsl,imx8mm-pcie - fsl,imx8mp-pcie - reg: - items: - - description: Data Bus Interface (DBI) registers. - - description: PCIe configuration space region. - - reg-names: - items: - - const: dbi - - const: config - clocks: minItems: 3 items: From patchwork Sun Dec 17 05:12:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13495752 Received: from EUR02-AM0-obe.outbound.protection.outlook.com (mail-am0eur02on2080.outbound.protection.outlook.com [40.107.247.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B95AEE568; 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Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by PAXPR04MB8174.eurprd04.prod.outlook.com (2603:10a6:102:1c4::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7091.36; Sun, 17 Dec 2023 05:13:26 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%7]) with mapi id 15.20.7091.034; Sun, 17 Dec 2023 05:13:26 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org Cc: Frank.li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v4 10/15] dt-bindings: imx6q-pcie: Add imx95 pcie compatible string Date: Sun, 17 Dec 2023 00:12:05 -0500 Message-Id: <20231217051210.754832-11-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231217051210.754832-1-Frank.Li@nxp.com> References: <20231217051210.754832-1-Frank.Li@nxp.com> X-ClientProxiedBy: BYAPR04CA0007.namprd04.prod.outlook.com (2603:10b6:a03:40::20) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|PAXPR04MB8174:EE_ X-MS-Office365-Filtering-Correlation-Id: 24da473f-d3cb-44dc-f956-08dbfebee61d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vMblpH04cnhG5hGNvi2ptnt5wjT0HNm3A20RMhV3DkLbUbssL3Vknw1cYz+sYESX7uPX1GZgMHr2CNXfAzi0SYLcCMoIR+Uo32E7qjxq2iN/tVYf9rKakisiJUT4fAHH/hMCg659DrrrLQ5RzmL3aEYpZEijSMisfxaejjVT7w71cCO3Hdw7KoBR1s/df8W8w+hQk+niieTMJEuTJJYVE2UOeLmOkl8yWMq4P/CNIaeCjiercsBLIyZ7iaE/q30SzfmE3WrIexnLRNdaPhKFE7aVh7hjx6iYe4NwjfsubbhuSgyVGlcvBgbTWFlRnMF/lnzQfy+LGk4XZpxk8Lp4Z2Ojt6Q3EdrzOpmFssHAK/NreREKNdJL6rKatXijSE9alidLDibOh3qE8U0j0kepSzROy9AYJVx1svdkFzxltxtG8AUQjRZqynjQPpSZuKzrSGMa6YoAWj/AmbALCR71tDvEvYnZq7buglGTX8baFq5deiSm/kn2M3QayShTLbHaD+hlhk6kdDWVCXtM4Y/Cr/4zXtKLE/l8aU+yo6BGl7uZcp1wL3Z3qCckL9eGeC2oaPGrz9epBdy5dCPEoqoPMFhpumRHskTQ+19tSrQB5Zy3YNKkZwVug5WS2hgA4eZUAAozYyUG4kkd7KK3mnKSibniPGVABB0Ivj4vR1eu51Amytehncrxnou8Y+a37zZvP2HS2eKwx/TBhaGZJApNnQCKQjL5t0hDXmrIUbP9+uoqROsYZjS7KEbQ622z/jiQTb1LIXSrW8YCVjWupTa2D56pPEy+jja/s7u+/XsHGTHLh0/J6nlWck6mQx8ZutJWeA2+QHrpo1wQhxcSxRPh1PPMzucOxy/yqNPnmV+hYFlp0XcDS0LX4HCuGl+J59NFgK2DCLVQ4CVJGO6t5nTxkrEdCq19Zu9tTcUIjFote0D9UOX+kgCHFFOhuX1p8lzx/0r8B0aiZDRP7AM1erlc9zQYAHo3wckhvKtg+JPE0ItM/HrbeugcB01hZYItWbjkWWgI6Fj8a7tVVs1x74ctDGMSVZQQG94MBzMm4EqlyEb1mCF03RP/B6N8OGjcZBYcvLLbJRiDN2YcwfV3dZCwdRaQg4ez96ODzilnE9N3lSBEuEZjwi4I0FX73hdnOit/iKO1Gx2Y/qy/+gqy9YiXm3PhQPDYSZlVryPaJal0QTzOHvziYkOsMJju7VuqQWk22CNNM8i7noWwvi0XCfCAqXWHZGfpP5mwqyymbhEYums/9tLQFFxEOP8h9K2JKuBStOU+IG61Pj3eSctWjNpGfjvcezJG7mKtJqClxHJWRtHGc1W3gcawD5g8qoMj1f81ABjWVYtuqHZjRBPKlarfshRzGPUOa+q/JxVl5BI4m+QW3LAhzMSWloVaZDUIjk6r9yvp2TUzTObU2t7vVwWDoFS6TWNhAdcNd07R2g0OE2krZPO+LCaguqN26HTzBtXygpLxBQWAOulC5O2FpaCtTV7MIb1vuo0C9YuoEypjzKC3CnVj8ptZu3hzX2UNWX3k/PCvDEzU0JitqZ2GlZNri4e0ZjN0YEv2OPxJnilrIDk= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 24da473f-d3cb-44dc-f956-08dbfebee61d X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Dec 2023 05:13:26.2668 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Vx5c//P9RZ3KBkbGQWEROuIE5H1SD48Wcf9mAadFJtIPCTYUc8UF++SDS1bQDxcaiSXCRrhe9ej9dOsoMXAhIw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8174 From: Richard Zhu Add i.MX95 PCIe "fsl,imx95-pcie" compatible string. Add "atu" and "app" to reg-names. Signed-off-by: Richard Zhu --- Notes: Change from v2 to v3 - Remove krzy's ACK tag - Add condition check for imx95, which required more reg-names then old platform, so need Krzy review again, Change from v1 to v2 - add Krzy's ACK tag .../bindings/pci/fsl,imx6q-pcie-common.yaml | 1 + .../bindings/pci/fsl,imx6q-pcie.yaml | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml index 0c50487a3866d..a8b34f58f8f49 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml @@ -207,6 +207,7 @@ allOf: - fsl,imx6sx-pcie - fsl,imx6q-pcie - fsl,imx6qp-pcie + - fsl,imx95-pcie - fsl,imx6sx-pcie-ep - fsl,imx6q-pcie-ep - fsl,imx6qp-pcie-ep diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index f20d4f0e3cb6c..8633c622bd178 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -29,6 +29,7 @@ properties: - fsl,imx8mq-pcie - fsl,imx8mm-pcie - fsl,imx8mp-pcie + - fsl,imx95-pcie clocks: minItems: 3 @@ -80,6 +81,22 @@ required: allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml# + - if: + properties: + compatible: + enum: + - fsl,imx95-pcie + then: + properties: + reg: + minItems: 4 + reg-names: + items: + - const: dbi + - const: atu + - const: app + - const: config + - if: properties: compatible: @@ -101,6 +118,7 @@ allOf: compatible: enum: - fsl,imx8mq-pcie + - fsl,imx95-pcie then: properties: clocks: From patchwork Sun Dec 17 05:12:06 2023 Content-Type: text/plain; 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Signed-off-by: Frank Li --- Notes: Change from v1 to v3 - none drivers/pci/controller/dwc/pci-imx6.c | 90 +++++++++++++++++++++++++-- 1 file changed, 85 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 02da650aa55ee..324c62cecfa5f 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -42,6 +42,25 @@ #define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12) #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8) +#define IMX95_PCIE_PHY_GEN_CTRL 0x0 +#define IMX95_PCIE_REF_USE_PAD BIT(17) + +#define IMX95_PCIE_PHY_MPLLA_CTRL 0x10 +#define IMX95_PCIE_PHY_MPLL_STATE BIT(30) + +#define IMX95_PCIE_SS_RW_REG_0 0xf0 +#define IMX95_PCIE_REF_CLKEN BIT(23) +#define IMX95_PCIE_PHY_CR_PARA_SEL BIT(9) + +#define IMX95_PE0_GEN_CTRL_1 0x1050 +#define IMX95_PCIE_DEVICE_TYPE GENMASK(3, 0) + +#define IMX95_PE0_GEN_CTRL_3 0x1058 +#define IMX95_PCIE_LTSSM_EN BIT(0) + +#define IMX95_PE0_PM_STS 0x1064 +#define IMX95_PCIE_PM_LINKST_IN_L2 BIT(14) + #define to_imx6_pcie(x) dev_get_drvdata((x)->dev) enum imx6_pcie_variants { @@ -52,6 +71,7 @@ enum imx6_pcie_variants { IMX8MQ, IMX8MM, IMX8MP, + IMX95, IMX8MQ_EP, IMX8MM_EP, IMX8MP_EP, @@ -63,6 +83,7 @@ enum imx6_pcie_variants { #define IMX6_PCIE_FLAG_HAS_PHY BIT(3) #define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4) #define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5) +#define IMX6_PCIE_FLAG_HAS_SERDES BIT(6) #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) @@ -179,6 +200,24 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; } +static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie) +{ + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX95_PCIE_SS_RW_REG_0, + IMX95_PCIE_PHY_CR_PARA_SEL, + IMX95_PCIE_PHY_CR_PARA_SEL); + + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX95_PCIE_PHY_GEN_CTRL, + IMX95_PCIE_REF_USE_PAD, 0); + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX95_PCIE_SS_RW_REG_0, + IMX95_PCIE_REF_CLKEN, + IMX95_PCIE_REF_CLKEN); + + return 0; +} + static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) { const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; @@ -579,6 +618,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); break; case IMX7D: + case IMX95: break; case IMX8MM: case IMX8MM_EP: @@ -696,10 +736,19 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) { struct dw_pcie *pci = imx6_pcie->pci; struct device *dev = pci->dev; + u32 val; reset_control_deassert(imx6_pcie->pciephy_reset); switch (imx6_pcie->drvdata->variant) { + case IMX95: + /* Polling the MPLL_STATE */ + if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr, + IMX95_PCIE_PHY_MPLLA_CTRL, val, + val & IMX95_PCIE_PHY_MPLL_STATE, + 10, 10000)) + dev_err(dev, "PCIe PLL lock timeout\n"); + break; case IMX7D: /* Workaround for ERR010728, failure of PCI-e PLL VCO to * oscillate, especially when cold. This turns off "Duty-cycle @@ -1278,12 +1327,32 @@ static int imx6_pcie_probe(struct platform_device *pdev) return PTR_ERR(imx6_pcie->turnoff_reset); } + if (imx6_pcie->drvdata->gpr) { /* Grab GPR config register range */ - imx6_pcie->iomuxc_gpr = - syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr); - if (IS_ERR(imx6_pcie->iomuxc_gpr)) { - dev_err(dev, "unable to find iomuxc registers\n"); - return PTR_ERR(imx6_pcie->iomuxc_gpr); + imx6_pcie->iomuxc_gpr = + syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr); + if (IS_ERR(imx6_pcie->iomuxc_gpr)) + return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr), + "unable to find iomuxc registers\n"); + } + + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_SERDES)) { + void __iomem *off = devm_platform_ioremap_resource_byname(pdev, "app"); + + if (IS_ERR(off)) + return dev_err_probe(dev, PTR_ERR(off), + "unable to find serdes registers\n"); + + static struct regmap_config regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + }; + + imx6_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, ®map_config); + if (IS_ERR(imx6_pcie->iomuxc_gpr)) + return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr), + "unable to find iomuxc registers\n"); } /* Grab PCIe PHY Tx Settings */ @@ -1447,6 +1516,16 @@ static const struct imx6_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, + [IMX95] = { + .variant = IMX95, + .flags = IMX6_PCIE_FLAG_HAS_SERDES, + .clk_names = {IMX6_CLKS_NO_PHYDRV, "pcie_aux"}, + .ltssm_off = IMX95_PE0_GEN_CTRL_3, + .ltssm_mask = IMX95_PCIE_LTSSM_EN, + .mode_off[0] = IMX95_PE0_GEN_CTRL_1, + .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, + .init_phy = imx95_pcie_init_phy, + }, [IMX8MQ_EP] = { .variant = IMX8MQ_EP, .flags = IMX6_PCIE_FLAG_HAS_PHY | @@ -1488,6 +1567,7 @@ static const struct of_device_id imx6_pcie_of_match[] = { { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], }, { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], }, { .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], }, + { .compatible = "fsl,imx95-pcie", .data = &drvdata[IMX95], }, { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, From patchwork Sun Dec 17 05:12:07 2023 Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: IJ3j7R+LR6ONaqVlybREoKWZAnkIzGsQT8Wcn+Fwuh5uuCfVnIEyD/W7ThRxZzxKSDQJ0mc2YIqSTZyD7JRyQHfCV7HSHIZBl4kRNtRyHd6c2F8fPNFIJbGPAA+ZXo0rTC3cuQ4jxj9KiIogufGnt6Vqa04S8KY0Jbl6cqMwG9Bt7WGCdnhSINVTTuS5j78fWFFvGQEfnMbvsqbMAl1Z10xqFW6thmFNuhmbioHeFy4bPPlHZO6r5Mvlrvh8AqgNvvI3XCV93DckRI3HD3SyZY7qASo86gqkHKdTUz8FIvs0aHImoJ1GjJtDsy4VDevkjGhtbhaHoRn+IPawL1UcO4ZOWsQYn2kOlUlP9VTx4Z69wrktBDNBz/YRADByK3adVxOv7Pi1Nm/C0421au++OPApNyy+c6ldGDDTy8PmG6oelKWLuSWyVx+fiNWQY5tHKDgmVDwuWQoYjQY+nX40UNn7U5ZrrYuiy0+fx95Ik6GaDb4H5DAPLma2rkT+52XQ4J6Q30UjuN+hmEmnObfck+DV5Bd92Qpe0pO5nfsASUl7HElX58Ho/yp8dAjRVdQhSx4LVlguZUy92CrdJ6RpKywjxN0v978gvxo3qrt2NXUg3zMlvERiwN09ADp+pJwQkkyt6CKL0BAtVXcMFxcFtqtwBNsUSOe//oGulMgT6HUz0ryesRbOOANYq21Aa5gSC2qpJya7yRb676c7mmgIOsFjxuyEWcNUqWuWHfuWU3bxhLSBFUxeCAGeLeFYJ6OG/sWz+FcR+m6jUPDfaOm9UMWMLD65ESfMcNb5YUK3gMkOVR7BuqmyG3YOZSvddFaxm1TiHrme0ZFA2dT3pDf7abICLucZRMQJ2odfQBemgt46q3fPCrB4CUdoU0RnVY5PuGQi+BpG7VCjwC7RCqxXE0mcBUW74tdV+ebi0I2jeInvYUzUpKpVQPln994yk99B65u6E4WtSIxSLxa7UYh50ibG047C7QuIZmVlY5HKqNVunTa9BjUwkkw47uBfwB3joVVSU7mhCaShiZ+Iq4s+quOfn7dROeqs2OEJW1f2JNeqOtu4MZW+hA4UCFmc9DfnLTcGGj/SkEAKjcnYdeMdL0sDBbs2U0T0LEn+H5vylMjf/8sXmdzzMZZTIS8qqPs4DGypFDnellpodpcCPo/+0nzMue9ZWnr0YC9QeKD95H2DujhnQu88XwMx3haibWxRybuJ3rur/uSttTfQWbNtg8bbaaMPfm1L/5dgFGkAsjtizgXuQ0N0WLcKRMA62WjvB/60i4px56B1x5cMP4qvYE5WhMFtDr9u3HdW9yzM34goPxW7nRlTZOe/0KHz62Tkzw90rmQSipKF22ltJ8+a+HkI2NJXj+OwQXIC65Sq/RtRV5+rwYBwGZLS+lRMLYVJsMlEV2gH0QSJxCn4IhOdslelctB5PLiYrnYoQI3DEz1Pn0wBnBtpjLm0BXZSwogD2+lkRbh2Muuuuh65vP8IKllVvm/oSRmuIczeK1w/xOQ0NpsUsLZN2bWA1Kxdax4++Z192eTAAh/sn+/q6M3UVcaQc6CCkDZgqvddL9h3C6c= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9e91e04a-d210-4959-9ced-08dbfebeec18 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Dec 2023 05:13:36.4830 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: wKsIdPfVxVdKMfq0RAGXISRzTrUYnqOA2rG4UiHjd6t4jCI5Mmp72kQMmDZJ7CUt6/v9R+dQUbxcc1uOdpDv6w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8174 The common dw_pcie_ep_init() already do the same thing. Needn't platform driver do it again. Signed-off-by: Frank Li --- Notes: Change from v1 to v3 - new patches drivers/pci/controller/dwc/pci-imx6.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 324c62cecfa5f..54b90f8576915 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1080,7 +1080,6 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, int ret; unsigned int pcie_dbi2_offset; struct dw_pcie_ep *ep; - struct resource *res; struct dw_pcie *pci = imx6_pcie->pci; struct dw_pcie_rp *pp = &pci->pp; struct device *dev = pci->dev; @@ -1099,14 +1098,8 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, pcie_dbi2_offset = SZ_4K; break; } - pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); - if (!res) - return -EINVAL; - ep->phys_base = res->start; - ep->addr_size = resource_size(res); - ep->page_size = SZ_64K; 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Sun, 17 Dec 2023 05:13:41 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org Cc: Frank.li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v4 13/15] PCI: imx6: Add epc_features in imx6_pcie_drvdata Date: Sun, 17 Dec 2023 00:12:08 -0500 Message-Id: <20231217051210.754832-14-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231217051210.754832-1-Frank.Li@nxp.com> References: <20231217051210.754832-1-Frank.Li@nxp.com> X-ClientProxiedBy: BYAPR04CA0007.namprd04.prod.outlook.com (2603:10b6:a03:40::20) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|PAXPR04MB8174:EE_ X-MS-Office365-Filtering-Correlation-Id: ccbbbbdb-b094-4bc0-6409-08dbfebeef2b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Gue2lDNCKXWiUkuBp2VhsXyqs/jmijfFrG8FhX3lD5irm+y4jTwfyT1rUmy2vH/uEuxjkB8PNn/gre+n9yr4Q//7e+cRJ2R943VRqD7CQEfmT23e60ylP8oSleqTn/UiwBdYfNBfGRX6Kyj7+UskFluVLVKeyXoECsuNUI3bcTEs1yAcZl1kpH2+f/pCvrtdzMBs6X+5NaI1jaSmolJwaOMFe0qUVfp4++PYqM07ugKJfyNkfZMa8d/h668qmSck3taBOXDkIqsw92y8m4MIeriQG21uMwkBFk3f8ZUU68UbO+7No0h9xeTGG/82iFRaWEgC1O0rioqVLiRGm/kUi/m12Nwv5inFSI+DH8Bk7rXR82irP2ymzy34hJKf+RzA0arXp2/ZeurJ8wyxJJjrpR+fMIacAA3qnJpiC1kUfEIsLo/V5Yh/WKjrbo3K8a2C7m8AHM0B6IW7wG833cVf1kgBMs2f+SCHfstGo0d/aNIDz2I/T4QTuCSLf6tJ3QYkYj/qEzBxxIAI9VBHolc1gEAnIncXTdp+9LlyH3eT6b+CBUv2Cs0fV8foYitiCfCNfm5DK1RJSoYot4W8oQlwOEvNbfab+yAXcqFC+IlqLCPNEOQvDPa1E83esHnhi6SswLFe3JxUGOxzNKA4PnWzMUBpiS4flw2uSXQII8Y6lP9BDWj6Bf5iI+ZSXf5OzrwWvpZDLlJ5Ik/DkJEwjxSZa3iARB6qHbGlA8hn2Lyol4KToso/OcHHqlgwhXuEphjF0D1L/hDxTNfRlH7fwyEyZwKzKHddJvnUsPtOzRlYLNHo0u1Rmzvqcz80y0koIx9KqEVvtQD1AbjyNVMZkADA08vzw3fIu8+AIbcFSVg8LX5pTMYanK/ECSvT1c9wfLVEPkV18ftLaLJ3YubGDwFx1TwtmEDkR9gonKrSZxBjL8dRn/kG6yokm1nCPoll4JK5McuijSDRM/yL0g1rOcKp2flI7dWBAt0ckW98xAf45xyQC0nVB+ONPGoEPKxfNzDSyMeE4CXjNsqyu+L1gnL4TGhFsf0ZwZQJno4fw3/rWe4yvlcM/Fst/uBptALyEvIK6YaAVeNWiKfoNaVcaOtCsF/Jig+V4Tzm7FUu5FjiBtZGas/61zuRENp46nZKTw6F8QBWscnNqta4z7LR0O89U2bbjqKJ3+dfENPvELIvD3KSldOEA8hYeYMJV404883SY91JtIuc5Fo+iRO8ugrQzruBM7nAsIYtSRf/YXPpxntxQvnUnAMuaJlwRow7yDb/9zsiIfVQBYfcbgJ+eyirYX618s3jbTCNEeetSbJyFUMWVOtdyXvTiHSppySLEu9p4rmG9wVgG/xW7lFZpkipPNFgGwUXoiglSlUy5eQoZoeR9n+6GS72+Z6wZA16x0R6xqYHQCJALX7QOnVnFsNvl5SpiNM/bt+3+dnZwAmmI9f0p2maluzimAbLD+fmGu9AMH9Kma3XMj/UAkVa5oTieqAGlfVF3vqAVLYcBinNR1IkJbH9epiV9LaF0cEmeaUbo+7+/qC1vdlo+lTrvQylbIEaaNxXkJl4KfdbkY3MJss= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: ccbbbbdb-b094-4bc0-6409-08dbfebeef2b X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Dec 2023 05:13:41.4508 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: OWUGO1xfTXJxji05gIvgf3bqmltgf83j3qV7d9XcRJwxbfg78LPg9bpQfmtL6SR7qwAxkNDczVMiOFOHpB4pkQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8174 The i.MX EP exhibits variations in epc_features among different EP configurations. This introduces the addition of epc_features in imx6_pcie_drvdata to accommodate these differences. It's important to note that there are no functional changes in this commit; instead, it lays the groundwork for supporting i.MX95 EP functions. Signed-off-by: Frank Li --- Notes: Change from v1 to v3 - new patch at v3 drivers/pci/controller/dwc/pci-imx6.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 54b90f8576915..8f7b1533e2869 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -104,6 +104,7 @@ struct imx6_pcie_drvdata { const u32 ltssm_mask; const u32 mode_off[IMX6_PCIE_MAX_INSTANCES]; const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES]; + const struct pci_epc_features *epc_features; int (*init_phy)(struct imx6_pcie *pcie); }; @@ -1065,7 +1066,10 @@ static const struct pci_epc_features imx8m_pcie_epc_features = { static const struct pci_epc_features* imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) { - return &imx8m_pcie_epc_features; + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); + + return imx6_pcie->drvdata->epc_features; } static const struct dw_pcie_ep_ops pcie_ep_ops = { @@ -1530,6 +1534,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .mode_off[1] = IOMUXC_GPR12, .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, + .epc_features = &imx8m_pcie_epc_features, .init_phy = imx8mq_pcie_init_phy, }, [IMX8MM_EP] = { @@ -1540,6 +1545,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .clk_names = {IMX6_CLKS_COMMON, "pcie_aux"}, .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .epc_features = &imx8m_pcie_epc_features, }, [IMX8MP_EP] = { .variant = IMX8MP_EP, @@ -1549,6 +1555,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .clk_names = {IMX6_CLKS_COMMON, "pcie_aux"}, .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .epc_features = &imx8m_pcie_epc_features, }, }; From patchwork Sun Dec 17 05:12:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13495756 Received: from EUR02-AM0-obe.outbound.protection.outlook.com (mail-am0eur02on2088.outbound.protection.outlook.com [40.107.247.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D227A1097E; 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Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by PAXPR04MB8174.eurprd04.prod.outlook.com (2603:10a6:102:1c4::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7091.36; Sun, 17 Dec 2023 05:13:46 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%7]) with mapi id 15.20.7091.034; Sun, 17 Dec 2023 05:13:46 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org Cc: Frank.li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v4 14/15] dt-bindings: imx6q-pcie: Add iMX95 pcie endpoint compatible string Date: Sun, 17 Dec 2023 00:12:09 -0500 Message-Id: <20231217051210.754832-15-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231217051210.754832-1-Frank.Li@nxp.com> References: <20231217051210.754832-1-Frank.Li@nxp.com> X-ClientProxiedBy: BYAPR04CA0007.namprd04.prod.outlook.com (2603:10b6:a03:40::20) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|PAXPR04MB8174:EE_ X-MS-Office365-Filtering-Correlation-Id: 25ebefff-68dd-4507-538a-08dbfebef226 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Add reg-name: "atu", "dbi2", "dma" and "serdes". Signed-off-by: Frank Li --- Notes: Change from v1 to v3 - new patches at v3 .../bindings/pci/fsl,imx6q-pcie-ep.yaml | 52 ++++++++++++++++--- 1 file changed, 44 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml index ee155ed5f1811..be9ea77ce8548 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml @@ -22,14 +22,7 @@ properties: - fsl,imx8mm-pcie-ep - fsl,imx8mq-pcie-ep - fsl,imx8mp-pcie-ep - - reg: - minItems: 2 - - reg-names: - items: - - const: dbi - - const: addr_space + - fsl,imx95-pcie-ep clocks: minItems: 3 @@ -62,11 +55,46 @@ required: allOf: - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml# + - if: + properties: + compatible: + enum: + - fsl,imx8mm-pcie-ep + - fsl,imx8mq-pcie-ep + - fsl,imx8mp-pcie-ep + then: + properties: + reg: + minItems: 2 + reg-names: + items: + - const: dbi + - const: addr_space + + - if: + properties: + compatible: + enum: + - fsl,imx95-pcie-ep + then: + properties: + reg: + minItems: 6 + reg-names: + items: + - const: dbi + - const: atu + - const: dbi2 + - const: app + - const: dma + - const: addr_space + - if: properties: compatible: enum: - fsl,imx8mq-pcie-ep + - fsl,imx95-pcie-ep then: properties: clocks: @@ -87,6 +115,14 @@ allOf: - const: pcie_bus - const: pcie_aux + - if: + properties: + compatible: + enum: + - fsl,imx95-pcie-ep + then: + properties: + linux,pci-domain: true unevaluatedProperties: false From patchwork Sun Dec 17 05:12:10 2023 Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: PmuLbqTbO/tLw5ild+I67jAo6lcTVw6Lj2EKbK5jT1bJtJXtIQ7blGHeMl9BwCC1NabzeXQKieCCQ/TCCxzvSeL0o5ZOsTjtv2vWImE25IIU8IizOTdnJkFDoQVBHvpuTIsqhwSX59H6g1A1/WekdPP8P1YIJSxgrOSPvKKSgC3X8EldBE/w4+17OMnFVWQGXUdXSsJShhPnubWL1vEIqtgwg+IDEfrO+x8kG3Ln5v4pcAmBb3KBIjCV1QBn4tlprgIlIM+IrGLD32nyZW2O1PEKtMGObGa0G4wONZk1jb3WYylV8AY0nHwnQJnRbFuzSfQAu1jzcwpxOBAviFEy+0d/+XVVa0rW7i4IbVMvQprch/UYU8JRoTlnRC/e3+mNYuYYyX3Ahm2rPlQOmJJJZ7Bt4biwbCUrZuysI5iLVWYUsdNiVrioWRFqhNnwsDmKBh4FCxuer/yEsCSE5uuZ06mNlBwBP3ssvW89CWNRD39gP8BsHepy4jw7Y1RJUPeNhEPz6nuKr03JqvZtp4jwucJeOgVoW8CSKV0yxZb0lJzKtNWGCSIBdem4aJB97i3l3k1OLed1V7ZXGqf46KjdlsABgD4Zae+y9q4E7VfeKRVoBxBH9fyyPqgKZP9yA5paY8zI117VajDqFh1diQdQZ3DxZbpZhOsW6Q6lNxHk8z5WUq0Kjxvj9IympIypC5HZBTxRHhs100qYOe7s52OHHLumraNEPb/0/4O6DtXnJIbJplcKiDiTht9bHXLd/oki/LC3S3JzZAMzEvwlASdxgsA0VDj+Ras3flJmA2QF+4e77jDDCwN7eJwWqbrGwfMKyfGc29uptu6IPuADZgCd6v7EA1VoUpA0bW3T8ZXXtZg0MbibRl/VHTbWbne5L+0lXrJdhpGPYopahFObeZY2pNaMzS16ri0uEtfuJAnsiIVz40Ve+SyAYEweTAZtuWY52o3WVw8GKTHJ/QaD7M5wcFoK1/dWWTyylJNUIZ5qY4EVI+sifvG2q4XWuV1IkDR9MS9/hr5na+uGfcoBWJchCR96F046KI+4ZEAB3ZU1737A+VkLH3bcfwRQPXGSvqKN9KYi+Qwy8G4PbLVpxO5uHG1ngtM6ThnD1EXLdOKJEFMbbGtUKKOYAdFLhOispBxWPGhm/Cu+RVe4GDnPXHw/IwsCCgQpq2PnFqx1+3+WeQHTbKFqyKM5j7kf/qfuu6WuCFEuYAdjm4kO2VxJy9PfIzQlozrYCheakkm6gYbpg23OppzKzUjZj2VCR6urLCXYKD7L6k4Sr8EtiAVhl+kr7UGhKp8FxwL4x0Sp1bB4WtVNZynaz25IYglL6NvC+wHmxRVf5KeffJIbLKTojOCsaSL7xPWGdrn4oSj/iQWiqr9ReKdtZsLebPQGeihnOasJNt3bY36yTMHFL9ShOwDGlAYbpP2cjK0AEah61PIvshOrxfW9YQj6qM6aV5IpT/ZoFv33Wk9SBHOS8VVtkYDHdIDqCz2NxTErmbboeDxCcjA4z9XW3GkY56cqPKVsRBkEEhTw2qUhz/17JM2Ejxyjont2Q6h80J/jcWER0ysFJk4= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6157824a-03da-421c-e0c0-08dbfebef51e X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Dec 2023 05:13:51.4345 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: qX6K7oHs0JcuTweJhAKs5f1BVotjeRJObmZD2DEqE80dQk4hsbGUJtZPDth+AkWV3+JX49DRUQ1n1KDmgysnRg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR04MB8415 Add iMX95 EP function support and add 64bit address support. Internal bus bridge for PCI support 64bit dma address in iMX95. So set call dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)). Signed-off-by: Frank Li --- Notes: Change from v3 to v4 - change align to 4k for imx95 Change from v1 to v3 - new patches at v3 drivers/pci/controller/dwc/pci-imx6.c | 45 +++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 8f7b1533e2869..5518c1b0d4fc1 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -75,6 +75,7 @@ enum imx6_pcie_variants { IMX8MQ_EP, IMX8MM_EP, IMX8MP_EP, + IMX95_EP, }; #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) @@ -84,6 +85,7 @@ enum imx6_pcie_variants { #define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4) #define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5) #define IMX6_PCIE_FLAG_HAS_SERDES BIT(6) +#define IMX6_PCIE_FLAG_SUPPORT_64BIT BIT(7) #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) @@ -620,6 +622,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) break; case IMX7D: case IMX95: + case IMX95_EP: break; case IMX8MM: case IMX8MM_EP: @@ -1063,6 +1066,23 @@ static const struct pci_epc_features imx8m_pcie_epc_features = { .align = SZ_64K, }; +/* + * BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme + * ================================================================================================ + * BAR0 | Enable | 64-bit | 1 MB | Programmable Size + * BAR1 | Disable | 32-bit | 64 KB | Fixed Size + * | (BAR0 is 64-bit) | if BAR0 is 32-bit | | As Bar0 is 64bit + * BAR2 | Enable | 32-bit | 1 MB | Programmable Size + * BAR3 | Enable | 32-bit | 64 KB | Programmable Size + * BAR4 | Enable | 32-bit | 1M | Programmable Size + * BAR5 | Enable | 32-bit | 64 KB | Programmable Size + */ +static const struct pci_epc_features imx95_pcie_epc_features = { + .msi_capable = true, + .bar_fixed_size[1] = SZ_64K, + .align = SZ_4K, +}; + static const struct pci_epc_features* imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) { @@ -1105,6 +1125,14 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset; + /* + * db2 information should fetch from dtb file. dw_pcie_ep_init() can get dbi_base2 from + * "dbi2" if pci->dbi_base2 is NULL. All code related pcie_dbi2_offset should be removed + * after all dts added "dbi2" reg. + */ + if (imx6_pcie->drvdata->variant == IMX95_EP) + pci->dbi_base2 = NULL; + ret = dw_pcie_ep_init(ep); if (ret) { dev_err(dev, "failed to initialize endpoint\n"); @@ -1352,6 +1380,9 @@ static int imx6_pcie_probe(struct platform_device *pdev) "unable to find iomuxc registers\n"); } + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); + /* Grab PCIe PHY Tx Settings */ if (of_property_read_u32(node, "fsl,tx-deemph-gen1", &imx6_pcie->tx_deemph_gen1)) @@ -1557,6 +1588,19 @@ static const struct imx6_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .epc_features = &imx8m_pcie_epc_features, }, + [IMX95_EP] = { + .variant = IMX95_EP, + .flags = IMX6_PCIE_FLAG_HAS_SERDES | + IMX6_PCIE_FLAG_SUPPORT_64BIT, + .clk_names = {IMX6_CLKS_NO_PHYDRV, "pcie_aux"}, + .ltssm_off = IMX95_PE0_GEN_CTRL_3, + .ltssm_mask = IMX95_PCIE_LTSSM_EN, + .mode_off[0] = IMX95_PE0_GEN_CTRL_1, + .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, + .init_phy = imx95_pcie_init_phy, + .epc_features = &imx95_pcie_epc_features, + .mode = DW_PCIE_EP_TYPE, + }, }; static const struct of_device_id imx6_pcie_of_match[] = { @@ -1571,6 +1615,7 @@ static const struct of_device_id imx6_pcie_of_match[] = { { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, + { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], }, {}, };