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bh=o80xoaBmG8h2A9FAJS+hScUpb9r7tnLzxTs/uXia+bM=; b=nur+1iy5MOOdFGQs8aEbhlTUfyz3/plUmfgqQ6QUqqGIOqnjuZyd9xczLAdM1hnKKoIZ2O/HZBYrKcIeToyR54+UUELi6ts3rLB1RoNERpQfxxJhWWSK0IyTFwOfgQGt5pA5HMxmQDGeFuVUPCL9JWCAkqP5FP1pvyaslS9WT2U= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Huang Rui To: Akihiko Odaki , =?utf-8?q?Marc-Andr=C3=A9_Lure?= =?utf-8?q?au?= , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Gerd Hoffmann , "Michael S . Tsirkin" , "Stefano Stabellini" , Anthony PERARD , Antonio Caggiano , "Dr . David Alan Gilbert" , Robert Beckett , Dmitry Osipenko , Gert Wollny , =?utf-8?q?Alex_Benn=C3=A9e?= , CC: , Gurchetan Singh , , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , Stefano Stabellini , =?utf-8?q?Christian_K?= =?utf-8?q?=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Huang Rui Subject: [PATCH v6 01/11] linux-headers: Update to kernel headers to add venus capset Date: Tue, 19 Dec 2023 15:53:10 +0800 Message-ID: <20231219075320.165227-2-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231219075320.165227-1-ray.huang@amd.com> References: <20231219075320.165227-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FB:EE_|DM6PR12MB4124:EE_ X-MS-Office365-Filtering-Correlation-Id: c04be24b-ffbd-412e-7046-08dc0067ae63 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lPAv71mITwNdRFsgYvx1taLgdviAJdQxigc2aP/N/dB/Vq+19jLqfe5pJqNJA+4LWcNsHEpHs96xowkUi6hbxgITUwsBf+uxMbr0W4XNHXdbb7iB0OgD2zdj/C9Fxlx2frdkCS1rUDWhCkYII2RmFJCPW+Y+CSPwAF5kcVIoCfPWPg1Uw67/2sTu4EyGmVcMGKXviUS4APov20dKENmfBIidgaz7FXee2LV5NKa48PoEKk6k79EwWWjt5ubcjfnt9ZmBUT6CmCM4hQmZwWt7PAQIjbXYtTvF0nMaZK3/a2JZf7H3Vi7y2x7btbacS3nA5R3h2auvlqNJfShBXMeP3+UqczJJ2cNK9Mx2l/Kj9FttOFy0WH8JgI2igLkvUFXskoDdtKp5tuCIwMqJqAv4+QCUu+4wvOrzcxOdFUQdg25j35/UAwwa3STFanReMSJkCV11vaT3RSXCcOZoYLSbeAMu2PoyqQAdPfPlruoOEsGvU+Gs/HJfoVP5K+q7NNSAupkh7/Ph6OWqc+aRKRNdQv7wYNHRTqqUMevZyRP9Rj/3kRv1HLu+hd33fIi3WvZ6RpHniGHzAPj3TTMN1OhqXl5xonc4/nU2sAI8e/lInSFxlhv/poir1PU5GBbc8fOnH9ArtRtRhpqYEthZiFw1bN8sc1w3XWjgdGrggdopNN8AJCjjQVL0uZVJVJEBjmAcDFVpSjiwjE8sOBkQcOGnR6tpuA/b6uqBRZRj1veDmdqgdg5Mc4gs7idGHZX+FzroGyW6Qvm6Df1D3/Z8DR45ww== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(136003)(376002)(39860400002)(346002)(230922051799003)(451199024)(1800799012)(64100799003)(82310400011)(186009)(46966006)(36840700001)(40470700004)(26005)(336012)(83380400001)(426003)(7696005)(47076005)(2616005)(36860700001)(1076003)(478600001)(4744005)(5660300002)(4326008)(16526019)(41300700001)(15650500001)(7416002)(6666004)(2906002)(8676002)(110136005)(966005)(316002)(40460700003)(8936002)(54906003)(70586007)(70206006)(86362001)(36756003)(81166007)(356005)(82740400003)(40480700001)(921008)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2023 07:54:08.5432 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c04be24b-ffbd-412e-7046-08dc0067ae63 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FB.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4124 Sync up kernel headers to update venus macro till they are merged into mainline. Signed-off-by: Huang Rui --- Changes in v6: - Venus capset is applied in kernel, so update it in qemu for future use. https://lore.kernel.org/lkml/b79dcf75-c9e8-490e-644f-3b97d95f7397@collabora.com/ https://cgit.freedesktop.org/drm-misc/commit/?id=216d86b9a430f3280e5b631c51e6fd1a7774cfa0 include/standard-headers/linux/virtio_gpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/standard-headers/linux/virtio_gpu.h b/include/standard-headers/linux/virtio_gpu.h index 2da48d3d4c..2db643ed8f 100644 --- a/include/standard-headers/linux/virtio_gpu.h +++ b/include/standard-headers/linux/virtio_gpu.h @@ -309,6 +309,8 @@ struct virtio_gpu_cmd_submit { #define VIRTIO_GPU_CAPSET_VIRGL 1 #define VIRTIO_GPU_CAPSET_VIRGL2 2 +/* 3 is reserved for gfxstream */ +#define VIRTIO_GPU_CAPSET_VENUS 4 /* VIRTIO_GPU_CMD_GET_CAPSET_INFO */ struct virtio_gpu_get_capset_info { From patchwork Tue Dec 19 07:53:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 13497948 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EE5D2C46CA2 for ; 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David Alan Gilbert" , Robert Beckett , Dmitry Osipenko , Gert Wollny , =?utf-8?q?Alex_Benn=C3=A9e?= , CC: , Gurchetan Singh , , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , Stefano Stabellini , =?utf-8?q?Christian_K?= =?utf-8?q?=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Huang Rui , Antonio Caggiano Subject: [PATCH v6 02/11] virtio-gpu: Configure new feature flag context_create_with_flags for virglrenderer Date: Tue, 19 Dec 2023 15:53:11 +0800 Message-ID: <20231219075320.165227-3-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231219075320.165227-1-ray.huang@amd.com> References: <20231219075320.165227-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FC:EE_|DM4PR12MB5246:EE_ X-MS-Office365-Filtering-Correlation-Id: 4bd061f2-5763-46b9-9e98-08dc0067b2da X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hEi40K5Yj/cvEb/bX2mxWH5rzyndN5KtrQlgR+KcM7ih2hhb0a3c5rIPkUWGT3S7Lod6I0ERn+f/WjXDDfq3VWU9HHPD2lPx3RzC8ACM1pLR+JVjNl3wxV8oRS2DQNLraKZpniznBHhw+/D9nQ47q90DEADVWs5RUu0vHtIBMfsx7gtNChnoP0DyOr3M2UkqjZ5td6nneqdXwZU7LCYeh+1HMekUdQO9LAS/2a47rMfQWKD/TADofAgXwfEVoQwtvTFOYk1lqkiNN+6Qbe1ezlFgyrEph4nWyaJfUPoZJ4T4G6xNMZMLqRjpiJ3hPROHZKNlb8W0gSOKKBg2Pd+SRAIg8WaCOkNtCHVPuGiq8ajMApHP/5t/mGhBGPKpV68GjOoj5y4uWHzu9B88uQ8aY0jFIZOaQcd38/KPrqKiDzELpbM0kZCbfuRUuEfol8JR29Ei5Ynf/fuuFf71f0DC3n3aOB86dN8Q1Uh7QeQosVDOfb3lC8vtjnTjdPoSPniM4ce9VvV5kEytT7p23egfEIICxklf2jvfyCxDqegNdOxqBfdvwKbQEOZ+CT+gkSRMG9AdpQJRJDUn+ORiF3TftFocMIdSJUB6I+egQp1+Kb4NYf2M9/WhAMMuqotAeAPxaE8vdgQRXbOcLs3ky+3QgKxy9Zq6K4HC62ELOybwXwP1pSHcfZAg6CopGjqj+1Qj5TeniPc4ewMa83foJ/1r0hU8ILwMH3JU/3+f9EmZ2OXARdwMUgNN0/Cfbmm9XshRSvYvJuamsJB5QJ/iULegMeFmBdmM0MGTn48pdbzJ3Zo= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(346002)(396003)(376002)(136003)(230922051799003)(82310400011)(64100799003)(186009)(451199024)(1800799012)(36840700001)(46966006)(40470700004)(40480700001)(86362001)(81166007)(356005)(36756003)(82740400003)(40460700003)(7696005)(6666004)(478600001)(41300700001)(70586007)(54906003)(70206006)(921008)(16526019)(336012)(26005)(1076003)(2616005)(47076005)(426003)(4744005)(2906002)(7416002)(110136005)(36860700001)(5660300002)(316002)(8936002)(8676002)(4326008)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2023 07:54:16.0664 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4bd061f2-5763-46b9-9e98-08dc0067b2da X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FC.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5246 Configure a new feature flag (context_create_with_flags) for virglrenderer. Originally-by: Antonio Caggiano Signed-off-by: Huang Rui Reviewed-by: Alex Bennée --- Changes in v6: - Move macros configurations under virgl.found() and rename HAVE_VIRGL_CONTEXT_CREATE_WITH_FLAGS. meson.build | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/meson.build b/meson.build index ec01f8b138..ea52ef1b9c 100644 --- a/meson.build +++ b/meson.build @@ -1050,6 +1050,10 @@ if not get_option('virglrenderer').auto() or have_system or have_vhost_user_gpu cc.has_member('struct virgl_renderer_resource_info_ext', 'd3d_tex2d', prefix: '#include ', dependencies: virgl)) + config_host_data.set('HAVE_VIRGL_CONTEXT_CREATE_WITH_FLAGS', + cc.has_function('virgl_renderer_context_create_with_flags', + prefix: '#include ', + dependencies: virgl)) endif endif rutabaga = not_found From patchwork Tue Dec 19 07:53:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 13497950 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 82913C41535 for ; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Huang Rui To: Akihiko Odaki , =?utf-8?q?Marc-Andr=C3=A9_Lure?= =?utf-8?q?au?= , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Gerd Hoffmann , "Michael S . Tsirkin" , "Stefano Stabellini" , Anthony PERARD , Antonio Caggiano , "Dr . David Alan Gilbert" , Robert Beckett , Dmitry Osipenko , Gert Wollny , =?utf-8?q?Alex_Benn=C3=A9e?= , CC: , Gurchetan Singh , , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , Stefano Stabellini , =?utf-8?q?Christian_K?= =?utf-8?q?=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Huang Rui , Antonio Caggiano Subject: [PATCH v6 03/11] virtio-gpu: Support context init feature with virglrenderer Date: Tue, 19 Dec 2023 15:53:12 +0800 Message-ID: <20231219075320.165227-4-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231219075320.165227-1-ray.huang@amd.com> References: <20231219075320.165227-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FB:EE_|CH3PR12MB7716:EE_ X-MS-Office365-Filtering-Correlation-Id: 1bc82c44-91f7-4633-1956-08dc0067bc7d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /cm2gXc1/JNXdY36bfebsljXl4vJij1lTwjsnsIvZV8LKN0BMKNpfbG+fB65x0qK4PsV114l5DID2nEbVeTh9xMB9EUeKYxFtxFuTi/qk0pfCnVnr5IlsqAR/oE/58yDIezonCGqLuC7y9cGy24/LlPyCthh6oNBMZNUyKOD6csHJr6ih+ga7oVKiIGuYA4pNfaLeu+mbU/I9IFiA2vI0CqeJfm33URdNEK8+/LVOWTHoZ7NKYdPIpdRbx9tjhVZKbVIT3l7cYLzDXkLg409Vgy8Xh+WLOXJD4KlgsOwlp0kuJ6ItyPSY/OcB+u9BzWkxmusiHWagAYa+xuNSgZ/mbpRtwUA/fWQuwIyTfnz/toGUv29fgvbQZREg0WqG4A1kgwYxKFfEZeVu9ll0KiGgJC8f6pJiztVvbscyZRNNYPZlCBCM9HmaB9fdGHpn5AIIL+ZH4EboQtXRtYZ6az0vLq7ceU7YZB2oXItJFuiobx9jkAqYUrq4mhnhRUy6bUO+U+9uwF9bZshe2cW/89DQFyKqeQkTTran6zX0ZRvMQw/o/xomJPhlSRqnminqo7rRWGHgUUWTFeofLaWcQbMdLt9oGoN7BBtrSLM/c71PK/mthNo7QP2yf2Ri48IgQ5SgxXemYYMhNhHB7fLZelegDWoDol7lNCHcyolK/fTfhmF1QRcsxiOfPvtl7S9R/kxol5++vgX4/ynBNFTE+Sn0quuc71IqjaBhz63hKvlfyg1XXRX9FeXpm2qHgS43ooCcsKXVaeEMq1ZgRUk70NoctUdFKn7XbfRINUhAVDSliM= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(346002)(396003)(376002)(136003)(230922051799003)(82310400011)(64100799003)(186009)(451199024)(1800799012)(36840700001)(46966006)(40470700004)(40480700001)(86362001)(81166007)(356005)(36756003)(82740400003)(40460700003)(7696005)(6666004)(478600001)(41300700001)(70586007)(54906003)(70206006)(921008)(16526019)(336012)(26005)(1076003)(2616005)(47076005)(83380400001)(426003)(2906002)(7416002)(110136005)(36860700001)(5660300002)(316002)(8936002)(8676002)(4326008)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2023 07:54:32.1995 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1bc82c44-91f7-4633-1956-08dc0067bc7d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FB.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7716 Patch "virtio-gpu: CONTEXT_INIT feature" has added the context_init feature flags. We would like to enable the feature with virglrenderer, so add to create virgl renderer context with flags using context_id when valid. Originally-by: Antonio Caggiano Signed-off-by: Huang Rui --- Changes in v6: - Handle the case while context_init is disabled. - Enable context_init by default. hw/display/virtio-gpu-virgl.c | 13 +++++++++++-- hw/display/virtio-gpu.c | 4 ++++ 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-virgl.c index 8bb7a2c21f..5bbc8071b2 100644 --- a/hw/display/virtio-gpu-virgl.c +++ b/hw/display/virtio-gpu-virgl.c @@ -106,8 +106,17 @@ static void virgl_cmd_context_create(VirtIOGPU *g, trace_virtio_gpu_cmd_ctx_create(cc.hdr.ctx_id, cc.debug_name); - virgl_renderer_context_create(cc.hdr.ctx_id, cc.nlen, - cc.debug_name); +#ifdef HAVE_VIRGL_CONTEXT_CREATE_WITH_FLAGS + if (cc.context_init && virtio_gpu_context_init_enabled(g->parent_obj.conf)) { + virgl_renderer_context_create_with_flags(cc.hdr.ctx_id, + cc.context_init, + cc.nlen, + cc.debug_name); + return; + } +#endif + + virgl_renderer_context_create(cc.hdr.ctx_id, cc.nlen, cc.debug_name); } static void virgl_cmd_context_destroy(VirtIOGPU *g, diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c index b016d3bac8..8b2f4c6be3 100644 --- a/hw/display/virtio-gpu.c +++ b/hw/display/virtio-gpu.c @@ -1619,6 +1619,10 @@ static Property virtio_gpu_properties[] = { DEFINE_PROP_BIT("blob", VirtIOGPU, parent_obj.conf.flags, VIRTIO_GPU_FLAG_BLOB_ENABLED, false), DEFINE_PROP_SIZE("hostmem", VirtIOGPU, parent_obj.conf.hostmem, 0), +#ifdef HAVE_VIRGL_CONTEXT_CREATE_WITH_FLAGS + DEFINE_PROP_BIT("context_init", VirtIOGPU, parent_obj.conf.flags, + VIRTIO_GPU_FLAG_CONTEXT_INIT_ENABLED, true), +#endif DEFINE_PROP_END_OF_LIST(), }; From patchwork Tue Dec 19 07:53:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 13497951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 060B3C46CA2 for ; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Huang Rui To: Akihiko Odaki , =?utf-8?q?Marc-Andr=C3=A9_Lure?= =?utf-8?q?au?= , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Gerd Hoffmann , "Michael S . Tsirkin" , "Stefano Stabellini" , Anthony PERARD , Antonio Caggiano , "Dr . David Alan Gilbert" , Robert Beckett , Dmitry Osipenko , Gert Wollny , =?utf-8?q?Alex_Benn=C3=A9e?= , CC: , Gurchetan Singh , , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , Stefano Stabellini , =?utf-8?q?Christian_K?= =?utf-8?q?=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Antonio Caggiano , Huang Rui Subject: [PATCH v6 04/11] virtio-gpu: Don't require udmabuf when blobs and virgl are enabled Date: Tue, 19 Dec 2023 15:53:13 +0800 Message-ID: <20231219075320.165227-5-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231219075320.165227-1-ray.huang@amd.com> References: <20231219075320.165227-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F6:EE_|DM6PR12MB4863:EE_ X-MS-Office365-Filtering-Correlation-Id: 934086c8-b3fa-421f-7fbf-08dc0067c166 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: q7GUOj+mSDtBeSW5AvfsXsKaqOMSxKAk0Ex7s4rCG458gMmUtzCsoyQ2e6nHG/8PW5qjuG0rfWqxVAA+avaO9z2XnaSGA1fZYgOwC21f4uej2c13aRSabTjToLB+6gBIZcjaQuet/n5pwXA4ylMYEpgdvFtGNg7ZnK7mvx2rAhkOe9IxZig255nWyvzU7T4Pwpb2OyCU4ncYt1YgmXcsPBIOrWdGizXlKXUA6rMniPqNaWZ3J0xa7JioBZVNz0otDgLtFouomMOmlbx8pz/voWRX47fUlcZ5b+djAcNil4+kzX+cOwQJKGf7yoORY581xZs7GBgxj0dhOSKQnHVJjR1EtGSTRRGkvyepPG0kKXrxH3rEHps7YnUEuYOzeGR5sy9GzPBiv3p6JoTC480FfP7LZPptBuRfcA+TA7+h15nfuZvORornSFQSwDNztapJuQUP7Z8FYz3CYncHF9hq1kRnsLCJS/2GqggkZxU6FJxVdWocAbU+dJ1fVtoo47/dWgaYHAFGSyxnhq4+TyxSX063lskdTkzQKQgR48HQBXdxF8Hww0GlvH6AsTEVWaL6Eb+hLrruXolllN9130cV8LY72sabwvnsGu4LOIcA5kVn76QUmeS1mYP786s15PNlirKSttaUL4ube5pEgdBNOzEdPBgfPEfM8Th90mpQuD00vVqPGG2WDdptPfx5X6UeMFoEo9zVw/6vULopEWE7KOX6fjQfyHI/rh5rdmJccfSq8ZY/FFHKnKO47MyQoqATwpBnZTyEPxJteZEEoM6g7nBhWLbjBIYU64iGUm2rUA0= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(396003)(136003)(346002)(39860400002)(230922051799003)(64100799003)(186009)(451199024)(1800799012)(82310400011)(36840700001)(46966006)(40470700004)(36860700001)(356005)(40480700001)(47076005)(40460700003)(336012)(426003)(26005)(1076003)(83380400001)(16526019)(2616005)(36756003)(86362001)(921008)(82740400003)(81166007)(478600001)(7696005)(6666004)(316002)(54906003)(110136005)(70206006)(70586007)(4326008)(8676002)(8936002)(7416002)(2906002)(5660300002)(41300700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2023 07:54:40.4556 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 934086c8-b3fa-421f-7fbf-08dc0067c166 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F6.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4863 From: Dmitry Osipenko The udmabuf usage is mandatory when virgl is disabled and blobs feature enabled in the Qemu machine configuration. If virgl and blobs are enabled, then udmabuf requirement is optional. Since udmabuf isn't widely supported by a popular Linux distros today, let's relax the udmabuf requirement for blobs=on,virgl=on. Now, a full-featured virtio-gpu acceleration is available to Qemu users without a need to have udmabuf available in the system. Reviewed-by: Antonio Caggiano Signed-off-by: Dmitry Osipenko Signed-off-by: Huang Rui Reviewed-by: Marc-André Lureau --- No change in v6. hw/display/virtio-gpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c index 8b2f4c6be3..4c3ec9d0ea 100644 --- a/hw/display/virtio-gpu.c +++ b/hw/display/virtio-gpu.c @@ -1443,6 +1443,7 @@ void virtio_gpu_device_realize(DeviceState *qdev, Error **errp) if (virtio_gpu_blob_enabled(g->parent_obj.conf)) { if (!virtio_gpu_rutabaga_enabled(g->parent_obj.conf) && + !virtio_gpu_virgl_enabled(g->parent_obj.conf) && !virtio_gpu_have_udmabuf()) { error_setg(errp, "need rutabaga or udmabuf for blob resources"); return; From patchwork Tue Dec 19 07:53:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 13497952 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 33CC1C46CA2 for ; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Huang Rui To: Akihiko Odaki , =?utf-8?q?Marc-Andr=C3=A9_Lure?= =?utf-8?q?au?= , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Gerd Hoffmann , "Michael S . Tsirkin" , "Stefano Stabellini" , Anthony PERARD , Antonio Caggiano , "Dr . David Alan Gilbert" , Robert Beckett , Dmitry Osipenko , Gert Wollny , =?utf-8?q?Alex_Benn=C3=A9e?= , CC: , Gurchetan Singh , , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , Stefano Stabellini , =?utf-8?q?Christian_K?= =?utf-8?q?=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Huang Rui Subject: [PATCH v6 05/11] virtio-gpu: Introduce virgl_gpu_resource structure Date: Tue, 19 Dec 2023 15:53:14 +0800 Message-ID: <20231219075320.165227-6-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231219075320.165227-1-ray.huang@amd.com> References: <20231219075320.165227-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F7:EE_|CH3PR12MB7689:EE_ X-MS-Office365-Filtering-Correlation-Id: 7db3e0b3-32b2-47c1-1214-08dc0067c528 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lAtoYfukDt1MoY3K87nkoXbs8OUr8IJKcEtYvVh7Ak/2MI9XmWnnr+scICo+UjOK69CmSgW9o0azfHo7I5CbxVO43ZvVa6xXHsLAH3ERDuumER+j4vrTcRBG6oBqmsIQWzegDKm10fSjJWUcQp2wr1hFxK0ofkgmDIxNizQTfgSNfstMgsT7wzPNXaeRK87dNT/oeJ4XQg7g5PfuSfQSrTps8uJ0uE4KdvqQRxuDz90xVMXONK6EtV6njRkcvG+/PJaE6jAbonL2IIQUm8WTUiCZYEyN+DDlPKZGCUAKHpUMWHCuIVPKCgOjh/VTkdvaopwqVZHaYBJ5GyqepowMql6+ktSn0ufMWlXwK/civTnM8IpzlJvUfHTq/c/bnwj6S0Mn1C52FNjw0cd4hl4J94hujTNstW0oMspJudR68otJxf12/ORbaW7syjZIWJh+z0e4Vfpz8ZKHx7IZvHhu825a0YEl9ntakKVKcTWlz7y+Uu6bDtZmsNaHVpGpxQqPT03r7SKxBDdvrb+yqoDaMER/7LOEl+Ja9aLol4XsN+uIhzA2Twqr2nAvF7I80ujkzI5mSDBRyhah6XLquXArSrjL9Ssugv2nPQy+Et/lONl3Cylnl8H0S/OPA58MTewSVsj0dDdaVkrOTk3wbP8/AvrXxUGQZXhAlcbMjIDBsUtJdyPCaZWSszyYgqYAZCy8uGbW2ycXOT+81/Evn5VYZ9dR45/yVr0ockhulz8VUlDwsj9ABYC/VCVMeOtIrN8tD689harnnlKAsXUdA0+4K2PdLYiCppLm5s6qV2kLpH4= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(376002)(39860400002)(136003)(396003)(230922051799003)(64100799003)(82310400011)(186009)(1800799012)(451199024)(36840700001)(46966006)(40470700004)(40480700001)(6666004)(1076003)(2616005)(426003)(16526019)(336012)(26005)(40460700003)(356005)(81166007)(82740400003)(921008)(36756003)(86362001)(47076005)(83380400001)(5660300002)(7696005)(36860700001)(8936002)(8676002)(4326008)(316002)(70586007)(70206006)(54906003)(110136005)(7416002)(2906002)(41300700001)(478600001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2023 07:54:46.7574 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7db3e0b3-32b2-47c1-1214-08dc0067c528 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F7.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7689 Introduce a new virgl_gpu_resource data structure and helper functions for virgl. It's used to add new member which is specific for virgl in following patches of blob memory support. Signed-off-by: Huang Rui --- New patch: - Introduce new struct virgl_gpu_resource to store virgl specific members. - Move resource initialization from path "virtio-gpu: Resource UUID" here. - Remove error handling of g_new0, because glib will abort() on OOM. - Set iov and iov_cnt in struct virtio_gpu_simple_resource for all types of resources. hw/display/virtio-gpu-virgl.c | 84 ++++++++++++++++++++++++++--------- 1 file changed, 64 insertions(+), 20 deletions(-) diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-virgl.c index 5bbc8071b2..faab374336 100644 --- a/hw/display/virtio-gpu-virgl.c +++ b/hw/display/virtio-gpu-virgl.c @@ -22,6 +22,23 @@ #include +struct virgl_gpu_resource { + struct virtio_gpu_simple_resource res; +}; + +static struct virgl_gpu_resource * +virgl_gpu_find_resource(VirtIOGPU *g, uint32_t resource_id) +{ + struct virtio_gpu_simple_resource *res; + + res = virtio_gpu_find_resource(g, resource_id); + if (!res) { + return NULL; + } + + return container_of(res, struct virgl_gpu_resource, res); +} + #if VIRGL_RENDERER_CALLBACKS_VERSION >= 4 static void * virgl_get_egl_display(G_GNUC_UNUSED void *cookie) @@ -35,11 +52,19 @@ static void virgl_cmd_create_resource_2d(VirtIOGPU *g, { struct virtio_gpu_resource_create_2d c2d; struct virgl_renderer_resource_create_args args; + struct virgl_gpu_resource *vres; VIRTIO_GPU_FILL_CMD(c2d); trace_virtio_gpu_cmd_res_create_2d(c2d.resource_id, c2d.format, c2d.width, c2d.height); + vres = g_new0(struct virgl_gpu_resource, 1); + vres->res.width = c2d.width; + vres->res.height = c2d.height; + vres->res.format = c2d.format; + vres->res.resource_id = c2d.resource_id; + QTAILQ_INSERT_HEAD(&g->reslist, &vres->res, next); + args.handle = c2d.resource_id; args.target = 2; args.format = c2d.format; @@ -59,11 +84,19 @@ static void virgl_cmd_create_resource_3d(VirtIOGPU *g, { struct virtio_gpu_resource_create_3d c3d; struct virgl_renderer_resource_create_args args; + struct virgl_gpu_resource *vres; VIRTIO_GPU_FILL_CMD(c3d); trace_virtio_gpu_cmd_res_create_3d(c3d.resource_id, c3d.format, c3d.width, c3d.height, c3d.depth); + vres = g_new0(struct virgl_gpu_resource, 1); + vres->res.width = c3d.width; + vres->res.height = c3d.height; + vres->res.format = c3d.format; + vres->res.resource_id = c3d.resource_id; + QTAILQ_INSERT_HEAD(&g->reslist, &vres->res, next); + args.handle = c3d.resource_id; args.target = c3d.target; args.format = c3d.format; @@ -82,19 +115,23 @@ static void virgl_cmd_resource_unref(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd) { struct virtio_gpu_resource_unref unref; - struct iovec *res_iovs = NULL; - int num_iovs = 0; + struct virgl_gpu_resource *vres; VIRTIO_GPU_FILL_CMD(unref); trace_virtio_gpu_cmd_res_unref(unref.resource_id); - virgl_renderer_resource_detach_iov(unref.resource_id, - &res_iovs, - &num_iovs); - if (res_iovs != NULL && num_iovs != 0) { - virtio_gpu_cleanup_mapping_iov(g, res_iovs, num_iovs); + vres = virgl_gpu_find_resource(g, unref.resource_id); + if (!vres) { + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; + return; } + + virgl_renderer_resource_detach_iov(unref.resource_id, NULL, NULL); virgl_renderer_resource_unref(unref.resource_id); + + QTAILQ_REMOVE(&g->reslist, &vres->res, next); + virtio_gpu_cleanup_mapping(g, &vres->res); + g_free(vres); } static void virgl_cmd_context_create(VirtIOGPU *g, @@ -310,44 +347,51 @@ static void virgl_resource_attach_backing(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd) { struct virtio_gpu_resource_attach_backing att_rb; - struct iovec *res_iovs; - uint32_t res_niov; + struct virgl_gpu_resource *vres; int ret; VIRTIO_GPU_FILL_CMD(att_rb); trace_virtio_gpu_cmd_res_back_attach(att_rb.resource_id); + vres = virgl_gpu_find_resource(g, att_rb.resource_id); + if (!vres) { + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; + return; + } + ret = virtio_gpu_create_mapping_iov(g, att_rb.nr_entries, sizeof(att_rb), - cmd, NULL, &res_iovs, &res_niov); + cmd, NULL, &vres->res.iov, + &vres->res.iov_cnt); if (ret != 0) { cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC; return; } ret = virgl_renderer_resource_attach_iov(att_rb.resource_id, - res_iovs, res_niov); + vres->res.iov, vres->res.iov_cnt); - if (ret != 0) - virtio_gpu_cleanup_mapping_iov(g, res_iovs, res_niov); + if (ret != 0) { + virtio_gpu_cleanup_mapping(g, &vres->res); + } } static void virgl_resource_detach_backing(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd) { struct virtio_gpu_resource_detach_backing detach_rb; - struct iovec *res_iovs = NULL; - int num_iovs = 0; + struct virgl_gpu_resource *vres; VIRTIO_GPU_FILL_CMD(detach_rb); trace_virtio_gpu_cmd_res_back_detach(detach_rb.resource_id); - virgl_renderer_resource_detach_iov(detach_rb.resource_id, - &res_iovs, - &num_iovs); - if (res_iovs == NULL || num_iovs == 0) { + vres = virgl_gpu_find_resource(g, detach_rb.resource_id); + if (!vres) { + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; return; } - virtio_gpu_cleanup_mapping_iov(g, res_iovs, num_iovs); + + virgl_renderer_resource_detach_iov(detach_rb.resource_id, NULL, NULL); + virtio_gpu_cleanup_mapping(g, &vres->res); } From patchwork Tue Dec 19 07:53:15 2023 Content-Type: text/plain; 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bh=NHthmq3LNlURxrALGteQJH0pznfSph2Flea36JzSsgY=; b=l0hbwTtsjmSZC/F/x9efoSXDKK17UB42jxjdjRcXiW5teYaWuZjGuBCXRA/k8snnLPloHp308N+7QGggb4FUnl2Lm+g+q+AZPQWjRkPmvBZGBxrpZwkoPxd1D4i4ac59zdoMY8acgTJvecN5qLJGb0vNz32WIvWF/qceraC/sb8= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Huang Rui To: Akihiko Odaki , =?utf-8?q?Marc-Andr=C3=A9_Lure?= =?utf-8?q?au?= , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Gerd Hoffmann , "Michael S . Tsirkin" , "Stefano Stabellini" , Anthony PERARD , Antonio Caggiano , "Dr . David Alan Gilbert" , Robert Beckett , Dmitry Osipenko , Gert Wollny , =?utf-8?q?Alex_Benn=C3=A9e?= , CC: , Gurchetan Singh , , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , Stefano Stabellini , =?utf-8?q?Christian_K?= =?utf-8?q?=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Huang Rui Subject: [PATCH v6 06/11] softmmu/memory: enable automatic deallocation of memory regions Date: Tue, 19 Dec 2023 15:53:15 +0800 Message-ID: <20231219075320.165227-7-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231219075320.165227-1-ray.huang@amd.com> References: <20231219075320.165227-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FB:EE_|PH8PR12MB6915:EE_ X-MS-Office365-Filtering-Correlation-Id: 8161af65-0cbb-42e1-1c1a-08dc0067c9ad X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LToTb6P6nsFg7OaWjSV02cosNDTZAB+ZJ01LIJwa9HgJ5YvoNgwdcHV62Q71NTJW+MxJbUiMQyEYjuixuvlxH2rJif+mBBxiPonm9mC32VUrzclNNayJbxFxoREe/aTDaF2lrcPY9ZsahMBmvOfOmHl37B2R7SV0cBQaybFw3Egf3tFUDEWmyiDTxwKkEPOuYD6wLdmw7oqkpapNoTWfHB7GuhK6byiPOJhkY0hmjgke1cs4KBAhw+vsijDxum8SDmfOCCrm/XycllwuoZj9E2xBhtKVg0kK1KyMY+ivWcZV/CxYaJTXKKK3Yz6DTCYhq1UQHtSzGvW9wEpifyv8UF+i518deHgVd+aejScheUi+ZZn62dajqboHcH0o8MG2sZ0LR2AzV4yJQcjphH3E3Pf4x0g22CJThUeyCP4NdDPyGA0h9xPHmnXNWJsRlvIY8tAPbipvMxhYLVN13k1qq54k3WVvULhqB969ACAlsSQTpEkAeF8iz5ATT0NPinsqZwlmSLM4GzrYfmiUSb3hKwuLSzD4jQwIsh/b2NxharkaXBVq+TkPTZ/i2QFL8vKuWH5EWfffUs3370u3KWWbezL/DOaUQva+viYwf6kr4qG3G5FJKtlDHAHkzxg8CrwIwdYjOHuv3w5tAAPIvoqe10pCLp3Ad3HN9sjhbSPnjR4LIgiH04PFmK1M1yRpk0MaHkPGbVndON+VkWFIk6B8zjRkDbv8fAEKSlgNMkUedSrgr0lkgfEc7SAtA9/U8P/2KFIO+p9wdF6828ip7BUHGyrJvAGWMys+DIs3/VotZEI= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(136003)(346002)(39860400002)(396003)(230922051799003)(451199024)(186009)(64100799003)(82310400011)(1800799012)(40470700004)(46966006)(36840700001)(5660300002)(82740400003)(356005)(66899024)(81166007)(7416002)(40460700003)(2906002)(36756003)(921008)(41300700001)(86362001)(316002)(7696005)(1076003)(8676002)(8936002)(4326008)(6666004)(40480700001)(336012)(426003)(70206006)(70586007)(54906003)(83380400001)(110136005)(36860700001)(478600001)(26005)(16526019)(2616005)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2023 07:54:54.3089 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8161af65-0cbb-42e1-1c1a-08dc0067c9ad X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FB.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6915 From: Xenia Ragiadakou When the memory region has a different life-cycle from that of her parent, could be automatically released, once has been unparent and once all of her references have gone away, via the object's free callback. However, currently, the address space subsystem keeps references to the memory region without first incrementing its object's reference count. As a result, the automatic deallocation of the object, not taking into account those references, results in use-after-free memory corruption. More specifically, reference to the memory region is kept in flatview ranges. If the reference count of the memory region is not incremented, flatview_destroy(), that is asynchronous, may be called after memory region's destruction. If the reference count of the memory region is incremented, memory region's destruction will take place after flatview_destroy() has released its references. This patch increases the reference count of an owned memory region object on each memory_region_ref() and decreases it on each memory_region_unref(). Signed-off-by: Xenia Ragiadakou Signed-off-by: Huang Rui --- Changes in v6: - remove in-code comment because it is confusing and explain the issue, that the patch attempts to fix, with more details in commit message system/memory.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/system/memory.c b/system/memory.c index 304fa843ea..4d5e7e7a4c 100644 --- a/system/memory.c +++ b/system/memory.c @@ -1824,6 +1824,7 @@ void memory_region_ref(MemoryRegion *mr) * we do not ref/unref them because it slows down DMA sensibly. */ if (mr && mr->owner) { + object_ref(OBJECT(mr)); object_ref(mr->owner); } } @@ -1832,6 +1833,7 @@ void memory_region_unref(MemoryRegion *mr) { if (mr && mr->owner) { object_unref(mr->owner); + object_unref(OBJECT(mr)); } } From patchwork Tue Dec 19 07:53:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 13497982 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0C333C46CA2 for ; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Huang Rui To: Akihiko Odaki , =?utf-8?q?Marc-Andr=C3=A9_Lure?= =?utf-8?q?au?= , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Gerd Hoffmann , "Michael S . Tsirkin" , "Stefano Stabellini" , Anthony PERARD , Antonio Caggiano , "Dr . David Alan Gilbert" , Robert Beckett , Dmitry Osipenko , Gert Wollny , =?utf-8?q?Alex_Benn=C3=A9e?= , CC: , Gurchetan Singh , , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , Stefano Stabellini , =?utf-8?q?Christian_K?= =?utf-8?q?=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Antonio Caggiano , Huang Rui Subject: [PATCH v6 07/11] virtio-gpu: Handle resource blob commands Date: Tue, 19 Dec 2023 15:53:16 +0800 Message-ID: <20231219075320.165227-8-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231219075320.165227-1-ray.huang@amd.com> References: <20231219075320.165227-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F6:EE_|CH2PR12MB4970:EE_ X-MS-Office365-Filtering-Correlation-Id: e62565d8-1199-4361-53ca-08dc0067d749 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: S7nIgxtub/IUXQ9SHuEq3QXmj+SF/FEwnP9Ov1Qhz2bXljfpmKJIbYesXimedsgG1l0DP6AAhHZ4yCt9Whwnyh1vMa3CIw4TxeGybefyZ1RPBhLu08QLqHG4gR+Jm2+lG5KaN5RDJa2BdGoucHHJDtukpGE+gZwFcPXQbs+BUHDB67lOMZ5oYU1DYs03PP7ZgwPFX7DQO3iTC4ZfJJr4WTMmZVsM3iTD7u77IjNR7L45jn2URBjRutoUSO054RRNMsS5pZTfnBl+7Y5l68sZ2Veel8B3mm0KFvNcqXertK1owSjESObgQ4Gy4HhVwMXSpcw8g7HtV3xvBx6ofsJLeh6fy5yn9hUYQP1vkfc78cjlpG40JObWaL85IeuQyc8X4dMyWxNz/0muaYhQ+v/FfMvzxq32cN1vr4m9we4oOtcNRnZetghfK467gqqnl4fxOn9BOcWlU2joscZux4LNL2+PJHMiWt1ImydfovKp7DaBC9tWAVKB5Sm2wuv2WMYa+O5yhJB2dYN1ZNhWfhZvAKbOjgkq0aUFVlX8qOaE9/dJ/6hScqdmxi4esJK4uksOqSg2V66lQaQgNbCLxXOuWtzxNsCidhU+4qKzaUZ1txeSxD+9V2uu/4hWcqk08eyooy0Ld7/b0Me0VBI/S4vFi4jIJv08NFbSQc/hLsMCyu0q6wxA9V50x0ZUUWxKxgsSu+3dWgKdxy0/xUN/EJnuLyfAG9QU6yLpvgkjD2y7bd9HxC9Kx3Vrm0VjuT5sgjLa0T5suigm/8okILM/icJ4fEuz/uF1B1M46wHUDNm69w4= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(396003)(346002)(376002)(39860400002)(230922051799003)(82310400011)(1800799012)(451199024)(186009)(64100799003)(46966006)(36840700001)(40470700004)(7696005)(36756003)(921008)(83380400001)(316002)(7416002)(426003)(336012)(110136005)(70206006)(40480700001)(30864003)(54906003)(70586007)(8676002)(4326008)(47076005)(8936002)(5660300002)(36860700001)(2906002)(6666004)(26005)(86362001)(16526019)(1076003)(478600001)(2616005)(41300700001)(82740400003)(40460700003)(81166007)(356005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2023 07:55:17.1431 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e62565d8-1199-4361-53ca-08dc0067d749 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F6.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4970 From: Antonio Caggiano Support BLOB resources creation, mapping and unmapping by calling the new stable virglrenderer 0.10 interface. Only enabled when available and via the blob config. E.g. -device virtio-vga-gl,blob=true Signed-off-by: Antonio Caggiano Signed-off-by: Dmitry Osipenko Signed-off-by: Xenia Ragiadakou Signed-off-by: Huang Rui --- Changes in v6: - Use new struct virgl_gpu_resource. - Unmap, unref and destroy the resource only after the memory region has been completely removed. - In unref check whether the resource is still mapped. - In unmap_blob check whether the resource has been already unmapped. - Fix coding style hw/display/virtio-gpu-virgl.c | 274 +++++++++++++++++++++++++++++++++- hw/display/virtio-gpu.c | 4 +- meson.build | 4 + 3 files changed, 276 insertions(+), 6 deletions(-) diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-virgl.c index faab374336..5a3a292f79 100644 --- a/hw/display/virtio-gpu-virgl.c +++ b/hw/display/virtio-gpu-virgl.c @@ -17,6 +17,7 @@ #include "trace.h" #include "hw/virtio/virtio.h" #include "hw/virtio/virtio-gpu.h" +#include "hw/virtio/virtio-gpu-bswap.h" #include "ui/egl-helpers.h" @@ -24,8 +25,62 @@ struct virgl_gpu_resource { struct virtio_gpu_simple_resource res; + uint32_t ref; + VirtIOGPU *g; + +#ifdef HAVE_VIRGL_RESOURCE_BLOB + /* only blob resource needs this region to be mapped as guest mmio */ + MemoryRegion *region; +#endif }; +static void vres_get_ref(struct virgl_gpu_resource *vres) +{ + uint32_t ref; + + ref = qatomic_fetch_inc(&vres->ref); + g_assert(ref < INT_MAX); +} + +static void virgl_resource_destroy(struct virgl_gpu_resource *vres) +{ + struct virtio_gpu_simple_resource *res; + VirtIOGPU *g; + + if (!vres) { + return; + } + + g = vres->g; + res = &vres->res; + QTAILQ_REMOVE(&g->reslist, res, next); + virtio_gpu_cleanup_mapping(g, res); + g_free(vres); +} + +static void virgl_resource_unref(struct virgl_gpu_resource *vres) +{ + struct virtio_gpu_simple_resource *res; + + if (!vres) { + return; + } + + res = &vres->res; + virgl_renderer_resource_detach_iov(res->resource_id, NULL, NULL); + virgl_renderer_resource_unref(res->resource_id); +} + +static void vres_put_ref(struct virgl_gpu_resource *vres) +{ + g_assert(vres->ref > 0); + + if (qatomic_fetch_dec(&vres->ref) == 1) { + virgl_resource_unref(vres); + virgl_resource_destroy(vres); + } +} + static struct virgl_gpu_resource * virgl_gpu_find_resource(VirtIOGPU *g, uint32_t resource_id) { @@ -59,6 +114,8 @@ static void virgl_cmd_create_resource_2d(VirtIOGPU *g, c2d.width, c2d.height); vres = g_new0(struct virgl_gpu_resource, 1); + vres_get_ref(vres); + vres->g = g; vres->res.width = c2d.width; vres->res.height = c2d.height; vres->res.format = c2d.format; @@ -91,6 +148,8 @@ static void virgl_cmd_create_resource_3d(VirtIOGPU *g, c3d.width, c3d.height, c3d.depth); vres = g_new0(struct virgl_gpu_resource, 1); + vres_get_ref(vres); + vres->g = g; vres->res.width = c3d.width; vres->res.height = c3d.height; vres->res.format = c3d.format; @@ -126,12 +185,21 @@ static void virgl_cmd_resource_unref(VirtIOGPU *g, return; } - virgl_renderer_resource_detach_iov(unref.resource_id, NULL, NULL); - virgl_renderer_resource_unref(unref.resource_id); +#ifdef HAVE_VIRGL_RESOURCE_BLOB + if (vres->region) { + VirtIOGPUBase *b = VIRTIO_GPU_BASE(g); + MemoryRegion *mr = vres->region; + + warn_report("%s: blob resource %d not unmapped", + __func__, unref.resource_id); + vres->region = NULL; + memory_region_set_enabled(mr, false); + memory_region_del_subregion(&b->hostmem, mr); + object_unparent(OBJECT(mr)); + } +#endif /* HAVE_VIRGL_RESOURCE_BLOB */ - QTAILQ_REMOVE(&g->reslist, &vres->res, next); - virtio_gpu_cleanup_mapping(g, &vres->res); - g_free(vres); + vres_put_ref(vres); } static void virgl_cmd_context_create(VirtIOGPU *g, @@ -470,6 +538,191 @@ static void virgl_cmd_get_capset(VirtIOGPU *g, g_free(resp); } +#ifdef HAVE_VIRGL_RESOURCE_BLOB + +static void virgl_resource_unmap(struct virgl_gpu_resource *vres) +{ + if (!vres) { + return; + } + + virgl_renderer_resource_unmap(vres->res.resource_id); + + vres_put_ref(vres); +} + +static void virgl_resource_blob_async_unmap(void *obj) +{ + MemoryRegion *mr = MEMORY_REGION(obj); + struct virgl_gpu_resource *vres = mr->opaque; + + virgl_resource_unmap(vres); + + g_free(obj); +} + +static void virgl_cmd_resource_create_blob(VirtIOGPU *g, + struct virtio_gpu_ctrl_command *cmd) +{ + struct virgl_gpu_resource *vres; + struct virtio_gpu_resource_create_blob cblob; + struct virgl_renderer_resource_create_blob_args virgl_args = { 0 }; + int ret; + + VIRTIO_GPU_FILL_CMD(cblob); + virtio_gpu_create_blob_bswap(&cblob); + trace_virtio_gpu_cmd_res_create_blob(cblob.resource_id, cblob.size); + + if (cblob.resource_id == 0) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: resource id 0 is not allowed\n", + __func__); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; + return; + } + + vres = virgl_gpu_find_resource(g, cblob.resource_id); + if (vres) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: resource already exists %d\n", + __func__, cblob.resource_id); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; + return; + } + + vres = g_new0(struct virgl_gpu_resource, 1); + vres_get_ref(vres); + vres->g = g; + vres->res.resource_id = cblob.resource_id; + vres->res.blob_size = cblob.size; + + if (cblob.blob_mem != VIRTIO_GPU_BLOB_MEM_HOST3D) { + ret = virtio_gpu_create_mapping_iov(g, cblob.nr_entries, sizeof(cblob), + cmd, &vres->res.addrs, + &vres->res.iov, &vres->res.iov_cnt); + if (!ret) { + g_free(vres); + cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC; + return; + } + } + + QTAILQ_INSERT_HEAD(&g->reslist, &vres->res, next); + + virgl_args.res_handle = cblob.resource_id; + virgl_args.ctx_id = cblob.hdr.ctx_id; + virgl_args.blob_mem = cblob.blob_mem; + virgl_args.blob_id = cblob.blob_id; + virgl_args.blob_flags = cblob.blob_flags; + virgl_args.size = cblob.size; + virgl_args.iovecs = vres->res.iov; + virgl_args.num_iovs = vres->res.iov_cnt; + + ret = virgl_renderer_resource_create_blob(&virgl_args); + if (ret) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: virgl blob create error: %s\n", + __func__, strerror(-ret)); + cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC; + } +} + +static void virgl_cmd_resource_map_blob(VirtIOGPU *g, + struct virtio_gpu_ctrl_command *cmd) +{ + struct virgl_gpu_resource *vres; + struct virtio_gpu_resource_map_blob mblob; + int ret; + void *data; + uint64_t size; + struct virtio_gpu_resp_map_info resp; + VirtIOGPUBase *b = VIRTIO_GPU_BASE(g); + + VIRTIO_GPU_FILL_CMD(mblob); + virtio_gpu_map_blob_bswap(&mblob); + + if (mblob.resource_id == 0) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: resource id 0 is not allowed\n", + __func__); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; + return; + } + + vres = virgl_gpu_find_resource(g, mblob.resource_id); + if (!vres) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: resource does not exist %d\n", + __func__, mblob.resource_id); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; + return; + } + if (vres->region) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: resource already mapped %d\n", + __func__, mblob.resource_id); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; + return; + } + + ret = virgl_renderer_resource_map(vres->res.resource_id, &data, &size); + if (ret) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: resource map error: %s\n", + __func__, strerror(-ret)); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; + return; + } + + vres_get_ref(vres); + vres->region = g_new0(MemoryRegion, 1); + memory_region_init_ram_ptr(vres->region, OBJECT(g), NULL, size, data); + vres->region->opaque = vres; + OBJECT(vres->region)->free = virgl_resource_blob_async_unmap; + memory_region_add_subregion(&b->hostmem, mblob.offset, vres->region); + memory_region_set_enabled(vres->region, true); + + memset(&resp, 0, sizeof(resp)); + resp.hdr.type = VIRTIO_GPU_RESP_OK_MAP_INFO; + virgl_renderer_resource_get_map_info(mblob.resource_id, &resp.map_info); + virtio_gpu_ctrl_response(g, cmd, &resp.hdr, sizeof(resp)); +} + +static void virgl_cmd_resource_unmap_blob(VirtIOGPU *g, + struct virtio_gpu_ctrl_command *cmd) +{ + struct virgl_gpu_resource *vres; + struct virtio_gpu_resource_unmap_blob ublob; + VirtIOGPUBase *b = VIRTIO_GPU_BASE(g); + MemoryRegion *mr; + + VIRTIO_GPU_FILL_CMD(ublob); + virtio_gpu_unmap_blob_bswap(&ublob); + + if (ublob.resource_id == 0) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: resource id 0 is not allowed\n", + __func__); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; + return; + } + + vres = virgl_gpu_find_resource(g, ublob.resource_id); + if (!vres) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: resource does not exist %d\n", + __func__, ublob.resource_id); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; + return; + } + + if (!vres->region) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: resource already unmapped %d\n", + __func__, ublob.resource_id); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; + return; + } + + mr = vres->region; + vres->region = NULL; + memory_region_set_enabled(mr, false); + memory_region_del_subregion(&b->hostmem, mr); + object_unparent(OBJECT(mr)); +} + +#endif /* HAVE_VIRGL_RESOURCE_BLOB */ + void virtio_gpu_virgl_process_cmd(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd) { @@ -536,6 +789,17 @@ void virtio_gpu_virgl_process_cmd(VirtIOGPU *g, case VIRTIO_GPU_CMD_GET_EDID: virtio_gpu_get_edid(g, cmd); break; +#ifdef HAVE_VIRGL_RESOURCE_BLOB + case VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB: + virgl_cmd_resource_create_blob(g, cmd); + break; + case VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB: + virgl_cmd_resource_map_blob(g, cmd); + break; + case VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB: + virgl_cmd_resource_unmap_blob(g, cmd); + break; +#endif /* HAVE_VIRGL_RESOURCE_BLOB */ default: cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC; break; diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c index 4c3ec9d0ea..8189c392dc 100644 --- a/hw/display/virtio-gpu.c +++ b/hw/display/virtio-gpu.c @@ -1449,10 +1449,12 @@ void virtio_gpu_device_realize(DeviceState *qdev, Error **errp) return; } +#ifndef HAVE_VIRGL_RESOURCE_BLOB if (virtio_gpu_virgl_enabled(g->parent_obj.conf)) { - error_setg(errp, "blobs and virgl are not compatible (yet)"); + error_setg(errp, "Linked virglrenderer does not support blob resources"); return; } +#endif } if (!virtio_gpu_base_device_realize(qdev, diff --git a/meson.build b/meson.build index ea52ef1b9c..629407128e 100644 --- a/meson.build +++ b/meson.build @@ -1054,6 +1054,10 @@ if not get_option('virglrenderer').auto() or have_system or have_vhost_user_gpu cc.has_function('virgl_renderer_context_create_with_flags', prefix: '#include ', dependencies: virgl)) + config_host_data.set('HAVE_VIRGL_RESOURCE_BLOB', + cc.has_function('virgl_renderer_resource_create_blob', + prefix: '#include ', + dependencies: virgl)) endif endif rutabaga = not_found From patchwork Tue Dec 19 07:53:17 2023 Content-Type: text/plain; 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bh=r6wM7XdDLz/vD6HCFSkY/1aVRVdBt1QQMsmUBQSoj30=; b=Dz5NnppdXVdZQ2D1d7fl/G5vqoMtjL90QOK1v9ZFa3RnLAtvks43CMG2TYBmB/Gwq0bijuxC0V/fZ4IDRdVErGEKG7MCITqenYgk7L+EgL2OKbreah3bPBl5gn0FYutBPLEXUGVRqNO12Y4R9uZ3aZN+Di5G035xAp2WJnR4os4= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Huang Rui To: Akihiko Odaki , =?utf-8?q?Marc-Andr=C3=A9_Lure?= =?utf-8?q?au?= , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Gerd Hoffmann , "Michael S . Tsirkin" , "Stefano Stabellini" , Anthony PERARD , Antonio Caggiano , "Dr . David Alan Gilbert" , Robert Beckett , Dmitry Osipenko , Gert Wollny , =?utf-8?q?Alex_Benn=C3=A9e?= , CC: , Gurchetan Singh , , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , Stefano Stabellini , =?utf-8?q?Christian_K?= =?utf-8?q?=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Antonio Caggiano , Huang Rui Subject: [PATCH v6 08/11] virtio-gpu: Resource UUID Date: Tue, 19 Dec 2023 15:53:17 +0800 Message-ID: <20231219075320.165227-9-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231219075320.165227-1-ray.huang@amd.com> References: <20231219075320.165227-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FC:EE_|DS7PR12MB5912:EE_ X-MS-Office365-Filtering-Correlation-Id: a8e63952-2d9e-4901-9f1a-08dc0067da7d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7F1yjdWR/CEy1ib18kKEI3rMswtuQLXbhP4gS/VvxwJBvxJqXcx4On8o4e0m9VSvV2v2cFOAtA1/ARBXZI/ZW4xma3O+fNEm/mAC9puLPzJB5OK4Vqyr0yJ3a/q7VrqIc/GURtIsgt7nm2T5rECDEJIHaOuoiNnzj27OnwZN1Xz4/2P6FpuG5eLZfOikadv2M+tbFGo2Tn0/XPrgaultecVuKGdCJzPab5Gu10SrT/LcKFWVS91fqyFXgx42yp7/DjZ++MY34o0d1oTLgfww+8FJn+rFsSAsC5seeiYhcZB6tsLIXdYiqoBg51cVx+e/jumejZorHXT0Z/FJ0gjJQP3gvJ/OMQulxBJ0ldVRNdWtHl8VB/F/Uk/dvVYsuvLlKY5ghg48weiehPQGYtNVNy49TkMUECdSVdWjAxyx3lVbnFOUjWUptEkkicOctnhyiCR+CeucSoXlYWYQXR/GBJeYqr6+JQQAH4itScQoFNxHM//uJDsjtMKaXKw+VoBg4T0AwZgsPq93zrLPsM1zrLkRmLnKSzp/Kx6PXijWINdizA7SpMLp9vbc3Qg1KRhzTpjw+OZdVPhz0yDoSKpSplb29ARBBmbOGMwhVidfBT9M9hlGCeygQqXzxSb5AEWaRewEP2inN5CvHlO03nAHetlwhlO6AiWAhiMbFri8mW7M8Fwjp7wjyRNsyrtlMAi9J22RcURm3ViWqtlMyklGvNyos8G6qt/dmkFiY1I2WOMI1AwtbdGQsbIRkL/vGs6lPHmauyueDN4GCWOApXStJVjMx9oCOJqYPHlRrDxyn/A= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(376002)(396003)(39860400002)(136003)(230922051799003)(1800799012)(82310400011)(186009)(64100799003)(451199024)(36840700001)(40470700004)(46966006)(40480700001)(40460700003)(921008)(70206006)(70586007)(81166007)(356005)(82740400003)(36756003)(86362001)(16526019)(36860700001)(1076003)(426003)(336012)(26005)(83380400001)(2616005)(7696005)(2906002)(8936002)(316002)(8676002)(110136005)(54906003)(478600001)(7416002)(4326008)(5660300002)(41300700001)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2023 07:55:22.5658 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a8e63952-2d9e-4901-9f1a-08dc0067da7d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FC.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5912 From: Antonio Caggiano Enable resource UUID feature and implement command resource assign UUID. This is done by introducing a hash table to map resource IDs to their UUIDs. Signed-off-by: Antonio Caggiano Signed-off-by: Huang Rui --- Changes in v6: - Set resource uuid as option. - Implement optional subsection of vmstate_virtio_gpu_resource_uuid_state or virtio live migration. - Use g_int_hash/g_int_equal instead of the default. - Move virtio_vgpu_simple_resource initialization in the earlier new patch "virtio-gpu: Introduce virgl_gpu_resource structure" hw/display/trace-events | 1 + hw/display/virtio-gpu-base.c | 4 ++ hw/display/virtio-gpu-virgl.c | 3 + hw/display/virtio-gpu.c | 119 +++++++++++++++++++++++++++++++++ include/hw/virtio/virtio-gpu.h | 7 ++ 5 files changed, 134 insertions(+) diff --git a/hw/display/trace-events b/hw/display/trace-events index 2336a0ca15..54d6894c59 100644 --- a/hw/display/trace-events +++ b/hw/display/trace-events @@ -41,6 +41,7 @@ virtio_gpu_cmd_res_create_blob(uint32_t res, uint64_t size) "res 0x%x, size %" P virtio_gpu_cmd_res_unref(uint32_t res) "res 0x%x" virtio_gpu_cmd_res_back_attach(uint32_t res) "res 0x%x" virtio_gpu_cmd_res_back_detach(uint32_t res) "res 0x%x" +virtio_gpu_cmd_res_assign_uuid(uint32_t res) "res 0x%x" virtio_gpu_cmd_res_xfer_toh_2d(uint32_t res) "res 0x%x" virtio_gpu_cmd_res_xfer_toh_3d(uint32_t res) "res 0x%x" virtio_gpu_cmd_res_xfer_fromh_3d(uint32_t res) "res 0x%x" diff --git a/hw/display/virtio-gpu-base.c b/hw/display/virtio-gpu-base.c index 37af256219..6bcee3882f 100644 --- a/hw/display/virtio-gpu-base.c +++ b/hw/display/virtio-gpu-base.c @@ -236,6 +236,10 @@ virtio_gpu_base_get_features(VirtIODevice *vdev, uint64_t features, features |= (1 << VIRTIO_GPU_F_CONTEXT_INIT); } + if (virtio_gpu_resource_uuid_enabled(g->conf)) { + features |= (1 << VIRTIO_GPU_F_RESOURCE_UUID); + } + return features; } diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-virgl.c index 5a3a292f79..be9da6e780 100644 --- a/hw/display/virtio-gpu-virgl.c +++ b/hw/display/virtio-gpu-virgl.c @@ -777,6 +777,9 @@ void virtio_gpu_virgl_process_cmd(VirtIOGPU *g, /* TODO add security */ virgl_cmd_ctx_detach_resource(g, cmd); break; + case VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID: + virtio_gpu_resource_assign_uuid(g, cmd); + break; case VIRTIO_GPU_CMD_GET_CAPSET_INFO: virgl_cmd_get_capset_info(g, cmd); break; diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c index 8189c392dc..466debb256 100644 --- a/hw/display/virtio-gpu.c +++ b/hw/display/virtio-gpu.c @@ -958,6 +958,37 @@ virtio_gpu_resource_detach_backing(VirtIOGPU *g, virtio_gpu_cleanup_mapping(g, res); } +void virtio_gpu_resource_assign_uuid(VirtIOGPU *g, + struct virtio_gpu_ctrl_command *cmd) +{ + struct virtio_gpu_simple_resource *res; + struct virtio_gpu_resource_assign_uuid assign; + struct virtio_gpu_resp_resource_uuid resp; + QemuUUID *uuid; + + VIRTIO_GPU_FILL_CMD(assign); + virtio_gpu_bswap_32(&assign, sizeof(assign)); + trace_virtio_gpu_cmd_res_assign_uuid(assign.resource_id); + + res = virtio_gpu_find_check_resource(g, assign.resource_id, false, __func__, &cmd->error); + if (!res) { + return; + } + + memset(&resp, 0, sizeof(resp)); + resp.hdr.type = VIRTIO_GPU_RESP_OK_RESOURCE_UUID; + + uuid = g_hash_table_lookup(g->resource_uuids, &assign.resource_id); + if (!uuid) { + uuid = g_new(QemuUUID, 1); + qemu_uuid_generate(uuid); + g_hash_table_insert(g->resource_uuids, &assign.resource_id, uuid); + } + + memcpy(resp.uuid, uuid, sizeof(QemuUUID)); + virtio_gpu_ctrl_response(g, cmd, &resp.hdr, sizeof(resp)); +} + void virtio_gpu_simple_process_cmd(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd) { @@ -1006,6 +1037,9 @@ void virtio_gpu_simple_process_cmd(VirtIOGPU *g, case VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING: virtio_gpu_resource_detach_backing(g, cmd); break; + case VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID: + virtio_gpu_resource_assign_uuid(g, cmd); + break; default: cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC; break; @@ -1400,6 +1434,57 @@ static int virtio_gpu_blob_load(QEMUFile *f, void *opaque, size_t size, return 0; } +static int virtio_gpu_resource_uuid_save(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field, + JSONWriter *vmdesc) +{ + VirtIOGPU *g = opaque; + struct virtio_gpu_simple_resource *res; + QemuUUID *uuid; + + /* in 2d mode we should never find unprocessed commands here */ + assert(QTAILQ_EMPTY(&g->cmdq)); + + QTAILQ_FOREACH(res, &g->reslist, next) { + qemu_put_be32(f, res->resource_id); + uuid = g_hash_table_lookup(g->resource_uuids, &res->resource_id); + qemu_put_buffer(f, (void *)uuid, sizeof(QemuUUID)); + } + qemu_put_be32(f, 0); /* end of list */ + + g_hash_table_destroy(g->resource_uuids); + + return 0; +} + +static int virtio_gpu_resource_uuid_load(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field) +{ + VirtIOGPU *g = opaque; + struct virtio_gpu_simple_resource *res; + uint32_t resource_id; + QemuUUID *uuid = NULL; + + g->resource_uuids = g_hash_table_new_full(g_int_hash, g_int_equal, NULL, g_free); + resource_id = qemu_get_be32(f); + while (resource_id != 0) { + res = virtio_gpu_find_resource(g, resource_id); + if (res) { + return -EINVAL; + } + + res = g_new0(struct virtio_gpu_simple_resource, 1); + res->resource_id = resource_id; + + qemu_get_buffer(f, (void *)uuid, sizeof(QemuUUID)); + g_hash_table_insert(g->resource_uuids, &res->resource_id, uuid); + + resource_id = qemu_get_be32(f); + } + + return 0; +} + static int virtio_gpu_post_load(void *opaque, int version_id) { VirtIOGPU *g = opaque; @@ -1475,12 +1560,15 @@ void virtio_gpu_device_realize(DeviceState *qdev, Error **errp) QTAILQ_INIT(&g->reslist); QTAILQ_INIT(&g->cmdq); QTAILQ_INIT(&g->fenceq); + + g->resource_uuids = g_hash_table_new_full(g_int_hash, g_int_equal, NULL, g_free); } static void virtio_gpu_device_unrealize(DeviceState *qdev) { VirtIOGPU *g = VIRTIO_GPU(qdev); + g_hash_table_destroy(g->resource_uuids); g_clear_pointer(&g->ctrl_bh, qemu_bh_delete); g_clear_pointer(&g->cursor_bh, qemu_bh_delete); g_clear_pointer(&g->reset_bh, qemu_bh_delete); @@ -1534,6 +1622,8 @@ void virtio_gpu_reset(VirtIODevice *vdev) g_free(cmd); } + g_hash_table_remove_all(g->resource_uuids); + virtio_gpu_base_reset(VIRTIO_GPU_BASE(vdev)); } @@ -1583,6 +1673,32 @@ const VMStateDescription vmstate_virtio_gpu_blob_state = { }, }; +static bool virtio_gpu_resource_uuid_state_needed(void *opaque) +{ + VirtIOGPU *g = VIRTIO_GPU(opaque); + + return virtio_gpu_resource_uuid_enabled(g->parent_obj.conf); +} + +const VMStateDescription vmstate_virtio_gpu_resource_uuid_state = { + .name = "virtio-gpu/resource_uuid", + .minimum_version_id = VIRTIO_GPU_VM_VERSION, + .version_id = VIRTIO_GPU_VM_VERSION, + .needed = virtio_gpu_resource_uuid_state_needed, + .fields = (const VMStateField[]){ + { + .name = "virtio-gpu/resource_uuid", + .info = &(const VMStateInfo) { + .name = "resource_uuid", + .get = virtio_gpu_resource_uuid_load, + .put = virtio_gpu_resource_uuid_save, + }, + .flags = VMS_SINGLE, + } /* device */, + VMSTATE_END_OF_LIST() + }, +}; + /* * For historical reasons virtio_gpu does not adhere to virtio migration * scheme as described in doc/virtio-migration.txt, in a sense that no @@ -1610,6 +1726,7 @@ static const VMStateDescription vmstate_virtio_gpu = { }, .subsections = (const VMStateDescription * []) { &vmstate_virtio_gpu_blob_state, + &vmstate_virtio_gpu_resource_uuid_state, NULL }, .post_load = virtio_gpu_post_load, @@ -1622,6 +1739,8 @@ static Property virtio_gpu_properties[] = { DEFINE_PROP_BIT("blob", VirtIOGPU, parent_obj.conf.flags, VIRTIO_GPU_FLAG_BLOB_ENABLED, false), DEFINE_PROP_SIZE("hostmem", VirtIOGPU, parent_obj.conf.hostmem, 0), + DEFINE_PROP_BIT("resource_uuid", VirtIOGPU, parent_obj.conf.flags, + VIRTIO_GPU_FLAG_RESOURCE_UUID_ENABLED, false), #ifdef HAVE_VIRGL_CONTEXT_CREATE_WITH_FLAGS DEFINE_PROP_BIT("context_init", VirtIOGPU, parent_obj.conf.flags, VIRTIO_GPU_FLAG_CONTEXT_INIT_ENABLED, true), diff --git a/include/hw/virtio/virtio-gpu.h b/include/hw/virtio/virtio-gpu.h index 584ba2ed73..76b410fe91 100644 --- a/include/hw/virtio/virtio-gpu.h +++ b/include/hw/virtio/virtio-gpu.h @@ -98,6 +98,7 @@ enum virtio_gpu_base_conf_flags { VIRTIO_GPU_FLAG_BLOB_ENABLED, VIRTIO_GPU_FLAG_CONTEXT_INIT_ENABLED, VIRTIO_GPU_FLAG_RUTABAGA_ENABLED, + VIRTIO_GPU_FLAG_RESOURCE_UUID_ENABLED, }; #define virtio_gpu_virgl_enabled(_cfg) \ @@ -114,6 +115,8 @@ enum virtio_gpu_base_conf_flags { (_cfg.flags & (1 << VIRTIO_GPU_FLAG_CONTEXT_INIT_ENABLED)) #define virtio_gpu_rutabaga_enabled(_cfg) \ (_cfg.flags & (1 << VIRTIO_GPU_FLAG_RUTABAGA_ENABLED)) +#define virtio_gpu_resource_uuid_enabled(_cfg) \ + (_cfg.flags & (1 << VIRTIO_GPU_FLAG_RESOURCE_UUID_ENABLED)) #define virtio_gpu_hostmem_enabled(_cfg) \ (_cfg.hostmem > 0) @@ -209,6 +212,8 @@ struct VirtIOGPU { QTAILQ_HEAD(, VGPUDMABuf) bufs; VGPUDMABuf *primary[VIRTIO_GPU_MAX_SCANOUTS]; } dmabuf; + + GHashTable *resource_uuids; }; struct VirtIOGPUClass { @@ -307,6 +312,8 @@ void virtio_gpu_cleanup_mapping_iov(VirtIOGPU *g, struct iovec *iov, uint32_t count); void virtio_gpu_cleanup_mapping(VirtIOGPU *g, struct virtio_gpu_simple_resource *res); +void virtio_gpu_resource_assign_uuid(VirtIOGPU *g, + struct virtio_gpu_ctrl_command *cmd); void virtio_gpu_process_cmdq(VirtIOGPU *g); void virtio_gpu_device_realize(DeviceState *qdev, Error **errp); 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Tsirkin" , "Stefano Stabellini" , Anthony PERARD , Antonio Caggiano , "Dr . David Alan Gilbert" , Robert Beckett , Dmitry Osipenko , Gert Wollny , =?utf-8?q?Alex_Benn=C3=A9e?= , CC: , Gurchetan Singh , , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , Stefano Stabellini , =?utf-8?q?Christian_K?= =?utf-8?q?=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Antonio Caggiano , Huang Rui Subject: [PATCH v6 09/11] virtio-gpu: Support Venus capset Date: Tue, 19 Dec 2023 15:53:18 +0800 Message-ID: <20231219075320.165227-10-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231219075320.165227-1-ray.huang@amd.com> References: <20231219075320.165227-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F6:EE_|SA1PR12MB5616:EE_ X-MS-Office365-Filtering-Correlation-Id: 4f96fe8b-e27a-486e-071e-08dc0067df5a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: wiXeoCvFzXOBNreRPBZnE+Uoo6BSfyiR7/rR8Cx0T4kw3fGduISpoV6LiNLpxMDMf4Vj7CkTl6wjT72VSKw9+pKIvKguxL9Q690S6rLJGe1Jyp27q6cKk4qb97Q8d2f8qy8ijjT6GmQdif0IzcrMsmlk+ruAKPSMox47lJHqZqV720SuUV7w5i3LP+OlFz9GGLXVz8ECa7/Up6l2hAlU48jl0roEXLYpHN7KQrVee9mwF1UbWTz6T6ra87jucPS8AdhRGSzRaZ2KGzKF7sDOBtT8jsivxA47xPpcSLs7FXr2FB5L6azA6pLXWfd84ah8E6TySMYt5H/HZHBmJwpmz+g1QuUDStQDKoauPYRqakuAwUiADL2tjM7vqeZiuyuLU8AmiruemuyOuy/F+3LFm0X6mzaO5YUYBifHSeG/G2puI8Nob9aUtjiAo2DacJ/31445r81X+bOL9dNFs2gDw8YDQEstwY47uiziXuMo8/jQDuXyCq5g8USMg+BAmbIaSmJnf1UDgEc5Cny8qVFpEL0b6d+G8LmZXBlGAPD53bPGbbr2XTDWEcG8BVeAUy4gM2bXtr7gWCscQcsdCe75zrbOLTUBWP8ia3AQfWX7V0cp5oz1ZVE3Ano7GKL9VkOFAkKMa86JMsim/VC411Evv9oCEJC0C8SHdmcauENMi5ou6+I++wH1BfHLFjdt4983fBay3/ZqlutuGqmh+p99nt3xV4fEoUl+2DxcXfRvuwQDQyGynGbzaCx6VtZas0kQwjpavieTFM5AJLFG2XJx/56mqUqZqSYUS8IXcXyQdpI= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(376002)(39860400002)(346002)(136003)(230922051799003)(451199024)(82310400011)(186009)(1800799012)(64100799003)(46966006)(40470700004)(36840700001)(40460700003)(40480700001)(426003)(16526019)(336012)(2616005)(1076003)(6666004)(7696005)(26005)(82740400003)(921008)(356005)(81166007)(36756003)(86362001)(8936002)(8676002)(4326008)(478600001)(110136005)(36860700001)(5660300002)(7416002)(2906002)(47076005)(83380400001)(41300700001)(70206006)(70586007)(54906003)(316002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2023 07:55:30.7212 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4f96fe8b-e27a-486e-071e-08dc0067df5a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F6.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB5616 From: Antonio Caggiano Add support for the Venus capset, which enables Vulkan support through the Venus Vulkan driver for virtio-gpu. Signed-off-by: Antonio Caggiano Signed-off-by: Huang Rui --- No change in v6. hw/display/virtio-gpu-virgl.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-virgl.c index be9da6e780..f35a751824 100644 --- a/hw/display/virtio-gpu-virgl.c +++ b/hw/display/virtio-gpu-virgl.c @@ -506,6 +506,11 @@ static void virgl_cmd_get_capset_info(VirtIOGPU *g, virgl_renderer_get_cap_set(resp.capset_id, &resp.capset_max_version, &resp.capset_max_size); + } else if (info.capset_index == 2) { + resp.capset_id = VIRTIO_GPU_CAPSET_VENUS; + virgl_renderer_get_cap_set(resp.capset_id, + &resp.capset_max_version, + &resp.capset_max_size); } else { resp.capset_max_version = 0; resp.capset_max_size = 0; @@ -978,10 +983,18 @@ int virtio_gpu_virgl_init(VirtIOGPU *g) int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g) { - uint32_t capset2_max_ver, capset2_max_size; + uint32_t capset2_max_ver, capset2_max_size, num_capsets; + num_capsets = 1; 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pr=C From: Huang Rui To: Akihiko Odaki , =?utf-8?q?Marc-Andr=C3=A9_Lure?= =?utf-8?q?au?= , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Gerd Hoffmann , "Michael S . Tsirkin" , "Stefano Stabellini" , Anthony PERARD , Antonio Caggiano , "Dr . David Alan Gilbert" , Robert Beckett , Dmitry Osipenko , Gert Wollny , =?utf-8?q?Alex_Benn=C3=A9e?= , CC: , Gurchetan Singh , , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , Stefano Stabellini , =?utf-8?q?Christian_K?= =?utf-8?q?=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Antonio Caggiano , Huang Rui Subject: [PATCH v6 10/11] virtio-gpu: Initialize Venus Date: Tue, 19 Dec 2023 15:53:19 +0800 Message-ID: <20231219075320.165227-11-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231219075320.165227-1-ray.huang@amd.com> References: <20231219075320.165227-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F9:EE_|CY8PR12MB7609:EE_ X-MS-Office365-Filtering-Correlation-Id: 4612d029-dba4-4586-d194-08dc0067e3fb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xCLb+vKXrvOzJsJcYukuVIz0BQ+QbCuOItwXMTGhoJBEoahC3U7nTIzUz1mDNezKoY0L0QWTlCPp+WXkCxEEv0nRH0Q4tUR61MmiakDnU0HNyGMk7WgDfXgJBBXUhOag8qsFDwWSpVXevH8wxRdoPpkZhORNX9TFSAJFJOrE5ZNTPhRoQg+RA7Tsy/yAV5nG7nxiGBN68DuiqIYYBslU5zfVoCR/EzvwbH7+8lngqR481tl+t/8mn4ylM+SfmdeTWBSz5sd8JiGSoxwk7LO6xQqKh0pqld2BHCfclGlmPSBimwJthkCHpXE31GGZRt4unZETkGOskKfHz2lb5sT2OWuxgULRL3WFSfjdTeGxNbsepCGaOMMYSOMsCYBMV5Y3zlHREFH/6o8Wef/I245x1JH22wbntj3I56f8Yx5Xu+p/U7qlY+qd49PHlhIwyowq9/cZXTePdfh+vWjjf4ftD8RJBFbrGvOa4UhlRaP5aSa4p5b1hq5d04incxqSkuORiqLg3y10PB27HLeN90wZ4CjMniN66yox2Go1NlXXP4h+ceJ+03ewgQplO79Y1mYFQTUi9Jx03oDzjlXQX6wNXzpT1GMuNwfdT1LJpRb5KD48xIT4Zc9ZO4jpI1uYiDGWlI1j5Jkjd0jZO1xIopGBNPpG2guqfroaJEZzq8tTfmZBdvUtz4ksVrS9TJo+giAmVqF38Iqw9yS0MaqKYe7vENcq316I/tf2JmocGfA8l6onb6NIQx6euRDh2K4EMARUet90zc5WMBlm/ebirIxyCsRD1dn9zDKa2Mt1SQJ8JtY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(39860400002)(346002)(396003)(376002)(230922051799003)(186009)(1800799012)(451199024)(64100799003)(82310400011)(40470700004)(46966006)(36840700001)(40460700003)(1076003)(2616005)(336012)(426003)(26005)(16526019)(7696005)(36860700001)(83380400001)(5660300002)(7416002)(41300700001)(2906002)(4744005)(6666004)(478600001)(316002)(4326008)(8676002)(70206006)(70586007)(54906003)(110136005)(8936002)(82740400003)(86362001)(81166007)(356005)(36756003)(47076005)(921008)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2023 07:55:38.4768 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4612d029-dba4-4586-d194-08dc0067e3fb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F9.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7609 From: Antonio Caggiano Request Venus when initializing VirGL. Signed-off-by: Antonio Caggiano Signed-off-by: Huang Rui --- Changes in v6: - Remove the unstable API flags check because virglrenderer is already 1.0. - Squash the render server flag support into "Initialize Venus". hw/display/virtio-gpu-virgl.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-virgl.c index f35a751824..c523a6717a 100644 --- a/hw/display/virtio-gpu-virgl.c +++ b/hw/display/virtio-gpu-virgl.c @@ -964,6 +964,10 @@ int virtio_gpu_virgl_init(VirtIOGPU *g) } #endif +#ifdef VIRGL_RENDERER_VENUS + flags |= VIRGL_RENDERER_VENUS | VIRGL_RENDERER_RENDER_SERVER; +#endif + ret = virgl_renderer_init(g, flags, &virtio_gpu_3d_cbs); if (ret != 0) { error_report("virgl could not be initialized: %d", ret); From patchwork Tue Dec 19 07:53:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 13497983 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0C00BC46CD2 for ; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Huang Rui To: Akihiko Odaki , =?utf-8?q?Marc-Andr=C3=A9_Lure?= =?utf-8?q?au?= , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Gerd Hoffmann , "Michael S . Tsirkin" , "Stefano Stabellini" , Anthony PERARD , Antonio Caggiano , "Dr . David Alan Gilbert" , Robert Beckett , Dmitry Osipenko , Gert Wollny , =?utf-8?q?Alex_Benn=C3=A9e?= , CC: , Gurchetan Singh , , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , Stefano Stabellini , =?utf-8?q?Christian_K?= =?utf-8?q?=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Huang Rui Subject: [PATCH v6 11/11] virtio-gpu: make blob scanout use dmabuf fd Date: Tue, 19 Dec 2023 15:53:20 +0800 Message-ID: <20231219075320.165227-12-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231219075320.165227-1-ray.huang@amd.com> References: <20231219075320.165227-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FC:EE_|SA1PR12MB8141:EE_ X-MS-Office365-Filtering-Correlation-Id: d7b6ddd3-053f-4938-68f5-08dc0067e860 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2ju7LSNow33RojR281hoe4o+6CoqX1jc20JLHbzOSWR5Ld1uJF691cmiR3/wZzY3guM7PdtTTBw+oScGhpdpWPtOFgNDwKmxf2vNZ9ic6ua8G+cqF8AoyOKNaFtDZ4jIh+FNpMoMXJWez2kFGog+T2TatW+wKdLNGlnWReqwoOfXdaDnSFODRsGD8aR4yUTl45W7hWoldylopexd0kc7KLVtol8CeazsjzXupaS4ySVJgJYvJhlguXve3ORcXtV0iUey8NksmZDnTkPKHRE/11/VUKxAiFLXTAmYzLDzTWhied1m+uyeqArnrmk7t4/7g4v7VK3b0CwDiwpUSLwvbtYBLRIJwvpf2AEYjjsFuCc4/rHKKScus8fSmh13B71G7a8IaWL055wjJ3tvxChVUHOB1e4SoBEhmnwLtMV8yh606h7eWO6nbtHmKx3yhTafe1FGTaoMfo3dLDVRbmfNuPMeRH0BZ+OaoTZ2Dg1hjkUsa99uOT2od5d1V+c4ouHTppDuqlweybOxRs+uwpqv47sx/vgGdgxnfLf1nzo09iUHgfDUYJOSZTk2dngx5t4l9kNifdAS7IgLWSEuyHe5dY3TflcHzYJKgpUUaxDtPNaWO7nndqq9krUokgzkUD64WDmGJFhwBiADUOgzPk+Xeit+Fq2jdNr4xNVEmtYQvEM15ISM2+H/Whef7Ovadc/IqfiiHjcS40EpNFzkhzCwSOVvKOCYop6pxaOs7fvxqV0gEE9BR6TsoO6c0E1ulnRty80eW39oldDuFL9QXKgjOw+g5m6a9QJPRZqfN2o7Hj8= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(136003)(376002)(346002)(39860400002)(230922051799003)(1800799012)(82310400011)(451199024)(186009)(64100799003)(46966006)(36840700001)(40470700004)(40480700001)(478600001)(2616005)(1076003)(70586007)(336012)(426003)(6666004)(83380400001)(316002)(54906003)(110136005)(5660300002)(7696005)(47076005)(8676002)(8936002)(4326008)(26005)(36860700001)(70206006)(16526019)(7416002)(2906002)(40460700003)(81166007)(356005)(82740400003)(41300700001)(921008)(86362001)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2023 07:55:45.8312 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d7b6ddd3-053f-4938-68f5-08dc0067e860 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FC.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8141 From: Robert Beckett This relies on a virglrenderer change to include the dmabuf fd when returning resource info. Signed-off-by: Robert Beckett Signed-off-by: Huang Rui --- Changes in v6: - Add scanout_blob function for virtio-gpu-virgl. - Update for new virgl_gpu_resource. hw/display/virtio-gpu-virgl.c | 104 +++++++++++++++++++++++++++++++++ hw/display/virtio-gpu.c | 4 +- include/hw/virtio/virtio-gpu.h | 6 ++ 3 files changed, 112 insertions(+), 2 deletions(-) diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-virgl.c index c523a6717a..c384225a98 100644 --- a/hw/display/virtio-gpu-virgl.c +++ b/hw/display/virtio-gpu-virgl.c @@ -18,6 +18,7 @@ #include "hw/virtio/virtio.h" #include "hw/virtio/virtio-gpu.h" #include "hw/virtio/virtio-gpu-bswap.h" +#include "hw/virtio/virtio-gpu-pixman.h" #include "ui/egl-helpers.h" @@ -726,6 +727,106 @@ static void virgl_cmd_resource_unmap_blob(VirtIOGPU *g, object_unparent(OBJECT(mr)); } +static void virgl_cmd_set_scanout_blob(VirtIOGPU *g, + struct virtio_gpu_ctrl_command *cmd) +{ + struct virgl_gpu_resource *vres; + struct virtio_gpu_framebuffer fb = { 0 }; + struct virtio_gpu_set_scanout_blob ss; + struct virgl_renderer_resource_info info; + uint64_t fbend; + + VIRTIO_GPU_FILL_CMD(ss); + virtio_gpu_scanout_blob_bswap(&ss); + trace_virtio_gpu_cmd_set_scanout_blob(ss.scanout_id, ss.resource_id, + ss.r.width, ss.r.height, ss.r.x, + ss.r.y); + + if (ss.scanout_id >= g->parent_obj.conf.max_outputs) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal scanout id specified %d", + __func__, ss.scanout_id); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID; + return; + } + + if (ss.resource_id == 0) { + virtio_gpu_disable_scanout(g, ss.scanout_id); + return; + } + + if (ss.width < 16 || + ss.height < 16 || + ss.r.x + ss.r.width > ss.width || + ss.r.y + ss.r.height > ss.height) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal scanout %d bounds for" + " resource %d, rect (%d,%d)+%d,%d, fb %d %d\n", + __func__, ss.scanout_id, ss.resource_id, + ss.r.x, ss.r.y, ss.r.width, ss.r.height, + ss.width, ss.height); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER; + return; + } + + if (!console_has_gl(g->parent_obj.scanout[ss.scanout_id].con)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: unable to scanout blot without GL!\n", __func__); + return; + } + + vres = virgl_gpu_find_resource(g, ss.resource_id); + if (!vres) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: illegal resource specified %d\n", + __func__, ss.resource_id); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; + return; + } + if (virgl_renderer_resource_get_info(ss.resource_id, &info)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: illegal virgl resource specified %d\n", + __func__, ss.resource_id); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; + return; + } + if (!vres->res.dmabuf_fd && info.fd) + vres->res.dmabuf_fd = info.fd; + + fb.format = virtio_gpu_get_pixman_format(ss.format); + if (!fb.format) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: host couldn't handle guest format %d\n", + __func__, ss.format); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER; + return; + } + + fb.bytes_pp = DIV_ROUND_UP(PIXMAN_FORMAT_BPP(fb.format), 8); + fb.width = ss.width; + fb.height = ss.height; + fb.stride = ss.strides[0]; + fb.offset = ss.offsets[0] + ss.r.x * fb.bytes_pp + ss.r.y * fb.stride; + + fbend = fb.offset; + fbend += fb.stride * (ss.r.height - 1); + fbend += fb.bytes_pp * ss.r.width; + if (fbend > vres->res.blob_size) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: fb end out of range\n", + __func__); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER; + return; + } + + g->parent_obj.enable = 1; + if (virtio_gpu_update_dmabuf(g, ss.scanout_id, &vres->res, + &fb, &ss.r)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: failed to update dmabuf\n", __func__); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER; + return; + } + virtio_gpu_update_scanout(g, ss.scanout_id, &vres->res, &ss.r); +} + #endif /* HAVE_VIRGL_RESOURCE_BLOB */ void virtio_gpu_virgl_process_cmd(VirtIOGPU *g, @@ -807,6 +908,9 @@ void virtio_gpu_virgl_process_cmd(VirtIOGPU *g, case VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB: virgl_cmd_resource_unmap_blob(g, cmd); break; + case VIRTIO_GPU_CMD_SET_SCANOUT_BLOB: + virgl_cmd_set_scanout_blob(g, cmd); + break; #endif /* HAVE_VIRGL_RESOURCE_BLOB */ default: cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC; diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c index 466debb256..492f578b4b 100644 --- a/hw/display/virtio-gpu.c +++ b/hw/display/virtio-gpu.c @@ -380,7 +380,7 @@ static void virtio_gpu_resource_create_blob(VirtIOGPU *g, QTAILQ_INSERT_HEAD(&g->reslist, res, next); } -static void virtio_gpu_disable_scanout(VirtIOGPU *g, int scanout_id) +void virtio_gpu_disable_scanout(VirtIOGPU *g, int scanout_id) { struct virtio_gpu_scanout *scanout = &g->parent_obj.scanout[scanout_id]; struct virtio_gpu_simple_resource *res; @@ -592,7 +592,7 @@ static void virtio_unref_resource(pixman_image_t *image, void *data) pixman_image_unref(data); } -static void virtio_gpu_update_scanout(VirtIOGPU *g, +void virtio_gpu_update_scanout(VirtIOGPU *g, uint32_t scanout_id, struct virtio_gpu_simple_resource *res, struct virtio_gpu_rect *r) diff --git a/include/hw/virtio/virtio-gpu.h b/include/hw/virtio/virtio-gpu.h index 76b410fe91..ac2adfb607 100644 --- a/include/hw/virtio/virtio-gpu.h +++ b/include/hw/virtio/virtio-gpu.h @@ -332,6 +332,12 @@ int virtio_gpu_update_dmabuf(VirtIOGPU *g, struct virtio_gpu_framebuffer *fb, struct virtio_gpu_rect *r); +void virtio_gpu_update_scanout(VirtIOGPU *g, + uint32_t scanout_id, + struct virtio_gpu_simple_resource *res, + struct virtio_gpu_rect *r); +void virtio_gpu_disable_scanout(VirtIOGPU *g, int scanout_id); + /* virtio-gpu-3d.c */ void virtio_gpu_virgl_process_cmd(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd);