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Tue, 19 Dec 2023 21:04:17 +0900 (KST) Received: from epsmtrp2.samsung.com (unknown [182.195.40.14]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPA id 20231219115856epcas5p371abeb4264f60309e597b90954e6d58c~iOccah9WH2290022900epcas5p3q; Tue, 19 Dec 2023 11:58:56 +0000 (GMT) Received: from epsmgmcp1.samsung.com (unknown [182.195.42.82]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20231219115856epsmtrp28a370703b93e31bb8b6b26a4170b69ba~iOccZwtbi3243832438epsmtrp2N; Tue, 19 Dec 2023 11:58:56 +0000 (GMT) X-AuditID: b6c32a44-3abff70000002177-ba-658186c10961 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgmcp1.samsung.com (Symantec Messaging Gateway) with SMTP id A3.CC.18939.08581856; Tue, 19 Dec 2023 20:58:56 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20231219115854epsmtip10f680a603d53d3817a7772a0cd8ddffb~iOcaZ7V7F0513305133epsmtip1l; Tue, 19 Dec 2023 11:58:54 +0000 (GMT) From: Varada Pavani To: mturquette@baylibre.com, sboyd@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com Cc: linux-samsung-soc@vger.kernel.org, alim.akhtar@samsung.com, aswani.reddy@samsung.com, pankaj.dubey@samsung.com, Varada Pavani Subject: [PATCH 1/2] dt-bindings: clock: Fix spelling mistake in 'tesla,fsd-clock.yaml' Date: Tue, 19 Dec 2023 17:28:33 +0530 Message-Id: <20231219115834.65720-1-v.pavani@samsung.com> X-Mailer: git-send-email 2.17.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrFKsWRmVeSWpSXmKPExsWy7bCmlu7BtsZUg08P2SwezNvGZnFo81Z2 izV7zzFZzD9yjtWi78VDZouPPfdYLS7vmsNmMeP8PiaLi6dcLRZt/cJucfhNO6vFv2sbWSxW 7frDaLGh9xW7A5/H+xut7B47Z91l99i0qpPN4861PWwefVtWMXp83iQXwBaVbZORmpiSWqSQ mpecn5KZl26r5B0c7xxvamZgqGtoaWGupJCXmJtqq+TiE6DrlpkDdK2SQlliTilQKCCxuFhJ 386mKL+0JFUhI7+4xFYptSAlp8CkQK84Mbe4NC9dLy+1xMrQwMDIFKgwITujq+cle8FD9ort S3axNjBeZ+ti5OSQEDCR+L9sNmMXIxeHkMBuRokfC8+zQzifGCWe7XvJAue0XjvODNPS+fIk G0RiJ6PEzO9XWCGcViaJC52bmUCq2AS0JFZPXQ6WEBF4zygxbfISMIdZYA6jxK2jN1lAqoQF IiXOrFgDZrMIqEpsWrAZzOYVsJR4eOMP1D55idUbDjCDNEsI3GOXOPDlHiNEwkViTUcDlC0s 8er4FnYIW0ri87u9QAdyANnJEu2fuCHCORKXdq9igrDtJQ5cmcMCUsIsoCmxfpc+RFhWYuqp dWAlzAJ8Er2/n0CV80rsmAdjK0ns3DEBypaQeLp6DdQmD4kPz1lBTCGBWInLTzInMMrOQpi/ gJFxFaNkakFxbnpqsmmBYV5qOTyikvNzNzGCE6GWyw7GG/P/6R1iZOJgPMQowcGsJMLrsqg+ VYg3JbGyKrUoP76oNCe1+BCjKTDAJjJLiSbnA1NxXkm8oYmlgYmZmZmJpbGZoZI47+vWuSlC AumJJanZqakFqUUwfUwcnFINTMH/N9Y6WHuV/ogs2Xfr6fW+BVIuSpuWJMaLPuQx858Y+NO8 3INpv8yX01pv/j848qkrYuHuudPUN8zg7ChzPnfw7plgdpWLdRV5125mMq3P+cp/sX1+vJln 0bEpayq7VvX4nljxN56jmY2L4fn3vx2GGwJ/uUdaLneduKq6LPxqFLtQ9sdV9UwzU22V37mc /n3ZdGtt1f2d9X8PLGUILGiefMZ2Z8P06e9mT+d6+Xb+/Ukp7oH/zOu+bBFxiZr+Ztcm3z/z bHsYex5oPnbKVL3d8/l40Py0fW681i7Op872r/zbUrLA6Mq/gluxe3RMJqR5Td5mcdVDtfOx OvMCZ42eyJ5ld2X8TvmnrT3xPliJpTgj0VCLuag4EQCY2moADQQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrCLMWRmVeSWpSXmKPExsWy7bCSnG5Da2OqwaRf/BYP5m1jszi0eSu7 xZq955gs5h85x2rR9+Ihs8XHnnusFpd3zWGzmHF+H5PFxVOuFou2fmG3OPymndXi37WNLBar dv1htNjQ+4rdgc/j/Y1Wdo+ds+6ye2xa1cnmcefaHjaPvi2rGD0+b5ILYIvisklJzcksSy3S t0vgyujqecle8JC9YvuSXawNjNfZuhg5OSQETCQ6X54Esrk4hAS2M0r0rV/CBJGQkNj5rZUZ whaWWPnvOTtEUTOTxI07TSwgCTYBLYnVU5ezgiREBH4CdX/7yALiMAssYJRY1doAViUsEC5x 9NUPsFEsAqoSmxZsBovzClhKPLzxB2qFvMTqDQeYJzDyLGBkWMUomlpQnJuem1xgqFecmFtc mpeul5yfu4kRHJBaQTsYl63/q3eIkYmD8RCjBAezkgivy6L6VCHelMTKqtSi/Pii0pzU4kOM 0hwsSuK8yjmdKUIC6YklqdmpqQWpRTBZJg5OqQYmbkHto58vR6tsnLpGrGy7IePfTtkjYYve r+J9e+TWT9Hre5+FW66WMDBc0zfV64uK/RMv2x+TJon12/0of/Qg8PWZHuOD384f+u2+9MoF LTv/cF/Os4GyR9iPJPNfyTbkWi97ZuP1bYGR1q8mKZRcnHA7VWvBxLtf5c/7u/ruVcj+uLX9 hez7uwmrbr7gZ/7/uuvQuk82AlVbnxrxs+30SPIo5fh5KVG8Xt7TNlXMif//rdJLf08muf61 +1EfutxFNXGz7Qtm/XmbFCf/vPFa6bD2ryfeMg+upa4VuPLUPGTN3uqe3WwzP7e8nFjE8vyz PW9d0VG21ybP+EU2B79I+NMhbedWl+er1pq2JX2dtxJLcUaioRZzUXEiAKj0wRK3AgAA X-CMS-MailID: 20231219115856epcas5p371abeb4264f60309e597b90954e6d58c X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20231219115856epcas5p371abeb4264f60309e597b90954e6d58c References: Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Fix typo 'inteernal' to 'internal' in 'Documentation/devicetree/ bindings/clock/tesla,fsd-clock.yaml'. Signed-off-by: Varada Pavani --- Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml b/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml index dc808e2f8327..b370a10a23a6 100644 --- a/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml +++ b/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml @@ -12,7 +12,7 @@ maintainers: description: | FSD clock controller consist of several clock management unit - (CMU), which generates clocks for various inteernal SoC blocks. + (CMU), which generates clocks for various internal SoC blocks. The root clock comes from external OSC clock (24 MHz). All available clocks are defined as preprocessor macros in From patchwork Tue Dec 19 11:58:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varada Pavani X-Patchwork-Id: 13498195 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C999518628 for ; Tue, 19 Dec 2023 12:04:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="MsSIktPl" Received: from epcas5p1.samsung.com (unknown [182.195.41.39]) by mailout1.samsung.com (KnoxPortal) with ESMTP id 20231219120436epoutp0147de0e330714c0249da12a07a2764be0~iOhZaGcIn2510025100epoutp012 for ; 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Tue, 19 Dec 2023 21:04:34 +0900 (KST) Received: from epsmtrp1.samsung.com (unknown [182.195.40.13]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPA id 20231219115858epcas5p469e925738bcb93ee88842fdea0f9d3f0~iOceah7X21311313113epcas5p4X; Tue, 19 Dec 2023 11:58:58 +0000 (GMT) Received: from epsmgmc1p1new.samsung.com (unknown [182.195.42.40]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20231219115858epsmtrp1fca3f53f13e8cc5e38f75c4d3e574a98~iOceY-HLe0150201502epsmtrp1h; Tue, 19 Dec 2023 11:58:58 +0000 (GMT) X-AuditID: b6c32a4b-60bfd700000025c8-e2-658186d24c6e Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgmc1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 2A.AB.07368.28581856; Tue, 19 Dec 2023 20:58:58 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20231219115856epsmtip1e2f14bde4a42468b3556abec4bcc0547~iOccdsqC20479904799epsmtip1n; Tue, 19 Dec 2023 11:58:56 +0000 (GMT) From: Varada Pavani To: mturquette@baylibre.com, sboyd@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com Cc: linux-samsung-soc@vger.kernel.org, alim.akhtar@samsung.com, aswani.reddy@samsung.com, pankaj.dubey@samsung.com, Varada Pavani Subject: [PATCH 2/2] clk: samsung: Fix typo error and extra space Date: Tue, 19 Dec 2023 17:28:34 +0530 Message-Id: <20231219115834.65720-2-v.pavani@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231219115834.65720-1-v.pavani@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpjk+LIzCtJLcpLzFFi42LZdlhTU/dSW2OqwfebFhYP5m1jszi0eSu7 xZq955gs5h85x2rR9+Ihs8XHnnusFpd3zWGzmHF+H5PFxVOuFou2fmG3OPymndXi37WNLBar dv1htNjQ+4rdgc/j/Y1Wdo+ds+6ye2xa1cnmcefaHjaPvi2rGD0+b5ILYIvKtslITUxJLVJI zUvOT8nMS7dV8g6Od443NTMw1DW0tDBXUshLzE21VXLxCdB1y8wBulZJoSwxpxQoFJBYXKyk b2dTlF9akqqQkV9cYquUWpCSU2BSoFecmFtcmpeul5daYmVoYGBkClSYkJ3x8vg5xoIzYhXP 1txmaWBcINTFyMkhIWAi0fFxLWMXIxeHkMBuRonPDetZIZxPjBL333+DynxjlNjRuI8doeU5 E4gtJLCXUWLp4kqIolYmiV03doIVsQloSayeuhxslIjAe0aJaZOXgDnMAnMYJW4dvcnSxcjB ISzgKNHQD3YIi4CqxIsjJ1hAbF4BS4mDp49BbZOXWL3hADOIzSlgJXF24Q92kDkSAq0cEosu 7GaDKHKRWLz8AiuELSzx6vgWqGYpiZf9bewguyQEkiXaP3FDhHMkLu1exQRh20scuDIH7Bxm AU2J9bv0IcKyElNPrQMrYRbgk+j9/QSqnFdixzwYW0li544JULaExNPVa9ggNnlIzDqmBQmT XkaJ6VsnM05glJuFsGEBI+MqRsnUguLc9NRi0wLjvNRyeKQl5+duYgQnSC3vHYyPHnzQO8TI xMF4iFGCg1lJhNdlUX2qEG9KYmVValF+fFFpTmrxIUZTYPBNZJYSTc4Hpui8knhDE0sDEzMz MxNLYzNDJXHe161zU4QE0hNLUrNTUwtSi2D6mDg4pRqYuiq65qT9YDCRflt69Hnvlg2ZMdO4 pC++srZde0NIbJWQ4Zu3iRF93PtaXr5+JROdm1gas1nJXXzt+ZcWS3O+75p+PTzz1C+W60/m qp3lippXeXeq5Bur6S6MsX2xJ+38Pkd0Hl7ZOf+NwpvTcXE99lNsNT9Fq3JufCW0+/7UHLH9 b7d/ZZYKOjr59fS4BRahDmtKXmStK2Dg1JpeOefT5MW/XeMOnEk6aXCVOUPqxaWSskuHS1hl C9dNfFa0+mRN3qLGHRqK96xTfJ7LpLxcpyVwT2Tnvsrpm7jnm+bu+Pn7V/IehvOSH80PvOQW CDh93nKp/5knM/VtPmxazWCzeXPzmYLzC16XaGavXGhhW6rEUpyRaKjFXFScCABqr3xuGQQA AA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrHLMWRmVeSWpSXmKPExsWy7bCSnG5Ta2OqQVu3lMWDedvYLA5t3spu sWbvOSaL+UfOsVr0vXjIbPGx5x6rxeVdc9gsZpzfx2Rx8ZSrxaKtX9gtDr9pZ7X4d20ji8Wq XX8YLTb0vmJ34PN4f6OV3WPnrLvsHptWdbJ53Lm2h82jb8sqRo/Pm+QC2KK4bFJSczLLUov0 7RK4Ml4eP8dYcEas4tma2ywNjAuEuhg5OSQETCQ6Pj5nArGFBHYzSvR8r4SIS0js/NbKDGEL S6z895y9i5ELqKaZSWLyrRuMIAk2AS2J1VOXs4IkRAR+Mkr0ffvIAuIwCyxglFjV2gDkcHAI CzhKNPSDbWMRUJV4ceQEC4jNK2ApcfD0MXaIDfISqzccANvGKWAlcXbhD3aIiywlZk2axjiB kW8BI8MqRsnUguLc9NxkwwLDvNRyveLE3OLSvHS95PzcTYzgINbS2MF4b/4/vUOMTByMhxgl OJiVRHhdFtWnCvGmJFZWpRblxxeV5qQWH2KU5mBREuc1nDE7RUggPbEkNTs1tSC1CCbLxMEp 1cD0zPFy2+NSpYue8tPr2brLrrNtW54qrJ46Y5v1HDm+OC/n/yEnZqS4fFw1rXCxjNvhQ333 7+atr5srL71m8/7MpwIP77iKffbcqJRw8634hu9Wiqyi+2KE2MVVl2rNtw+3+awrecdv0/Wk pbwlvLmBM/PKD/yYJpx3+fRP4877SzYHNsUulpVpWv2h00iz+so8/1072VbU8urNZbx63qnh esECbVknq7+P8x5KvTDi5t7DdIZnf5eiz/3prbmvthmK3LSL5HxpJvs+VuKk3SH7LTbTm6aI ymjJLot6zcFTl2EnOXX3v5cbpvrZXm/xsuC+a7fZ4HC6VL7D20cdCmd68yTv2TlKvcxMl/x1 uEyJpTgj0VCLuag4EQAwy+7B0QIAAA== X-CMS-MailID: 20231219115858epcas5p469e925738bcb93ee88842fdea0f9d3f0 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20231219115858epcas5p469e925738bcb93ee88842fdea0f9d3f0 References: <20231219115834.65720-1-v.pavani@samsung.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Remove extra spaces and fix spelling mistakes in 'drivers/ clk/samsung/clk-cpu.c' and 'drivers/clk/samsung/clk-cpu.h' Signed-off-by: Varada Pavani --- drivers/clk/samsung/clk-cpu.c | 6 +++--- drivers/clk/samsung/clk-cpu.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c index 3e62ade120c5..18568b8b1b9b 100644 --- a/drivers/clk/samsung/clk-cpu.c +++ b/drivers/clk/samsung/clk-cpu.c @@ -19,7 +19,7 @@ * clock and the corresponding rate changes of the auxillary clocks of the CPU * domain. The platform clock driver provides a clock register configuration * for each configurable rate which is then used to program the clock hardware - * registers to acheive a fast co-oridinated rate change for all the CPU domain + * registers to achieve a fast co-oridinated rate change for all the CPU domain * clocks. * * On a rate change request for the CPU clock, the rate change is propagated @@ -181,7 +181,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, * If the old parent clock speed is less than the clock speed of * the alternate parent, then it should be ensured that at no point * the armclk speed is more than the old_prate until the dividers are - * set. Also workaround the issue of the dividers being set to lower + * set. Also workaround the issue of the dividers being set to lower * values before the parent clock speed is set to new lower speed * (this can result in too high speed of armclk output clocks). */ @@ -303,7 +303,7 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, * If the old parent clock speed is less than the clock speed of * the alternate parent, then it should be ensured that at no point * the armclk speed is more than the old_prate until the dividers are - * set. Also workaround the issue of the dividers being set to lower + * set. Also workaround the issue of the dividers being set to lower * values before the parent clock speed is set to new lower speed * (this can result in too high speed of armclk output clocks). */ diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h index fc9f67a3b22e..e0a1651174e6 100644 --- a/drivers/clk/samsung/clk-cpu.h +++ b/drivers/clk/samsung/clk-cpu.h @@ -33,7 +33,7 @@ struct exynos_cpuclk_cfg_data { * @hw: handle between CCF and CPU clock. * @alt_parent: alternate parent clock to use when switching the speed * of the primary parent clock. - * @ctrl_base: base address of the clock controller. + * @ctrl_base: base address of the clock controller. * @lock: cpu clock domain register access lock. * @cfg: cpu clock rate configuration data. * @num_cfgs: number of array elements in @cfg array.