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[82.149.12.148]) by smtp.gmail.com with ESMTPSA id v14-20020a05600c444e00b0040c58e410a3sm8703224wmn.14.2023.12.20.12.36.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Dec 2023 12:36:11 -0800 (PST) From: Jernej Skrabec To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, wens@csie.org, samuel@sholland.org, andrew@lunn.ch, hkallweit1@gmail.com, linux@armlinux.org.uk, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Corentin Labbe , Jernej Skrabec Subject: [PATCH v5 1/3] phy: handle optional regulator for PHY Date: Wed, 20 Dec 2023 21:35:35 +0100 Message-ID: <20231220203537.83479-2-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231220203537.83479-1-jernej.skrabec@gmail.com> References: <20231220203537.83479-1-jernej.skrabec@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org From: Corentin Labbe Add handling of optional regulators for PHY. Regulators need to be enabled before PHY scanning, so MDIO bus initiate this task. Signed-off-by: Corentin Labbe Signed-off-by: Jernej Skrabec --- drivers/net/mdio/fwnode_mdio.c | 53 ++++++++++++++++++++++++++++++++-- drivers/net/phy/phy_device.c | 6 ++++ include/linux/phy.h | 3 ++ 3 files changed, 60 insertions(+), 2 deletions(-) diff --git a/drivers/net/mdio/fwnode_mdio.c b/drivers/net/mdio/fwnode_mdio.c index fd02f5cbc853..bd5a27eaf40c 100644 --- a/drivers/net/mdio/fwnode_mdio.c +++ b/drivers/net/mdio/fwnode_mdio.c @@ -11,6 +11,7 @@ #include #include #include +#include MODULE_AUTHOR("Calvin Johnson "); MODULE_LICENSE("GPL"); @@ -58,6 +59,40 @@ fwnode_find_mii_timestamper(struct fwnode_handle *fwnode) return register_mii_timestamper(arg.np, arg.args[0]); } +static int +fwnode_regulator_get_bulk_enabled(struct device *dev, + struct fwnode_handle *fwnode, + struct regulator_bulk_data **consumers) +{ + struct device_node *np; + int ret, reg_cnt; + + np = to_of_node(fwnode); + if (!np) + return 0; + + reg_cnt = of_regulator_bulk_get_all(dev, np, consumers); + if (reg_cnt < 0) { + ret = reg_cnt; + goto clean_consumers; + } + + if (reg_cnt == 0) + return 0; + + ret = regulator_bulk_enable(reg_cnt, *consumers); + if (ret) + goto clean_consumers; + + return reg_cnt; + +clean_consumers: + kfree(*consumers); + *consumers = NULL; + + return ret; +} + int fwnode_mdiobus_phy_device_register(struct mii_bus *mdio, struct phy_device *phy, struct fwnode_handle *child, u32 addr) @@ -113,12 +148,13 @@ EXPORT_SYMBOL(fwnode_mdiobus_phy_device_register); int fwnode_mdiobus_register_phy(struct mii_bus *bus, struct fwnode_handle *child, u32 addr) { + struct regulator_bulk_data *consumers = NULL; struct mii_timestamper *mii_ts = NULL; struct pse_control *psec = NULL; struct phy_device *phy; + int rc, reg_cnt; bool is_c45; u32 phy_id; - int rc; psec = fwnode_find_pse_control(child); if (IS_ERR(psec)) @@ -130,6 +166,12 @@ int fwnode_mdiobus_register_phy(struct mii_bus *bus, goto clean_pse; } + reg_cnt = fwnode_regulator_get_bulk_enabled(&bus->dev, child, &consumers); + if (reg_cnt < 0) { + rc = reg_cnt; + goto clean_mii_ts; + } + is_c45 = fwnode_device_is_compatible(child, "ethernet-phy-ieee802.3-c45"); if (is_c45 || fwnode_get_phy_id(child, &phy_id)) phy = get_phy_device(bus, addr, is_c45); @@ -137,9 +179,12 @@ int fwnode_mdiobus_register_phy(struct mii_bus *bus, phy = phy_device_create(bus, addr, phy_id, 0, NULL); if (IS_ERR(phy)) { rc = PTR_ERR(phy); - goto clean_mii_ts; + goto clean_regulators; } + phy->regulator_cnt = reg_cnt; + phy->consumers = consumers; + if (is_acpi_node(child)) { phy->irq = bus->irq[addr]; @@ -174,6 +219,10 @@ int fwnode_mdiobus_register_phy(struct mii_bus *bus, clean_phy: phy_device_free(phy); +clean_regulators: + if (reg_cnt > 0) + regulator_bulk_disable(reg_cnt, consumers); + kfree(consumers); clean_mii_ts: unregister_mii_timestamper(mii_ts); clean_pse: diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 2ce74593d6e4..31b6913ceed1 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include @@ -3400,6 +3401,11 @@ static int phy_remove(struct device *dev) phydev->drv = NULL; + if (phydev->regulator_cnt > 0) + regulator_bulk_disable(phydev->regulator_cnt, phydev->consumers); + + kfree(phydev->consumers); + return 0; } diff --git a/include/linux/phy.h b/include/linux/phy.h index 3cc52826f18e..832cb2d4f76a 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -757,6 +757,9 @@ struct phy_device { void (*phy_link_change)(struct phy_device *phydev, bool up); void (*adjust_link)(struct net_device *dev); + int regulator_cnt; + struct regulator_bulk_data *consumers; + #if IS_ENABLED(CONFIG_MACSEC) /* MACsec management functions */ const struct macsec_ops *macsec_ops; From patchwork Wed Dec 20 20:35:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 13500437 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8E034879E; 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[82.149.12.148]) by smtp.gmail.com with ESMTPSA id v14-20020a05600c444e00b0040c58e410a3sm8703224wmn.14.2023.12.20.12.36.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Dec 2023 12:36:12 -0800 (PST) From: Jernej Skrabec To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, wens@csie.org, samuel@sholland.org, andrew@lunn.ch, hkallweit1@gmail.com, linux@armlinux.org.uk, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Ondrej Jirman , Corentin Labbe , Jernej Skrabec Subject: [PATCH v5 2/3] arm64: dts: allwinner: orange-pi-3: Enable ethernet Date: Wed, 20 Dec 2023 21:35:36 +0100 Message-ID: <20231220203537.83479-3-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231220203537.83479-1-jernej.skrabec@gmail.com> References: <20231220203537.83479-1-jernej.skrabec@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ondrej Jirman Orange Pi 3 has two regulators that power the Realtek RTL8211E PHY. According to the datasheet, both regulators need to be enabled at the same time, or that "phy-io" should be enabled slightly earlier than "ephy" regulator. RTL8211E/RTL8211EG datasheet says: Note 4: 2.5V (or 1.8/1.5V) RGMII power should be risen simultaneously or slightly earlier than 3.3V power. Rising 2.5V (or 1.8/1.5V) power later than 3.3V power may lead to errors. Signed-off-by: Ondrej Jirman Signed-off-by: Corentin Labbe Signed-off-by: Jernej Skrabec --- .../dts/allwinner/sun50i-h6-orangepi-3.dts | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts index 6fc65e8db220..6ed8613a3169 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts @@ -13,6 +13,7 @@ / { compatible = "xunlong,orangepi-3", "allwinner,sun50i-h6"; aliases { + ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; }; @@ -55,6 +56,17 @@ led-1 { }; }; + reg_gmac_2v5: gmac-2v5 { + compatible = "regulator-fixed"; + regulator-name = "gmac-2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ + off-on-delay-us = <100000>; + vin-supply = <®_vcc5v>; + }; + reg_vcc5v: vcc5v { /* board wide 5V supply directly from the DC jack */ compatible = "regulator-fixed"; @@ -113,6 +125,33 @@ &ehci3 { status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; + phy-mode = "rgmii-id"; + phy-handle = <&ext_rgmii_phy>; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + /* + * The board uses 2.5V RGMII signalling. Power sequence to enable + * the phy is to enable GMAC-2V5 and GMAC-3V (aldo2) power rails + * at the same time and to wait 100ms. The driver enables phy-io + * first. Delay is achieved with enable-ramp-delay on reg_aldo2. + */ + phy-io-supply = <®_gmac_2v5>; + ephy-supply = <®_aldo2>; + + reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */ + reset-assert-us = <15000>; + reset-deassert-us = <40000>; + }; +}; + &gpu { mali-supply = <®_dcdcc>; status = "okay"; @@ -211,6 +250,7 @@ reg_aldo2: aldo2 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "vcc33-audio-tv-ephy-mac"; + regulator-enable-ramp-delay = <100000>; }; /* ALDO3 is shorted to CLDO1 */ From patchwork Wed Dec 20 20:35:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 13500438 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7B6548CF4; Wed, 20 Dec 2023 20:36:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="EgjBIk3E" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-40c48d7a7a7so698505e9.3; Wed, 20 Dec 2023 12:36:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1703104574; x=1703709374; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yT4onLSCJnRO5OsDAsoEnYosn/gTLA+uZJCYGELgzHg=; b=EgjBIk3EGX1vIK//UQixsKSQqlfL9c8wTIc07xiTB0xgbiAnI83CDBl4rrdQbOL70W AwkhexIUP/i5nZOOqtPO2tCYjZMbGTcV1E0rhCWNBkLFe6wc8jhAfdMjz57idBHY60oo b4Nr8DBq9fMT4cH8ILd+cWuCt4nZnKYzmGopy02l9UsZpz9Y79IuCvbUaKgCtKJa2VYl ZyOHh3vdnMqP6lsYDJx1e0tX7IxyEuzxuJTxRy4rChdEUJD7zLl6UfXUSN2++poH1L2L go20SpDqZBRVYAODSMCW/bWClEWmHCc+p23Q1M/whjbwk8EBDXca+j8FuuJeHRJU5zXk rlEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703104574; x=1703709374; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yT4onLSCJnRO5OsDAsoEnYosn/gTLA+uZJCYGELgzHg=; b=jbw7Da6jf310kEtoD7OWQ3dVyn/FOqrh2dP4lFrs4+EQ8KHOadAKo/ZFqqTCcfEJej 8tbMR58E/4N+3xdY41saq5btmr3lQvyEir5vPUUwtqOaSt1XwBM9rV//5oC2y4BWEd0Y 4vSI/p7UoOya+gNdJzObDdOoJYrTrjdnnJm78mlAIrbjpVuB17DrLNZ0l2vzkgDwgHlu yZ2zkcRy97DD/Stm8dRy8rXqqnUpWIsILfOIOVNWpuPAoJPKGFIyHlPe+lZuUA8NnLUD PSPK6KsPjTK4edozPaIgJ6ANETzpFAg4vWjhwr4H6pzryJj8Z/VMCZLJLWLjiyDRzOPG ZkeA== X-Gm-Message-State: AOJu0YxAkiTnt0tdxdTj8R3NFn+r61C8EhxKE0RUhaouhTntQpEW0ziZ 4O9kgObUGlSwvPYSKBt4Zto= X-Google-Smtp-Source: AGHT+IEtwDmn2IbaAJwe9giXx+3hvOdMNOXDyWm03ZJR089ngNLl2e5wGYDa27uVUhlHEo6c4G1Paw== X-Received: by 2002:a05:600c:524f:b0:40c:2822:958f with SMTP id fc15-20020a05600c524f00b0040c2822958fmr127184wmb.73.1703104574143; Wed, 20 Dec 2023 12:36:14 -0800 (PST) Received: from localhost.localdomain (82-149-12-148.dynamic.telemach.net. [82.149.12.148]) by smtp.gmail.com with ESMTPSA id v14-20020a05600c444e00b0040c58e410a3sm8703224wmn.14.2023.12.20.12.36.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Dec 2023 12:36:13 -0800 (PST) From: Jernej Skrabec To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, wens@csie.org, samuel@sholland.org, andrew@lunn.ch, hkallweit1@gmail.com, linux@armlinux.org.uk, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Jernej Skrabec Subject: [PATCH v5 3/3] arm64: dts: allwinner: orange-pi-one-plus: Fix ethernet Date: Wed, 20 Dec 2023 21:35:37 +0100 Message-ID: <20231220203537.83479-4-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231220203537.83479-1-jernej.skrabec@gmail.com> References: <20231220203537.83479-1-jernej.skrabec@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Orange Pi One Plus has two regulators that power the Realtek RTL8211E PHY. According to the datasheet, both regulators need to be enabled at the same time, or that "phy-io" should be enabled slightly earlier than "ephy" regulator. RTL8211E/RTL8211EG datasheet says: Note 4: 2.5V (or 1.8/1.5V) RGMII power should be risen simultaneously or slightly earlier than 3.3V power. Rising 2.5V (or 1.8/1.5V) power later than 3.3V power may lead to errors. Original submission ignored these rules, so it works in some cases but not all. On top of that, regulator voltages don't reflect actual ones in hardware. Rework ethernet and PHY nodes to properly reflect HW. Fixes: 7ee32a17e0d6 ("arm64: dts: allwinner: h6: orangepi-one-plus: Enable ethernet") Signed-off-by: Jernej Skrabec --- .../allwinner/sun50i-h6-orangepi-one-plus.dts | 29 ++++++++++++++----- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts index 29a081e72a9b..9c76eecaacce 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts @@ -12,15 +12,15 @@ aliases { ethernet0 = &emac; }; - reg_gmac_3v3: gmac-3v3 { + reg_gmac_2v5: gmac-2v5 { compatible = "regulator-fixed"; - regulator-name = "vcc-gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; + regulator-name = "gmac-2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; enable-active-high; gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ - vin-supply = <®_aldo2>; + off-on-delay-us = <100000>; + vin-supply = <®_vcc5v>; }; }; @@ -29,7 +29,6 @@ &emac { pinctrl-0 = <&ext_rgmii_pins>; phy-mode = "rgmii-id"; phy-handle = <&ext_rgmii_phy>; - phy-supply = <®_gmac_3v3>; allwinner,rx-delay-ps = <200>; allwinner,tx-delay-ps = <200>; status = "okay"; @@ -39,5 +38,21 @@ &mdio { ext_rgmii_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; + /* + * The board uses 2.5V RGMII signalling. Power sequence to enable + * the phy is to enable GMAC-2V5 and GMAC-3V (aldo2) power rails + * at the same time and to wait 100ms. The driver enables phy-io + * first. Delay is achieved with enable-ramp-delay on reg_aldo2. + */ + phy-io-supply = <®_gmac_2v5>; + ephy-supply = <®_aldo2>; + + reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */ + reset-assert-us = <15000>; + reset-deassert-us = <40000>; }; }; + +®_aldo2 { + regulator-enable-ramp-delay = <100000>; +};