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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id j7-20020a056512108700b0050e6df07728sm45983lfg.180.2023.12.22.07.13.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 07:13:22 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: a6475537-a0dc-11ee-98eb-6d05b1d4d9a1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1703258003; x=1703862803; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aUowHZBO2nKGCuJs3sPxh/R77AFxLnhXhueIKgvrApM=; b=Gjc2YyuFkoMVS0OBAeNIKBL0uiGHUVamJGP68ZxS9q0niCSrFrWJP+6Nwg8htS4lZI DkaPW9n4WV81RW5+DZSBpvrk311er3IcY5/ms79HzY+y8KluyRfxoe4w1yzdEbJhMnI7 0o8w7JoRGOkpRzUWfcG4C+w2gfRJrSrCd81JScLvIKbc73uXNRezl8mLKFwBHKImj4lv ewF9NFsDp1+dlL2BAt+1rNCIt8TdfUEVTOvaayZcJWeihSGHBvuhJpg4+oqAM3kfY5Kz IcSAR/yoVqcJl/hz/mTgJNngCJEpu1ud7Vrh5RRXED9FhYd06C+KNI2pslyexonOhQng UM4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703258003; x=1703862803; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aUowHZBO2nKGCuJs3sPxh/R77AFxLnhXhueIKgvrApM=; b=qAZjEkTyVuiF/uT+2RQwCOVvJQGqA2r2upJg6sISBrjZqnSjupb1H+B7kUeY3uBbF7 fRb6j4gDTnpiuzhpiRwpq59xrnjlNnOz6Nm3dJPoWyGasCfaqj2BUf+TMcORaENYqnnt sC8nq8jBy86egXY1ArJGkMLtxQvj7UVa71CMuYtEpx7bJjinnNXS6f2VbenFRoL1Bsj/ +Ntpio4SmCqLcbJAN70/MvJkuI9AMU2TvdizJMNr1GqbtODhFPc2EcoORzEdym5FN5Qr DlPPRdDXN1zsFL4Sj2DXcWacGfUar8ZRkLSZZzictA06AIRRp9AV1+F2FGbLHqi7brQV n+gg== X-Gm-Message-State: AOJu0Yzes1O9R6/nexyewqZ74bHS1CqeaCQFopcylmtkyXZhvdvJbxhu 48yyH9/Qo3PbLYyLumpL4hKdiqTof1U= X-Google-Smtp-Source: AGHT+IFozsh/kiyobZ4kDQYj+0L75QU4g1ERaPe2rKw2zh5mHWUkxXda334d+R1Yp45yknRXl8H6+w== X-Received: by 2002:a05:6512:2fc:b0:50e:242a:775e with SMTP id m28-20020a05651202fc00b0050e242a775emr796416lfq.106.1703258002781; Fri, 22 Dec 2023 07:13:22 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Doug Goldstein , Stefano Stabellini , Alistair Francis , Bob Eshleman , Connor Davis Subject: [PATCH v3 01/34] xen/riscv: disable unnecessary configs Date: Fri, 22 Dec 2023 17:12:45 +0200 Message-ID: <76eeb5b411ccab16ba9696132d6962c169cbf131.1703255175.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 This patch disables unnecessary configs for two cases: 1. By utilizing EXTRA_FIXED_RANDCONFIG and risc-fixed-randconfig.yaml file for randconfig builds (GitLab CI jobs). 2. By using tiny64_defconfig for non-randconfig builds. Signed-off-by: Oleksii Kurochko --- Changes in V3: - Remove EXTRA_FIXED_RANDCONFIG for non-randconfig jobs. For non-randconfig jobs, it is sufficient to disable configs by using the defconfig. - Remove double blank lines in build.yaml file before archlinux-current-gcc-riscv64-debug --- Changes in V2: - update the commit message. - remove xen/arch/riscv/Kconfig changes. --- .../gitlab-ci/riscv-fixed-randconfig.yaml | 27 +++++++++++++++++++ xen/arch/riscv/configs/tiny64_defconfig | 17 ++++++++++++ 2 files changed, 44 insertions(+) diff --git a/automation/gitlab-ci/riscv-fixed-randconfig.yaml b/automation/gitlab-ci/riscv-fixed-randconfig.yaml index f1282b40c9..344f39c2d8 100644 --- a/automation/gitlab-ci/riscv-fixed-randconfig.yaml +++ b/automation/gitlab-ci/riscv-fixed-randconfig.yaml @@ -5,3 +5,30 @@ CONFIG_EXPERT=y CONFIG_GRANT_TABLE=n CONFIG_MEM_ACCESS=n + CONFIG_COVERAGE=n + CONFIG_SCHED_CREDIT=n + CONFIG_SCHED_CREDIT2=n + CONFIG_SCHED_RTDS=n + CONFIG_SCHED_NULL=n + CONFIG_SCHED_ARINC653=n + CONFIG_TRACEBUFFER=n + CONFIG_HYPFS=n + CONFIG_SPECULATIVE_HARDEN_ARRAY=n + CONFIG_ARGO=n + CONFIG_HYPFS_CONFIG=n + CONFIG_CORE_PARKING=n + CONFIG_DEBUG_TRACE=n + CONFIG_IOREQ_SERVER=n + CONFIG_CRASH_DEBUG=n + CONFIG_KEXEC=n + CONFIG_LIVEPATCH=n + CONFIG_NUMA=n + CONFIG_PERF_COUNTERS=n + CONFIG_HAS_PMAP=n + CONFIG_TRACEBUFFER=n + CONFIG_XENOPROF=n + CONFIG_COMPAT=n + CONFIG_COVERAGE=n + CONFIG_UBSAN=n + CONFIG_NEEDS_LIBELF=n + CONFIG_XSM=n diff --git a/xen/arch/riscv/configs/tiny64_defconfig b/xen/arch/riscv/configs/tiny64_defconfig index 09defe236b..35915255e6 100644 --- a/xen/arch/riscv/configs/tiny64_defconfig +++ b/xen/arch/riscv/configs/tiny64_defconfig @@ -7,6 +7,23 @@ # CONFIG_GRANT_TABLE is not set # CONFIG_SPECULATIVE_HARDEN_ARRAY is not set # CONFIG_MEM_ACCESS is not set +# CONFIG_ARGO is not set +# CONFIG_HYPFS_CONFIG is not set +# CONFIG_CORE_PARKING is not set +# CONFIG_DEBUG_TRACE is not set +# CONFIG_IOREQ_SERVER is not set +# CONFIG_CRASH_DEBUG is not setz +# CONFIG_KEXEC is not set +# CONFIG_LIVEPATCH is not set +# CONFIG_NUMA is not set +# CONFIG_PERF_COUNTERS is not set +# CONFIG_HAS_PMAP is not set +# CONFIG_TRACEBUFFER is not set +# CONFIG_XENOPROF is not set +# CONFIG_COMPAT is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +# CONFIG_NEEDS_LIBELF is not set CONFIG_RISCV_64=y CONFIG_DEBUG=y From patchwork Fri Dec 22 15:12:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503438 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2C1FEC46CD2 for ; Fri, 22 Dec 2023 15:13:46 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659408.1028998 (Exim 4.92) (envelope-from ) id 1rGhDL-0007QL-G3; Fri, 22 Dec 2023 15:13:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 659408.1028998; Fri, 22 Dec 2023 15:13:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDL-0007OL-CD; Fri, 22 Dec 2023 15:13:27 +0000 Received: by outflank-mailman (input) for mailman id 659408; Fri, 22 Dec 2023 15:13:26 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDK-0007Ie-IC for xen-devel@lists.xenproject.org; Fri, 22 Dec 2023 15:13:26 +0000 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [2a00:1450:4864:20::12c]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id a7206e26-a0dc-11ee-98eb-6d05b1d4d9a1; Fri, 22 Dec 2023 16:13:25 +0100 (CET) Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-50e70583191so93566e87.3 for ; Fri, 22 Dec 2023 07:13:25 -0800 (PST) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id j7-20020a056512108700b0050e6df07728sm45983lfg.180.2023.12.22.07.13.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 07:13:23 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: a7206e26-a0dc-11ee-98eb-6d05b1d4d9a1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1703258004; x=1703862804; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SyAi66B5lJY94tJWtmKWdmtOpI6CB1uTFL6t5fi0m/g=; b=Rons/20rjHGfl/fPOMzvE0aHDMwx2GxooaFf18i49f/3t3n7RHJ+c41NAWa/QMmJds itHEYXYzSilRuXGZDM8ZI4azLWsi300MCdINmtlgWCNJ06qHe6m6MHeJA1Him/kqK5zW Y3NeZIe85yIahpigB30uNlFpMv2SjO0UObjdT1mmXv9Bzrgi287SxI8nYJAhV7uc+qkI JdAjqwkuGHC7fHHmVynvwrjLDGPQIPoW6PqNcP0nY6Tmg2VIlx8nAMdmDKeWmdYTQlOZ FPvtYsywu8XvehBJWoZidpRSANdFrcnRscglzDqTLmY+FkOIu+vfju8K38vw+VWzO7pV 6pBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703258004; x=1703862804; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SyAi66B5lJY94tJWtmKWdmtOpI6CB1uTFL6t5fi0m/g=; b=W2YVLsflFnC/AI5hizB34o99Qf9dwSvzi5FyMXxlX8iYQcAl0Ks0VJmhkIJZiVZdNZ KUFWNmQJPblbT9uB/Ev2BIpgP8aKeUyOQBzrIC8cPIq5kH1cZPTn9PFYL7uH86SHhLdD tDa2lC9olJTBXyiefy1rpixNTsx01WBAlG8PCMoJNU2U5s+8NbFSi1T6fQw13UDvjGkI DVE8lkKNFU1pn0juKbPPNMbpmeuwTz5+lke+UXNR35i7AH+7gNU9Mn+Y02Y+1qeg0x+g 25rJWKP4ocNXISEXKwDtaAH1azLEn4Y4SCzYKK9jsj8ZHAhm+z8i04vNLEimpJPWu1Lq bxUA== X-Gm-Message-State: AOJu0YxfdLwlTlrERDrSVsgZUhx99etqKz56lKei9NFoidIgr4lb56Bj KXUi7YJoFuWG9iLDb/y5cip3Jt45Txg= X-Google-Smtp-Source: AGHT+IEs+7oMk9zQ5GgSxjUfE24HdOn2Y1G6Urt5uFHmiLl/OsPtyoUC9y51SQjsL9FLWz+ePFoRPw== X-Received: by 2002:ac2:4d12:0:b0:50e:3b1:bf45 with SMTP id r18-20020ac24d12000000b0050e03b1bf45mr705673lfi.18.1703258004475; Fri, 22 Dec 2023 07:13:24 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v3 02/34] xen/riscv: use some asm-generic headers Date: Fri, 22 Dec 2023 17:12:46 +0200 Message-ID: <78a86aa86645c4c23a6294900385264c17a48864.1703255175.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Some headers are the same as asm-generic verions of them so use them instead of arch-specific headers. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- As [PATCH v6 0/9] Introduce generic headers (https://lore.kernel.org/xen-devel/cover.1703072575.git.oleksii.kurochko@gmail.com/) is not stable, the list in asm/Makefile can be changed, but the changes will be easy. --- Changes in V3: - remove monitor.h from the RISC-V asm/Makefile list. - add Acked-by: Jan Beulich --- Changes in V2: - New commit introduced in V2. --- xen/arch/riscv/include/asm/Makefile | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 xen/arch/riscv/include/asm/Makefile diff --git a/xen/arch/riscv/include/asm/Makefile b/xen/arch/riscv/include/asm/Makefile new file mode 100644 index 0000000000..adb752b804 --- /dev/null +++ b/xen/arch/riscv/include/asm/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only +generic-y += altp2m.h +generic-y += device.h +generic-y += div64.h +generic-y += hardirq.h +generic-y += hypercall.h +generic-y += iocap.h +generic-y += numa.h +generic-y += paging.h +generic-y += percpu.h +generic-y += random.h +generic-y += softirq.h +generic-y += vm_event.h From patchwork Fri Dec 22 15:12:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503436 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 543C6C4706F for ; Fri, 22 Dec 2023 15:13:45 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659409.1029021 (Exim 4.92) (envelope-from ) id 1rGhDM-000818-Vn; Fri, 22 Dec 2023 15:13:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 659409.1029021; Fri, 22 Dec 2023 15:13:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDM-00080z-Qx; Fri, 22 Dec 2023 15:13:28 +0000 Received: by outflank-mailman (input) for mailman id 659409; Fri, 22 Dec 2023 15:13:27 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDL-0007Ie-IS for xen-devel@lists.xenproject.org; Fri, 22 Dec 2023 15:13:27 +0000 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [2a00:1450:4864:20::131]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id a7fa042d-a0dc-11ee-98eb-6d05b1d4d9a1; Fri, 22 Dec 2023 16:13:26 +0100 (CET) Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-50e23a4df33so2371240e87.2 for ; Fri, 22 Dec 2023 07:13:26 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/arch/riscv/include/asm/cpufeature.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 xen/arch/riscv/include/asm/cpufeature.h diff --git a/xen/arch/riscv/include/asm/cpufeature.h b/xen/arch/riscv/include/asm/cpufeature.h new file mode 100644 index 0000000000..c08b7d67ad --- /dev/null +++ b/xen/arch/riscv/include/asm/cpufeature.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_RISCV_CPUFEATURE_H +#define __ASM_RISCV_CPUFEATURE_H + +#ifndef __ASSEMBLY__ + +static inline unsigned int cpu_nr_siblings(unsigned int cpu) +{ + return 1; +} + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_RISCV_CPUFEATURE_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Fri Dec 22 15:12:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503439 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D87EC47073 for ; Fri, 22 Dec 2023 15:13:46 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659411.1029040 (Exim 4.92) (envelope-from ) id 1rGhDP-00005Q-E9; Fri, 22 Dec 2023 15:13:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 659411.1029040; Fri, 22 Dec 2023 15:13:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDP-00005G-AL; Fri, 22 Dec 2023 15:13:31 +0000 Received: by outflank-mailman (input) for mailman id 659411; Fri, 22 Dec 2023 15:13:29 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDN-0007Ie-Sv for xen-devel@lists.xenproject.org; Fri, 22 Dec 2023 15:13:29 +0000 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [2a00:1450:4864:20::232]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id a995ebae-a0dc-11ee-98eb-6d05b1d4d9a1; Fri, 22 Dec 2023 16:13:29 +0100 (CET) Received: by mail-lj1-x232.google.com with SMTP id 38308e7fff4ca-2ccae380df2so5219351fa.1 for ; Fri, 22 Dec 2023 07:13:29 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/arch/riscv/include/asm/guest_atomics.h | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 xen/arch/riscv/include/asm/guest_atomics.h diff --git a/xen/arch/riscv/include/asm/guest_atomics.h b/xen/arch/riscv/include/asm/guest_atomics.h new file mode 100644 index 0000000000..98f7df7b6a --- /dev/null +++ b/xen/arch/riscv/include/asm/guest_atomics.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_RISCV_GUEST_ATOMICS_H +#define __ASM_RISCV_GUEST_ATOMICS_H + +#define guest_testop(name) \ +static inline int guest_##name(struct domain *d, int nr, volatile void *p) \ +{ \ + (void) d; \ + (void) nr; \ + (void) p; \ + \ + ASSERT_UNREACHABLE(); \ + \ + return 0; \ +} + +#define guest_bitop(name) \ +static inline void guest_##name(struct domain *d, int nr, volatile void *p) \ +{ \ + (void) d; \ + (void) nr; \ + (void) p; \ + ASSERT_UNREACHABLE(); \ +} + +guest_bitop(set_bit) +guest_bitop(clear_bit) +guest_bitop(change_bit) + +#undef guest_bitop + +guest_testop(test_and_set_bit) +guest_testop(test_and_clear_bit) +guest_testop(test_and_change_bit) + +#undef guest_testop + +#define guest_test_bit(d, nr, p) ((void)(d), test_bit(nr, p)) + +#endif /* __ASM_RISCV_GUEST_ATOMICS_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Fri Dec 22 15:12:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503432 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 43B85C4706C for ; Fri, 22 Dec 2023 15:13:44 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659413.1029054 (Exim 4.92) (envelope-from ) id 1rGhDR-0000Qu-1Y; Fri, 22 Dec 2023 15:13:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 659413.1029054; Fri, 22 Dec 2023 15:13:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDQ-0000QH-Tr; Fri, 22 Dec 2023 15:13:32 +0000 Received: by outflank-mailman (input) for mailman id 659413; Fri, 22 Dec 2023 15:13:32 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDQ-0000EM-4g for xen-devel@lists.xenproject.org; Fri, 22 Dec 2023 15:13:32 +0000 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [2a00:1450:4864:20::136]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id aa03252b-a0dc-11ee-9b0f-b553b5be7939; Fri, 22 Dec 2023 16:13:30 +0100 (CET) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-50e2d00f99cso2277740e87.0 for ; Fri, 22 Dec 2023 07:13:30 -0800 (PST) Received: from fedora.. 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((ops)->fn(args)) @@ -345,7 +347,9 @@ extern int iommu_get_extra_reserved_device_memory(iommu_grdm_t *func, #endif struct domain_iommu { +#ifdef CONFIG_HAS_PASSTHROUGH struct arch_iommu arch; +#endif /* iommu_ops */ const struct iommu_ops *platform_ops; From patchwork Fri Dec 22 15:12:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503440 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BAAFC47077 for ; Fri, 22 Dec 2023 15:13:46 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659412.1029050 (Exim 4.92) (envelope-from ) id 1rGhDQ-0000NI-OB; Fri, 22 Dec 2023 15:13:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 659412.1029050; Fri, 22 Dec 2023 15:13:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDQ-0000N1-JM; Fri, 22 Dec 2023 15:13:32 +0000 Received: by outflank-mailman (input) for mailman id 659412; Fri, 22 Dec 2023 15:13:32 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDQ-0007Ie-3c for xen-devel@lists.xenproject.org; Fri, 22 Dec 2023 15:13:32 +0000 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [2a00:1450:4864:20::12d]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id aae1dd13-a0dc-11ee-98eb-6d05b1d4d9a1; Fri, 22 Dec 2023 16:13:31 +0100 (CET) Received: by mail-lf1-x12d.google.com with SMTP id 2adb3069b0e04-50e6bcca684so531274e87.0 for ; Fri, 22 Dec 2023 07:13:31 -0800 (PST) Received: from fedora.. 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Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich Acked-by: Shawn Anastasio --- Changes in V3: - new patch. --- xen/arch/arm/include/asm/Makefile | 1 + xen/arch/ppc/include/asm/Makefile | 1 + xen/arch/ppc/include/asm/nospec.h | 15 --------------- xen/arch/riscv/include/asm/Makefile | 1 + .../include/asm => include/asm-generic}/nospec.h | 10 +++++----- 5 files changed, 8 insertions(+), 20 deletions(-) delete mode 100644 xen/arch/ppc/include/asm/nospec.h rename xen/{arch/arm/include/asm => include/asm-generic}/nospec.h (54%) diff --git a/xen/arch/arm/include/asm/Makefile b/xen/arch/arm/include/asm/Makefile index c3f4291ee2..dfb4e9e45c 100644 --- a/xen/arch/arm/include/asm/Makefile +++ b/xen/arch/arm/include/asm/Makefile @@ -3,6 +3,7 @@ generic-y += altp2m.h generic-y += device.h generic-y += hardirq.h generic-y += iocap.h +generic-y += nospec.h generic-y += numa.h generic-y += paging.h generic-y += percpu.h diff --git a/xen/arch/ppc/include/asm/Makefile b/xen/arch/ppc/include/asm/Makefile index adb752b804..0e96ad54c3 100644 --- a/xen/arch/ppc/include/asm/Makefile +++ b/xen/arch/ppc/include/asm/Makefile @@ -5,6 +5,7 @@ generic-y += div64.h generic-y += hardirq.h generic-y += hypercall.h generic-y += iocap.h +generic-y += nospec.h generic-y += numa.h generic-y += paging.h generic-y += percpu.h diff --git a/xen/arch/ppc/include/asm/nospec.h b/xen/arch/ppc/include/asm/nospec.h deleted file mode 100644 index b97322e48d..0000000000 --- a/xen/arch/ppc/include/asm/nospec.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* From arch/arm/include/asm/nospec.h. */ -#ifndef __ASM_PPC_NOSPEC_H__ -#define __ASM_PPC_NOSPEC_H__ - -static inline bool evaluate_nospec(bool condition) -{ - return condition; -} - -static inline void block_speculation(void) -{ -} - -#endif /* __ASM_PPC_NOSPEC_H__ */ diff --git a/xen/arch/riscv/include/asm/Makefile b/xen/arch/riscv/include/asm/Makefile index adb752b804..0e96ad54c3 100644 --- a/xen/arch/riscv/include/asm/Makefile +++ b/xen/arch/riscv/include/asm/Makefile @@ -5,6 +5,7 @@ generic-y += div64.h generic-y += hardirq.h generic-y += hypercall.h generic-y += iocap.h +generic-y += nospec.h generic-y += numa.h generic-y += paging.h generic-y += percpu.h diff --git a/xen/arch/arm/include/asm/nospec.h b/xen/include/asm-generic/nospec.h similarity index 54% rename from xen/arch/arm/include/asm/nospec.h rename to xen/include/asm-generic/nospec.h index 51c7aea4f4..5ded9746f3 100644 --- a/xen/arch/arm/include/asm/nospec.h +++ b/xen/include/asm-generic/nospec.h @@ -1,8 +1,8 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright 2018 Amazon.com, Inc. or its affiliates. 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Only rebase. --- xen/arch/riscv/include/asm/setup.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 xen/arch/riscv/include/asm/setup.h diff --git a/xen/arch/riscv/include/asm/setup.h b/xen/arch/riscv/include/asm/setup.h new file mode 100644 index 0000000000..7613a5dbd0 --- /dev/null +++ b/xen/arch/riscv/include/asm/setup.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ASM_RISCV_SETUP_H__ +#define __ASM_RISCV_SETUP_H__ + +#define max_init_domid (0) + +#endif /* __ASM_RISCV_SETUP_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Fri Dec 22 15:12:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503433 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6971BC41535 for ; Fri, 22 Dec 2023 15:13:44 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659415.1029079 (Exim 4.92) (envelope-from ) id 1rGhDU-0001D3-A4; Fri, 22 Dec 2023 15:13:36 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 659415.1029079; Fri, 22 Dec 2023 15:13:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDU-0001Cg-0e; Fri, 22 Dec 2023 15:13:36 +0000 Received: by outflank-mailman (input) for mailman id 659415; Fri, 22 Dec 2023 15:13:35 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDT-0000EM-3P for xen-devel@lists.xenproject.org; Fri, 22 Dec 2023 15:13:35 +0000 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [2a00:1450:4864:20::12d]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id ac0a0b38-a0dc-11ee-9b0f-b553b5be7939; Fri, 22 Dec 2023 16:13:33 +0100 (CET) Received: by mail-lf1-x12d.google.com with SMTP id 2adb3069b0e04-50e64eb3bc7so1191194e87.0 for ; Fri, 22 Dec 2023 07:13:33 -0800 (PST) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id j7-20020a056512108700b0050e6df07728sm45983lfg.180.2023.12.22.07.13.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 07:13:32 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ac0a0b38-a0dc-11ee-9b0f-b553b5be7939 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1703258012; x=1703862812; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7Q3XxAtohZzVdjBCMrkOnkvpWvJ70uTXiyTPxPvaq7s=; b=R71DaK6d1iFDpovI1a3GtSNH9tTpYaFupHU0K2oZ9wxjeUabc/0Z78HePRj9f7d+vo +sFGojNvCRZQ77Jxh9WxVmlslRSDEMAVLkt+cK5oZA6k8ONOZAyIxlfbK2szGg4Rstaz Hc6IMPutUvTYEM96l2AufNoKg7lMKlLjjFrYDqZhxXvNi+tWB9Z8yp54W0TD1qP13aX8 hslpFBZRl70pBV043Kq1gsxmAygwsM3ULISmOnJ2LHHcXUMVN09Ng+YEl+69hAPa0qin n01xnJqiJnhnAwcOvlgn0brBUNmx0GOutYENCZM5h/u/8B0fOfaUtDNXsDTdnp8d4Mud tW2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703258012; x=1703862812; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7Q3XxAtohZzVdjBCMrkOnkvpWvJ70uTXiyTPxPvaq7s=; b=IjhkEtG3dpLAMWpHMaxaTKNriWeGtwHbNjq/2Hy5o4Eec2oaeScF6DKDHyhPV9g8Bi I+EAc/vjSPIspELQZkeptC0tmP6MfG2LVR1dMJ59/wW2ccQxNBfOfmva0YfQQBCPTxSY pzwPgPQAdtfuZQzPFL336lNJQksC+0cYOZJ30A2M22zcF2/1vhdk+isRZET8X5burFmQ vgnnlxp9ERYUqgAxkJ4qIoz6jew0lKCNdOmhEGpcOhTK7gOMnBYs6jo4+4o9rZ/DrzsN Oznhcxapbqw1FjzJOqGTcAImYvNtxP5dCRUHy5lBnnpq6QHuym3i8g1SJDKCwjh8j1os CFXA== X-Gm-Message-State: AOJu0Yx7sW7NGdyasYuKN2DKAgARGmfSMmAb+2NO02VALnUGdR8+yyQG x4U3B0DLvNFRJaCN+/HpsTNFNNOVBS0= X-Google-Smtp-Source: AGHT+IEW9ubjMihjpDo9U++LZhjCgyS3BxzeXAuDpx4kXU0ymEUqqZmZivdoUK3FLQJj/AzT5vUOXQ== X-Received: by 2002:a05:6512:10ca:b0:50e:6a65:fa97 with SMTP id k10-20020a05651210ca00b0050e6a65fa97mr758709lfg.33.1703258012409; Fri, 22 Dec 2023 07:13:32 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v3 09/34] xen/riscv: introduce system.h Date: Fri, 22 Dec 2023 17:12:53 +0200 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V3: - Add SPDX - fix code style issue - change prototype of local_irq_is_enabled to return bool. update the return code. - update the code style --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/system.h | 90 +++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 xen/arch/riscv/include/asm/system.h diff --git a/xen/arch/riscv/include/asm/system.h b/xen/arch/riscv/include/asm/system.h new file mode 100644 index 0000000000..08c12158fc --- /dev/null +++ b/xen/arch/riscv/include/asm/system.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _ASM_RISCV_BARRIER_H +#define _ASM_RISCV_BARRIER_H + +#include + +#include + +#ifndef __ASSEMBLY__ + +#define RISCV_FENCE(p, s) \ + __asm__ __volatile__ ( "fence " #p "," #s : : : "memory" ) + +/* These barriers need to enforce ordering on both devices or memory. */ +#define mb() RISCV_FENCE(iorw, iorw) +#define rmb() RISCV_FENCE(ir, ir) +#define wmb() RISCV_FENCE(ow, ow) + +/* These barriers do not need to enforce ordering on devices, just memory. */ +#define smp_mb() RISCV_FENCE(rw, rw) +#define smp_rmb() RISCV_FENCE(r, r) +#define smp_wmb() RISCV_FENCE(w, w) +#define smp_mb__before_atomic() smp_mb() +#define smp_mb__after_atomic() smp_mb() + +/* +#define smp_store_release(p, v) \ +do { \ + compiletime_assert_atomic_type(*p); \ + RISCV_FENCE(rw, w); \ + WRITE_ONCE(*p, v); \ +} while (0) + +#define smp_load_acquire(p) \ +({ \ + typeof(*p) p1 = READ_ONCE(*p); \ + compiletime_assert_atomic_type(*p); \ + RISCV_FENCE(r,rw); \ + p1; \ +}) +*/ + +static inline unsigned long local_save_flags(void) +{ + return csr_read(sstatus); +} + +static inline void local_irq_enable(void) +{ + csr_set(sstatus, SSTATUS_SIE); +} + +static inline void local_irq_disable(void) +{ + csr_clear(sstatus, SSTATUS_SIE); +} + +#define local_irq_save(x) \ +({ \ + x = csr_read_clear(CSR_SSTATUS, SSTATUS_SIE); \ + local_irq_disable(); \ +}) + +static inline void local_irq_restore(unsigned long flags) +{ + csr_set(CSR_SSTATUS, flags & SSTATUS_SIE); +} + +static inline bool local_irq_is_enabled(void) +{ + unsigned long flags = local_save_flags(); + + return (flags & SSTATUS_SIE) != 0; +} + +#define arch_fetch_and_add(x, v) __sync_fetch_and_add(x, v) + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_RISCV_BARRIER_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Fri Dec 22 15:12:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503442 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3D9BBC47074 for ; Fri, 22 Dec 2023 15:13:46 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659416.1029089 (Exim 4.92) (envelope-from ) id 1rGhDV-0001XA-Om; Fri, 22 Dec 2023 15:13:37 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 659416.1029089; Fri, 22 Dec 2023 15:13:37 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDV-0001WW-HP; Fri, 22 Dec 2023 15:13:37 +0000 Received: by outflank-mailman (input) for mailman id 659416; Fri, 22 Dec 2023 15:13:35 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDT-0007Ie-Bo for xen-devel@lists.xenproject.org; Fri, 22 Dec 2023 15:13:35 +0000 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [2a00:1450:4864:20::129]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id ac920e5b-a0dc-11ee-98eb-6d05b1d4d9a1; Fri, 22 Dec 2023 16:13:34 +0100 (CET) Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-50e6e7afc6aso248187e87.0 for ; Fri, 22 Dec 2023 07:13:34 -0800 (PST) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id j7-20020a056512108700b0050e6df07728sm45983lfg.180.2023.12.22.07.13.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 07:13:32 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ac920e5b-a0dc-11ee-98eb-6d05b1d4d9a1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1703258014; x=1703862814; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2JE4E+ikBT3kCGEtmaswU2jTg1kUfQURiufyZCoF+Bw=; b=SpLyBQB0vvB7iwXJddZrKFNigHNDBLqebbJbR5pbZVqzCXYR0YthCVBXlvnO7uJ+0l ysqG8EXslSCby8rT0rkO2HeaWc8o9sahqgcVfFtwz8x9g8v3NEhwBKUKlAM+M7rza+Tu donQQt/c5cwJNG6gj3SEMkI/lk5m0VZy/9fk8dnl0Q3U5TsLKsylnEWAPGlbo/7m+Pow dpFNV2pXVJB3F+IMLTbNlD5uAk7ng9EXb68xG+/19re4EBQvLRa7lB0KnT+YQCZFg0RK HhVdyl3kAsflV4B+oJSxB6/tZ0bIzve180cRW4Kn2QhJH7tpdXkt+1QrFWeAmDvCUvii prmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703258014; x=1703862814; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2JE4E+ikBT3kCGEtmaswU2jTg1kUfQURiufyZCoF+Bw=; b=SlcJ70GL+42Jwwjudt19lZOYmMk9tcz6JPB5/e+FX5uEx8j92yJ1Ls6xKFcNj1SjXl sH226+YdL81/tDSGgbk4Qpzfv/oyg05BLlR2FwKMguPaiTltU+8kebWE4slSSTtiStj1 ncAGAw2VsH4e2s+AIKcYTud9uKW5b6X/rplgV+oOJlJ7beyrIODPdEkW3tCj+xZO9AL1 YLKY6DwvVYPPvz5j1Y3qt+XIb9AnZV4yV9tbe51mzPR+WbU3h/pISi9xp8pXRYNOmZ4D YEiNlDK5WOU2KH1IHJh/rxi+mSjCTIMZHzmyPBPK/rRbOkrstphWXBuow/GR6+YXRiAB vndQ== X-Gm-Message-State: AOJu0YxNiXfSyLG/FqDoriJ1MHVtXhPZ1hhhAGNKZPs3EASNnTAHGRz9 KKGyHN5KHWT7IufUKTjGMEgpDpV3CqE= X-Google-Smtp-Source: AGHT+IGpd/0hiB+zCZilXc4I6ZZfGlmkv6Pk7jLrKmo5auefyzV8pg3QMFMrfPUbTX4YIECUkj/dQg== X-Received: by 2002:a05:6512:311b:b0:50e:6888:78d5 with SMTP id n27-20020a056512311b00b0050e688878d5mr769196lfb.3.1703258013676; Fri, 22 Dec 2023 07:13:33 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v3 10/34] xen/riscv: introduce bitops.h Date: Fri, 22 Dec 2023 17:12:54 +0200 Message-ID: <841d59c3950970f4937da200cf8f04aa39132e14.1703255175.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Taken from Linux-6.4.0-rc1 Xen's bitops.h consists of several Linux's headers: * linux/arch/include/asm/bitops.h: * The following function were removed as they aren't used in Xen: * test_and_change_bit * test_and_set_bit_lock * clear_bit_unlock * __clear_bit_unlock * The following functions were renamed in the way how they are used by common code: * __test_and_set_bit * __test_and_clear_bit * The declaration and implementation of the following functios were updated to make Xen build happy: * clear_bit * set_bit * __test_and_clear_bit * __test_and_set_bit * linux/include/asm-generic/bitops/find.h ( only few function declaration were taken, as implementation will be provided by Xen ). * linux/arch/include/linux/bits.h ( taken only definitions for BIT_MASK, BIT_WORD, BITS_PER_BYTE ) Additionaly, the following bit ops are introduced: * __ffs * ffsl * fls * flsl * ffs * ffz * find_first_bit_set * hweight64 * test_bit Some of the introduced bit operations are included in asm-generic, as they exhibit similarity across multiple architectures. Signed-off-by: Oleksii Kurochko --- Changes in V3: - update the commit message - Introduce the following asm-generic bitops headers: create mode 100644 xen/arch/riscv/include/asm/bitops.h create mode 100644 xen/include/asm-generic/bitops/bitops-bits.h create mode 100644 xen/include/asm-generic/bitops/ffs.h create mode 100644 xen/include/asm-generic/bitops/ffz.h create mode 100644 xen/include/asm-generic/bitops/find-first-bit-set.h create mode 100644 xen/include/asm-generic/bitops/fls.h create mode 100644 xen/include/asm-generic/bitops/flsl.h create mode 100644 xen/include/asm-generic/bitops/hweight.h create mode 100644 xen/include/asm-generic/bitops/test-bit.h - switch some bitops functions to asm-generic's versions. - re-sync some macros with Linux kernel version mentioned in the commit message. - Xen code style fixes. --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/bitops.h | 267 ++++++++++++++++++ xen/include/asm-generic/bitops/bitops-bits.h | 10 + xen/include/asm-generic/bitops/ffs.h | 9 + xen/include/asm-generic/bitops/ffz.h | 13 + .../asm-generic/bitops/find-first-bit-set.h | 17 ++ xen/include/asm-generic/bitops/fls.h | 18 ++ xen/include/asm-generic/bitops/flsl.h | 10 + xen/include/asm-generic/bitops/hweight.h | 13 + xen/include/asm-generic/bitops/test-bit.h | 16 ++ 9 files changed, 373 insertions(+) create mode 100644 xen/arch/riscv/include/asm/bitops.h create mode 100644 xen/include/asm-generic/bitops/bitops-bits.h create mode 100644 xen/include/asm-generic/bitops/ffs.h create mode 100644 xen/include/asm-generic/bitops/ffz.h create mode 100644 xen/include/asm-generic/bitops/find-first-bit-set.h create mode 100644 xen/include/asm-generic/bitops/fls.h create mode 100644 xen/include/asm-generic/bitops/flsl.h create mode 100644 xen/include/asm-generic/bitops/hweight.h create mode 100644 xen/include/asm-generic/bitops/test-bit.h diff --git a/xen/arch/riscv/include/asm/bitops.h b/xen/arch/riscv/include/asm/bitops.h new file mode 100644 index 0000000000..d210f529c8 --- /dev/null +++ b/xen/arch/riscv/include/asm/bitops.h @@ -0,0 +1,267 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2012 Regents of the University of California */ + +#ifndef _ASM_RISCV_BITOPS_H +#define _ASM_RISCV_BITOPS_H + +#include + +#include + +/* Based on linux/arch/include/linux/bits.h */ + +#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) +#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) + +#define __set_bit(n,p) set_bit(n,p) +#define __clear_bit(n,p) clear_bit(n,p) + +/* Based on linux/arch/include/asm/bitops.h */ + +#if ( BITS_PER_LONG == 64 ) +#define __AMO(op) "amo" #op ".d" +#elif ( BITS_PER_LONG == 32 ) +#define __AMO(op) "amo" #op ".w" +#else +#error "Unexpected BITS_PER_LONG" +#endif + +#define __test_and_op_bit_ord(op, mod, nr, addr, ord) \ +({ \ + unsigned long __res, __mask; \ + __mask = BIT_MASK(nr); \ + __asm__ __volatile__ ( \ + __AMO(op) #ord " %0, %2, %1" \ + : "=r" (__res), "+A" (addr[BIT_WORD(nr)]) \ + : "r" (mod(__mask)) \ + : "memory"); \ + ((__res & __mask) != 0); \ +}) + +#define __op_bit_ord(op, mod, nr, addr, ord) \ + __asm__ __volatile__ ( \ + __AMO(op) #ord " zero, %1, %0" \ + : "+A" (addr[BIT_WORD(nr)]) \ + : "r" (mod(BIT_MASK(nr))) \ + : "memory"); + +#define __test_and_op_bit(op, mod, nr, addr) \ + __test_and_op_bit_ord(op, mod, nr, addr, .aqrl) +#define __op_bit(op, mod, nr, addr) \ + __op_bit_ord(op, mod, nr, addr, ) + +/* Bitmask modifiers */ +#define __NOP(x) (x) +#define __NOT(x) (~(x)) + +/** + * __test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation may be reordered on other architectures than x86. + */ +static inline int __test_and_set_bit(int nr, volatile void *p) +{ + volatile uint32_t *addr = p; + + return __test_and_op_bit(or, __NOP, nr, addr); +} + +/** + * __test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation can be reordered on other architectures other than x86. + */ +static inline int __test_and_clear_bit(int nr, volatile void *p) +{ + volatile uint32_t *addr = p; + + return __test_and_op_bit(and, __NOT, nr, addr); +} + +/** + * set_bit - Atomically set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Note: there are no guarantees that this function will not be reordered + * on non x86 architectures, so if you are writing portable code, + * make sure not to rely on its reordering guarantees. + * + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void set_bit(int nr, volatile void *p) +{ + volatile uint32_t *addr = p; + + __op_bit(or, __NOP, nr, addr); +} + +/** + * clear_bit - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * Note: there are no guarantees that this function will not be reordered + * on non x86 architectures, so if you are writing portable code, + * make sure not to rely on its reordering guarantees. + */ +static inline void clear_bit(int nr, volatile void *p) +{ + volatile uint32_t *addr = p; + + __op_bit(and, __NOT, nr, addr); +} + +#undef __test_and_op_bit +#undef __op_bit +#undef __NOP +#undef __NOT +#undef __AMO + +#define test_and_set_bit __test_and_set_bit +#define test_and_clear_bit __test_and_clear_bit + +/* Based on linux/include/asm-generic/bitops/find.h */ + +#ifndef find_next_bit +/** + * find_next_bit - find the next set bit in a memory region + * @addr: The address to base the search on + * @offset: The bitnumber to start searching at + * @size: The bitmap size in bits + */ +extern unsigned long find_next_bit(const unsigned long *addr, unsigned long + size, unsigned long offset); +#endif + +#ifndef find_next_zero_bit +/** + * find_next_zero_bit - find the next cleared bit in a memory region + * @addr: The address to base the search on + * @offset: The bitnumber to start searching at + * @size: The bitmap size in bits + */ +extern unsigned long find_next_zero_bit(const unsigned long *addr, unsigned + long size, unsigned long offset); +#endif + +/** + * find_first_bit - find the first set bit in a memory region + * @addr: The address to start the search at + * @size: The maximum size to search + * + * Returns the bit number of the first set bit. + */ +extern unsigned long find_first_bit(const unsigned long *addr, + unsigned long size); + +/** + * find_first_zero_bit - find the first cleared bit in a memory region + * @addr: The address to start the search at + * @size: The maximum size to search + * + * Returns the bit number of the first cleared bit. + */ +extern unsigned long find_first_zero_bit(const unsigned long *addr, + unsigned long size); + +/** + * ffs - find first bit in word. + * @word: The word to search + * + * Returns 0 if no bit exists, otherwise returns 1-indexed bit location. + */ +static inline unsigned long __ffs(unsigned long word) +{ + int num = 0; + +#if BITS_PER_LONG == 64 + if ((word & 0xffffffff) == 0) { + num += 32; + word >>= 32; + } +#endif + if ((word & 0xffff) == 0) { + num += 16; + word >>= 16; + } + if ((word & 0xff) == 0) { + num += 8; + word >>= 8; + } + if ((word & 0xf) == 0) { + num += 4; + word >>= 4; + } + if ((word & 0x3) == 0) { + num += 2; + word >>= 2; + } + if ((word & 0x1) == 0) + num += 1; + return num; +} + +/** + * ffsl - find first bit in long. + * @word: The word to search + * + * Returns 0 if no bit exists, otherwise returns 1-indexed bit location. + */ +static inline unsigned int ffsl(unsigned long word) +{ + int num = 1; + + if (!word) + return 0; + +#if BITS_PER_LONG == 64 + if ((word & 0xffffffff) == 0) { + num += 32; + word >>= 32; + } +#endif + if ((word & 0xffff) == 0) { + num += 16; + word >>= 16; + } + if ((word & 0xff) == 0) { + num += 8; + word >>= 8; + } + if ((word & 0xf) == 0) { + num += 4; + word >>= 4; + } + if ((word & 0x3) == 0) { + num += 2; + word >>= 2; + } + if ((word & 0x1) == 0) + num += 1; + return num; +} + +#include +#include +#include +#include +#include +#include +#include + +#endif /* _ASM_RISCV_BITOPS_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/asm-generic/bitops/bitops-bits.h b/xen/include/asm-generic/bitops/bitops-bits.h new file mode 100644 index 0000000000..8a57e47c63 --- /dev/null +++ b/xen/include/asm-generic/bitops/bitops-bits.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_GENERIC_BITOPS_BITS_H_ +#define _ASM_GENERIC_BITOPS_BITS_H_ + +#define BITOP_BITS_PER_WORD 32 +#define BITOP_MASK(nr) (1UL << ((nr) % BITOP_BITS_PER_WORD)) +#define BITOP_WORD(nr) ((nr) / BITOP_BITS_PER_WORD) +#define BITS_PER_BYTE 8 + +#endif /* _ASM_GENERIC_BITOPS_BITS_H_ */ \ No newline at end of file diff --git a/xen/include/asm-generic/bitops/ffs.h b/xen/include/asm-generic/bitops/ffs.h new file mode 100644 index 0000000000..3f75fded14 --- /dev/null +++ b/xen/include/asm-generic/bitops/ffs.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_GENERIC_BITOPS_FFS_H_ +#define _ASM_GENERIC_BITOPS_FFS_H_ + +#include + +#define ffs(x) ({ unsigned int t_ = (x); fls(ISOLATE_LSB(t_)); }) + +#endif /* _ASM_GENERIC_BITOPS_FFS_H_ */ diff --git a/xen/include/asm-generic/bitops/ffz.h b/xen/include/asm-generic/bitops/ffz.h new file mode 100644 index 0000000000..92c35455d5 --- /dev/null +++ b/xen/include/asm-generic/bitops/ffz.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_GENERIC_BITOPS_FFZ_H_ +#define _ASM_GENERIC_BITOPS_FFZ_H_ + +/* + * ffz - find first zero in word. + * @word: The word to search + * + * Undefined if no zero exists, so code should check against ~0UL first. + */ +#define ffz(x) __ffs(~(x)) + +#endif /* _ASM_GENERIC_BITOPS_FFZ_H_ */ \ No newline at end of file diff --git a/xen/include/asm-generic/bitops/find-first-bit-set.h b/xen/include/asm-generic/bitops/find-first-bit-set.h new file mode 100644 index 0000000000..8ae9751b11 --- /dev/null +++ b/xen/include/asm-generic/bitops/find-first-bit-set.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_GENERIC_BITOPS_FIND_FIRST_BIT_SET_H_ +#define _ASM_GENERIC_BITOPS_FIND_FIRST_BIT_SET_H_ + +/** + * find_first_set_bit - find the first set bit in @word + * @word: the word to search + * + * Returns the bit-number of the first set bit (first bit being 0). + * The input must *not* be zero. + */ +static inline unsigned int find_first_set_bit(unsigned long word) +{ + return ffsl(word) - 1; +} + +#endif /* _ASM_GENERIC_BITOPS_FIND_FIRST_BIT_SET_H_ */ \ No newline at end of file diff --git a/xen/include/asm-generic/bitops/fls.h b/xen/include/asm-generic/bitops/fls.h new file mode 100644 index 0000000000..f232925080 --- /dev/null +++ b/xen/include/asm-generic/bitops/fls.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_GENERIC_BITOPS_FLS_H_ +#define _ASM_GENERIC_BITOPS_FLS_H_ + +/** + * fls - find last (most-significant) bit set + * @x: the word to search + * + * This is defined the same way as ffs. + * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. + */ + +static inline int fls(unsigned int x) +{ + return generic_fls(x); +} + +#endif /* _ASM_GENERIC_BITOPS_FLS_H_ */ \ No newline at end of file diff --git a/xen/include/asm-generic/bitops/flsl.h b/xen/include/asm-generic/bitops/flsl.h new file mode 100644 index 0000000000..127221056e --- /dev/null +++ b/xen/include/asm-generic/bitops/flsl.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_GENERIC_BITOPS_FLSL_H_ +#define _ASM_GENERIC_BITOPS_FLSL_H_ + +static inline int flsl(unsigned long x) +{ + return generic_flsl(x); +} + +#endif /* _ASM_GENERIC_BITOPS_FLSL_H_ */ \ No newline at end of file diff --git a/xen/include/asm-generic/bitops/hweight.h b/xen/include/asm-generic/bitops/hweight.h new file mode 100644 index 0000000000..0d7577054e --- /dev/null +++ b/xen/include/asm-generic/bitops/hweight.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_GENERIC_BITOPS_HWEIGHT_H_ +#define _ASM_GENERIC_BITOPS_HWEIGHT_H_ + +/* + * hweightN - returns the hamming weight of a N-bit word + * @x: the word to weigh + * + * The Hamming Weight of a number is the total number of bits set in it. + */ +#define hweight64(x) generic_hweight64(x) + +#endif /* _ASM_GENERIC_BITOPS_HWEIGHT_H_ */ diff --git a/xen/include/asm-generic/bitops/test-bit.h b/xen/include/asm-generic/bitops/test-bit.h new file mode 100644 index 0000000000..9fa36652e3 --- /dev/null +++ b/xen/include/asm-generic/bitops/test-bit.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_GENERIC_BITOPS_TESTBIT_H_ +#define _ASM_GENERIC_BITOPS_TESTBIT_H_ + +/** + * test_bit - Determine whether a bit is set + * @nr: bit number to test + * @addr: Address to start counting from + */ +static inline int test_bit(int nr, const volatile void *addr) +{ + const volatile unsigned int *p = addr; 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Only rebase. --- xen/arch/riscv/include/asm/flushtlb.h | 33 +++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 xen/arch/riscv/include/asm/flushtlb.h diff --git a/xen/arch/riscv/include/asm/flushtlb.h b/xen/arch/riscv/include/asm/flushtlb.h new file mode 100644 index 0000000000..3bdcb08e3a --- /dev/null +++ b/xen/arch/riscv/include/asm/flushtlb.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_RISCV_FLUSHTLB_H__ +#define __ASM_RISCV_FLUSHTLB_H__ + +#include + +/* + * Filter the given set of CPUs, removing those that definitely flushed their + * TLB since @page_timestamp. + */ +/* XXX lazy implementation just doesn't clear anything.... */ +static inline void tlbflush_filter(cpumask_t *mask, uint32_t page_timestamp) {} + +#define tlbflush_current_time() (0) + +static inline void page_set_tlbflush_timestamp(struct page_info *page) +{ + BUG(); +} + +/* Flush specified CPUs' TLBs */ +void arch_flush_tlb_mask(const cpumask_t *mask); + +#endif /* __ASM_RISCV_FLUSHTLB_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Fri Dec 22 15:12:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503443 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4228C4706E for ; Fri, 22 Dec 2023 15:13:48 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659418.1029103 (Exim 4.92) (envelope-from ) id 1rGhDX-0001qZ-GV; Fri, 22 Dec 2023 15:13:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 659418.1029103; Fri, 22 Dec 2023 15:13:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDX-0001o8-26; Fri, 22 Dec 2023 15:13:39 +0000 Received: by outflank-mailman (input) for mailman id 659418; Fri, 22 Dec 2023 15:13:37 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDV-0007Ie-CR for xen-devel@lists.xenproject.org; Fri, 22 Dec 2023 15:13:37 +0000 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [2a00:1450:4864:20::12e]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id adcc1087-a0dc-11ee-98eb-6d05b1d4d9a1; Fri, 22 Dec 2023 16:13:36 +0100 (CET) Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-50e23a4df33so2371452e87.2 for ; Fri, 22 Dec 2023 07:13:36 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/arch/riscv/include/asm/smp.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 xen/arch/riscv/include/asm/smp.h diff --git a/xen/arch/riscv/include/asm/smp.h b/xen/arch/riscv/include/asm/smp.h new file mode 100644 index 0000000000..336db5906e --- /dev/null +++ b/xen/arch/riscv/include/asm/smp.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_RISCV_SMP_H +#define __ASM_RISCV_SMP_H + +#include +#include + +DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_mask); +DECLARE_PER_CPU(cpumask_var_t, cpu_core_mask); + +#define cpu_is_offline(cpu) unlikely(!cpu_online(cpu)) + +/* + * Do we, for platform reasons, need to actually keep CPUs online when we + * would otherwise prefer them to be off? + */ +#define park_offline_cpus false + +#endif + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Fri Dec 22 15:12:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503463 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 35193C41535 for ; Fri, 22 Dec 2023 15:27:42 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659587.1029299 (Exim 4.92) (envelope-from ) id 1rGhR0-0001wm-1H; Fri, 22 Dec 2023 15:27:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 659587.1029299; Fri, 22 Dec 2023 15:27:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhQz-0001wf-Uv; Fri, 22 Dec 2023 15:27:33 +0000 Received: by outflank-mailman (input) for mailman id 659587; Fri, 22 Dec 2023 15:27:32 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDW-0007Ie-RV for xen-devel@lists.xenproject.org; Fri, 22 Dec 2023 15:13:38 +0000 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [2a00:1450:4864:20::132]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id aeb859c4-a0dc-11ee-98eb-6d05b1d4d9a1; Fri, 22 Dec 2023 16:13:38 +0100 (CET) Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-50e3cdcf010so2163803e87.2 for ; Fri, 22 Dec 2023 07:13:38 -0800 (PST) Received: from fedora.. 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Addionally, were updated: * add emulation of {cmp}xchg for 1/2 byte types * replace tabs with spaces * replace __* varialbed with *__ Signed-off-by: Oleksii Kurochko --- Changes in V3: - update the commit message - add emulation of {cmp}xchg_... for 1 and 2 bytes types --- Changes in V2: - update the comment at the top of the header. - change xen/lib.h to xen/bug.h. - sort inclusion of headers properly. --- xen/arch/riscv/include/asm/cmpxchg.h | 496 +++++++++++++++++++++++++++ 1 file changed, 496 insertions(+) create mode 100644 xen/arch/riscv/include/asm/cmpxchg.h diff --git a/xen/arch/riscv/include/asm/cmpxchg.h b/xen/arch/riscv/include/asm/cmpxchg.h new file mode 100644 index 0000000000..916776c403 --- /dev/null +++ b/xen/arch/riscv/include/asm/cmpxchg.h @@ -0,0 +1,496 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (C) 2014 Regents of the University of California */ + +#ifndef _ASM_RISCV_CMPXCHG_H +#define _ASM_RISCV_CMPXCHG_H + +#include +#include + +#include +#include +#include + +#define __xchg_relaxed(ptr, new, size) \ +({ \ + __typeof__(ptr) ptr__ = (ptr); \ + __typeof__(new) new__ = (new); \ + __typeof__(*(ptr)) ret__; \ + switch (size) \ + { \ + case 4: \ + asm volatile( \ + " amoswap.w %0, %2, %1\n" \ + : "=r" (ret__), "+A" (*ptr__) \ + : "r" (new__) \ + : "memory" ); \ + break; \ + case 8: \ + asm volatile( \ + " amoswap.d %0, %2, %1\n" \ + : "=r" (ret__), "+A" (*ptr__) \ + : "r" (new__) \ + : "memory" ); \ + break; \ + default: \ + ASSERT_UNREACHABLE(); \ + } \ + ret__; \ +}) + +#define xchg_relaxed(ptr, x) \ +({ \ + __typeof__(*(ptr)) x_ = (x); \ + (__typeof__(*(ptr))) __xchg_relaxed((ptr), x_, sizeof(*(ptr))); \ +}) + +#define __xchg_acquire(ptr, new, size) \ +({ \ + __typeof__(ptr) ptr__ = (ptr); \ + __typeof__(new) new__ = (new); \ + __typeof__(*(ptr)) ret__; \ + switch (size) \ + { \ + case 4: \ + asm volatile( \ + " amoswap.w %0, %2, %1\n" \ + RISCV_ACQUIRE_BARRIER \ + : "=r" (ret__), "+A" (*ptr__) \ + : "r" (new__) \ + : "memory" ); \ + break; \ + case 8: \ + asm volatile( \ + " amoswap.d %0, %2, %1\n" \ + RISCV_ACQUIRE_BARRIER \ + : "=r" (ret__), "+A" (*ptr__) \ + : "r" (new__) \ + : "memory" ); \ + break; \ + default: \ + ASSERT_UNREACHABLE(); \ + } \ + ret__; \ +}) + +#define xchg_acquire(ptr, x) \ +({ \ + __typeof__(*(ptr)) x_ = (x); \ + (__typeof__(*(ptr))) __xchg_acquire((ptr), x_, sizeof(*(ptr))); \ +}) + +#define __xchg_release(ptr, new, size) \ +({ \ + __typeof__(ptr) ptr__ = (ptr); \ + __typeof__(new) new__ = (new); \ + __typeof__(*(ptr)) ret__; \ + switch (size) \ + { \ + case 4: \ + asm volatile ( \ + RISCV_RELEASE_BARRIER \ + " amoswap.w %0, %2, %1\n" \ + : "=r" (ret__), "+A" (*ptr__) \ + : "r" (new__) \ + : "memory"); \ + break; \ + case 8: \ + asm volatile ( \ + RISCV_RELEASE_BARRIER \ + " amoswap.d %0, %2, %1\n" \ + : "=r" (ret__), "+A" (*ptr__) \ + : "r" (new__) \ + : "memory"); \ + break; \ + default: \ + ASSERT_UNREACHABLE(); \ + } \ + ret__; \ +}) + +#define xchg_release(ptr, x) \ +({ \ + __typeof__(*(ptr)) x_ = (x); \ + (__typeof__(*(ptr))) __xchg_release((ptr), x_, sizeof(*(ptr))); \ +}) + +static always_inline uint32_t __xchg_case_4(volatile uint32_t *ptr, + uint32_t new) +{ + __typeof__(*(ptr)) ret; + + asm volatile ( + " amoswap.w.aqrl %0, %2, %1\n" + : "=r" (ret), "+A" (*ptr) + : "r" (new) + : "memory" ); + + return ret; +} + +static always_inline uint64_t __xchg_case_8(volatile uint64_t *ptr, + uint64_t new) +{ + __typeof__(*(ptr)) ret; + + asm volatile( \ + " amoswap.d.aqrl %0, %2, %1\n" \ + : "=r" (ret), "+A" (*ptr) \ + : "r" (new) \ + : "memory" ); \ + + return ret; +} + +static always_inline unsigned short __cmpxchg_case_2(volatile uint32_t *ptr, + uint32_t old, + uint32_t new); + +static always_inline unsigned short __cmpxchg_case_1(volatile uint32_t *ptr, + uint32_t old, + uint32_t new); + +static inline unsigned long __xchg(volatile void *ptr, unsigned long x, int size) +{ + switch (size) { + case 1: + return __cmpxchg_case_1(ptr, (uint32_t)-1, x); + case 2: + return __cmpxchg_case_2(ptr, (uint32_t)-1, x); + case 4: + return __xchg_case_4(ptr, x); + case 8: + return __xchg_case_8(ptr, x); + default: + ASSERT_UNREACHABLE(); + } + + return -1; +} + +#define xchg(ptr,x) \ +({ \ + __typeof__(*(ptr)) ret__; \ + ret__ = (__typeof__(*(ptr))) \ + __xchg((ptr), (unsigned long)(x), sizeof(*(ptr))); \ + ret__; \ +}) + +#define xchg32(ptr, x) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) != 4); \ + xchg((ptr), (x)); \ +}) + +#define xchg64(ptr, x) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ + xchg((ptr), (x)); \ +}) + +/* + * Atomic compare and exchange. Compare OLD with MEM, if identical, + * store NEW in MEM. Return the initial value in MEM. Success is + * indicated by comparing RETURN with OLD. + */ +#define __cmpxchg_relaxed(ptr, old, new, size) \ +({ \ + __typeof__(ptr) ptr__ = (ptr); \ + __typeof__(*(ptr)) __old = (old); \ + __typeof__(*(ptr)) new__ = (new); \ + __typeof__(*(ptr)) ret__; \ + register unsigned int __rc; \ + switch (size) \ + { \ + case 4: \ + asm volatile( \ + "0: lr.w %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.w %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + "1:\n" \ + : "=&r" (ret__), "=&r" (__rc), "+A" (*ptr__) \ + : "rJ" (__old), "rJ" (new__) \ + : "memory"); \ + break; \ + case 8: \ + asm volatile( \ + "0: lr.d %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.d %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + "1:\n" \ + : "=&r" (ret__), "=&r" (__rc), "+A" (*ptr__) \ + : "rJ" (__old), "rJ" (new__) \ + : "memory"); \ + break; \ + default: \ + ASSERT_UNREACHABLE(); \ + } \ + ret__; \ +}) + +#define cmpxchg_relaxed(ptr, o, n) \ +({ \ + __typeof__(*(ptr)) o_ = (o); \ + __typeof__(*(ptr)) n_ = (n); \ + (__typeof__(*(ptr))) __cmpxchg_relaxed((ptr), \ + o_, n_, sizeof(*(ptr))); \ +}) + +#define __cmpxchg_acquire(ptr, old, new, size) \ +({ \ + __typeof__(ptr) ptr__ = (ptr); \ + __typeof__(*(ptr)) __old = (old); \ + __typeof__(*(ptr)) new__ = (new); \ + __typeof__(*(ptr)) ret__; \ + register unsigned int __rc; \ + switch (size) \ + { \ + case 4: \ + asm volatile( \ + "0: lr.w %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.w %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + RISCV_ACQUIRE_BARRIER \ + "1:\n" \ + : "=&r" (ret__), "=&r" (__rc), "+A" (*ptr__) \ + : "rJ" (__old), "rJ" (new__) \ + : "memory"); \ + break; \ + case 8: \ + asm volatile( \ + "0: lr.d %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.d %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + RISCV_ACQUIRE_BARRIER \ + "1:\n" \ + : "=&r" (ret__), "=&r" (__rc), "+A" (*ptr__) \ + : "rJ" (__old), "rJ" (new__) \ + : "memory"); \ + break; \ + default: \ + ASSERT_UNREACHABLE(); \ + } \ + ret__; \ +}) + +#define cmpxchg_acquire(ptr, o, n) \ +({ \ + __typeof__(*(ptr)) o_ = (o); \ + __typeof__(*(ptr)) n_ = (n); \ + (__typeof__(*(ptr))) __cmpxchg_acquire((ptr), o_, n_, sizeof(*(ptr))); \ +}) + +#define __cmpxchg_release(ptr, old, new, size) \ +({ \ + __typeof__(ptr) ptr__ = (ptr); \ + __typeof__(*(ptr)) __old = (old); \ + __typeof__(*(ptr)) new__ = (new); \ + __typeof__(*(ptr)) ret__; \ + register unsigned int __rc; \ + switch (size) \ + { \ + case 4: \ + asm volatile ( \ + RISCV_RELEASE_BARRIER \ + "0: lr.w %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.w %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + "1:\n" \ + : "=&r" (ret__), "=&r" (__rc), "+A" (*ptr__) \ + : "rJ" (__old), "rJ" (new__) \ + : "memory" ); \ + break; \ + case 8: \ + asm volatile ( \ + RISCV_RELEASE_BARRIER \ + "0: lr.d %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.d %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + "1:\n" \ + : "=&r" (ret__), "=&r" (__rc), "+A" (*ptr__) \ + : "rJ" (__old), "rJ" (new__) \ + : "memory" ); \ + break; \ + default: \ + ASSERT_UNREACHABLE(); \ + } \ + ret__; \ +}) + +#define cmpxchg_release(ptr, o, n) \ +({ \ + __typeof__(*(ptr)) _o_ = (o); \ + __typeof__(*(ptr)) _n_ = (n); \ + (__typeof__(*(ptr))) __cmpxchg_release((ptr), _o_, _n_, sizeof(*(ptr))); \ +}) + +static always_inline uint32_t __cmpxchg_case_4(volatile uint32_t *ptr, + uint32_t old, + uint32_t new) +{ + uint32_t ret; + register uint32_t rc; + + asm volatile ( + "0: lr.w %0, %2\n" + " bne %0, %z3, 1f\n" + " sc.w.rl %1, %z4, %2\n" + " bnez %1, 0b\n" + " fence rw, rw\n" + "1:\n" + : "=&r" (ret), "=&r" (rc), "+A" (*ptr) + : "rJ" (old), "rJ" (new) + : "memory" ); + + return ret; +} + +static always_inline uint64_t __cmpxchg_case_8(volatile uint64_t *ptr, + uint64_t old, + uint64_t new) +{ + uint64_t ret; + register uint32_t rc; + + asm volatile( + "0: lr.d %0, %2\n" + " bne %0, %z3, 1f\n" + " sc.d.rl %1, %z4, %2\n" + " bnez %1, 0b\n" + " fence rw, rw\n" + "1:\n" + : "=&r" (ret), "=&r" (rc), "+A" (*ptr) + : "rJ" (old), "rJ" (new) + : "memory"); + + return ret; +} + +#define __emulate_cmpxchg_case1_2(ptr, new, read_func, cmpxchg_func, swap_byte_mask_base)\ +({ \ + __typeof__(*(ptr)) read_val; \ + __typeof__(*(ptr)) swapped_new; \ + __typeof__(*(ptr)) ret; \ + __typeof__(*(ptr)) new_ = (__typeof__(*(ptr)))new; \ + \ + __typeof__(ptr) aligned_ptr = (__typeof__(ptr))((unsigned long)ptr & ~3); \ + __typeof__(*(ptr)) mask_off = ((unsigned long)ptr & 3) * 8; \ + __typeof__(*(ptr)) mask = \ + (__typeof__(*(ptr)))swap_byte_mask_base << mask_off; \ + __typeof__(*(ptr)) masked_new = (new_ << mask_off) & mask; \ + \ + do { \ + read_val = read_func(aligned_ptr); \ + swapped_new = read_val & ~mask; \ + swapped_new |= masked_new; \ + ret = cmpxchg_func(aligned_ptr, read_val, swapped_new); \ + } while ( ret != read_val ); \ + \ + ret = MASK_EXTR(swapped_new, mask); \ + ret; \ +}) + +static always_inline unsigned short __cmpxchg_case_2(volatile uint32_t *ptr, + uint32_t old, + uint32_t new) +{ + (void) old; + + if (((unsigned long)ptr & 3) == 3) + { +#ifdef CONFIG_64BIT + return __emulate_cmpxchg_case1_2((uint64_t *)ptr, new, + readq, __cmpxchg_case_8, 0xffffU); +#else + #error "add emulation support of cmpxchg for CONFIG_32BIT" +#endif + } + else + return __emulate_cmpxchg_case1_2((uint32_t *)ptr, new, + readl, __cmpxchg_case_4, 0xffffU); +} + +static always_inline unsigned short __cmpxchg_case_1(volatile uint32_t *ptr, + uint32_t old, + uint32_t new) +{ + (void) old; + + return __emulate_cmpxchg_case1_2((uint32_t *)ptr, new, + readl, __cmpxchg_case_4, 0xffU); +} + +static always_inline unsigned long __cmpxchg(volatile void *ptr, + unsigned long old, + unsigned long new, + int size) +{ + switch (size) + { + case 1: + return __cmpxchg_case_1(ptr, old, new); + case 2: + return __cmpxchg_case_2(ptr, old, new); + case 4: + return __cmpxchg_case_4(ptr, old, new); + case 8: + return __cmpxchg_case_8(ptr, old, new); + default: + ASSERT_UNREACHABLE(); + } + + return old; +} + +#define cmpxchg(ptr, o, n) \ +({ \ + __typeof__(*(ptr)) ret__; \ + ret__ = (__typeof__(*(ptr))) \ + __cmpxchg((ptr), (unsigned long)(o), (unsigned long)(n), \ + sizeof(*(ptr))); \ + ret__; \ +}) + +#define cmpxchg_local(ptr, o, n) \ + (__cmpxchg_relaxed((ptr), (o), (n), sizeof(*(ptr)))) + +#define cmpxchg32(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) != 4); \ + cmpxchg((ptr), (o), (n)); \ +}) + +#define cmpxchg32_local(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) != 4); \ + cmpxchg_relaxed((ptr), (o), (n)) \ +}) + +#define cmpxchg64(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ + cmpxchg((ptr), (o), (n)); \ +}) + +#define cmpxchg64_local(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ + cmpxchg_relaxed((ptr), (o), (n)); \ +}) + +#endif /* _ASM_RISCV_CMPXCHG_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Fri Dec 22 15:12:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503460 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74C56C41535 for ; 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id j7-20020a056512108700b0050e6df07728sm45983lfg.180.2023.12.22.07.13.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 07:13:37 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: af824e17-a0dc-11ee-98eb-6d05b1d4d9a1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1703258018; x=1703862818; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rExImBCWONv5dbwNEtVk4jkk4u+ady4+FS4w6vB3FbQ=; b=MGKLvEcM/3BDqOqhfPvZ4xpqx2bnnYMCsb3GXBd+4t9L1PU4q1lNAfkGyEp6c7pKxM YbhwV/2SJnb7FDT96Qb8kfQ1Ab3soGLIQPgR1wotvsK4k+SbtsA83TSr3MgUc6k1je8p 7qLSIIwhU6H5Tv9caS42zV5Sgdja9reNfP+7RpRo/C/rxvedbkNBcZn0Yy4M6RJfslCr cpABSPTCW85nJBB9nAVh3exytXQLTCriYvwMbG1+jgj//Mtxjtuznb/STAg14wP4zZ4D PjRPSwYIgMVptNS8wLlTl6u1Hi9yPn9HEl8RZuK76AX3m0t5dnGoYC6IYtZU0geG9BXs +oNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703258018; x=1703862818; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rExImBCWONv5dbwNEtVk4jkk4u+ady4+FS4w6vB3FbQ=; b=IZrk3rul7meZ+i22anoAs/iBcYpLpEZUpTGy/mbAKKGyzOAPzvzvz/Ms+ybIYz3eQZ C9YYg6mgg6wnyO6Zvnsc304MeSIMeD3kd877NYx7beo48tOnQW0KU+655ZqbnRl0oT29 i/BDBOlppQEK5aEk3wd2OwfLDfrQjcFbYJIih9DMe9NlfXiootXsQRXPuF/hPRrGi8Cj nE4+DBCqFjrE/HFn8Qk6T1jsJDRDGEFLGK1N5mQYB5eOkhCpfpbd6hj54koZbzXMgCyk YHfX2vGNw5s3GkwgapeCV8CMNS7pryFOwapGSm95MdhEkNIDYwSHXgLn1Iql+v/TiTMB ikpg== X-Gm-Message-State: AOJu0YyC+OLmKF7xaWm4BRtOqnitl1R9fDXqi66XVBF2lW0Arab6NYfc FJwyicwZgF1A/k9m7q3M5J+gqzprpVo= X-Google-Smtp-Source: AGHT+IEoUnbSc/5ClfmCHitQNnDFFoQ+T++4BqBl2iLxA7ayy7a8WYp6J6h8zryGHB3wXXb+RUIuNA== X-Received: by 2002:a05:6512:5c4:b0:50e:67f6:40cd with SMTP id o4-20020a05651205c400b0050e67f640cdmr888636lfo.19.1703258018122; Fri, 22 Dec 2023 07:13:38 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v3 14/34] xen/riscv: introduce io.h Date: Fri, 22 Dec 2023 17:12:58 +0200 Message-ID: <5d2c032481792a3fe5bd5f1cae42d95f6e9b54b1.1703255175.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 The header taken form Linux 6.4.0-rc1 and is based on arch/riscv/include/asm/mmio.h. Addionally, to the header was added definions of ioremap_*(). Signed-off-by: Oleksii Kurochko --- Changes in V3: - re-sync with linux kernel - update the commit message --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/io.h | 142 ++++++++++++++++++++++++++++++++ 1 file changed, 142 insertions(+) create mode 100644 xen/arch/riscv/include/asm/io.h diff --git a/xen/arch/riscv/include/asm/io.h b/xen/arch/riscv/include/asm/io.h new file mode 100644 index 0000000000..ead466eb2d --- /dev/null +++ b/xen/arch/riscv/include/asm/io.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h + * which was based on arch/arm/include/io.h + * + * Copyright (C) 1996-2000 Russell King + * Copyright (C) 2012 ARM Ltd. + * Copyright (C) 2014 Regents of the University of California + */ + + +#ifndef _ASM_RISCV_IO_H +#define _ASM_RISCV_IO_H + +#include + +/* + * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't + * change the properties of memory regions. This should be fixed by the + * upcoming platform spec. + */ +#define ioremap_nocache(addr, size) ioremap((addr), (size)) +#define ioremap_wc(addr, size) ioremap((addr), (size)) +#define ioremap_wt(addr, size) ioremap((addr), (size)) + +/* Generic IO read/write. These perform native-endian accesses. */ +#define __raw_writeb __raw_writeb +static inline void __raw_writeb(u8 val, volatile void __iomem *addr) +{ + asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr)); +} + +#define __raw_writew __raw_writew +static inline void __raw_writew(u16 val, volatile void __iomem *addr) +{ + asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr)); +} + +#define __raw_writel __raw_writel +static inline void __raw_writel(u32 val, volatile void __iomem *addr) +{ + asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr)); +} + +#ifdef CONFIG_64BIT +#define __raw_writeq __raw_writeq +static inline void __raw_writeq(u64 val, volatile void __iomem *addr) +{ + asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr)); +} +#endif + +#define __raw_readb __raw_readb +static inline u8 __raw_readb(const volatile void __iomem *addr) +{ + u8 val; + + asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr)); + return val; +} + +#define __raw_readw __raw_readw +static inline u16 __raw_readw(const volatile void __iomem *addr) +{ + u16 val; + + asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr)); + return val; +} + +#define __raw_readl __raw_readl +static inline u32 __raw_readl(const volatile void __iomem *addr) +{ + u32 val; + + asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr)); + return val; +} + +#ifdef CONFIG_64BIT +#define __raw_readq __raw_readq +static inline u64 __raw_readq(const volatile void __iomem *addr) +{ + u64 val; + + asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr)); + return val; +} +#endif + +/* + * Unordered I/O memory access primitives. These are even more relaxed than + * the relaxed versions, as they don't even order accesses between successive + * operations to the I/O regions. + */ +#define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; }) +#define readw_cpu(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; }) +#define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; }) + +#define writeb_cpu(v,c) ((void)__raw_writeb((v),(c))) +#define writew_cpu(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c))) +#define writel_cpu(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c))) + +#ifdef CONFIG_64BIT +#define readq_cpu(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; }) +#define writeq_cpu(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c))) +#endif + +/* + * I/O memory access primitives. Reads are ordered relative to any + * following Normal memory access. Writes are ordered relative to any prior + * Normal memory access. The memory barriers here are necessary as RISC-V + * doesn't define any ordering between the memory space and the I/O space. + */ +#define __io_br() do {} while (0) +#define __io_ar(v) __asm__ __volatile__ ("fence i,r" : : : "memory"); +#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory"); +#define __io_aw() do { } while (0) + +#define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; }) +#define readw(c) ({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; }) +#define readl(c) ({ u32 __v; __io_br(); __v = readl_cpu(c); __io_ar(__v); __v; }) + +#define writeb(v,c) ({ __io_bw(); writeb_cpu((v),(c)); __io_aw(); }) +#define writew(v,c) ({ __io_bw(); writew_cpu((v),(c)); __io_aw(); }) +#define writel(v,c) ({ __io_bw(); writel_cpu((v),(c)); __io_aw(); }) + +#ifdef CONFIG_64BIT +#define readq(c) ({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(__v); __v; }) +#define writeq(v,c) ({ __io_bw(); writeq_cpu((v),(c)); __io_aw(); }) +#endif + +#endif /* _ASM_RISCV_IO_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Fri Dec 22 15:12:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503459 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 089EFC46CD2 for ; Fri, 22 Dec 2023 15:25:08 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659542.1029250 (Exim 4.92) (envelope-from ) id 1rGhOU-0006om-Jy; Fri, 22 Dec 2023 15:24:58 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 659542.1029250; Fri, 22 Dec 2023 15:24:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhOU-0006of-H5; Fri, 22 Dec 2023 15:24:58 +0000 Received: by outflank-mailman (input) for mailman id 659542; Fri, 22 Dec 2023 15:24:57 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDZ-0007Ie-0U for xen-devel@lists.xenproject.org; Fri, 22 Dec 2023 15:13:41 +0000 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [2a00:1450:4864:20::135]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id b0141b8d-a0dc-11ee-98eb-6d05b1d4d9a1; Fri, 22 Dec 2023 16:13:40 +0100 (CET) Received: by mail-lf1-x135.google.com with SMTP id 2adb3069b0e04-50e49a0b5caso2392226e87.0 for ; Fri, 22 Dec 2023 07:13:40 -0800 (PST) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id j7-20020a056512108700b0050e6df07728sm45983lfg.180.2023.12.22.07.13.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 07:13:38 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b0141b8d-a0dc-11ee-98eb-6d05b1d4d9a1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1703258019; x=1703862819; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mOwqAKIhXH+0XZ7x1OiU/ECPxpe/imzx7o+LpLoS1i0=; b=en2QSOETszdf5M2mVqeYWd4V3ujptKa14hGWQ8RWD67Dd6DXiySN54S3DDA+FmfWnp GAhshkDSgu/G9tgmd8AG6Bn5pCWWwS6f2mQZbzx95/NhZ1Zge2fVs/ypRtF8LoWQqKY2 CK2CF+or/sdLyg+vGXAGWqrsbIpLhq11pOQzWsS+U7o2nmMnsMBGEEfB2d9I1Uv2B935 qQ/phGBuzKdB/obJuF2gsIxY75inBC+2xMEHT0Zyq6xc64cPC8eG16DYJmwra/INcdvX ITD9mpuNPqxEG30XUBsQkubi0F9Bxt1KwfHIqTp3b8JNHMXAPad/hcd0hMEb68c5eK4e BNlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703258019; x=1703862819; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mOwqAKIhXH+0XZ7x1OiU/ECPxpe/imzx7o+LpLoS1i0=; b=P3uhspXpeTCYrsQcWcl7gy9FspLKd39ij7LMWZpXvXZnDrlqd+0jpOP5Grxiybpo1l y5XWAw3AKmkz1c1svJPYilq006v9fODHAmyk/NKZWukMuyiOs4yn0WP2YKd5DzFLvofW 365otdWP6SKG2pX2plFh4MbCRBvSF0RolrtxCT5SjaCbzE2qxsmgsS8+n5Bmxf2sZXim buy+vG11C/RZke7/T87GCNCV7gVGlE+rQcOxEH0dNxWxBHvi/H644F5DLTIGCgkQbPiZ YHeYJI3nEy4zRjMfwH9HogX378HSOrnsWuBh0EoovLOXeIAAKZXQDsr4Nuoht3tm1525 e1kw== X-Gm-Message-State: AOJu0Yz9yvkbBEMUAeaav2FJwzCL7hi4ki82onvnfCyhZLwXAOCtNMm5 vHIpCFqv6nCptbtMnIcI+TFEfXMH9HA= X-Google-Smtp-Source: AGHT+IH6EnT8IJBJwZ4VCRfWZjiCy5GmU+qEc/YW5PJ53Mw5nlU6Ak0wpMLw6M2Wj836iANLqaSE8w== X-Received: by 2002:ac2:454e:0:b0:50e:384c:289a with SMTP id j14-20020ac2454e000000b0050e384c289amr761863lfm.78.1703258019469; Fri, 22 Dec 2023 07:13:39 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Bobby Eshleman , Alistair Francis , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu , Oleksii Kurochko Subject: [PATCH v3 15/34] xen/riscv: introduce atomic.h Date: Fri, 22 Dec 2023 17:12:59 +0200 Message-ID: <54f5f13a4ee3de3c3cf4ba2b4d0347bb77bb7d08.1703255175.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 From: Bobby Eshleman Additionally, this patch introduces macros in fence.h, which are utilized in atomic.h. Signed-off-by: Oleksii Kurochko --- Changes in V3: - update the commit message - add SPDX for fence.h - code style fixes - Remove /* TODO: ... */ for add_sized macros. It looks correct to me. - re-order the patch - merge to this patch fence.h --- Changes in V2: - Change an author of commit. I got this header from Bobby's old repo. --- xen/arch/riscv/include/asm/atomic.h | 384 ++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/fence.h | 13 + 2 files changed, 397 insertions(+) create mode 100644 xen/arch/riscv/include/asm/atomic.h create mode 100644 xen/arch/riscv/include/asm/fence.h diff --git a/xen/arch/riscv/include/asm/atomic.h b/xen/arch/riscv/include/asm/atomic.h new file mode 100644 index 0000000000..725326a9d1 --- /dev/null +++ b/xen/arch/riscv/include/asm/atomic.h @@ -0,0 +1,384 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Taken and modified from Linux. + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Copyright (C) 2012 Regents of the University of California + * Copyright (C) 2017 SiFive + * Copyright (C) 2021 Vates SAS + */ + +#ifndef _ASM_RISCV_ATOMIC_H +#define _ASM_RISCV_ATOMIC_H + +#include +#include +#include +#include +#include + +void __bad_atomic_size(void); + +static always_inline void read_atomic_size(const volatile void *p, + void *res, + unsigned int size) +{ + switch ( size ) + { + case 1: *(uint8_t *)res = readb((const uint8_t *)p); break; + case 2: *(uint16_t *)res = readw((const uint16_t *)p); break; + case 4: *(uint32_t *)res = readl((const uint32_t *)p); break; + case 8: *(uint32_t *)res = readq((const uint64_t *)p); break; + default: __bad_atomic_size(); break; + } +} + +#define read_atomic(p) ({ \ + union { typeof(*p) val; char c[0]; } x_; \ + read_atomic_size(p, x_.c, sizeof(*p)); \ + x_.val; \ +}) + + +#define write_atomic(p, x) ({ \ + typeof(*p) x__ = (x); \ + switch ( sizeof(*p) ) \ + { \ + case 1: writeb((uint8_t)x__, (uint8_t *) p); break; \ + case 2: writew((uint16_t)x__, (uint16_t *) p); break; \ + case 4: writel((uint32_t)x__, (uint32_t *) p); break; \ + case 8: writeq((uint64_t)x__, (uint64_t *) p); break; \ + default: __bad_atomic_size(); break; \ + } \ + x__; \ +}) + +#define add_sized(p, x) ({ \ + typeof(*(p)) x__ = (x); \ + switch ( sizeof(*(p)) ) \ + { \ + case 1: writeb(read_atomic(p) + x__, (uint8_t *)(p)); break; \ + case 2: writew(read_atomic(p) + x__, (uint16_t *)(p)); break; \ + case 4: writel(read_atomic(p) + x__, (uint32_t *)(p)); break; \ + default: __bad_atomic_size(); break; \ + } \ +}) + +/* + * __unqual_scalar_typeof(x) - Declare an unqualified scalar type, leaving + * non-scalar types unchanged. + * + * Prefer C11 _Generic for better compile-times and simpler code. Note: 'char' + * is not type-compatible with 'signed char', and we define a separate case. + */ +#define __scalar_type_to_expr_cases(type) \ + unsigned type: (unsigned type)0, \ + signed type: (signed type)0 + +#define __unqual_scalar_typeof(x) typeof( \ + _Generic((x), \ + char: (char)0, \ + __scalar_type_to_expr_cases(char), \ + __scalar_type_to_expr_cases(short), \ + __scalar_type_to_expr_cases(int), \ + __scalar_type_to_expr_cases(long), \ + __scalar_type_to_expr_cases(long long), \ + default: (x))) + +#define READ_ONCE(x) (*(const volatile __unqual_scalar_typeof(x) *)&(x)) +#define WRITE_ONCE(x, val) \ + do { \ + *(volatile typeof(x) *)&(x) = (val); \ + } while (0) + +#define __atomic_acquire_fence() \ + __asm__ __volatile__( RISCV_ACQUIRE_BARRIER "" ::: "memory" ) + +#define __atomic_release_fence() \ + __asm__ __volatile__( RISCV_RELEASE_BARRIER "" ::: "memory" ); + +static inline int atomic_read(const atomic_t *v) +{ + return READ_ONCE(v->counter); +} + +static inline int _atomic_read(atomic_t v) +{ + return v.counter; +} + +static inline void atomic_set(atomic_t *v, int i) +{ + WRITE_ONCE(v->counter, i); +} + +static inline void _atomic_set(atomic_t *v, int i) +{ + v->counter = i; +} + +static inline int atomic_sub_and_test(int i, atomic_t *v) +{ + return atomic_sub_return(i, v) == 0; +} + +static inline void atomic_inc(atomic_t *v) +{ + atomic_add(1, v); +} + +static inline int atomic_inc_return(atomic_t *v) +{ + return atomic_add_return(1, v); +} + +static inline void atomic_dec(atomic_t *v) +{ + atomic_sub(1, v); +} + +static inline int atomic_dec_return(atomic_t *v) +{ + return atomic_sub_return(1, v); +} + +static inline int atomic_dec_and_test(atomic_t *v) +{ + return atomic_sub_return(1, v) == 0; +} + +static inline int atomic_add_negative(int i, atomic_t *v) +{ + return atomic_add_return(i, v) < 0; +} + +static inline int atomic_inc_and_test(atomic_t *v) +{ + return atomic_add_return(1, v) == 0; +} + +/* + * First, the atomic ops that have no ordering constraints and therefor don't + * have the AQ or RL bits set. These don't return anything, so there's only + * one version to worry about. + */ +#define ATOMIC_OP(op, asm_op, I, asm_type, c_type, prefix) \ +static inline \ +void atomic##prefix##_##op(c_type i, atomic##prefix##_t *v) \ +{ \ + __asm__ __volatile__ ( \ + " amo" #asm_op "." #asm_type " zero, %1, %0" \ + : "+A" (v->counter) \ + : "r" (I) \ + : "memory" ); \ +} \ + +#define ATOMIC_OPS(op, asm_op, I) \ + ATOMIC_OP (op, asm_op, I, w, int, ) + +ATOMIC_OPS(add, add, i) +ATOMIC_OPS(sub, add, -i) +ATOMIC_OPS(and, and, i) +ATOMIC_OPS( or, or, i) +ATOMIC_OPS(xor, xor, i) + +#undef ATOMIC_OP +#undef ATOMIC_OPS + +/* + * Atomic ops that have ordered, relaxed, acquire, and release variants. + * There's two flavors of these: the arithmatic ops have both fetch and return + * versions, while the logical ops only have fetch versions. + */ +#define ATOMIC_FETCH_OP(op, asm_op, I, asm_type, c_type, prefix) \ +static inline \ +c_type atomic##prefix##_fetch_##op##_relaxed(c_type i, \ + atomic##prefix##_t *v) \ +{ \ + register c_type ret; \ + __asm__ __volatile__ ( \ + " amo" #asm_op "." #asm_type " %1, %2, %0" \ + : "+A" (v->counter), "=r" (ret) \ + : "r" (I) \ + : "memory" ); \ + return ret; \ +} \ +static inline \ +c_type atomic##prefix##_fetch_##op(c_type i, atomic##prefix##_t *v) \ +{ \ + register c_type ret; \ + __asm__ __volatile__ ( \ + " amo" #asm_op "." #asm_type ".aqrl %1, %2, %0" \ + : "+A" (v->counter), "=r" (ret) \ + : "r" (I) \ + : "memory" ); \ + return ret; \ +} + +#define ATOMIC_OP_RETURN(op, asm_op, c_op, I, asm_type, c_type, prefix) \ +static inline \ +c_type atomic##prefix##_##op##_return_relaxed(c_type i, \ + atomic##prefix##_t *v) \ +{ \ + return atomic##prefix##_fetch_##op##_relaxed(i, v) c_op I; \ +} \ +static inline \ +c_type atomic##prefix##_##op##_return(c_type i, atomic##prefix##_t *v) \ +{ \ + return atomic##prefix##_fetch_##op(i, v) c_op I; \ +} + +#define ATOMIC_OPS(op, asm_op, c_op, I) \ + ATOMIC_FETCH_OP( op, asm_op, I, w, int, ) \ + ATOMIC_OP_RETURN(op, asm_op, c_op, I, w, int, ) + +ATOMIC_OPS(add, add, +, i) +ATOMIC_OPS(sub, add, +, -i) + +#define atomic_add_return_relaxed atomic_add_return_relaxed +#define atomic_sub_return_relaxed atomic_sub_return_relaxed +#define atomic_add_return atomic_add_return +#define atomic_sub_return atomic_sub_return + +#define atomic_fetch_add_relaxed atomic_fetch_add_relaxed +#define atomic_fetch_sub_relaxed atomic_fetch_sub_relaxed +#define atomic_fetch_add atomic_fetch_add +#define atomic_fetch_sub atomic_fetch_sub + +#undef ATOMIC_OPS + +#define ATOMIC_OPS(op, asm_op, I) \ + ATOMIC_FETCH_OP(op, asm_op, I, w, int, ) + +ATOMIC_OPS(and, and, i) +ATOMIC_OPS( or, or, i) +ATOMIC_OPS(xor, xor, i) + +#define atomic_fetch_and_relaxed atomic_fetch_and_relaxed +#define atomic_fetch_or_relaxed atomic_fetch_or_relaxed +#define atomic_fetch_xor_relaxed atomic_fetch_xor_relaxed +#define atomic_fetch_and atomic_fetch_and +#define atomic_fetch_or atomic_fetch_or +#define atomic_fetch_xor atomic_fetch_xor + +#undef ATOMIC_OPS + +#undef ATOMIC_FETCH_OP +#undef ATOMIC_OP_RETURN + +/* This is required to provide a full barrier on success. */ +static inline int atomic_add_unless(atomic_t *v, int a, int u) +{ + int prev, rc; + + __asm__ __volatile__ ( + "0: lr.w %[p], %[c]\n" + " beq %[p], %[u], 1f\n" + " add %[rc], %[p], %[a]\n" + " sc.w.rl %[rc], %[rc], %[c]\n" + " bnez %[rc], 0b\n" + " fence rw, rw\n" + "1:\n" + : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) + : [a]"r" (a), [u]"r" (u) + : "memory"); + return prev; +} +#define atomic_fetch_add_unless atomic_fetch_add_unless + +/* + * atomic_{cmp,}xchg is required to have exactly the same ordering semantics as + * {cmp,}xchg and the operations that return, so they need a full barrier. + */ +#define ATOMIC_OP(c_t, prefix, size) \ +static inline \ +c_t atomic##prefix##_xchg_relaxed(atomic##prefix##_t *v, c_t n) \ +{ \ + return __xchg_relaxed(&(v->counter), n, size); \ +} \ +static inline \ +c_t atomic##prefix##_xchg_acquire(atomic##prefix##_t *v, c_t n) \ +{ \ + return __xchg_acquire(&(v->counter), n, size); \ +} \ +static inline \ +c_t atomic##prefix##_xchg_release(atomic##prefix##_t *v, c_t n) \ +{ \ + return __xchg_release(&(v->counter), n, size); \ +} \ +static inline \ +c_t atomic##prefix##_xchg(atomic##prefix##_t *v, c_t n) \ +{ \ + return __xchg(&(v->counter), n, size); \ +} \ +static inline \ +c_t atomic##prefix##_cmpxchg_relaxed(atomic##prefix##_t *v, \ + c_t o, c_t n) \ +{ \ + return __cmpxchg_relaxed(&(v->counter), o, n, size); \ +} \ +static inline \ +c_t atomic##prefix##_cmpxchg_acquire(atomic##prefix##_t *v, \ + c_t o, c_t n) \ +{ \ + return __cmpxchg_acquire(&(v->counter), o, n, size); \ +} \ +static inline \ +c_t atomic##prefix##_cmpxchg_release(atomic##prefix##_t *v, \ + c_t o, c_t n) \ +{ \ + return __cmpxchg_release(&(v->counter), o, n, size); \ +} \ +static inline \ +c_t atomic##prefix##_cmpxchg(atomic##prefix##_t *v, c_t o, c_t n) \ +{ \ + return __cmpxchg(&(v->counter), o, n, size); \ +} + +#define ATOMIC_OPS() \ + ATOMIC_OP(int, , 4) + +ATOMIC_OPS() + +#define atomic_xchg_relaxed atomic_xchg_relaxed +#define atomic_xchg_acquire atomic_xchg_acquire +#define atomic_xchg_release atomic_xchg_release +#define atomic_xchg atomic_xchg +#define atomic_cmpxchg_relaxed atomic_cmpxchg_relaxed +#define atomic_cmpxchg_acquire atomic_cmpxchg_acquire +#define atomic_cmpxchg_release atomic_cmpxchg_release +#define atomic_cmpxchg atomic_cmpxchg + +#undef ATOMIC_OPS +#undef ATOMIC_OP + +static inline int atomic_sub_if_positive(atomic_t *v, int offset) +{ + int prev, rc; + + __asm__ __volatile__ ( + "0: lr.w %[p], %[c]\n" + " sub %[rc], %[p], %[o]\n" + " bltz %[rc], 1f\n" + " sc.w.rl %[rc], %[rc], %[c]\n" + " bnez %[rc], 0b\n" + " fence rw, rw\n" + "1:\n" + : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) + : [o]"r" (offset) + : "memory" ); + return prev - offset; +} + +#define atomic_dec_if_positive(v) atomic_sub_if_positive(v, 1) + +#endif /* _ASM_RISCV_ATOMIC_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/riscv/include/asm/fence.h b/xen/arch/riscv/include/asm/fence.h new file mode 100644 index 0000000000..b3f6b1c20a --- /dev/null +++ b/xen/arch/riscv/include/asm/fence.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef _ASM_RISCV_FENCE_H +#define _ASM_RISCV_FENCE_H + +#ifdef CONFIG_SMP +#define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n" +#define RISCV_RELEASE_BARRIER "\tfence rw, w\n" +#else +#define RISCV_ACQUIRE_BARRIER +#define RISCV_RELEASE_BARRIER +#endif + +#endif /* _ASM_RISCV_FENCE_H */ From patchwork Fri Dec 22 15:13:00 2023 Content-Type: text/plain; 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Suggested-by: Jan Beulich Signed-off-by: Oleksii Kurochko --- Changes in V3: - new patch. --- xen/arch/riscv/include/asm/fence.h | 11 +- xen/common/Kconfig | 3 + xen/lib/Makefile | 1 + xen/lib/find-next-bit.c | 281 +++++++++++++++++++++++++++++ 4 files changed, 295 insertions(+), 1 deletion(-) create mode 100644 xen/lib/find-next-bit.c diff --git a/xen/arch/riscv/include/asm/fence.h b/xen/arch/riscv/include/asm/fence.h index b3f6b1c20a..5d9a851ae8 100644 --- a/xen/arch/riscv/include/asm/fence.h +++ b/xen/arch/riscv/include/asm/fence.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _ASM_RISCV_FENCE_H #define _ASM_RISCV_FENCE_H @@ -11,3 +11,12 @@ #endif #endif /* _ASM_RISCV_FENCE_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/common/Kconfig b/xen/common/Kconfig index 310ad4229c..56ce34ffd4 100644 --- a/xen/common/Kconfig +++ b/xen/common/Kconfig @@ -47,6 +47,9 @@ config ARCH_MAP_DOMAIN_PAGE config GENERIC_BUG_FRAME bool +config GENERIC_FIND_NEXT_BIT + bool + config HAS_ALTERNATIVE bool diff --git a/xen/lib/Makefile b/xen/lib/Makefile index 2d9ebb945f..66237a45c5 100644 --- a/xen/lib/Makefile +++ b/xen/lib/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_X86) += x86/ lib-y += bsearch.o lib-y += ctors.o lib-y += ctype.o +lib-$(CONFIG_GENERIC_FIND_NEXT_BIT) += find-next-bit.o lib-y += list-sort.o lib-y += memchr.o lib-y += memchr_inv.o diff --git a/xen/lib/find-next-bit.c b/xen/lib/find-next-bit.c new file mode 100644 index 0000000000..ca6f82277e --- /dev/null +++ b/xen/lib/find-next-bit.c @@ -0,0 +1,281 @@ +/* find_next_bit.c: fallback find next bit implementation + * + * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include + +#include + +#ifndef find_next_bit +/* + * Find the next set bit in a memory region. + */ +unsigned long find_next_bit(const unsigned long *addr, unsigned long size, + unsigned long offset) +{ + const unsigned long *p = addr + BIT_WORD(offset); + unsigned long result = offset & ~(BITS_PER_LONG-1); + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset %= BITS_PER_LONG; + if (offset) { + tmp = *(p++); + tmp &= (~0UL << offset); + if (size < BITS_PER_LONG) + goto found_first; + if (tmp) + goto found_middle; + size -= BITS_PER_LONG; + result += BITS_PER_LONG; + } + while (size & ~(BITS_PER_LONG-1)) { + if ((tmp = *(p++))) + goto found_middle; + result += BITS_PER_LONG; + size -= BITS_PER_LONG; + } + if (!size) + return result; + tmp = *p; + +found_first: + tmp &= (~0UL >> (BITS_PER_LONG - size)); + if (tmp == 0UL) /* Are any bits set? */ + return result + size; /* Nope. */ +found_middle: + return result + __ffs(tmp); +} +EXPORT_SYMBOL(find_next_bit); +#endif + +#ifndef find_next_zero_bit +/* + * This implementation of find_{first,next}_zero_bit was stolen from + * Linus' asm-alpha/bitops.h. + */ +unsigned long find_next_zero_bit(const unsigned long *addr, unsigned long size, + unsigned long offset) +{ + const unsigned long *p = addr + BIT_WORD(offset); + unsigned long result = offset & ~(BITS_PER_LONG-1); + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset %= BITS_PER_LONG; + if (offset) { + tmp = *(p++); + tmp |= ~0UL >> (BITS_PER_LONG - offset); + if (size < BITS_PER_LONG) + goto found_first; + if (~tmp) + goto found_middle; + size -= BITS_PER_LONG; + result += BITS_PER_LONG; + } + while (size & ~(BITS_PER_LONG-1)) { + if (~(tmp = *(p++))) + goto found_middle; + result += BITS_PER_LONG; + size -= BITS_PER_LONG; + } + if (!size) + return result; + tmp = *p; + +found_first: + tmp |= ~0UL << size; + if (tmp == ~0UL) /* Are any bits zero? */ + return result + size; /* Nope. */ +found_middle: + return result + ffz(tmp); +} +EXPORT_SYMBOL(find_next_zero_bit); +#endif + +#ifndef find_first_bit +/* + * Find the first set bit in a memory region. + */ +unsigned long find_first_bit(const unsigned long *addr, unsigned long size) +{ + const unsigned long *p = addr; + unsigned long result = 0; + unsigned long tmp; + + while (size & ~(BITS_PER_LONG-1)) { + if ((tmp = *(p++))) + goto found; + result += BITS_PER_LONG; + size -= BITS_PER_LONG; + } + if (!size) + return result; + + tmp = (*p) & (~0UL >> (BITS_PER_LONG - size)); + if (tmp == 0UL) /* Are any bits set? */ + return result + size; /* Nope. */ +found: + return result + __ffs(tmp); +} +EXPORT_SYMBOL(find_first_bit); +#endif + +#ifndef find_first_zero_bit +/* + * Find the first cleared bit in a memory region. + */ +unsigned long find_first_zero_bit(const unsigned long *addr, unsigned long size) +{ + const unsigned long *p = addr; + unsigned long result = 0; + unsigned long tmp; + + while (size & ~(BITS_PER_LONG-1)) { + if (~(tmp = *(p++))) + goto found; + result += BITS_PER_LONG; + size -= BITS_PER_LONG; + } + if (!size) + return result; + + tmp = (*p) | (~0UL << size); + if (tmp == ~0UL) /* Are any bits zero? */ + return result + size; /* Nope. */ +found: + return result + ffz(tmp); +} +EXPORT_SYMBOL(find_first_zero_bit); +#endif + +#ifdef __BIG_ENDIAN + +/* include/linux/byteorder does not support "unsigned long" type */ +static inline unsigned long ext2_swabp(const unsigned long * x) +{ +#if BITS_PER_LONG == 64 + return (unsigned long) __swab64p((u64 *) x); +#elif BITS_PER_LONG == 32 + return (unsigned long) __swab32p((u32 *) x); +#else +#error BITS_PER_LONG not defined +#endif +} + +/* include/linux/byteorder doesn't support "unsigned long" type */ +static inline unsigned long ext2_swab(const unsigned long y) +{ +#if BITS_PER_LONG == 64 + return (unsigned long) __swab64((u64) y); +#elif BITS_PER_LONG == 32 + return (unsigned long) __swab32((u32) y); +#else +#error BITS_PER_LONG not defined +#endif +} + +#ifndef find_next_zero_bit_le +unsigned long find_next_zero_bit_le(const void *addr, unsigned + long size, unsigned long offset) +{ + const unsigned long *p = addr; + unsigned long result = offset & ~(BITS_PER_LONG - 1); + unsigned long tmp; + + if (offset >= size) + return size; + p += BIT_WORD(offset); + size -= result; + offset &= (BITS_PER_LONG - 1UL); + if (offset) { + tmp = ext2_swabp(p++); + tmp |= (~0UL >> (BITS_PER_LONG - offset)); + if (size < BITS_PER_LONG) + goto found_first; + if (~tmp) + goto found_middle; + size -= BITS_PER_LONG; + result += BITS_PER_LONG; + } + + while (size & ~(BITS_PER_LONG - 1)) { + if (~(tmp = *(p++))) + goto found_middle_swap; + result += BITS_PER_LONG; + size -= BITS_PER_LONG; + } + if (!size) + return result; + tmp = ext2_swabp(p); +found_first: + tmp |= ~0UL << size; + if (tmp == ~0UL) /* Are any bits zero? */ + return result + size; /* Nope. Skip ffz */ +found_middle: + return result + ffz(tmp); + +found_middle_swap: + return result + ffz(ext2_swab(tmp)); +} +EXPORT_SYMBOL(find_next_zero_bit_le); +#endif + +#ifndef find_next_bit_le +unsigned long find_next_bit_le(const void *addr, unsigned + long size, unsigned long offset) +{ + const unsigned long *p = addr; + unsigned long result = offset & ~(BITS_PER_LONG - 1); + unsigned long tmp; + + if (offset >= size) + return size; + p += BIT_WORD(offset); + size -= result; + offset &= (BITS_PER_LONG - 1UL); + if (offset) { + tmp = ext2_swabp(p++); + tmp &= (~0UL << offset); + if (size < BITS_PER_LONG) + goto found_first; + if (tmp) + goto found_middle; + size -= BITS_PER_LONG; + result += BITS_PER_LONG; + } + + while (size & ~(BITS_PER_LONG - 1)) { + tmp = *(p++); + if (tmp) + goto found_middle_swap; + result += BITS_PER_LONG; + size -= BITS_PER_LONG; + } + if (!size) + return result; + tmp = ext2_swabp(p); +found_first: + tmp &= (~0UL >> (BITS_PER_LONG - size)); + if (tmp == 0UL) /* Are any bits set? */ + return result + size; /* Nope. */ +found_middle: + return result + __ffs(tmp); + +found_middle_swap: + return result + __ffs(ext2_swab(tmp)); +} +EXPORT_SYMBOL(find_next_bit_le); +#endif + +#endif /* __BIG_ENDIAN */ From patchwork Fri Dec 22 15:13:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503462 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E02CAC41535 for ; Fri, 22 Dec 2023 15:26:37 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659568.1029289 (Exim 4.92) (envelope-from ) id 1rGhPy-0000nn-MY; Fri, 22 Dec 2023 15:26:30 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 659568.1029289; Fri, 22 Dec 2023 15:26:30 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhPy-0000ng-Jw; Fri, 22 Dec 2023 15:26:30 +0000 Received: by outflank-mailman (input) for mailman id 659568; Fri, 22 Dec 2023 15:26:29 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDa-0007Ie-Ti for xen-devel@lists.xenproject.org; Fri, 22 Dec 2023 15:13:42 +0000 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [2a00:1450:4864:20::130]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id b15ed366-a0dc-11ee-98eb-6d05b1d4d9a1; Fri, 22 Dec 2023 16:13:42 +0100 (CET) Received: by mail-lf1-x130.google.com with SMTP id 2adb3069b0e04-50e616ef769so1939112e87.1 for ; Fri, 22 Dec 2023 07:13:42 -0800 (PST) Received: from fedora.. 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id j7-20020a056512108700b0050e6df07728sm45983lfg.180.2023.12.22.07.13.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 07:13:42 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b229c2ad-a0dc-11ee-9b0f-b553b5be7939 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1703258023; x=1703862823; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4V2ccNLv7fzBgrDA9NE+pKZEtsNt5JBlW/j5gZeAoxQ=; b=Bnck0/07C2dN3BfTp4TB4qV9WXuq/95rW/SU+auhAgBCWaDLS8W25gyrQOjb0mGBEe pCzg37AtwK4SYY2Mr874NXbKgT+wjBspWLO9K1kvyWmiL2C93bKyc7iHUIy36by62eea ZzMu2O+WgwUeB0eekkF4100jf4X+NDmPKA0lQWHlPb8jFI9yYVk9cLIm2BV3oBCg3Ksi 35TZ4N/9qwfLzKC/4DUD0iuCsqnmvpa9ZXw1GdbPjjfVXwLG6QdAv5OYAUDaMAkGhf62 kbBOO7kPSpI9YfnFiIrXmiedNeaFVHB1NxDYnZLb4pkfqkqRdD9xiB+/WurqNhgSWZJE 5FSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703258023; x=1703862823; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4V2ccNLv7fzBgrDA9NE+pKZEtsNt5JBlW/j5gZeAoxQ=; b=f4Yvht0AXKxrgnXE77ZF1RmuegbY+HgHeW2YD2jOThLGzEVKLJXwsSWyRnh1/9gy0W tf/CMAmIgGMwhhBVuzrLoxAgTzcaY/sTjcaZSzzMR7ahrqeU7CzWiuioOzygjk9B5YcR UPcHldUlRRbleSGZraYNCPd1rfvex6xUOA8Dadnto0EYKAwo4r4+q2CZe8Mgs56XGQHT BGCSKSkNTQXeFBbm7TbywY5W/BOoV2sgMO6kBKacz7wbOBZUY1hnbkeRcRKwPRoerY3C vD1jPsNoEPVvvZDT+Vsqv+C5LNQiUkcb12wP/KcsK5Exo0gesMCLVibVW/OpMic/HPo6 uuNA== X-Gm-Message-State: AOJu0Yy6WuLH6srq1m/E3X1j9YpOVOlnEi7w2+5OdzM/DewdI0zaGu0Q 5pptNWhGKJ52wnvkD6c+/dk+Xo5cX6s= X-Google-Smtp-Source: AGHT+IE/3AWabe7B55/sEwLUkis+9P0Cr660xvAYN/IeOC4KxvvX9AADNDzH0XBBpHD95ttIVEky2w== X-Received: by 2002:ac2:4259:0:b0:50e:3877:caba with SMTP id m25-20020ac24259000000b0050e3877cabamr392669lfl.52.1703258022592; Fri, 22 Dec 2023 07:13:42 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v3 18/34] xen/riscv: introduce domain.h Date: Fri, 22 Dec 2023 17:13:02 +0200 Message-ID: <6bec4f93bea5ae3e13ac314c59fa6b9898deb998.1703255175.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V3: - add SPDX - add Acked-by: Jan Beulich - update the commit message --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/domain.h | 53 +++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 xen/arch/riscv/include/asm/domain.h diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/asm/domain.h new file mode 100644 index 0000000000..0f5dc2be40 --- /dev/null +++ b/xen/arch/riscv/include/asm/domain.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_RISCV_DOMAIN_H__ +#define __ASM_RISCV_DOMAIN_H__ + +#include +#include + +struct hvm_domain +{ + uint64_t params[HVM_NR_PARAMS]; +}; + +#define is_domain_direct_mapped(d) ((void)(d), 0) + +struct arch_vcpu_io { +}; + +struct arch_vcpu { +}; + +struct arch_domain { + struct hvm_domain hvm; +}; + +#include + +static inline struct vcpu_guest_context *alloc_vcpu_guest_context(void) +{ + return xmalloc(struct vcpu_guest_context); +} + +static inline void free_vcpu_guest_context(struct vcpu_guest_context *vgc) +{ + xfree(vgc); +} + +struct guest_memory_policy {}; +static inline void update_guest_memory_policy(struct vcpu *v, + struct guest_memory_policy *gmp) +{} + +static inline void arch_vcpu_block(struct vcpu *v) {} + +#endif /* __ASM_RISCV_DOMAIN_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Fri Dec 22 15:13:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503458 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E35FC46CD2 for ; Fri, 22 Dec 2023 15:25:05 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659543.1029255 (Exim 4.92) (envelope-from ) id 1rGhOU-0006qs-Tr; Fri, 22 Dec 2023 15:24:58 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 659543.1029255; Fri, 22 Dec 2023 15:24:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhOU-0006qP-Nh; Fri, 22 Dec 2023 15:24:58 +0000 Received: by outflank-mailman (input) for mailman id 659543; Fri, 22 Dec 2023 15:24:57 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDd-0007Ie-GL for xen-devel@lists.xenproject.org; Fri, 22 Dec 2023 15:13:45 +0000 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [2a00:1450:4864:20::134]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id b2f175bc-a0dc-11ee-98eb-6d05b1d4d9a1; Fri, 22 Dec 2023 16:13:45 +0100 (CET) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-50e3901c2e2so2351849e87.0 for ; Fri, 22 Dec 2023 07:13:45 -0800 (PST) Received: from fedora.. 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+ +struct arch_irq_desc { + unsigned int type; +}; + +static inline void arch_move_irqs(struct vcpu *v) +{ + BUG(); +} + +#endif /* __ASM_RISCV_IRQ_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Fri Dec 22 15:13:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503457 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 05FF3C41535 for ; Fri, 22 Dec 2023 15:24:48 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659539.1029240 (Exim 4.92) (envelope-from ) id 1rGhO8-0006Ap-90; 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id j7-20020a056512108700b0050e6df07728sm45983lfg.180.2023.12.22.07.13.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 07:13:45 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b477d9f3-a0dc-11ee-98eb-6d05b1d4d9a1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1703258026; x=1703862826; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=X2XgyDBcB0wcGp/eGfwcZrl9kaDJvnjyiwZy9l3W62o=; b=Fg1lQOU9rBjX8r+NJIeKiH7DSkZrrf8YZJshrxyjoRGXkqZ05HblmECNlCCUm5+1Zs oPJMT+dHfwtpZd7xlGFrcvVTYJ9BxXtCKsz7/u6485MQOstOS5V7bVk0DVj0yRflioDU FxrElPfGN4KOsUiCt5KLJ0L2G/O5r5UbAmnQgnoBtZHtuFS20WiKUGvypQbaVtxT3/iL 4HyQLiulEjQ9SvYWwHUfmRUwxa0HzkSH3JpAgTI+rbVH++4F3v2IytA9rk49Eeu9wZfP nSR+tP+5yiM/52Q5zDgM/DOEm7/Wl974JvyU2ABv9s9z8A3RwhyC0z6Un8qz3m7yqeGg /HDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703258026; x=1703862826; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X2XgyDBcB0wcGp/eGfwcZrl9kaDJvnjyiwZy9l3W62o=; b=Y/+U26X/1s0MRdsNDerK3KvaVEY5eI7Fbc2RUg2ytkW1KC9N/ALhoOZ2+6NQEvAtI2 /ad/R14Ct7MGNIZ6+dYr4MT2L+Ru3krecvsfLCOX2fuldmeMTZaelXEX2D3H+lJnZ1gL L1hud6EvDwYziBugDUd3Ko4yQfjiqOR52db+b01B5z0VNWCOCBwevzlY3236NcywI+rh mc313LUyEkVZKZgiVEw7sZnYTak1XdGd7QiEpbezMDQIKU8JU2ICg7Y/VM8BRYb87I4V c3cVjWcCFFVNAE5v4j9p1e1sN/ta3gt9wdBQCeJJ0sieFOhTby42VhY3L6FKFOWPtLaX Nz+A== X-Gm-Message-State: AOJu0Yy9yer93aI3C4qbXvpcePh7Qz/CApG7jFtSZmn/pLor6H+ywcST bYxz8aylVdBLvFMvQXpZbroQo7WY3K4= X-Google-Smtp-Source: AGHT+IFXlcx/J+Wls40o8XEL6UZ9HqMfyy2MVVMj21ySD20VMnVDQq8+43xyNlSyIR/iyL3GdDY2FQ== X-Received: by 2002:a05:6512:2185:b0:50e:3082:1afe with SMTP id b5-20020a056512218500b0050e30821afemr340432lft.22.1703258026484; Fri, 22 Dec 2023 07:13:46 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Shawn Anastasio , Alistair Francis , Bob Eshleman , Connor Davis Subject: [PATCH v3 21/34] xen/riscv: introduce p2m.h Date: Fri, 22 Dec 2023 17:13:05 +0200 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko --- Changes in V3: - add SPDX - drop unneeded for now p2m types. - return false in all functions implemented with BUG() inside. - update the commit message --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/ppc/include/asm/p2m.h | 3 +- xen/arch/riscv/include/asm/p2m.h | 102 +++++++++++++++++++++++++++++++ 2 files changed, 103 insertions(+), 2 deletions(-) create mode 100644 xen/arch/riscv/include/asm/p2m.h diff --git a/xen/arch/ppc/include/asm/p2m.h b/xen/arch/ppc/include/asm/p2m.h index 25ba054668..3bc05b7c05 100644 --- a/xen/arch/ppc/include/asm/p2m.h +++ b/xen/arch/ppc/include/asm/p2m.h @@ -50,8 +50,7 @@ static inline void memory_type_changed(struct domain *d) static inline int guest_physmap_mark_populate_on_demand(struct domain *d, unsigned long gfn, unsigned int order) { - BUG_ON("unimplemented"); - return 1; + return -EOPNOTSUPP; } static inline int guest_physmap_add_entry(struct domain *d, diff --git a/xen/arch/riscv/include/asm/p2m.h b/xen/arch/riscv/include/asm/p2m.h new file mode 100644 index 0000000000..d270ef6635 --- /dev/null +++ b/xen/arch/riscv/include/asm/p2m.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_RISCV_P2M_H__ +#define __ASM_RISCV_P2M_H__ + +#include + +#define paddr_bits PADDR_BITS + +/* + * List of possible type for each page in the p2m entry. + * The number of available bit per page in the pte for this purpose is 4 bits. + * So it's possible to only have 16 fields. If we run out of value in the + * future, it's possible to use higher value for pseudo-type and don't store + * them in the p2m entry. + */ +typedef enum { + p2m_invalid = 0, /* Nothing mapped here */ + p2m_ram_rw, /* Normal read/write guest RAM */ +} p2m_type_t; + +#include + +static inline int get_page_and_type(struct page_info *page, + struct domain *domain, + unsigned long type) +{ + BUG(); + return -EINVAL; +} + +/* Look up a GFN and take a reference count on the backing page. */ +typedef unsigned int p2m_query_t; +#define P2M_ALLOC (1u<<0) /* Populate PoD and paged-out entries */ +#define P2M_UNSHARE (1u<<1) /* Break CoW sharing */ + +static inline struct page_info *get_page_from_gfn( + struct domain *d, unsigned long gfn, p2m_type_t *t, p2m_query_t q) +{ + BUG(); + return NULL; +} + +static inline void memory_type_changed(struct domain *d) +{ + BUG(); +} + + +static inline int guest_physmap_mark_populate_on_demand(struct domain *d, unsigned long gfn, + unsigned int order) +{ + return -EOPNOTSUPP; +} + +static inline int guest_physmap_add_entry(struct domain *d, + gfn_t gfn, + mfn_t mfn, + unsigned long page_order, + p2m_type_t t) +{ + BUG(); + return -EINVAL; +} + +/* Untyped version for RAM only, for compatibility */ +static inline int __must_check +guest_physmap_add_page(struct domain *d, gfn_t gfn, mfn_t mfn, + unsigned int page_order) +{ + return guest_physmap_add_entry(d, gfn, mfn, page_order, p2m_ram_rw); +} + +static inline mfn_t gfn_to_mfn(struct domain *d, gfn_t gfn) +{ + BUG(); + return _mfn(0); +} + +static inline bool arch_acquire_resource_check(struct domain *d) +{ + /* + * The reference counting of foreign entries in set_foreign_p2m_entry() + * is supported on RISCV. + */ + return true; +} + +static inline void p2m_altp2m_check(struct vcpu *v, uint16_t idx) +{ + /* Not supported on RISCV. */ +} + +#endif /* __ASM_RISCV_P2M_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Fri Dec 22 15:13:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503455 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99203C41535 for ; Fri, 22 Dec 2023 15:22:45 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659519.1029219 (Exim 4.92) (envelope-from ) id 1rGhMD-0004i0-M8; Fri, 22 Dec 2023 15:22:37 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 659519.1029219; Fri, 22 Dec 2023 15:22:37 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhMD-0004ht-Ie; Fri, 22 Dec 2023 15:22:37 +0000 Received: by outflank-mailman (input) for mailman id 659519; Fri, 22 Dec 2023 15:22:37 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDi-0007Ie-Hb for xen-devel@lists.xenproject.org; Fri, 22 Dec 2023 15:13:50 +0000 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [2a00:1450:4864:20::231]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id b519b854-a0dc-11ee-98eb-6d05b1d4d9a1; Fri, 22 Dec 2023 16:13:48 +0100 (CET) Received: by mail-lj1-x231.google.com with SMTP id 38308e7fff4ca-2cc9b31a27bso23537211fa.3 for ; Fri, 22 Dec 2023 07:13:48 -0800 (PST) Received: from fedora.. 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+ +/* TODO: implement */ +static inline void force_update_vcpu_system_time(struct vcpu *v) { BUG(); } + +typedef unsigned long cycles_t; + +static inline cycles_t get_cycles(void) +{ + return csr_read(CSR_TIME); +} + +#endif /* __ASM_RISCV_TIME_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Fri Dec 22 15:13:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8F36CC46CD2 for ; Fri, 22 Dec 2023 15:14:03 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659431.1029148 (Exim 4.92) (envelope-from ) id 1rGhDl-0004Tu-70; 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id j7-20020a056512108700b0050e6df07728sm45983lfg.180.2023.12.22.07.13.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 07:13:49 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b5d4849c-a0dc-11ee-9b0f-b553b5be7939 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1703258029; x=1703862829; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T52fIi71TBD9YYe45Jg/S335i1e9OJBp7DE409RKwwg=; b=IGljKhOGLYXlJgJV03dxSNBk1+mRe5F703064ChoG8WpTpF+zWAsWQkcSON1PizbpM eRKrgMcX+VR8h14IzL4x6dcHFSR4XZMSKyfeoY/GncL6n2q9UZ85pkpWMSvbBYFab7zG jnxXbVPm58NycnUXAONIXniRyjh4MkXFumBvsWDSEwx+b5tiV45DEoaXTzGfGmA+//is jxKvTR0OZuj0ZmcCt2r8jjAwIpPJa4nI7UOiydzAGsjmDFdtsApLkwDXCMu5Z/vJHRJF 0VXgHLTBR/69rUGli/Cf0GRrQ595BsgYZ6q6GDUoscWLhlsk/nEWegalDW2gbLWflCCg N/Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703258029; x=1703862829; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T52fIi71TBD9YYe45Jg/S335i1e9OJBp7DE409RKwwg=; b=MDB7xgh3Em0ct95sTZAyGaWXqARKbc/T9GJlZ8Jndm36ALZaovBd4VB6czq+Wij1zA YwDC1mhxGizCKy387THD9suirvUXAs/EMcZ6uTLV/nf5rV/ERiMWwVth2ZqR3zVgjlf/ oZYqze0DYc4G1xF+PhvZ4Rt3Q8x+Xit3jGObMTqEwC2je/LVSdJlaYpmJBZ+OMPhpFJd qx/QbWyCDM0cA/tqA0eMHlBxa6W93roUUDPunutqw5d7JLd89YRn+xHFmzpBjjzdRACs tZAnTpPwFNuJoNNLuIeUkAvbfMJ3KBbdgCHt+vvbzgAvCsBfAs9D7eCypqAedDyrPXAy rtgg== X-Gm-Message-State: AOJu0Yw0sXT2X4ZdKBqIqH+H8TlRntgWvwMaK05R7T48Re6EtbYT6akJ bOUfBVdy23XqvLoDaJ02TCZ6CedifkE= X-Google-Smtp-Source: AGHT+IGQXJGum15CcvPL14JMoNUzh9rD3gWGXNQtyvIOk6hSJHgzRUvC57lC84yap9EicWBfh3PDHQ== X-Received: by 2002:a05:6512:3f12:b0:50e:684c:7207 with SMTP id y18-20020a0565123f1200b0050e684c7207mr499315lfa.86.1703258029256; Fri, 22 Dec 2023 07:13:49 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v3 24/34] xen/riscv: introduce event.h Date: Fri, 22 Dec 2023 17:13:08 +0200 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko --- Changes in V3: - add SPDX - add BUG() inside stubs. - update the commit message --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/event.h | 40 ++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 xen/arch/riscv/include/asm/event.h diff --git a/xen/arch/riscv/include/asm/event.h b/xen/arch/riscv/include/asm/event.h new file mode 100644 index 0000000000..65cc5ae168 --- /dev/null +++ b/xen/arch/riscv/include/asm/event.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_RISCV_EVENT_H__ +#define __ASM_RISCV_EVENT_H__ + +#include + +void vcpu_mark_events_pending(struct vcpu *v); + +static inline int vcpu_event_delivery_is_enabled(struct vcpu *v) +{ + BUG(); + return 0; +} + +static inline int local_events_need_delivery(void) +{ + BUG(); + return 0; +} + +static inline void local_event_delivery_enable(void) +{ + BUG(); +} + +/* No arch specific virq definition now. Default to global. */ +static inline bool arch_virq_is_global(unsigned int virq) +{ + return true; +} + +#endif +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Fri Dec 22 15:13:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503448 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C2042C41535 for ; Fri, 22 Dec 2023 15:14:03 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659434.1029158 (Exim 4.92) (envelope-from ) id 1rGhDn-0004uR-5t; Fri, 22 Dec 2023 15:13:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 659434.1029158; Fri, 22 Dec 2023 15:13:55 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDm-0004tu-S7; Fri, 22 Dec 2023 15:13:54 +0000 Received: by outflank-mailman (input) for mailman id 659434; Fri, 22 Dec 2023 15:13:54 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDm-0000EM-0d for xen-devel@lists.xenproject.org; Fri, 22 Dec 2023 15:13:54 +0000 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [2a00:1450:4864:20::12b]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id b6447457-a0dc-11ee-9b0f-b553b5be7939; Fri, 22 Dec 2023 16:13:50 +0100 (CET) Received: by mail-lf1-x12b.google.com with SMTP id 2adb3069b0e04-50e34a72660so2373305e87.1 for ; Fri, 22 Dec 2023 07:13:50 -0800 (PST) Received: from fedora.. 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+ +static inline uint32_t arch_monitor_get_capabilities(struct domain *d) +{ + BUG_ON("unimplemented"); + return 0; +} + +#endif /* __ASM_RISCV_MONITOR_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Fri Dec 22 15:13:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E19EEC4706C for ; Fri, 22 Dec 2023 15:14:04 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659437.1029167 (Exim 4.92) (envelope-from ) id 1rGhDo-0005Kj-PH; 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id j7-20020a056512108700b0050e6df07728sm45983lfg.180.2023.12.22.07.13.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 07:13:50 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b6b03b49-a0dc-11ee-9b0f-b553b5be7939 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1703258031; x=1703862831; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8eSPhcTFUbPdwgMRF6vEav6OFJOc3ZFzJrrGmImsUM0=; b=EOGqhNVpiET431qw1h4wdrFYYucOEGr5chxN9RVNRCmkAMW5Kh/0QfBc/apq8vtaVS Y/bOwf2UOtZX1BOs6dRCGqHfz07iHchZzNVyLa4f5dfJ85NuPTTd9suB61XP0pG6ocOD 6hqEIMW4mrzBOnbxN7OhNvGNobK/s/0wRkH6YzEmf6B5akQUlTWdPF9W6mxcvuMjw3dI 99DfzJcM8RA50MnZRBD9neaUtduEfsE53OggZArSh+eBvD4108LqaUToBRffoMzMm87i YSyhjdJBGsjEw1ALLr3EdRwO1bXyJB5Axr4LrpyY2eP/KL9+McejE056t8xNzUN03xBG o9OA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703258031; x=1703862831; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8eSPhcTFUbPdwgMRF6vEav6OFJOc3ZFzJrrGmImsUM0=; b=AIUofAPWslNPup/RTc+1f2ohAiFJmtWhvAiTGTQl4HGwWZU3T4L0DT6HDDiXOoxBwP SyidFTHP/DR914XdUd76i3kRNUtlBLaULUeP2TucHfoQNlLJdUodjPT5fRFrtlIINgfj 9uzKhAF0L8FK/HUlrm3BI5nKS3LMWW79DHiNNOkN27VQfkUR60fg8uRo/x3PLzUL7R0O zBrUpcC1OjymGGAEW0rKiRPxw/xWt5bf7JFoh4lTsJ71NFk24s0coXtk4fxmSFXaqXHJ gZJHULv4KFfa5UX8GK/Ddu+vFRTjKBif2Bu3ncgQxStAOIC3vJUUJlqDDlZaoLs1Rq68 2vfA== X-Gm-Message-State: AOJu0Yzk4s+9B2ed7q0u3G1row65yuzV8yCQOUyUV/Qw0eKjSOOf7uk8 dwVXCGF8dqytqvsoABY3ynax39oNjF0= X-Google-Smtp-Source: AGHT+IFEsG1MNqzjtUyGkWJ9ZAJ+YosHac50huzAaqYgJlmtxmj/WwHQhQuiJDgzV9FUBmOvcwQc8g== X-Received: by 2002:ac2:5ed1:0:b0:50e:696e:168d with SMTP id d17-20020ac25ed1000000b0050e696e168dmr406590lfq.10.1703258030783; Fri, 22 Dec 2023 07:13:50 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v3 26/34] xen/riscv: add definition of __read_mostly Date: Fri, 22 Dec 2023 17:13:10 +0200 Message-ID: <0ce2db672e336896761144b81b21ddf89329e00b.1703255175.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 The definition of __read_mostly should be removed in: https://lore.kernel.org/xen-devel/f25eb5c9-7c14-6e23-8535-2c66772b333e@suse.com/ The patch introduces it in arch-specific header to not block enabling of full Xen build for RISC-V. Signed-off-by: Oleksii Kurochko --- - [PATCH] move __read_mostly to xen/cache.h [2] Right now, the patch series doesn't have a direct dependency on [2] and it provides __read_mostly in the patch: [PATCH v3 26/34] xen/riscv: add definition of __read_mostly However, it will be dropped as soon as [2] is merged or at least when the final version of the patch [2] is provided. [2] https://lore.kernel.org/xen-devel/f25eb5c9-7c14-6e23-8535-2c66772b333e@suse.com/ --- xen/arch/riscv/include/asm/cache.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/riscv/include/asm/cache.h b/xen/arch/riscv/include/asm/cache.h index 69573eb051..94bd94db53 100644 --- a/xen/arch/riscv/include/asm/cache.h +++ b/xen/arch/riscv/include/asm/cache.h @@ -3,4 +3,6 @@ #ifndef _ASM_RISCV_CACHE_H #define _ASM_RISCV_CACHE_H +#define __read_mostly __section(".data.read_mostly") + #endif /* _ASM_RISCV_CACHE_H */ From patchwork Fri Dec 22 15:13:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503451 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6861AC46CD2 for ; Fri, 22 Dec 2023 15:19:38 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659495.1029180 (Exim 4.92) (envelope-from ) id 1rGhJ8-0001Kp-Ei; Fri, 22 Dec 2023 15:19:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 659495.1029180; Fri, 22 Dec 2023 15:19:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhJ8-0001Ki-Bk; Fri, 22 Dec 2023 15:19:26 +0000 Received: by outflank-mailman (input) for mailman id 659495; Fri, 22 Dec 2023 15:19:25 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDl-0007Ie-I9 for xen-devel@lists.xenproject.org; Fri, 22 Dec 2023 15:13:53 +0000 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [2a00:1450:4864:20::12e]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id b73781d9-a0dc-11ee-98eb-6d05b1d4d9a1; Fri, 22 Dec 2023 16:13:52 +0100 (CET) Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-50e23a4df33so2371709e87.2 for ; Fri, 22 Dec 2023 07:13:52 -0800 (PST) Received: from fedora.. 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Signed-off-by: Oleksii Kurochko --- Changes in V3: - drop OFFSET_BITS, and use PAGE_SHIFT instead. - code style fixes. - add comment how macros are useful. - move all memory related layout definitions close to comment with memory layout description. - make memory layout description generic for any MMU mode. --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/config.h | 85 +++++++++++++++++++---------- 1 file changed, 55 insertions(+), 30 deletions(-) diff --git a/xen/arch/riscv/include/asm/config.h b/xen/arch/riscv/include/asm/config.h index f0544c6a20..fb9fc9daaa 100644 --- a/xen/arch/riscv/include/asm/config.h +++ b/xen/arch/riscv/include/asm/config.h @@ -6,6 +6,14 @@ #include #include +#ifdef CONFIG_RISCV_64 +#define CONFIG_PAGING_LEVELS 3 +#define RV_STAGE1_MODE SATP_MODE_SV39 +#else +#define CONFIG_PAGING_LEVELS 2 +#define RV_STAGE1_MODE SATP_MODE_SV32 +#endif + /* * RISC-V64 Layout: * @@ -22,25 +30,56 @@ * * It means that: * top VA bits are simply ignored for the purpose of translating to PA. +#endif * - * ============================================================================ - * Start addr | End addr | Size | Slot |area description - * ============================================================================ - * FFFFFFFFC0800000 | FFFFFFFFFFFFFFFF |1016 MB | L2 511 | Unused - * FFFFFFFFC0600000 | FFFFFFFFC0800000 | 2 MB | L2 511 | Fixmap - * FFFFFFFFC0200000 | FFFFFFFFC0600000 | 4 MB | L2 511 | FDT - * FFFFFFFFC0000000 | FFFFFFFFC0200000 | 2 MB | L2 511 | Xen - * ... | 1 GB | L2 510 | Unused - * 0000003200000000 | 0000007F80000000 | 309 GB | L2 200-509 | Direct map - * ... | 1 GB | L2 199 | Unused - * 0000003100000000 | 00000031C0000000 | 3 GB | L2 196-198 | Frametable - * ... | 1 GB | L2 195 | Unused - * 0000003080000000 | 00000030C0000000 | 1 GB | L2 194 | VMAP - * ... | 194 GB | L2 0 - 193 | Unused - * ============================================================================ + * SATP_MODE_SV32 | SATP_MODE_SV39 | SATP_MODE_SV48 | SATP_MODE_SV57 + * ==================|==================|==================|================= + * BA0 | FFFFFFFFFFE00000 | FFFFFFFFC0000000 | FFFFFF8000000000 | FFFF000000000000 + * BA1 | 0000000019000000 | 0000003200000000 | 0000640000000000 | 00C8000000000000 + * BA2 | 0000000018800000 | 0000003100000000 | 0000620000000000 | 00C4000000000000 + * BA3 | 0000000018400000 | 0000003080000000 | 0000610000000000 | 00C2000000000000 * -#endif + * =============================================================================== + * Start addr | End addr | Size | Root PT slot | Area description + * =============================================================================== + * BA0 + 0x800000 | FFFFFFFFFFFFFFFF |1016 MB | 511 | Unused + * BA0 + 0x400000 | BA0 + 0x800000 | 2 MB | 511 | Fixmap + * BA0 + 0x200000 | BA0 + 0x400000 | 4 MB | 511 | FDT + * BA0 | BA0 + 0x200000 | 2 MB | 511 | Xen + * ... | 1 GB | 510 | Unused + * BA1 + 0x000000 | BA1 + 0x4D80000000 | 309 GB | 200-509 | Direct map + * ... | 1 GB | 199 | Unused + * BA2 + 0x000000 | BA2 + 0xC0000000 | 3 GB | 196-198 | Frametable + * ... | 1 GB | 195 | Unused + * BA3 + 0x000000 | BA3 + 0x40000000 | 1 GB | 194 | VMAP + * ... | 194 GB | 0 - 193 | Unused + * =============================================================================== */ +#define VPN_BITS (9) + +#define HYP_PT_ROOT_LEVEL (CONFIG_PAGING_LEVELS - 1) + +#ifdef CONFIG_RISCV_64 + +#define SLOTN_ENTRY_BITS (HYP_PT_ROOT_LEVEL * VPN_BITS + PAGE_SHIFT) +#define SLOTN(slot) (_AT(vaddr_t, slot) << SLOTN_ENTRY_BITS) +#define SLOTN_ENTRY_SIZE SLOTN(1) + +#define XEN_VIRT_START 0xFFFFFFFFC0000000 /* (_AC(-1, UL) + 1 - GB(1)) */ + +#define FRAMETABLE_VIRT_START SLOTN(196) +#define FRAMETABLE_SIZE GB(3) +#define FRAMETABLE_NR (FRAMETABLE_SIZE / sizeof(*frame_table)) +#define FRAMETABLE_VIRT_END (FRAMETABLE_VIRT_START + FRAMETABLE_SIZE - 1) + +#define VMAP_VIRT_START SLOTN(194) +#define VMAP_VIRT_SIZE GB(1) + +#else +#error "RV32 isn't supported" +#endif + +#define HYPERVISOR_VIRT_START XEN_VIRT_START #if defined(CONFIG_RISCV_64) # define LONG_BYTEORDER 3 @@ -77,24 +116,10 @@ name: #endif -#ifdef CONFIG_RISCV_64 -#define XEN_VIRT_START 0xFFFFFFFFC0000000 /* (_AC(-1, UL) + 1 - GB(1)) */ -#else -#error "RV32 isn't supported" -#endif - #define SMP_CACHE_BYTES (1 << 6) #define STACK_SIZE PAGE_SIZE -#ifdef CONFIG_RISCV_64 -#define CONFIG_PAGING_LEVELS 3 -#define RV_STAGE1_MODE SATP_MODE_SV39 -#else -#define CONFIG_PAGING_LEVELS 2 -#define RV_STAGE1_MODE SATP_MODE_SV32 -#endif - #define IDENT_AREA_SIZE 64 #endif /* __RISCV_CONFIG_H__ */ From patchwork Fri Dec 22 15:13:12 2023 Content-Type: text/plain; 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Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V3: - add SPDX - drop a forward declaration of struct vcpu; - update guest_cpu_user_regs() macros - replace get_processor_id with smp_processor_id - update the commit message - code style fixes --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/current.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/xen/arch/riscv/include/asm/current.h b/xen/arch/riscv/include/asm/current.h index d84f15dc50..1694f68c6f 100644 --- a/xen/arch/riscv/include/asm/current.h +++ b/xen/arch/riscv/include/asm/current.h @@ -3,6 +3,21 @@ #ifndef __ASM_CURRENT_H #define __ASM_CURRENT_H +#include +#include +#include + +#ifndef __ASSEMBLY__ + +/* Which VCPU is "current" on this PCPU. */ +DECLARE_PER_CPU(struct vcpu *, curr_vcpu); + +#define current this_cpu(curr_vcpu) +#define set_current(vcpu) do { current = (vcpu); } while (0) +#define get_cpu_current(cpu) per_cpu(curr_vcpu, cpu) + +#define guest_cpu_user_regs() ({ BUG(); NULL; }) + #define switch_stack_and_jump(stack, fn) do { \ asm volatile ( \ "mv sp, %0\n" \ @@ -10,4 +25,8 @@ unreachable(); \ } while ( false ) +#define get_per_cpu_offset() __per_cpu_offset[smp_processor_id()] + +#endif /* __ASSEMBLY__ */ + #endif /* __ASM_CURRENT_H */ From patchwork Fri Dec 22 15:13:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503465 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 414A6C41535 for ; Fri, 22 Dec 2023 15:29:41 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659612.1029320 (Exim 4.92) (envelope-from ) id 1rGhSt-0003wL-QK; Fri, 22 Dec 2023 15:29:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 659612.1029320; Fri, 22 Dec 2023 15:29:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhSt-0003wE-MG; Fri, 22 Dec 2023 15:29:31 +0000 Received: by outflank-mailman (input) for mailman id 659612; Fri, 22 Dec 2023 15:29:30 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDm-0007Ie-IX for xen-devel@lists.xenproject.org; Fri, 22 Dec 2023 15:13:54 +0000 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [2a00:1450:4864:20::12f]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id b81e5a7d-a0dc-11ee-98eb-6d05b1d4d9a1; Fri, 22 Dec 2023 16:13:53 +0100 (CET) Received: by mail-lf1-x12f.google.com with SMTP id 2adb3069b0e04-50e67e37661so1185022e87.0 for ; Fri, 22 Dec 2023 07:13:53 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/arch/riscv/include/asm/mm.h | 3 --- xen/arch/riscv/include/asm/page.h | 22 ++++++++++++++++++++++ 2 files changed, 22 insertions(+), 3 deletions(-) diff --git a/xen/arch/riscv/include/asm/mm.h b/xen/arch/riscv/include/asm/mm.h index 07c7a0abba..57026e134d 100644 --- a/xen/arch/riscv/include/asm/mm.h +++ b/xen/arch/riscv/include/asm/mm.h @@ -5,9 +5,6 @@ #include -#define pfn_to_paddr(pfn) ((paddr_t)(pfn) << PAGE_SHIFT) -#define paddr_to_pfn(pa) ((unsigned long)((pa) >> PAGE_SHIFT)) - extern unsigned char cpu0_boot_stack[]; void setup_initial_pagetables(void); diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm/page.h index 95074e29b3..85176702d5 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -6,6 +6,7 @@ #ifndef __ASSEMBLY__ #include +#include #include #include @@ -32,6 +33,10 @@ #define PTE_LEAF_DEFAULT (PTE_VALID | PTE_READABLE | PTE_WRITABLE) #define PTE_TABLE (PTE_VALID) +#define PAGE_HYPERVISOR_RW (PTE_VALID | PTE_READABLE | PTE_WRITABLE) + +#define PAGE_HYPERVISOR PAGE_HYPERVISOR_RW + /* Calculate the offsets into the pagetables for a given VA */ #define pt_linear_offset(lvl, va) ((va) >> XEN_PT_LEVEL_SHIFT(lvl)) @@ -46,6 +51,9 @@ typedef struct { #endif } pte_t; +#define pfn_to_paddr(pfn) ((paddr_t)(pfn) << PAGE_SHIFT) +#define paddr_to_pfn(pa) ((unsigned long)((pa) >> PAGE_SHIFT)) + static inline pte_t paddr_to_pte(paddr_t paddr, unsigned int permissions) { @@ -62,6 +70,20 @@ static inline bool pte_is_valid(pte_t p) return p.pte & PTE_VALID; } +static inline void invalidate_icache(void) +{ + BUG(); +} + +#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) +#define copy_page(dp, sp) memcpy(dp, sp, PAGE_SIZE) + +/* TODO: Flush the dcache for an entire page. */ +static inline void flush_page_to_ram(unsigned long mfn, bool sync_icache) +{ + BUG(); +} + #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_PAGE_H */ From patchwork Fri Dec 22 15:13:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503453 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 03E3FC46CD2 for ; Fri, 22 Dec 2023 15:19:53 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659498.1029200 (Exim 4.92) (envelope-from ) id 1rGhJS-0002AL-TW; Fri, 22 Dec 2023 15:19:46 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 659498.1029200; Fri, 22 Dec 2023 15:19:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhJS-0002AE-Qs; Fri, 22 Dec 2023 15:19:46 +0000 Received: by outflank-mailman (input) for mailman id 659498; Fri, 22 Dec 2023 15:19:45 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDn-0007Ie-MB for xen-devel@lists.xenproject.org; Fri, 22 Dec 2023 15:13:55 +0000 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [2a00:1450:4864:20::136]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id b8f8621c-a0dc-11ee-98eb-6d05b1d4d9a1; Fri, 22 Dec 2023 16:13:55 +0100 (CET) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-50e2d00f99cso2278210e87.0 for ; Fri, 22 Dec 2023 07:13:55 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/arch/riscv/include/asm/processor.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/xen/arch/riscv/include/asm/processor.h b/xen/arch/riscv/include/asm/processor.h index 6db681d805..a3bff6c9c3 100644 --- a/xen/arch/riscv/include/asm/processor.h +++ b/xen/arch/riscv/include/asm/processor.h @@ -12,6 +12,9 @@ #ifndef __ASSEMBLY__ +/* TODO: need to be implemeted */ +#define smp_processor_id() 0 + /* On stack VCPU state */ struct cpu_user_regs { @@ -53,6 +56,18 @@ struct cpu_user_regs unsigned long pregs; }; +/* TODO: need to implement */ +#define cpu_to_core(cpu) (0) +#define cpu_to_socket(cpu) (0) + +static inline void cpu_relax(void) +{ + /* Encoding of the pause instruction */ + __asm__ __volatile__ ( ".insn 0x100000F" ); + + barrier(); +} + static inline void wfi(void) { __asm__ __volatile__ ("wfi"); From patchwork Fri Dec 22 15:13:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503456 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A5481C46CD2 for ; Fri, 22 Dec 2023 15:24:11 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659535.1029230 (Exim 4.92) (envelope-from ) id 1rGhNb-0005aP-0M; Fri, 22 Dec 2023 15:24:03 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 659535.1029230; Fri, 22 Dec 2023 15:24:02 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhNa-0005aI-Ta; Fri, 22 Dec 2023 15:24:02 +0000 Received: by outflank-mailman (input) for mailman id 659535; Fri, 22 Dec 2023 15:24:01 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDs-0000EM-1v for xen-devel@lists.xenproject.org; Fri, 22 Dec 2023 15:14:00 +0000 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [2a00:1450:4864:20::12e]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id b97f9e37-a0dc-11ee-9b0f-b553b5be7939; Fri, 22 Dec 2023 16:13:56 +0100 (CET) Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-50e6ee5b7ffso192009e87.3 for ; Fri, 22 Dec 2023 07:13:56 -0800 (PST) Received: from fedora.. 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+ return NULL; +} + +/* + * We define non-underscored wrappers for above conversion functions. + * These are overriden in various source files while underscored version + * remain intact. + */ +#define virt_to_mfn(va) __virt_to_mfn(va) +#define mfn_to_virt(mfn) __mfn_to_virt(mfn) + +struct page_info +{ + /* Each frame can be threaded onto a doubly-linked list. */ + struct page_list_entry list; + + /* Reference count and various PGC_xxx flags and fields. */ + unsigned long count_info; + + /* Context-dependent fields follow... */ + union { + /* Page is in use: ((count_info & PGC_count_mask) != 0). */ + struct { + /* Type reference count and various PGT_xxx flags and fields. */ + unsigned long type_info; + } inuse; + /* Page is on a free list: ((count_info & PGC_count_mask) == 0). */ + union { + struct { + /* + * Index of the first *possibly* unscrubbed page in the buddy. + * One more bit than maximum possible order to accommodate + * INVALID_DIRTY_IDX. + */ +#define INVALID_DIRTY_IDX ((1UL << (MAX_ORDER + 1)) - 1) + unsigned long first_dirty:MAX_ORDER + 1; + + /* Do TLBs need flushing for safety before next page use? */ + bool need_tlbflush:1; + +#define BUDDY_NOT_SCRUBBING 0 +#define BUDDY_SCRUBBING 1 +#define BUDDY_SCRUB_ABORT 2 + unsigned long scrub_state:2; + }; + + unsigned long val; + } free; + + } u; + + union { + /* Page is in use, but not as a shadow. */ + struct { + /* Owner of this page (zero if page is anonymous). */ + struct domain *domain; + } inuse; + + /* Page is on a free list. */ + struct { + /* Order-size of the free chunk this page is the head of. */ + unsigned int order; + } free; + + } v; + + union { + /* + * Timestamp from 'TLB clock', used to avoid extra safety flushes. + * Only valid for: a) free pages, and b) pages with zero type count + */ + uint32_t tlbflush_timestamp; + }; + uint64_t pad; +}; + +#define frame_table ((struct page_info *)FRAMETABLE_VIRT_START) + +/* PDX of the first page in the frame table. */ +extern unsigned long frametable_base_pdx; + +/* Convert between machine frame numbers and page-info structures. */ +#define mfn_to_page(mfn) \ + (frame_table + (mfn_to_pdx(mfn) - frametable_base_pdx)) +#define page_to_mfn(pg) \ + pdx_to_mfn((unsigned long)((pg) - frame_table) + frametable_base_pdx) + +static inline void *page_to_virt(const struct page_info *pg) +{ + return mfn_to_virt(mfn_x(page_to_mfn(pg))); +} + +/* + * Common code requires get_page_type and put_page_type. + * We don't care about typecounts so we just do the minimum to make it + * happy. + */ +static inline int get_page_type(struct page_info *page, unsigned long type) +{ + return 1; +} + +static inline void put_page_type(struct page_info *page) +{ +} + +static inline void put_page_and_type(struct page_info *page) +{ + put_page_type(page); + put_page(page); +} + +/* + * RISC-V does not have an M2P, but common code expects a handful of + * M2P-related defines and functions. Provide dummy versions of these. + */ +#define INVALID_M2P_ENTRY (~0UL) +#define SHARED_M2P_ENTRY (~0UL - 1UL) +#define SHARED_M2P(_e) ((_e) == SHARED_M2P_ENTRY) + +/* Xen always owns P2M on RISC-V */ +#define set_gpfn_from_mfn(mfn, pfn) do { (void) (mfn), (void)(pfn); } while (0) +#define mfn_to_gfn(d, mfn) ((void)(d), _gfn(mfn_x(mfn))) + +#define PDX_GROUP_SHIFT (16 + 5) + +static inline unsigned long domain_get_maximum_gpfn(struct domain *d) +{ + BUG(); + return 0; +} + +static inline long arch_memory_op(int op, XEN_GUEST_HANDLE_PARAM(void) arg) +{ + BUG(); + return 0; +} + +/* + * On RISCV, all the RAM is currently direct mapped in Xen. + * Hence return always true. + */ +static inline bool arch_mfns_in_directmap(unsigned long mfn, unsigned long nr) +{ + return true; +} + +#define PG_shift(idx) (BITS_PER_LONG - (idx)) +#define PG_mask(x, idx) (x ## UL << PG_shift(idx)) + +#define PGT_none PG_mask(0, 1) /* no special uses of this page */ +#define PGT_writable_page PG_mask(1, 1) /* has writable mappings? */ +#define PGT_type_mask PG_mask(1, 1) /* Bits 31 or 63. */ + + /* Count of uses of this frame as its current type. */ +#define PGT_count_width PG_shift(2) +#define PGT_count_mask ((1UL<count_info&PGC_state) == PGC_state_##st) + +/* Count of references to this frame. */ +#define PGC_count_width PG_shift(9) +#define PGC_count_mask ((1UL<count_info&PGC_state) == PGC_state_##st) + +#define _PGC_extra PG_shift(10) +#define PGC_extra PG_mask(1, 10) + +#define is_xen_heap_page(page) ((page)->count_info & PGC_xen_heap) +#define is_xen_heap_mfn(mfn) \ + (mfn_valid(mfn) && is_xen_heap_page(mfn_to_page(mfn))) + +#define is_xen_fixed_mfn(mfn) \ + ((mfn_to_maddr(mfn) >= virt_to_maddr(&_start)) && \ + (mfn_to_maddr(mfn) <= virt_to_maddr((vaddr_t)_end - 1))) + +#define page_get_owner(_p) (_p)->v.inuse.domain +#define page_set_owner(_p,_d) ((_p)->v.inuse.domain = (_d)) + +/* TODO: implement */ +#define mfn_valid(mfn) ({ (void) (mfn); 0; }) + +#define mfn_to_gfn(d, mfn) ((void)(d), _gfn(mfn_x(mfn))) + +#define domain_set_alloc_bitsize(d) ((void)0) +#define domain_clamp_alloc_bitsize(d, b) (b) + +#define PFN_ORDER(_pfn) ((_pfn)->v.free.order) + extern unsigned char cpu0_boot_stack[]; void setup_initial_pagetables(void); @@ -17,4 +260,9 @@ unsigned long calc_phys_offset(void); void turn_on_mmu(unsigned long ra); +static inline unsigned int arch_get_dma_bitsize(void) +{ + return 32; /* TODO */ +} + #endif /* _ASM_RISCV_MM_H */ From patchwork Fri Dec 22 15:13:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503466 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BD829C41535 for ; Fri, 22 Dec 2023 15:30:34 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659616.1029330 (Exim 4.92) (envelope-from ) id 1rGhTf-0005aO-2R; Fri, 22 Dec 2023 15:30:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 659616.1029330; Fri, 22 Dec 2023 15:30:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhTe-0005aH-VS; Fri, 22 Dec 2023 15:30:18 +0000 Received: by outflank-mailman (input) for mailman id 659616; Fri, 22 Dec 2023 15:30:17 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rGhDq-0007Ie-JV for xen-devel@lists.xenproject.org; Fri, 22 Dec 2023 15:13:58 +0000 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [2a00:1450:4864:20::130]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id ba256bba-a0dc-11ee-98eb-6d05b1d4d9a1; Fri, 22 Dec 2023 16:13:57 +0100 (CET) Received: by mail-lf1-x130.google.com with SMTP id 2adb3069b0e04-50e67e37661so1185101e87.0 for ; Fri, 22 Dec 2023 07:13:57 -0800 (PST) Received: from fedora.. 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703258036; x=1703862836; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Uux9/ht9n0zyze2Voqi+gHdYW+rWh4M6V1sJINQk3xU=; b=fVLXyDjb0arnTgencPLiLWXq6LW3ZyZRsznI0881foVtKiGAf6UqSnCRU/PhlVTgiJ Nuo79uslrZiw8e2UbzOd143Ruvv0/NyCrSUoOmu2T6kVcL3cXU/+AwUHbYuG6Zu+K3as hKiDCn6Tsy7StiiRAtHDZ5U6rlbqSmU6fib8Wa8psNdqjv60e5pwURrOHlX1AosX+8UU cXZxE1jrL4MwqdSSPkHgJ4a7KeSdvjLJ11HDbFIqBGnG5rPFIREeKTNDnNiQvo5A8EX+ FKCgfJ06l8EHcPyCxY53kHoukGamgx3a5ybEORxmH5DNIvNMZk7AM0w4hxgdSeEjciuJ Vu1w== X-Gm-Message-State: AOJu0YxaskvRJh5vsHglEyQi3REgfYsoyRLc191fgtISNHwVys3fIm9G ndpJGpCbR2mcy/67gjDDnjaxfHWPrew= X-Google-Smtp-Source: AGHT+IHt4XL5rDn3bEpiRVYVH6Zms098+K5COh19581fksN1rQs27jcWIB3PCkLPywoTig2bVM5vvA== X-Received: by 2002:ac2:5628:0:b0:50e:66b1:15f6 with SMTP id b8-20020ac25628000000b0050e66b115f6mr891368lff.100.1703258036274; Fri, 22 Dec 2023 07:13:56 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v3 32/34] xen/rirscv: add minimal amount of stubs to build full Xen Date: Fri, 22 Dec 2023 17:13:16 +0200 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko --- Changes in V3: - code style fixes. - update attribute for frametable_base_pdx and frametable_virt_end to __ro_after_init. insteaf of read_mostly. - use BUG() instead of assert_failed/WARN for newly introduced stubs. - drop "#include " in stubs.c and use forward declaration instead. - drop ack_node() and end_node() as they aren't used now. --- Changes in V2: - define udelay stub - remove 'select HAS_PDX' from RISC-V Kconfig because of https://lore.kernel.org/xen-devel/20231006144405.1078260-1-andrew.cooper3@citrix.com/ --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/early_printk.c | 168 -------------- xen/arch/riscv/mm.c | 52 ++++- xen/arch/riscv/setup.c | 9 +- xen/arch/riscv/stubs.c | 422 ++++++++++++++++++++++++++++++++++ xen/arch/riscv/traps.c | 25 ++ 6 files changed, 507 insertions(+), 170 deletions(-) create mode 100644 xen/arch/riscv/stubs.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 2fefe14e7c..5523191bb7 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -4,6 +4,7 @@ obj-y += mm.o obj-$(CONFIG_RISCV_64) += riscv64/ obj-y += sbi.o obj-y += setup.o +obj-y += stubs.o obj-y += traps.o $(TARGET): $(TARGET)-syms diff --git a/xen/arch/riscv/early_printk.c b/xen/arch/riscv/early_printk.c index 60742a042d..610c814f54 100644 --- a/xen/arch/riscv/early_printk.c +++ b/xen/arch/riscv/early_printk.c @@ -40,171 +40,3 @@ void early_printk(const char *str) str++; } } - -/* - * The following #if 1 ... #endif should be removed after printk - * and related stuff are ready. - */ -#if 1 - -#include -#include - -/** - * strlen - Find the length of a string - * @s: The string to be sized - */ -size_t (strlen)(const char * s) -{ - const char *sc; - - for (sc = s; *sc != '\0'; ++sc) - /* nothing */; - return sc - s; -} - -/** - * memcpy - Copy one area of memory to another - * @dest: Where to copy to - * @src: Where to copy from - * @count: The size of the area. - * - * You should not use this function to access IO space, use memcpy_toio() - * or memcpy_fromio() instead. - */ -void *(memcpy)(void *dest, const void *src, size_t count) -{ - char *tmp = (char *) dest, *s = (char *) src; - - while (count--) - *tmp++ = *s++; - - return dest; -} - -int vsnprintf(char* str, size_t size, const char* format, va_list args) -{ - size_t i = 0; /* Current position in the output string */ - size_t written = 0; /* Total number of characters written */ - char* dest = str; - - while ( format[i] != '\0' && written < size - 1 ) - { - if ( format[i] == '%' ) - { - i++; - - if ( format[i] == '\0' ) - break; - - if ( format[i] == '%' ) - { - if ( written < size - 1 ) - { - dest[written] = '%'; - written++; - } - i++; - continue; - } - - /* - * Handle format specifiers. - * For simplicity, only %s and %d are implemented here. - */ - - if ( format[i] == 's' ) - { - char* arg = va_arg(args, char*); - size_t arglen = strlen(arg); - - size_t remaining = size - written - 1; - - if ( arglen > remaining ) - arglen = remaining; - - memcpy(dest + written, arg, arglen); - - written += arglen; - i++; - } - else if ( format[i] == 'd' ) - { - int arg = va_arg(args, int); - - /* Convert the integer to string representation */ - char numstr[32]; /* Assumes a maximum of 32 digits */ - int numlen = 0; - int num = arg; - size_t remaining; - - if ( arg < 0 ) - { - if ( written < size - 1 ) - { - dest[written] = '-'; - written++; - } - - num = -arg; - } - - do - { - numstr[numlen] = '0' + num % 10; - num = num / 10; - numlen++; - } while ( num > 0 ); - - /* Reverse the string */ - for (int j = 0; j < numlen / 2; j++) - { - char tmp = numstr[j]; - numstr[j] = numstr[numlen - 1 - j]; - numstr[numlen - 1 - j] = tmp; - } - - remaining = size - written - 1; - - if ( numlen > remaining ) - numlen = remaining; - - memcpy(dest + written, numstr, numlen); - - written += numlen; - i++; - } - } - else - { - if ( written < size - 1 ) - { - dest[written] = format[i]; - written++; - } - i++; - } - } - - if ( size > 0 ) - dest[written] = '\0'; - - return written; -} - -void printk(const char *format, ...) -{ - static char buf[1024]; - - va_list args; - va_start(args, format); - - (void)vsnprintf(buf, sizeof(buf), format, args); - - early_printk(buf); - - va_end(args); -} - -#endif - diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index 053f043a3d..6cf6f45f7f 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -1,19 +1,23 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include #include +#include #include #include #include #include -#include #include #include +unsigned long __ro_after_init frametable_base_pdx; +unsigned long __ro_after_init frametable_virt_end; + struct mmu_desc { unsigned int num_levels; unsigned int pgtbl_count; @@ -294,3 +298,49 @@ unsigned long __init calc_phys_offset(void) phys_offset = load_start - XEN_VIRT_START; return phys_offset; } + +void put_page(struct page_info *page) +{ + BUG(); +} + +unsigned long get_upper_mfn_bound(void) +{ + /* No memory hotplug yet, so current memory limit is the final one. */ + return max_page - 1; +} + +void arch_dump_shared_mem_info(void) +{ + BUG(); +} + +int populate_pt_range(unsigned long virt, unsigned long nr_mfns) +{ + BUG(); + return -1; +} + +int xenmem_add_to_physmap_one(struct domain *d, unsigned int space, + union add_to_physmap_extra extra, + unsigned long idx, gfn_t gfn) +{ + BUG(); + + return 0; +} + +int destroy_xen_mappings(unsigned long s, unsigned long e) +{ + BUG(); + return -1; +} + +int map_pages_to_xen(unsigned long virt, + mfn_t mfn, + unsigned long nr_mfns, + unsigned int flags) +{ + BUG(); + return -1; +} diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 6593f601c1..8944e0ecfe 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -2,9 +2,16 @@ #include #include +#include + +#include #include -#include + +void arch_get_xen_caps(xen_capabilities_info_t *info) +{ + assert_failed("need to be implemented"); +} /* Xen stack for bringing up the first CPU. */ unsigned char __initdata cpu0_boot_stack[STACK_SIZE] diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c new file mode 100644 index 0000000000..c69d5b5482 --- /dev/null +++ b/xen/arch/riscv/stubs.c @@ -0,0 +1,422 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include +#include +#include +#include + +#include + +/* smpboot.c */ + +cpumask_t cpu_online_map; +cpumask_t cpu_present_map; +cpumask_t cpu_possible_map; + +/* ID of the PCPU we're running on */ +DEFINE_PER_CPU(unsigned int, cpu_id); +/* XXX these seem awfully x86ish... */ +/* representing HT siblings of each logical CPU */ +DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_mask); +/* representing HT and core siblings of each logical CPU */ +DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_mask); + +nodemask_t __read_mostly node_online_map = { { [0] = 1UL } }; + +/* time.c */ + +unsigned long __read_mostly cpu_khz; /* CPU clock frequency in kHz. */ + +s_time_t get_s_time(void) +{ + BUG(); +} + +int reprogram_timer(s_time_t timeout) +{ + BUG(); +} + +void send_timer_event(struct vcpu *v) +{ + BUG(); +} + +void domain_set_time_offset(struct domain *d, int64_t time_offset_seconds) +{ + BUG(); +} + +/* shutdown.c */ + +void machine_restart(unsigned int delay_millisecs) +{ + BUG(); +} + +void machine_halt(void) +{ + BUG(); +} + +/* vm_event.c */ + +struct vm_event_st; + +void vm_event_fill_regs(struct vm_event_st *req) +{ + BUG(); +} + +void vm_event_set_registers(struct vcpu *v, struct vm_event_st *rsp) +{ + BUG(); +} + +void vm_event_monitor_next_interrupt(struct vcpu *v) +{ + /* Not supported on RISCV. */ +} + +void vm_event_reset_vmtrace(struct vcpu *v) +{ + /* Not supported on RISCV. */ +} + +/* domctl.c */ + +long arch_do_domctl(struct xen_domctl *domctl, struct domain *d, + XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl) +{ + BUG(); +} + +void arch_get_domain_info(const struct domain *d, + struct xen_domctl_getdomaininfo *info) +{ + BUG(); +} + +void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c) +{ + BUG(); +} + +/* monitor.c */ + +int arch_monitor_domctl_event(struct domain *d, + struct xen_domctl_monitor_op *mop) +{ + BUG(); +} + +/* smp.c */ + +void arch_flush_tlb_mask(const cpumask_t *mask) +{ + BUG(); +} + +void smp_send_event_check_mask(const cpumask_t *mask) +{ + BUG(); +} + +void smp_send_call_function_mask(const cpumask_t *mask) +{ + BUG(); +} + +/* irq.c */ + +struct pirq *alloc_pirq_struct(struct domain *d) +{ + BUG(); +} + +int pirq_guest_bind(struct vcpu *v, struct pirq *pirq, int will_share) +{ + BUG(); +} + +void pirq_guest_unbind(struct domain *d, struct pirq *pirq) +{ + BUG(); +} + +void pirq_set_affinity(struct domain *d, int pirq, const cpumask_t *mask) +{ + BUG(); +} + +hw_irq_controller no_irq_type = { + .typename = "none", + .startup = irq_startup_none, + .shutdown = irq_shutdown_none, + .enable = irq_enable_none, + .disable = irq_disable_none, +}; + +int arch_init_one_irq_desc(struct irq_desc *desc) +{ + BUG(); +} + +void smp_send_state_dump(unsigned int cpu) +{ + BUG(); +} + +/* domain.c */ + +DEFINE_PER_CPU(struct vcpu *, curr_vcpu); +unsigned long __per_cpu_offset[NR_CPUS]; + +void context_switch(struct vcpu *prev, struct vcpu *next) +{ + BUG(); +} + +void continue_running(struct vcpu *same) +{ + BUG(); +} + +void sync_local_execstate(void) +{ + BUG(); +} + +void sync_vcpu_execstate(struct vcpu *v) +{ + BUG(); +} + +void startup_cpu_idle_loop(void) +{ + BUG(); +} + +void free_domain_struct(struct domain *d) +{ + BUG(); +} + +void dump_pageframe_info(struct domain *d) +{ + BUG(); +} + +void free_vcpu_struct(struct vcpu *v) +{ + BUG(); +} + +int arch_vcpu_create(struct vcpu *v) +{ + BUG(); +} + +void arch_vcpu_destroy(struct vcpu *v) +{ + BUG(); +} + +void vcpu_switch_to_aarch64_mode(struct vcpu *v) +{ + BUG(); +} + +int arch_sanitise_domain_config(struct xen_domctl_createdomain *config) +{ + BUG(); +} + +int arch_domain_create(struct domain *d, + struct xen_domctl_createdomain *config, + unsigned int flags) +{ + BUG(); +} + +int arch_domain_teardown(struct domain *d) +{ + BUG(); +} + +void arch_domain_destroy(struct domain *d) +{ + BUG(); +} + +void arch_domain_shutdown(struct domain *d) +{ + BUG(); +} + +void arch_domain_pause(struct domain *d) +{ + BUG(); +} + +void arch_domain_unpause(struct domain *d) +{ + BUG(); +} + +int arch_domain_soft_reset(struct domain *d) +{ + BUG(); +} + +void arch_domain_creation_finished(struct domain *d) +{ + BUG(); +} + +int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c) +{ + BUG(); +} + +int arch_initialise_vcpu(struct vcpu *v, XEN_GUEST_HANDLE_PARAM(void) arg) +{ + BUG(); +} + +int arch_vcpu_reset(struct vcpu *v) +{ + BUG(); +} + +int domain_relinquish_resources(struct domain *d) +{ + BUG(); +} + +void arch_dump_domain_info(struct domain *d) +{ + BUG(); +} + +void arch_dump_vcpu_info(struct vcpu *v) +{ + BUG(); +} + +void vcpu_mark_events_pending(struct vcpu *v) +{ + BUG(); +} + +void vcpu_update_evtchn_irq(struct vcpu *v) +{ + BUG(); +} + +void vcpu_block_unless_event_pending(struct vcpu *v) +{ + BUG(); +} + +void vcpu_kick(struct vcpu *v) +{ + BUG(); +} + +struct domain *alloc_domain_struct(void) +{ + BUG(); +} + +struct vcpu *alloc_vcpu_struct(const struct domain *d) +{ + BUG(); +} + +unsigned long +hypercall_create_continuation(unsigned int op, const char *format, ...) +{ + BUG(); +} + +int __init parse_arch_dom0_param(const char *s, const char *e) +{ + BUG(); +} + +/* guestcopy.c */ + +unsigned long raw_copy_to_guest(void *to, const void *from, unsigned int len) +{ + BUG(); +} + +unsigned long raw_copy_from_guest(void *to, const void __user *from, + unsigned int len) +{ + BUG(); +} + +/* sysctl.c */ + +long arch_do_sysctl(struct xen_sysctl *sysctl, + XEN_GUEST_HANDLE_PARAM(xen_sysctl_t) u_sysctl) +{ + BUG(); +} + +void arch_do_physinfo(struct xen_sysctl_physinfo *pi) +{ + BUG(); +} + +/* p2m.c */ + +int arch_set_paging_mempool_size(struct domain *d, uint64_t size) +{ + BUG(); +} + +int unmap_mmio_regions(struct domain *d, + gfn_t start_gfn, + unsigned long nr, + mfn_t mfn) +{ + BUG(); +} + +int map_mmio_regions(struct domain *d, + gfn_t start_gfn, + unsigned long nr, + mfn_t mfn) +{ + BUG(); +} + +int set_foreign_p2m_entry(struct domain *d, const struct domain *fd, + unsigned long gfn, mfn_t mfn) +{ + BUG(); +} + +/* Return the size of the pool, in bytes. */ +int arch_get_paging_mempool_size(struct domain *d, uint64_t *size) +{ + BUG(); +} + +/* delay.c */ + +void udelay(unsigned long usecs) +{ + BUG_ON("unimplemented"); +} + +/* guest_access.h */ + +static inline unsigned long raw_clear_guest(void *to, unsigned int len) +{ + BUG_ON("unimplemented"); +} diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index ccd3593f5a..ca56df75d8 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -4,6 +4,10 @@ * * RISC-V Trap handlers */ + +#include +#include + #include #include @@ -11,3 +15,24 @@ void do_trap(struct cpu_user_regs *cpu_regs) { die(); } + +void vcpu_show_execution_state(struct vcpu *v) +{ + assert_failed("need to be implented"); +} + +void show_execution_state(const struct cpu_user_regs *regs) +{ + printk("implement show_execution_state(regs)\n"); +} + +void arch_hypercall_tasklet_result(struct vcpu *v, long res) +{ + assert_failed("need to be implented"); +} + +enum mc_disposition arch_do_multicall_call(struct mc_state *state) +{ + assert_failed("need to be implented"); + return mc_continue; +} From patchwork Fri Dec 22 15:13:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13503452 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 89D8CC41535 for ; Fri, 22 Dec 2023 15:19:39 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.659496.1029190 (Exim 4.92) (envelope-from ) id 1rGhJD-0001cM-Mp; Fri, 22 Dec 2023 15:19:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 659496.1029190; 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Only rebase. --- xen/arch/riscv/Makefile | 16 +++++++++++++++- xen/arch/riscv/arch.mk | 4 ---- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 5523191bb7..c10d43c7e5 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -11,10 +11,24 @@ $(TARGET): $(TARGET)-syms $(OBJCOPY) -O binary -S $< $@ $(TARGET)-syms: $(objtree)/prelink.o $(obj)/xen.lds - $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< $(build_id_linker) -o $@ + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< \ + $(objtree)/common/symbols-dummy.o -o $(dot-target).0 + $(NM) -pa --format=sysv $(dot-target).0 \ + | $(objtree)/tools/symbols $(all_symbols) --sysv --sort \ + > $(dot-target).0.S + $(MAKE) $(build)=$(@D) $(dot-target).0.o + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< \ + $(dot-target).0.o -o $(dot-target).1 + $(NM) -pa --format=sysv $(dot-target).1 \ + | $(objtree)/tools/symbols $(all_symbols) --sysv --sort \ + > $(dot-target).1.S + $(MAKE) $(build)=$(@D) $(dot-target).1.o + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< $(build_id_linker) \ + $(dot-target).1.o -o $@ $(NM) -pa --format=sysv $@ \ | $(objtree)/tools/symbols --all-symbols --xensyms --sysv --sort \ > $@.map + rm -f $(@D)/.$(@F).[0-9]* $(obj)/xen.lds: $(src)/xen.lds.S FORCE $(call if_changed_dep,cpp_lds_S) diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk index 8403f96b6f..12b1673fae 100644 --- a/xen/arch/riscv/arch.mk +++ b/xen/arch/riscv/arch.mk @@ -13,7 +13,3 @@ riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c # -mcmodel=medlow would force Xen into the lower half. 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