From patchwork Wed Jan 3 03:13:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13509633 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0DE72179AA; Wed, 3 Jan 2024 03:09:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="V0IGfVSw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704251375; x=1735787375; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=y4GdVfvr4r3TS2jPrXzPuftPnG1qKJX1nHclPM7uF4Y=; b=V0IGfVSwEe3nvtV02yFbK6g1F/UmV/sfTNBRDFisJc2SHdyGm90IpD5J eBwErT38LEpuUiH53lS5w+tDNTSvF/gPyfVEyf7MhMxm90DmfreZ/lEUK mUKkxeCk7bVsvr2DRyIZAkFCCFGuE5Sjonnq7qBp2Ab8hk0dGNHQQlekm tKKYtHVodc1WW/dyww+ZbkVmYE8cQQC22s9q9NAK1mcvyBuKpmt+/S/FY 5jKfZMqRbKZxT/frqRt/EHaTdxyK3Zh2OnYqOfxK9zgJivPys3nEMGQuJ 09xhev3Zx2+qbkskzeVsqumRjjbfydgHWPpbNY9138+6pip3dM5fai9PN w==; X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="10343118" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="10343118" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2024 19:09:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="729665910" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="729665910" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by orsmga003.jf.intel.com with ESMTP; 02 Jan 2024 19:09:30 -0800 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini , Jim Mattson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v3 01/11] x86: pmu: Remove duplicate code in pmu_init() Date: Wed, 3 Jan 2024 11:13:59 +0800 Message-Id: <20240103031409.2504051-2-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> References: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Xiong Zhang There are totally same code in pmu_init() helper, remove the duplicate code. Signed-off-by: Xiong Zhang Signed-off-by: Dapeng Mi --- lib/x86/pmu.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/lib/x86/pmu.c b/lib/x86/pmu.c index 0f2afd650bc9..d06e94553024 100644 --- a/lib/x86/pmu.c +++ b/lib/x86/pmu.c @@ -16,11 +16,6 @@ void pmu_init(void) pmu.fixed_counter_width = (cpuid_10.d >> 5) & 0xff; } - if (pmu.version > 1) { - pmu.nr_fixed_counters = cpuid_10.d & 0x1f; - pmu.fixed_counter_width = (cpuid_10.d >> 5) & 0xff; - } - pmu.nr_gp_counters = (cpuid_10.a >> 8) & 0xff; pmu.gp_counter_width = (cpuid_10.a >> 16) & 0xff; pmu.gp_counter_mask_length = (cpuid_10.a >> 24) & 0xff; From patchwork Wed Jan 3 03:14:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13509634 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53F3018050; Wed, 3 Jan 2024 03:09:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EF1M32V1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704251378; x=1735787378; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kfSCHGv/CfTNu74cuaUBe9OREwyoA2RBsBWS61xedrk=; b=EF1M32V11YXtj4z32ZUgMykRigj3I3rCzWbJPfOhoOXjOo3vSpJWTXQO g/UNX/fuaOwBOGLdNeaXI8CEePum9Bv5snsDEYT3pBmTitFu221rljvCl j01m1ikEgrZbVimS+4wPFEQYdCqFsHt0TH5P1UHEItBU/lyme3NiQcfNT Guf/+dNKdm2k5Qzsq92pcXuqMo/2He0hZX8SsP2ARKVoCLyfpnIC7gfRm hb3HtI+lfkwbZOpXiWWTaREzROa1M9iy3ks7Xuin+hdBNd/T2UhFitANu qUzMc1Gl5NJ3Y8jAeOcAMm2fbY4nndRc9/shuSwidT2gY71iMeXPPmeQq g==; X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="10343125" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="10343125" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2024 19:09:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="729665921" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="729665921" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by orsmga003.jf.intel.com with ESMTP; 02 Jan 2024 19:09:33 -0800 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini , Jim Mattson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v3 02/11] x86: pmu: Enlarge cnt[] length to 64 in check_counters_many() Date: Wed, 3 Jan 2024 11:14:00 +0800 Message-Id: <20240103031409.2504051-3-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> References: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Considering there are already 8 GP counters and 4 fixed counters on latest Intel processors, like Sapphire Rapids. The original cnt[] array length 10 is definitely not enough to cover all supported PMU counters on these new processors even through currently KVM only supports 3 fixed counters at most. This would cause out of bound memory access and may trigger false alarm on PMU counter validation It's probably more and more GP and fixed counters are introduced in the future and then directly extends the cnt[] array length to 64 once and for all. Signed-off-by: Dapeng Mi Reviewed-by: Jim Mattson --- x86/pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/x86/pmu.c b/x86/pmu.c index 0def28695c70..a13b8a8398c6 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -254,7 +254,7 @@ static void check_fixed_counters(void) static void check_counters_many(void) { - pmu_counter_t cnt[10]; + pmu_counter_t cnt[64]; int i, n; for (i = 0, n = 0; n < pmu.nr_gp_counters; i++) { From patchwork Wed Jan 3 03:14:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13509635 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A97FF182DD; Wed, 3 Jan 2024 03:09:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lTK7QezD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704251381; x=1735787381; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZTgziGb6S+JjPB/4NsS2emVW8oxagsATmMkk72RlKZU=; b=lTK7QezDnVYzUoi2x6HC5fc5GGc7Br8ncihslZTP+uABlNp+2UPF+9D8 Cu2b5/pHVxuW1j57diNjKvwuxL69rOlYokdVs9dNOz09FZkkjkXN4Vscv MJ5bCCTeWn+pk103h3HgeQb7H+JxZL406RxDSR/L3QG1+bWDBEKQUlr7v w7FRo3TNRcEXzxDRyzsx5sqTFNEuJx4LUfedjlq7hEDw2dFTi3wTsgdxX cRcE6j5lQ+RnkSJTixCLrxySrQygodUkNsAXZUDxbxH0/59pZlMBVl+sY GTCEPKY0JwFD+czIZ8RTXwXo9EDli1jMWqQFczIG5yRcOBSPN3y71Etde g==; X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="10343131" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="10343131" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2024 19:09:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="729665930" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="729665930" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by orsmga003.jf.intel.com with ESMTP; 02 Jan 2024 19:09:37 -0800 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini , Jim Mattson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v3 03/11] x86: pmu: Add asserts to warn inconsistent fixed events and counters Date: Wed, 3 Jan 2024 11:14:01 +0800 Message-Id: <20240103031409.2504051-4-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> References: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Current PMU code deosn't check whether PMU fixed counter number is larger than pre-defined fixed events. If so, it would cause memory access out of range. So add assert to warn this invalid case. Signed-off-by: Dapeng Mi Reviewed-by: Mingwei Zhang --- x86/pmu.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index a13b8a8398c6..a42fff8d8b36 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -111,8 +111,12 @@ static struct pmu_event* get_counter_event(pmu_counter_t *cnt) for (i = 0; i < gp_events_size; i++) if (gp_events[i].unit_sel == (cnt->config & 0xffff)) return &gp_events[i]; - } else - return &fixed_events[cnt->ctr - MSR_CORE_PERF_FIXED_CTR0]; + } else { + int idx = cnt->ctr - MSR_CORE_PERF_FIXED_CTR0; + + assert(idx < ARRAY_SIZE(fixed_events)); + return &fixed_events[idx]; + } return (void*)0; } @@ -245,6 +249,7 @@ static void check_fixed_counters(void) }; int i; + assert(pmu.nr_fixed_counters <= ARRAY_SIZE(fixed_events)); for (i = 0; i < pmu.nr_fixed_counters; i++) { cnt.ctr = fixed_events[i].unit_sel; measure_one(&cnt); @@ -266,6 +271,7 @@ static void check_counters_many(void) gp_events[i % gp_events_size].unit_sel; n++; } + assert(pmu.nr_fixed_counters <= ARRAY_SIZE(fixed_events)); for (i = 0; i < pmu.nr_fixed_counters; i++) { cnt[n].ctr = fixed_events[i].unit_sel; cnt[n].config = EVNTSEL_OS | EVNTSEL_USR; From patchwork Wed Jan 3 03:14:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13509636 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0ECD318657; Wed, 3 Jan 2024 03:09:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="CF/B0rch" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704251385; x=1735787385; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IFRmYSrTmp2pxalXjLvBMU2+p6f3KOk5hMuD5pr8++o=; b=CF/B0rchhttdHjZIi6qOw6XwO2OQnj34waFacoSZHU83mJQ/gg/Qo2hL dTFIs56Y2FK7+unpkQek2PAX+mrhnCada5UBYZ9VcXw+NPD2bfmTeki25 zrkpp7TvR70zI4K9fMoSDgOu1Sdt9BWUoYFSacKtXr0gi/gB48nxU3s6V dC/S5lS7JHUJwBgKZm5+GZpR0UVnvvztEf7WKxhyX5TKrDb5p1ngCJXxr fnO5AiOSQQJUYvqbRcdjz3SduqQtkak5BUsQGTVuZgvJxyWJ30NDzV2wS /661zVJaewB37m3VhBBNKc3N5VuVIWO8cKS6kUYDXWNihB4bIi7kDcV06 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="10343137" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="10343137" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2024 19:09:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="729665937" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="729665937" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by orsmga003.jf.intel.com with ESMTP; 02 Jan 2024 19:09:40 -0800 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini , Jim Mattson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v3 04/11] x86: pmu: Switch instructions and core cycles events sequence Date: Wed, 3 Jan 2024 11:14:02 +0800 Message-Id: <20240103031409.2504051-5-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> References: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When running pmu test on SPR, sometimes the following failure is reported. PMU version: 2 GP counters: 8 GP counter width: 48 Mask length: 8 Fixed counters: 3 Fixed counter width: 48 1000000 <= 55109398 <= 50000000 FAIL: Intel: core cycles-0 1000000 <= 18279571 <= 50000000 PASS: Intel: core cycles-1 1000000 <= 12238092 <= 50000000 PASS: Intel: core cycles-2 1000000 <= 7981727 <= 50000000 PASS: Intel: core cycles-3 1000000 <= 6984711 <= 50000000 PASS: Intel: core cycles-4 1000000 <= 6773673 <= 50000000 PASS: Intel: core cycles-5 1000000 <= 6697842 <= 50000000 PASS: Intel: core cycles-6 1000000 <= 6747947 <= 50000000 PASS: Intel: core cycles-7 The count of the "core cycles" on first counter would exceed the upper boundary and leads to a failure, and then the "core cycles" count would drop gradually and reach a stable state. That looks reasonable. The "core cycles" event is defined as the 1st event in xxx_gp_events[] array and it is always verified at first. when the program loop() is executed at the first time it needs to warm up the pipeline and cache, such as it has to wait for cache is filled. All these warm-up work leads to a quite large core cycles count which may exceeds the verification range. The event "instructions" instead of "core cycles" is a good choice as the warm-up event since it would always return a fixed count. Thus switch instructions and core cycles events sequence in the xxx_gp_events[] array. Signed-off-by: Dapeng Mi --- x86/pmu.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index a42fff8d8b36..67ebfbe55b49 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -31,16 +31,16 @@ struct pmu_event { int min; int max; } intel_gp_events[] = { - {"core cycles", 0x003c, 1*N, 50*N}, {"instructions", 0x00c0, 10*N, 10.2*N}, + {"core cycles", 0x003c, 1*N, 50*N}, {"ref cycles", 0x013c, 1*N, 30*N}, {"llc references", 0x4f2e, 1, 2*N}, {"llc misses", 0x412e, 1, 1*N}, {"branches", 0x00c4, 1*N, 1.1*N}, {"branch misses", 0x00c5, 0, 0.1*N}, }, amd_gp_events[] = { - {"core cycles", 0x0076, 1*N, 50*N}, {"instructions", 0x00c0, 10*N, 10.2*N}, + {"core cycles", 0x0076, 1*N, 50*N}, {"branches", 0x00c2, 1*N, 1.1*N}, {"branch misses", 0x00c3, 0, 0.1*N}, }, fixed_events[] = { @@ -307,7 +307,7 @@ static void check_counter_overflow(void) int i; pmu_counter_t cnt = { .ctr = MSR_GP_COUNTERx(0), - .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel /* instructions */, + .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[0].unit_sel /* instructions */, }; overflow_preset = measure_for_overflow(&cnt); @@ -365,11 +365,11 @@ static void check_gp_counter_cmask(void) { pmu_counter_t cnt = { .ctr = MSR_GP_COUNTERx(0), - .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel /* instructions */, + .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[0].unit_sel /* instructions */, }; cnt.config |= (0x2 << EVNTSEL_CMASK_SHIFT); measure_one(&cnt); - report(cnt.count < gp_events[1].min, "cmask"); + report(cnt.count < gp_events[0].min, "cmask"); } static void do_rdpmc_fast(void *ptr) @@ -446,7 +446,7 @@ static void check_running_counter_wrmsr(void) uint64_t count; pmu_counter_t evt = { .ctr = MSR_GP_COUNTERx(0), - .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel, + .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[0].unit_sel, }; report_prefix_push("running counter wrmsr"); @@ -455,7 +455,7 @@ static void check_running_counter_wrmsr(void) loop(); wrmsr(MSR_GP_COUNTERx(0), 0); stop_event(&evt); - report(evt.count < gp_events[1].min, "cntr"); + report(evt.count < gp_events[0].min, "cntr"); /* clear status before overflow test */ if (this_cpu_has_perf_global_status()) @@ -493,7 +493,7 @@ static void check_emulated_instr(void) pmu_counter_t instr_cnt = { .ctr = MSR_GP_COUNTERx(1), /* instructions */ - .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel, + .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[0].unit_sel, }; report_prefix_push("emulated instruction"); From patchwork Wed Jan 3 03:14:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13509637 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38A0818B19; Wed, 3 Jan 2024 03:09:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; 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02 Jan 2024 19:09:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="729665941" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="729665941" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by orsmga003.jf.intel.com with ESMTP; 02 Jan 2024 19:09:44 -0800 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini , Jim Mattson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v3 05/11] x86: pmu: Refine fixed_events[] names Date: Wed, 3 Jan 2024 11:14:03 +0800 Message-Id: <20240103031409.2504051-6-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> References: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In SDM the fixed counter is numbered from 0 but currently the fixed_events names are numbered from 1. It would cause confusion for users. So Change the fixed_events[] names to number from 0 as well and keep identical with SDM. Signed-off-by: Dapeng Mi Reviewed-by: Mingwei Zhang --- x86/pmu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 67ebfbe55b49..a2c64a1ce95b 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -44,9 +44,9 @@ struct pmu_event { {"branches", 0x00c2, 1*N, 1.1*N}, {"branch misses", 0x00c3, 0, 0.1*N}, }, fixed_events[] = { - {"fixed 1", MSR_CORE_PERF_FIXED_CTR0, 10*N, 10.2*N}, - {"fixed 2", MSR_CORE_PERF_FIXED_CTR0 + 1, 1*N, 30*N}, - {"fixed 3", MSR_CORE_PERF_FIXED_CTR0 + 2, 0.1*N, 30*N} + {"fixed 0", MSR_CORE_PERF_FIXED_CTR0, 10*N, 10.2*N}, + {"fixed 1", MSR_CORE_PERF_FIXED_CTR0 + 1, 1*N, 30*N}, + {"fixed 2", MSR_CORE_PERF_FIXED_CTR0 + 2, 0.1*N, 30*N} }; char *buf; From patchwork Wed Jan 3 03:14:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13509638 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C7DD18E00; Wed, 3 Jan 2024 03:09:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ID6m0ohx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704251391; x=1735787391; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lWYg4zV2NcJ4nxhSpA6Fg/s1u8gQGW0XjbSleu1w/Jo=; b=ID6m0ohxfEQNdo11ngGMnYKGDk++nSIzSxrOHOJm9WZSZNC1ZgI3+KjH 0iEJnBRVRpapdvZ2AYnqQ/R3RuWK5kg6tyEDBIGMZDLotVGLkPjH551A6 FacB5ciBdIEYCOpR5nIxeTi09vug/iat+ozGSPr+XYfa9b8RD7t112dfX VsLW4sWRrZ+cV1GJXJdPD09naavbJDVq4Nkea8SGyYcAZFsE6kFCAO3m8 Z6VLft4ZEHSAAXP978vuIrYwnW5kDoiBobS0jlfZAb9uCBHw4N0kiZj7v JAarTI3Fn8KKRuYppgExAjwWkhnBseC/UhtZ8YpipO/6XzldT9ZsTaR0R g==; X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="10343149" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="10343149" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2024 19:09:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="729665948" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="729665948" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by orsmga003.jf.intel.com with ESMTP; 02 Jan 2024 19:09:47 -0800 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini , Jim Mattson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v3 06/11] x86: pmu: Remove blank line and redundant space Date: Wed, 3 Jan 2024 11:14:04 +0800 Message-Id: <20240103031409.2504051-7-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> References: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 code style changes. Signed-off-by: Dapeng Mi Reviewed-by: Mingwei Zhang --- x86/pmu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index a2c64a1ce95b..46bed66c5c9f 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -207,8 +207,7 @@ static noinline void __measure(pmu_counter_t *evt, uint64_t count) static bool verify_event(uint64_t count, struct pmu_event *e) { // printf("%d <= %ld <= %d\n", e->min, count, e->max); - return count >= e->min && count <= e->max; - + return count >= e->min && count <= e->max; } static bool verify_counter(pmu_counter_t *cnt) From patchwork Wed Jan 3 03:14:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13509639 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77C1418EA5; Wed, 3 Jan 2024 03:09:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Y1GnUrsN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704251398; x=1735787398; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VsfReKWKrlyt+Eg4eEpxHPMlAigKAPvNomF616KoHYs=; b=Y1GnUrsNkT/N+0X8jzVZYcXI2zjPjMFwVDai23ai3ay5DdE+yZCq22O8 US7AjyLN0kiK3jq/n42vjhFtCN/H85ClXy950bVcNm5rnWF7lBQmklD8X NKNXUZXUYMPnj+iDCpqFuiYfGJScGseW4eB1yMklhRqYZXUl84tG0Jwa9 uplwuPoHc5WLs9OKnCB27WM+iPA8foma/iJ+vCdfyd0eeg+awEgrhKszX NZ1IX2NwLUA9lhJAuJACeE/Zi/EKh99jTb1JP1asrfO6ZTk7+EyRiLlhF 53l977paB0QYKHzDsv/spJw7YP1aGjaA4UCOGUTzKRxDZlGmmQ8kdUF1P Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="10343159" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="10343159" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2024 19:09:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="729665956" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="729665956" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by orsmga003.jf.intel.com with ESMTP; 02 Jan 2024 19:09:50 -0800 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini , Jim Mattson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v3 07/11] x86: pmu: Enable and disable PMCs in loop() asm blob Date: Wed, 3 Jan 2024 11:14:05 +0800 Message-Id: <20240103031409.2504051-8-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> References: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Currently enabling PMCs, executing loop() and disabling PMCs are divided 3 separated functions. So there could be other instructions executed between enabling PMCS and running loop() or running loop() and disabling PMCs, e.g. if there are multiple counters enabled in measure_many() function, the instructions which enabling the 2nd and more counters would be counted in by the 1st counter. So current implementation can only verify the correctness of count by an rough range rather than a precise count even for instructions and branches events. Strictly speaking, this verification is meaningless as the test could still pass even though KVM vPMU has something wrong and reports an incorrect instructions or branches count which is in the rough range. Thus, move the PMCs enabling and disabling into the loop() asm blob and ensure only the loop asm instructions would be counted, then the instructions or branches events can be verified with an precise count instead of an rough range. Signed-off-by: Dapeng Mi --- x86/pmu.c | 83 +++++++++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 69 insertions(+), 14 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 46bed66c5c9f..88b89ad889b9 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -18,6 +18,20 @@ #define EXPECTED_INSTR 17 #define EXPECTED_BRNCH 5 +// Instrustion number of LOOP_ASM code +#define LOOP_INSTRNS 10 +#define LOOP_ASM \ + "1: mov (%1), %2; add $64, %1;\n\t" \ + "nop; nop; nop; nop; nop; nop; nop;\n\t" \ + "loop 1b;\n\t" + +#define PRECISE_LOOP_ASM \ + "wrmsr;\n\t" \ + "mov %%ecx, %%edi; mov %%ebx, %%ecx;\n\t" \ + LOOP_ASM \ + "mov %%edi, %%ecx; xor %%eax, %%eax; xor %%edx, %%edx;\n\t" \ + "wrmsr;\n\t" + typedef struct { uint32_t ctr; uint64_t config; @@ -54,13 +68,43 @@ char *buf; static struct pmu_event *gp_events; static unsigned int gp_events_size; -static inline void loop(void) + +static inline void __loop(void) +{ + unsigned long tmp, tmp2, tmp3; + + asm volatile(LOOP_ASM + : "=c"(tmp), "=r"(tmp2), "=r"(tmp3) + : "0"(N), "1"(buf)); +} + +/* + * Enable and disable counters in a whole asm blob to ensure + * no other instructions are counted in the time slot between + * counters enabling and really LOOP_ASM code executing. + * Thus counters can verify instructions and branches events + * against precise counts instead of a rough valid count range. + */ +static inline void __precise_count_loop(u64 cntrs) { unsigned long tmp, tmp2, tmp3; + unsigned int global_ctl = pmu.msr_global_ctl; + u32 eax = cntrs & (BIT_ULL(32) - 1); + u32 edx = cntrs >> 32; - asm volatile("1: mov (%1), %2; add $64, %1; nop; nop; nop; nop; nop; nop; nop; loop 1b" - : "=c"(tmp), "=r"(tmp2), "=r"(tmp3): "0"(N), "1"(buf)); + asm volatile(PRECISE_LOOP_ASM + : "=b"(tmp), "=r"(tmp2), "=r"(tmp3) + : "a"(eax), "d"(edx), "c"(global_ctl), + "0"(N), "1"(buf) + : "edi"); +} +static inline void loop(u64 cntrs) +{ + if (!this_cpu_has_perf_global_ctrl()) + __loop(); + else + __precise_count_loop(cntrs); } volatile uint64_t irq_received; @@ -159,18 +203,17 @@ static void __start_event(pmu_counter_t *evt, uint64_t count) ctrl = (ctrl & ~(0xf << shift)) | (usrospmi << shift); wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, ctrl); } - global_enable(evt); apic_write(APIC_LVTPC, PMI_VECTOR); } static void start_event(pmu_counter_t *evt) { __start_event(evt, 0); + global_enable(evt); } -static void stop_event(pmu_counter_t *evt) +static void __stop_event(pmu_counter_t *evt) { - global_disable(evt); if (is_gp(evt)) { wrmsr(MSR_GP_EVENT_SELECTx(event_to_global_idx(evt)), evt->config & ~EVNTSEL_EN); @@ -182,14 +225,24 @@ static void stop_event(pmu_counter_t *evt) evt->count = rdmsr(evt->ctr); } +static void stop_event(pmu_counter_t *evt) +{ + global_disable(evt); + __stop_event(evt); +} + static noinline void measure_many(pmu_counter_t *evt, int count) { int i; + u64 cntrs = 0; + + for (i = 0; i < count; i++) { + __start_event(&evt[i], 0); + cntrs |= BIT_ULL(event_to_global_idx(&evt[i])); + } + loop(cntrs); for (i = 0; i < count; i++) - start_event(&evt[i]); - loop(); - for (i = 0; i < count; i++) - stop_event(&evt[i]); + __stop_event(&evt[i]); } static void measure_one(pmu_counter_t *evt) @@ -199,9 +252,11 @@ static void measure_one(pmu_counter_t *evt) static noinline void __measure(pmu_counter_t *evt, uint64_t count) { + u64 cntrs = BIT_ULL(event_to_global_idx(evt)); + __start_event(evt, count); - loop(); - stop_event(evt); + loop(cntrs); + __stop_event(evt); } static bool verify_event(uint64_t count, struct pmu_event *e) @@ -451,7 +506,7 @@ static void check_running_counter_wrmsr(void) report_prefix_push("running counter wrmsr"); start_event(&evt); - loop(); + __loop(); wrmsr(MSR_GP_COUNTERx(0), 0); stop_event(&evt); report(evt.count < gp_events[0].min, "cntr"); @@ -468,7 +523,7 @@ static void check_running_counter_wrmsr(void) wrmsr(MSR_GP_COUNTERx(0), count); - loop(); + __loop(); stop_event(&evt); if (this_cpu_has_perf_global_status()) { From patchwork Wed Jan 3 03:14:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13509640 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51C5818EB1; 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a="10343166" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="10343166" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2024 19:10:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="729665980" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="729665980" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by orsmga003.jf.intel.com with ESMTP; 02 Jan 2024 19:09:55 -0800 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini , Jim Mattson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v3 08/11] x86: pmu: Improve instruction and branches events verification Date: Wed, 3 Jan 2024 11:14:06 +0800 Message-Id: <20240103031409.2504051-9-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> References: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 If HW supports GLOBAL_CTRL MSR, enabling and disabling PMCs are moved in __precise_count_loop(). Thus, instructions and branches events can be verified against a precise count instead of a rough range. Signed-off-by: Dapeng Mi --- x86/pmu.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/x86/pmu.c b/x86/pmu.c index 88b89ad889b9..b764827c1c3d 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -25,6 +25,10 @@ "nop; nop; nop; nop; nop; nop; nop;\n\t" \ "loop 1b;\n\t" +/*Enable GLOBAL_CTRL + disable GLOBAL_CTRL instructions */ +#define PRECISE_EXTRA_INSTRNS (2 + 4) +#define PRECISE_LOOP_INSTRNS (N * LOOP_INSTRNS + PRECISE_EXTRA_INSTRNS) +#define PRECISE_LOOP_BRANCHES (N) #define PRECISE_LOOP_ASM \ "wrmsr;\n\t" \ "mov %%ecx, %%edi; mov %%ebx, %%ecx;\n\t" \ @@ -107,6 +111,24 @@ static inline void loop(u64 cntrs) __precise_count_loop(cntrs); } +static void adjust_events_range(struct pmu_event *gp_events, int branch_idx) +{ + /* + * If HW supports GLOBAL_CTRL MSR, enabling and disabling PMCs are + * moved in __precise_count_loop(). Thus, instructions and branches + * events can be verified against a precise count instead of a rough + * range. + */ + if (this_cpu_has_perf_global_ctrl()) { + /* instructions event */ + gp_events[0].min = PRECISE_LOOP_INSTRNS; + gp_events[0].max = PRECISE_LOOP_INSTRNS; + /* branches event */ + gp_events[branch_idx].min = PRECISE_LOOP_BRANCHES; + gp_events[branch_idx].max = PRECISE_LOOP_BRANCHES; + } +} + volatile uint64_t irq_received; static void cnt_overflow(isr_regs_t *regs) @@ -771,6 +793,7 @@ static void check_invalid_rdpmc_gp(void) int main(int ac, char **av) { + int branch_idx; setup_vm(); handle_irq(PMI_VECTOR, cnt_overflow); buf = malloc(N*64); @@ -784,13 +807,16 @@ int main(int ac, char **av) } gp_events = (struct pmu_event *)intel_gp_events; gp_events_size = sizeof(intel_gp_events)/sizeof(intel_gp_events[0]); + branch_idx = 5; report_prefix_push("Intel"); set_ref_cycle_expectations(); } else { gp_events_size = sizeof(amd_gp_events)/sizeof(amd_gp_events[0]); gp_events = (struct pmu_event *)amd_gp_events; + branch_idx = 2; report_prefix_push("AMD"); } + adjust_events_range(gp_events, branch_idx); printf("PMU version: %d\n", pmu.version); printf("GP counters: %d\n", pmu.nr_gp_counters); From patchwork Wed Jan 3 03:14:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13509641 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD34319463; Wed, 3 Jan 2024 03:10:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="jaOdIqdh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704251403; x=1735787403; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ggD022wR84eJIDVFaJvrBBLC8iM3MXpUAJp9grwTY5c=; b=jaOdIqdhjNOVG2PVsQDLtksIY2ZirVCejRu9P0SlMsoTR7kOm6dhsT+7 KU/YOf3E/f+U6PrV4Ql6Eu16nka87XPqOz3HZohY0K3/lK2A0hRgqDQZ4 d4VvBP0FAtAN1Gi+vG2boC9QLau0uxuCx157YFClazgQnls7YK8Wlbmkg eY4w6tYIquyRv8wnsp+sOatbpk+P4fkS7E4tc0BvJtce1fAmGczfy7d+H 30qDqFzwpI8ul5qaVv7OhEH+KYEXi5+r/Czo0uC9N6FmVnBJ8YIlatz/U CYZJOoQJL3icoqs5dUCJ8hVIn8MdRTyifyUYCAkH2RQk9vV/a5uual5yv Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="10343171" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="10343171" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2024 19:10:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="729665992" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="729665992" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by orsmga003.jf.intel.com with ESMTP; 02 Jan 2024 19:09:59 -0800 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini , Jim Mattson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v3 09/11] x86: pmu: Improve LLC misses event verification Date: Wed, 3 Jan 2024 11:14:07 +0800 Message-Id: <20240103031409.2504051-10-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> References: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When running pmu test on SPR, sometimes the following failure is reported. 1 <= 0 <= 1000000 FAIL: Intel: llc misses-4 Currently The LLC misses occurring only depends on probability. It's possible that there is no LLC misses happened in the whole loop(), especially along with processors have larger and larger cache size just like what we observed on SPR. Thus, add clflush instruction into the loop() asm blob and ensure once LLC miss is triggered at least. Suggested-by: Jim Mattson Signed-off-by: Dapeng Mi --- x86/pmu.c | 43 ++++++++++++++++++++++++++++++------------- 1 file changed, 30 insertions(+), 13 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index b764827c1c3d..8fd3db0fbf81 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -20,19 +20,21 @@ // Instrustion number of LOOP_ASM code #define LOOP_INSTRNS 10 -#define LOOP_ASM \ +#define LOOP_ASM(_clflush) \ + _clflush "\n\t" \ + "mfence;\n\t" \ "1: mov (%1), %2; add $64, %1;\n\t" \ "nop; nop; nop; nop; nop; nop; nop;\n\t" \ "loop 1b;\n\t" -/*Enable GLOBAL_CTRL + disable GLOBAL_CTRL instructions */ -#define PRECISE_EXTRA_INSTRNS (2 + 4) +/*Enable GLOBAL_CTRL + disable GLOBAL_CTRL + clflush/mfence instructions */ +#define PRECISE_EXTRA_INSTRNS (2 + 4 + 2) #define PRECISE_LOOP_INSTRNS (N * LOOP_INSTRNS + PRECISE_EXTRA_INSTRNS) #define PRECISE_LOOP_BRANCHES (N) -#define PRECISE_LOOP_ASM \ +#define PRECISE_LOOP_ASM(_clflush) \ "wrmsr;\n\t" \ "mov %%ecx, %%edi; mov %%ebx, %%ecx;\n\t" \ - LOOP_ASM \ + LOOP_ASM(_clflush) \ "mov %%edi, %%ecx; xor %%eax, %%eax; xor %%edx, %%edx;\n\t" \ "wrmsr;\n\t" @@ -72,14 +74,30 @@ char *buf; static struct pmu_event *gp_events; static unsigned int gp_events_size; +#define _loop_asm(_clflush) \ +do { \ + asm volatile(LOOP_ASM(_clflush) \ + : "=c"(tmp), "=r"(tmp2), "=r"(tmp3) \ + : "0"(N), "1"(buf)); \ +} while (0) + +#define _precise_loop_asm(_clflush) \ +do { \ + asm volatile(PRECISE_LOOP_ASM(_clflush) \ + : "=b"(tmp), "=r"(tmp2), "=r"(tmp3) \ + : "a"(eax), "d"(edx), "c"(global_ctl), \ + "0"(N), "1"(buf) \ + : "edi"); \ +} while (0) static inline void __loop(void) { unsigned long tmp, tmp2, tmp3; - asm volatile(LOOP_ASM - : "=c"(tmp), "=r"(tmp2), "=r"(tmp3) - : "0"(N), "1"(buf)); + if (this_cpu_has(X86_FEATURE_CLFLUSH)) + _loop_asm("clflush (%1)"); + else + _loop_asm("nop"); } /* @@ -96,11 +114,10 @@ static inline void __precise_count_loop(u64 cntrs) u32 eax = cntrs & (BIT_ULL(32) - 1); u32 edx = cntrs >> 32; - asm volatile(PRECISE_LOOP_ASM - : "=b"(tmp), "=r"(tmp2), "=r"(tmp3) - : "a"(eax), "d"(edx), "c"(global_ctl), - "0"(N), "1"(buf) - : "edi"); + if (this_cpu_has(X86_FEATURE_CLFLUSH)) + _precise_loop_asm("clflush (%1)"); + else + _precise_loop_asm("nop"); } static inline void loop(u64 cntrs) From patchwork Wed Jan 3 03:14:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13509642 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F0B5199BA; Wed, 3 Jan 2024 03:10:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ixumY8aB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704251407; x=1735787407; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=z72wvalERNtglXdFe8pPE83KEOIKaIWcyGSzLUbOvDI=; b=ixumY8aBQOIA1m9LZaMEx+qy7AZHiVz52HmKzcu6l//fAJ2NBF/2zVBr mpERtf11o9D85zSiw6up3ufVuXrdPKgyvr+YZbr77JJiXQtpCdaWTthqZ qVFvaXE6xEd9GDKbedJETIzdxNkni54XtGHLKdB9P06E95B1v8We4TU2W 3fc2vB0nZrMucpDayYizIcgZYssl+lZAQNaFpOGDjWPiswYLhPrbmJmIq fiDx6aRfC8sNmqdmOj7eCEezwdHjMXWe83Wfh8dPaq1lhGfRAhq8MHh9J t1RUbn/0M7S+uWnlzYw+Fj8RwWRxkTg6ivKpDHIRWskGVZfftrG75ACwQ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="10343176" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="10343176" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2024 19:10:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="729666003" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="729666003" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by orsmga003.jf.intel.com with ESMTP; 02 Jan 2024 19:10:02 -0800 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini , Jim Mattson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v3 10/11] x86: pmu: Add IBPB indirect jump asm blob Date: Wed, 3 Jan 2024 11:14:08 +0800 Message-Id: <20240103031409.2504051-11-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> References: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Currently the lower boundary of branch misses event is set to 0. Strictly speaking 0 shouldn't be a valid count since it can't tell us if branch misses event counter works correctly or even disabled. Whereas it's also possible and reasonable that branch misses event count is 0 especailly for such simple loop() program with advanced branch predictor. To eliminate such ambiguity and make branch misses event verification more acccurately, an extra IBPB indirect jump asm blob is appended and IBPB command is leveraged to clear the branch target buffer and force to cause a branch miss for the indirect jump. Suggested-by: Jim Mattson Signed-off-by: Dapeng Mi --- x86/pmu.c | 56 +++++++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 42 insertions(+), 14 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 8fd3db0fbf81..c8d4a0dcd362 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -27,14 +27,26 @@ "nop; nop; nop; nop; nop; nop; nop;\n\t" \ "loop 1b;\n\t" -/*Enable GLOBAL_CTRL + disable GLOBAL_CTRL + clflush/mfence instructions */ -#define PRECISE_EXTRA_INSTRNS (2 + 4 + 2) +#define IBPB_JMP_INSTRNS 7 +#define IBPB_JMP_BRANCHES 1 +#define IBPB_JMP_ASM(_wrmsr) \ + "mov $1, %%eax; xor %%edx, %%edx;\n\t" \ + "mov $73, %%ecx;\n\t" \ + _wrmsr "\n\t" \ + "lea 2f, %%rax;\n\t" \ + "jmp *%%rax;\n\t" \ + "nop;\n\t" \ + "2: nop;\n\t" + +/* GLOBAL_CTRL enable + disable + clflush/mfence + IBPB_JMP */ +#define PRECISE_EXTRA_INSTRNS (2 + 4 + 2 + IBPB_JMP_INSTRNS) #define PRECISE_LOOP_INSTRNS (N * LOOP_INSTRNS + PRECISE_EXTRA_INSTRNS) -#define PRECISE_LOOP_BRANCHES (N) -#define PRECISE_LOOP_ASM(_clflush) \ +#define PRECISE_LOOP_BRANCHES (N + IBPB_JMP_BRANCHES) +#define PRECISE_LOOP_ASM(_clflush, _wrmsr) \ "wrmsr;\n\t" \ "mov %%ecx, %%edi; mov %%ebx, %%ecx;\n\t" \ LOOP_ASM(_clflush) \ + IBPB_JMP_ASM(_wrmsr) \ "mov %%edi, %%ecx; xor %%eax, %%eax; xor %%edx, %%edx;\n\t" \ "wrmsr;\n\t" @@ -74,30 +86,42 @@ char *buf; static struct pmu_event *gp_events; static unsigned int gp_events_size; -#define _loop_asm(_clflush) \ +#define _loop_asm(_clflush, _wrmsr) \ do { \ asm volatile(LOOP_ASM(_clflush) \ + IBPB_JMP_ASM(_wrmsr) \ : "=c"(tmp), "=r"(tmp2), "=r"(tmp3) \ - : "0"(N), "1"(buf)); \ + : "0"(N), "1"(buf) \ + : "eax", "edx"); \ } while (0) -#define _precise_loop_asm(_clflush) \ +#define _precise_loop_asm(_clflush, _wrmsr) \ do { \ - asm volatile(PRECISE_LOOP_ASM(_clflush) \ + asm volatile(PRECISE_LOOP_ASM(_clflush, _wrmsr) \ : "=b"(tmp), "=r"(tmp2), "=r"(tmp3) \ : "a"(eax), "d"(edx), "c"(global_ctl), \ "0"(N), "1"(buf) \ : "edi"); \ } while (0) +static int has_ibpb(void) +{ + return this_cpu_has(X86_FEATURE_SPEC_CTRL) || + this_cpu_has(X86_FEATURE_AMD_IBPB); +} + static inline void __loop(void) { unsigned long tmp, tmp2, tmp3; - if (this_cpu_has(X86_FEATURE_CLFLUSH)) - _loop_asm("clflush (%1)"); + if (this_cpu_has(X86_FEATURE_CLFLUSH) && has_ibpb()) + _loop_asm("clflush (%1)", "wrmsr"); + else if (this_cpu_has(X86_FEATURE_CLFLUSH)) + _loop_asm("clflush (%1)", "nop"); + else if (has_ibpb()) + _loop_asm("nop", "wrmsr"); else - _loop_asm("nop"); + _loop_asm("nop", "nop"); } /* @@ -114,10 +138,14 @@ static inline void __precise_count_loop(u64 cntrs) u32 eax = cntrs & (BIT_ULL(32) - 1); u32 edx = cntrs >> 32; - if (this_cpu_has(X86_FEATURE_CLFLUSH)) - _precise_loop_asm("clflush (%1)"); + if (this_cpu_has(X86_FEATURE_CLFLUSH) && has_ibpb()) + _precise_loop_asm("clflush (%1)", "wrmsr"); + else if (this_cpu_has(X86_FEATURE_CLFLUSH)) + _precise_loop_asm("clflush (%1)", "nop"); + else if (has_ibpb()) + _precise_loop_asm("nop", "wrmsr"); else - _precise_loop_asm("nop"); + _precise_loop_asm("nop", "nop"); } static inline void loop(u64 cntrs) From patchwork Wed Jan 3 03:14:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13509643 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F63E19BBA; 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a="10343183" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="10343183" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2024 19:10:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="729666013" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="729666013" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by orsmga003.jf.intel.com with ESMTP; 02 Jan 2024 19:10:06 -0800 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini , Jim Mattson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v3 11/11] x86: pmu: Improve branch misses event verification Date: Wed, 3 Jan 2024 11:14:09 +0800 Message-Id: <20240103031409.2504051-12-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> References: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Since IBPB command is already leveraged to force one branch miss triggering, the lower boundary of branch misses event can be set to 1 instead of 0 on IBPB supported processors. Thus the ambiguity from 0 can be eliminated. Signed-off-by: Dapeng Mi --- x86/pmu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/x86/pmu.c b/x86/pmu.c index c8d4a0dcd362..d5c3fcfaa84c 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -172,6 +172,16 @@ static void adjust_events_range(struct pmu_event *gp_events, int branch_idx) gp_events[branch_idx].min = PRECISE_LOOP_BRANCHES; gp_events[branch_idx].max = PRECISE_LOOP_BRANCHES; } + + /* + * If HW supports IBPB, one branch miss is forced to trigger by + * IBPB command. Thus overwrite the lower boundary of branch misses + * event to 1. + */ + if (has_ibpb()) { + /* branch misses event */ + gp_events[branch_idx + 1].min = 1; + } } volatile uint64_t irq_received;