From patchwork Wed Jan 3 14:28:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Gantois X-Patchwork-Id: 13510114 X-Patchwork-Delegate: kieran@bingham.xyz Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46F231A59D; Wed, 3 Jan 2024 14:28:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="BhhDi2i8" Received: by mail.gandi.net (Postfix) with ESMTPSA id A287E6000E; Wed, 3 Jan 2024 14:28:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1704292100; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sIzE85qqMU4ljpuVTgJrBzU9sL9vWxRn1Kuat+K5IJY=; b=BhhDi2i820PKEIjVb8tsSUzcTWykZmsBGYRCPClziJp83Ljiftdi+GLvHHUsM81zoCPfvj j0jvoSHlZLHTY2rpAaQNLHxC2AwRTzO83Idszu9hHutueS3jT9xXXM6njHBCqcQulKF5pG PZUSjxuKU/17lG/oq/NfhBUmaz9N8tPwqY2DCgGZoJxJai23f5JGCsQ2MUNXlh2Dq0/SQq 0B8htGid8qvasKIwKbxUSHe8HTk4Cz+ZNcy0zYH24MzYobIyrmH8aMOIvg7NpAagQ6J96T dAPU9x6DOmeAdyVCgGs2VUmUXrHnukTSjEqX1B6kx6Wy2XxYsz06HPYb8RJBmA== From: Romain Gantois To: Alexandre Torgue , Jose Abreu , Russell King , Andrew Lunn , Jakub Kicinski , Heiner Kallweit Cc: "David S. Miller" , Eric Dumazet , Paolo Abeni , Maxime Coquelin , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Marek Vasut , Clark Wang , Miquel Raynal , Sylvain Girard , Pascal EBERHARD , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Romain Gantois Subject: [PATCH net 1/5] net: phy: add PHY_F_RXC_ALWAYS_ON to PHY dev flags Date: Wed, 3 Jan 2024 15:28:21 +0100 Message-ID: <20240103142827.168321-2-romain.gantois@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103142827.168321-1-romain.gantois@bootlin.com> References: <20240103142827.168321-1-romain.gantois@bootlin.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: romain.gantois@bootlin.com From: Russell King Some MAC controllers (e.g. stmmac) require their connected PHY to continuously provide a receive clock signal. This can cause issues in two cases: 1. The clock signal hasn't been started yet by the time the MAC driver initializes its hardware. This can make the initialization fail, as in the case of the rzn1 GMAC1 driver. 2. The clock signal is cut during a power saving event. By the time the MAC is brought back up, the clock signal is still not active since phylink_start hasn't been called yet. This brings us back to case 1. If a PHY driver reads this flag, it should ensure that the receive clock signal is started as soon as possible, and that it isn't brought down when the PHY goes into suspend. Signed-off-by: Russell King [rgantois: commit log] Signed-off-by: Romain Gantois --- drivers/net/phy/phylink.c | 10 +++++++++- include/linux/phy.h | 1 + include/linux/phylink.h | 4 ++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 25c19496a336..f26b13d916d4 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -1837,6 +1837,8 @@ static int phylink_bringup_phy(struct phylink *pl, struct phy_device *phy, static int phylink_attach_phy(struct phylink *pl, struct phy_device *phy, phy_interface_t interface) { + u32 flags = 0; + if (WARN_ON(pl->cfg_link_an_mode == MLO_AN_FIXED || (pl->cfg_link_an_mode == MLO_AN_INBAND && phy_interface_mode_is_8023z(interface) && !pl->sfp_bus))) @@ -1845,7 +1847,10 @@ static int phylink_attach_phy(struct phylink *pl, struct phy_device *phy, if (pl->phydev) return -EBUSY; - return phy_attach_direct(pl->netdev, phy, 0, interface); + if (pl->config->mac_requires_rxc) + flags |= PHY_F_RXC_ALWAYS_ON; + + return phy_attach_direct(pl->netdev, phy, flags, interface); } /** @@ -1948,6 +1953,9 @@ int phylink_fwnode_phy_connect(struct phylink *pl, pl->link_config.interface = pl->link_interface; } + if (pl->config->mac_requires_rxc) + flags |= PHY_F_RXC_ALWAYS_ON; + ret = phy_attach_direct(pl->netdev, phy_dev, flags, pl->link_interface); phy_device_free(phy_dev); diff --git a/include/linux/phy.h b/include/linux/phy.h index bd285950972c..c6cb53412273 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -764,6 +764,7 @@ struct phy_device { /* Generic phy_device::dev_flags */ #define PHY_F_NO_IRQ 0x80000000 +#define PHY_F_RXC_ALWAYS_ON BIT(30) static inline struct phy_device *to_phy_device(const struct device *dev) { diff --git a/include/linux/phylink.h b/include/linux/phylink.h index 875439ab45de..8430ac7ead11 100644 --- a/include/linux/phylink.h +++ b/include/linux/phylink.h @@ -204,6 +204,9 @@ enum phylink_op_type { * @poll_fixed_state: if true, starts link_poll, * if MAC link is at %MLO_AN_FIXED mode. * @mac_managed_pm: if true, indicate the MAC driver is responsible for PHY PM. + * @mac_requires_rxc: if true, the MAC always requires a receive clock from PHY. + * The PHY driver should start the clock signal as soon as + * possible and avoid stopping it during suspend events. * @ovr_an_inband: if true, override PCS to MLO_AN_INBAND * @get_fixed_state: callback to execute to determine the fixed link state, * if MAC link is at %MLO_AN_FIXED mode. @@ -216,6 +219,7 @@ struct phylink_config { enum phylink_op_type type; bool poll_fixed_state; bool mac_managed_pm; + bool mac_requires_rxc; bool ovr_an_inband; void (*get_fixed_state)(struct phylink_config *config, struct phylink_link_state *state); From patchwork Wed Jan 3 14:28:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Gantois X-Patchwork-Id: 13510115 X-Patchwork-Delegate: kieran@bingham.xyz Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E2791A5A6; Wed, 3 Jan 2024 14:28:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="PjkXE8zV" Received: by mail.gandi.net (Postfix) with ESMTPSA id D3ABE60006; Wed, 3 Jan 2024 14:28:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1704292102; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yi/l6zN1wrokE9qEz9TLn6vcJko+Bnseka46HyXgyU4=; b=PjkXE8zV+hyPTh8jtSX8pVHB1Rto9Ayqaet+5qq1/JUSrwutQmvqOcPDB+ZknY6SrSwSna i3cLoBqrLCd4AJPJE4qdOcaJcqpPgbGJyyHduLtkEojAH21k/fdjghBbAr+XuQxpt6hq/6 zzKkYaaOjPjYMjax1X6mEFux2vheRcTyfnmH0d8BYqa0drrZzEnAV/UHU9ON6NUQoQ3Nyd bEs1zWjyP0NQHvQF19r26RdIYWJN76MnGGcjGn8L91Oaf3Ks/gDmS+zYqEYRxEU/v4T1cA hH1YDeA+Dmy2PLY1iSQXUWlbtwngc6qNxTS8IbqAmgAKlGj5SkI/NSUU3R3hfQ== From: Romain Gantois To: Alexandre Torgue , Jose Abreu , Russell King , Andrew Lunn , Jakub Kicinski , Heiner Kallweit Cc: Romain Gantois , "David S. Miller" , Eric Dumazet , Paolo Abeni , Maxime Coquelin , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Marek Vasut , Clark Wang , Miquel Raynal , Sylvain Girard , Pascal EBERHARD , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH net 2/5] net: phy: add rxc_always_on flag to phylink_pcs Date: Wed, 3 Jan 2024 15:28:22 +0100 Message-ID: <20240103142827.168321-3-romain.gantois@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103142827.168321-1-romain.gantois@bootlin.com> References: <20240103142827.168321-1-romain.gantois@bootlin.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: romain.gantois@bootlin.com Some MAC drivers (e.g. stmmac) require a continuous receive clock signal to be generated by a PCS that is handled by a standalone PCS driver. Such a PCS driver does not have access to a PHY device, thus cannot check the PHY_F_RXC_ALWAYS_ON flag. They cannot check max_requires_rxc in the phylink config either, since it is a private member. Therefore, a new flag is needed to signal to the PCS that it should keep the RX clock signal up at all times. Signed-off-by: Romain Gantois --- drivers/net/phy/phylink.c | 3 +++ include/linux/phylink.h | 5 +++++ 2 files changed, 8 insertions(+) diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index f26b13d916d4..a5a5fe91d213 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -663,6 +663,9 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl, return -EINVAL; } + if (pl->config->mac_requires_rxc) + pcs->rxc_always_on = true; + /* Validate the link parameters with the PCS */ if (pcs->ops->pcs_validate) { ret = pcs->ops->pcs_validate(pcs, supported, state); diff --git a/include/linux/phylink.h b/include/linux/phylink.h index 8430ac7ead11..e1527e35f997 100644 --- a/include/linux/phylink.h +++ b/include/linux/phylink.h @@ -462,6 +462,10 @@ struct phylink_pcs_ops; * @phylink: pointer to &struct phylink_config * @neg_mode: provide PCS neg mode via "mode" argument * @poll: poll the PCS for link changes + * @rxc_always_on: The MAC driver requires the reference clock + * to always be on. Standalone PCS drivers who + * do not have access to a PHY device can check + * this instead of PHY_F_RXC_ALWAYS_ON. * * This structure is designed to be embedded within the PCS private data, * and will be passed between phylink and the PCS. @@ -474,6 +478,7 @@ struct phylink_pcs { struct phylink *phylink; bool neg_mode; bool poll; + bool rxc_always_on; }; /** From patchwork Wed Jan 3 14:28:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Romain Gantois X-Patchwork-Id: 13510116 X-Patchwork-Delegate: kieran@bingham.xyz Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8029B1A704; Wed, 3 Jan 2024 14:28:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="oB/z7ORE" Received: by mail.gandi.net (Postfix) with ESMTPSA id D156B6000C; Wed, 3 Jan 2024 14:28:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1704292104; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Wp8DYMknUb7GCV6xvdPdeHPJMzkPaB2xD+HrP3VM8GM=; b=oB/z7ORENEshnW+G77deGCmY+G/XJmhFAHxDZVQxBKRiwPDd6b0sVihw/tZuLR1iR5hWVz r2xRI0DVcDyB/23d4rCbk3s1w6ZzfQMNyZXUHPXS+JyMEhaW21lBTxgSkqWvzXK+GswyYn tNyjC6NHEq4Hs0asFaZMkUYuKcam4NxRb9uhHB/UCk04pk3moUDgdBvvGuV+ciBAPd7brb EbEIPNpJI1YCw9jqMJhsw7HaoRkD/nP1E1ECTV+5guiN/Ygfgviabqi5gHKa8SHGlie8ek R8IAxuHRQAZciwGtGnm43swudWzoz8mxFVrWS/xqEdDwTmfFD4W2vhPLDEyfzw== From: Romain Gantois To: Alexandre Torgue , Jose Abreu , Russell King , Andrew Lunn , Jakub Kicinski , Heiner Kallweit Cc: "David S. Miller" , Eric Dumazet , Paolo Abeni , Maxime Coquelin , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Marek Vasut , Clark Wang , Miquel Raynal , Sylvain Girard , Pascal EBERHARD , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Romain Gantois Subject: [PATCH net 3/5] net: stmmac: Signal to PHY/PCS drivers to keep RX clock on Date: Wed, 3 Jan 2024 15:28:23 +0100 Message-ID: <20240103142827.168321-4-romain.gantois@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103142827.168321-1-romain.gantois@bootlin.com> References: <20240103142827.168321-1-romain.gantois@bootlin.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: romain.gantois@bootlin.com From: Russell King There is a reocurring issue with stmmac controllers where the MAC fails to initialize its hardware if an RX clock signal isn't provided on the MAC/PHY link. This causes issues when PHY or PCS devices either go into suspend while cutting the RX clock or do not bring the clock signal up early enough for the MAC to initialize successfully. Set the mac_requires_rxc flag in the stmmac phylink config so that PHY/PCS drivers know to keep the RX clock up at all times. Reported-by: Clark Wang Link: https://lore.kernel.org/all/20230202081559.3553637-1-xiaoning.wang@nxp.com/ Reported-by: Clément Léger Link: https://lore.kernel.org/linux-arm-kernel/20230116103926.276869-4-clement.leger@bootlin.com/ Signed-off-by: Russell King [rgantois: commit log] Signed-off-by: Romain Gantois --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 37e64283f910..ffecc28de234 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -1221,6 +1221,11 @@ static int stmmac_phy_setup(struct stmmac_priv *priv) priv->phylink_config.type = PHYLINK_NETDEV; priv->phylink_config.mac_managed_pm = true; + /* stmmac always requires a receive clock in order for things like + * hardware reset to work. + */ + priv->phylink_config.mac_requires_rxc = true; + mdio_bus_data = priv->plat->mdio_bus_data; if (mdio_bus_data) priv->phylink_config.ovr_an_inband = From patchwork Wed Jan 3 14:28:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Gantois X-Patchwork-Id: 13510117 X-Patchwork-Delegate: kieran@bingham.xyz Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5F111A5B2; Wed, 3 Jan 2024 14:28:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="N2j3iknY" Received: by mail.gandi.net (Postfix) with ESMTPSA id 023A76000A; Wed, 3 Jan 2024 14:28:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1704292107; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kc+VywqWiAtkZwy1URbvRhLNjrTT3W9D6r0SmXbXHdA=; b=N2j3iknYDfyGoRYRjzVc5OKDZ7a9w84rrYzP0on45AElgkhzNVzf76/a/hcXRCwJkvUiKG b5xbG3TcVTcw2pgbwH6ypnpUgQY7w/U1HoKohC43UV0MBhO4XHTSG/afopHk2KnwogLKbJ g6F89KAopvGj29HcCMan+UVFOo6lLD9nkDufPyDNda7vIklNpWWOboRNWvkXEDMU/Gd+yg YTUcMczJKGOKS47T+Bw/sVq6uqG7qoWw0+YpjFPWTHG+IvKJ1YJLtBkmcZ24hdq0GyVYRx QewXTy3W7j5HuePQBlySJfYxyYNGYqI0eNRXhMHyYgN3vdL3wL1T+hez8qRR7Q== From: Romain Gantois To: Alexandre Torgue , Jose Abreu , Russell King , Andrew Lunn , Jakub Kicinski , Heiner Kallweit Cc: "David S. Miller" , Eric Dumazet , Paolo Abeni , Maxime Coquelin , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Marek Vasut , Clark Wang , Miquel Raynal , Sylvain Girard , Pascal EBERHARD , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Romain Gantois Subject: [PATCH net 4/5] net: phy: at803x: Avoid hibernating if MAC requires RX clock Date: Wed, 3 Jan 2024 15:28:24 +0100 Message-ID: <20240103142827.168321-5-romain.gantois@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103142827.168321-1-romain.gantois@bootlin.com> References: <20240103142827.168321-1-romain.gantois@bootlin.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: romain.gantois@bootlin.com From: Russell King Stmmac controllers connected to an at803x PHY cannot resume properly after suspend when WoL is enabled. This happens because the MAC requires an RX clock generated by the PHY to initialize its hardware properly. But the RX clock is cut when the PHY suspends and isn't brought up until the MAC driver resumes the phylink. Prevent the at803x PHY driver from going into suspend if the attached MAC driver always requires an RX clock signal. Reported-by: Clark Wang Link: https://lore.kernel.org/all/20230202081559.3553637-1-xiaoning.wang@nxp.com/ Signed-off-by: Russell King [rgantois: commit log] Signed-off-by: Romain Gantois --- drivers/net/phy/at803x.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 37fb033e1c29..410776281ff6 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -995,7 +995,8 @@ static int at803x_hibernation_mode_config(struct phy_device *phydev) /* The default after hardware reset is hibernation mode enabled. After * software reset, the value is retained. */ - if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE)) + if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE) && + !(phydev->dev_flags & PHY_F_RXC_ALWAYS_ON)) return 0; return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, From patchwork Wed Jan 3 14:28:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Romain Gantois X-Patchwork-Id: 13510118 X-Patchwork-Delegate: kieran@bingham.xyz Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3ABD41A71F; Wed, 3 Jan 2024 14:28:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="NLIgcVMN" Received: by mail.gandi.net (Postfix) with ESMTPSA id 043CD6000D; Wed, 3 Jan 2024 14:28:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1704292109; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hmed1jEpoZI+pixYHArlZGQKHPpdNarPzqdiGktR7JI=; b=NLIgcVMNlWi0/VrDdnLc+QqsaPfWKXhZvk1NqViiDyZoMs1+PEZ28REKDlv2RaCmv99Ia7 O3cKXIDjObnrrQ3k0kn9fwsvvKqeQYbdKq+GSSSPXeT6XihHjUEddonlcvdgea4nUuiYj3 FfWkiCOgoXFtcJjzjK2S9E9j3GmrLOlKufDkFOhe7QRchKn+MgCN8eO0Z8lB6sJEzSZtQ3 h4YuROcxNvOczQb+kJni36zKsewpgKSiObzwFvhwbiPjq3rGXm0z+aQI92ISmJuj5KketI D1tZS5HrIcfnYpp1E8jLoIKm6Ii3WoXpr7EpCo0gY1IqmDHEW5buHcXJxCOeYQ== From: Romain Gantois To: Alexandre Torgue , Jose Abreu , Russell King , Andrew Lunn , Jakub Kicinski , Heiner Kallweit Cc: Romain Gantois , "David S. Miller" , Eric Dumazet , Paolo Abeni , Maxime Coquelin , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Marek Vasut , Clark Wang , Miquel Raynal , Sylvain Girard , Pascal EBERHARD , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH net 5/5] net: pcs: rzn1-miic: Init RX clock early if MAC requires it Date: Wed, 3 Jan 2024 15:28:25 +0100 Message-ID: <20240103142827.168321-6-romain.gantois@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103142827.168321-1-romain.gantois@bootlin.com> References: <20240103142827.168321-1-romain.gantois@bootlin.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: romain.gantois@bootlin.com The GMAC1 controller in the RZN1 IP requires the RX MII clock signal to be started before it initializes its own hardware, thus before it calls phylink_start. Check the rxc_always_on pcs flag and enable the clock signal during the link validation phase. Reported-by: Clément Léger Link: https://lore.kernel.org/linux-arm-kernel/20230116103926.276869-4-clement.leger@bootlin.com/ Signed-off-by: Romain Gantois --- drivers/net/pcs/pcs-rzn1-miic.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-miic.c index 97139c07130f..bf796491b826 100644 --- a/drivers/net/pcs/pcs-rzn1-miic.c +++ b/drivers/net/pcs/pcs-rzn1-miic.c @@ -271,12 +271,20 @@ static void miic_link_up(struct phylink_pcs *pcs, unsigned int mode, static int miic_validate(struct phylink_pcs *pcs, unsigned long *supported, const struct phylink_link_state *state) { - if (phy_interface_mode_is_rgmii(state->interface) || - state->interface == PHY_INTERFACE_MODE_RMII || - state->interface == PHY_INTERFACE_MODE_MII) - return 1; + int ret = 1; - return -EINVAL; + if (!phy_interface_mode_is_rgmii(state->interface) && + state->interface != PHY_INTERFACE_MODE_RMII && + state->interface != PHY_INTERFACE_MODE_MII) + return -EINVAL; + + if (pcs->rxc_always_on) { + ret = miic_config(pcs, 0, state->interface, NULL, false); + if (ret) + pr_err("Error: Failed to init RX clock in RZN1 MIIC PCS!"); + } + + return ret; } static const struct phylink_pcs_ops miic_phylink_ops = {