From patchwork Thu Jan 4 03:21:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Sousa X-Patchwork-Id: 13510756 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B0A7C4707B for ; Thu, 4 Jan 2024 03:22:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8EF0710E379; Thu, 4 Jan 2024 03:22:36 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0DE3410E373 for ; Thu, 4 Jan 2024 03:22:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704338555; x=1735874555; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+UTXE9JEF/VmXpToL0iM83ifKJsdnMU2g8w2no4AZgE=; b=FKj4OpQ6FyCIcYdXPz4erjUNa5opKCTWcT+EUC2TwXfzuFDdskJp/WxV UlZdg8E7sBvO/86bUatvQQY3cQwuY0U8R2V06emwHe0R6Plo6q3khFNQn 04rZYX+miy2JDjB+1Dm3VaxCjcJQVqPB8FzOtf/pkl2jFxmvdDkWKq+KF 9o3I/X3Kyw1n2JAQzEzoRBxzQv97MpReDSPqOY7wJOx+/AgxPku69JtWb EgyUs4JYpb+On/66PlvzCb/oKLfOgmbccmDn2DwsHaGN/DQ9z8qrc2fLf VzEvDtRnadbMU5tnTDbgLd0nYO0T7znYr1BcKOHD1Siby7WEMOFiNU2zt Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10942"; a="483295289" X-IronPort-AV: E=Sophos;i="6.04,329,1695711600"; d="scan'208";a="483295289" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2024 19:22:30 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10942"; a="850623670" X-IronPort-AV: E=Sophos;i="6.04,329,1695711600"; d="scan'208";a="850623670" Received: from rpasham-mobl1.amr.corp.intel.com (HELO gjsousa-mobl2.intel.com) ([10.125.176.66]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2024 19:22:29 -0800 From: Gustavo Sousa To: intel-gfx@lists.freedesktop.org Subject: [PATCH 1/4] drm/i915/xe2lpd: Update bxt_sanitize_cdclk() Date: Thu, 4 Jan 2024 00:21:47 -0300 Message-ID: <20240104032150.118954-2-gustavo.sousa@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240104032150.118954-1-gustavo.sousa@intel.com> References: <20240104032150.118954-1-gustavo.sousa@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" With Xe2_LPD, there were changes to the way CDCLK_CTL must be programmed. Those were reflected on _bxt_set_cdclk() with commit 3d3696c0fed1 ("drm/i915/lnl: Start using CDCLK through PLL"), but bxt_sanitize_cdclk() was left out. This was causing some issues when loading the driver with a pre-existing active display configuration: the driver would mistakenly take the current value of CDCLK_CTL as wrong and the sanitization would be triggered. In a scenario where the display was already configured with a high CDCLKC and had plane(s) enabled, FIFO underrun errors were reported, because the current sanitization code selects the minimum possible CDCLK. Fix that by updating bxt_sanitize_cdclk() to match the changes made in _bxt_set_cdclk(). Ideally, we would have a common function to derive the value for CDCLK_CTL, but that can be done in a future change. Signed-off-by: Gustavo Sousa Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_cdclk.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index c5fecde7afa8..0012e3171f3f 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2071,7 +2071,10 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) if (vco != dev_priv->display.cdclk.hw.vco) goto sanitize; - expected = skl_cdclk_decimal(cdclk); + if (DISPLAY_VER(dev_priv) >= 20) + expected = MDCLK_SOURCE_SEL_CDCLK_PLL; + else + expected = skl_cdclk_decimal(cdclk); /* Figure out what CD2X divider we should be using for this cdclk */ if (HAS_CDCLK_SQUASH(dev_priv)) From patchwork Thu Jan 4 03:21:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Sousa X-Patchwork-Id: 13510752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0F041C4706F for ; Thu, 4 Jan 2024 03:22:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AEBFC10E35B; Thu, 4 Jan 2024 03:22:35 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2E89410E35B for ; Thu, 4 Jan 2024 03:22:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704338555; x=1735874555; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UPbTkOhrRqhyyB8Phf2x2nB9INtCOl4mAIM4puXupGM=; b=iBxD0k+9eMxaOJ8GwsC/lBUNvbNu1SB6K2EjYay5jeJLkSQuWlHePrtS fV07HOSC4p9iqH4jN0NSxCzdVm87y7E2L4VdLB06ik2JpGnMP0GeyD37e esToMsgpmFSaIZvv6oLmnJAYvFiq8KjidlJsBPYCKdsn2MCHb4vrxQoi7 aj8q8RaL/fk7imDk0eQv1gWijA4qahzDoqBklheFMrdyRRESw/F2wvDLp wSE7X4lnuUGcPegLcYCBO4NxIpm+FcYgZJK+8stScbEt3ePN+ygd/XFzM yKQ77AoE9O14bsb6bk2wviKPmFhB2UJLpvsxxh7Qa/BtyODnWK0CSFofQ A==; X-IronPort-AV: E=McAfee;i="6600,9927,10942"; a="483295290" X-IronPort-AV: E=Sophos;i="6.04,329,1695711600"; d="scan'208";a="483295290" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2024 19:22:31 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10942"; a="850623674" X-IronPort-AV: E=Sophos;i="6.04,329,1695711600"; d="scan'208";a="850623674" Received: from rpasham-mobl1.amr.corp.intel.com (HELO gjsousa-mobl2.intel.com) ([10.125.176.66]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2024 19:22:30 -0800 From: Gustavo Sousa To: intel-gfx@lists.freedesktop.org Subject: [PATCH 2/4] drm/i915/cdclk: Extract bxt_cdclk_ctl() Date: Thu, 4 Jan 2024 00:21:48 -0300 Message-ID: <20240104032150.118954-3-gustavo.sousa@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240104032150.118954-1-gustavo.sousa@intel.com> References: <20240104032150.118954-1-gustavo.sousa@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This makes the code better readable and will be used later in bxt_sanitize_cdclk(). Signed-off-by: Gustavo Sousa Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_cdclk.c | 57 +++++++++++++--------- 1 file changed, 35 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 0012e3171f3f..b9354ad46fee 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1900,15 +1900,47 @@ static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv) dev_priv->display.cdclk.hw.vco > 0; } +static u32 bxt_cdclk_ctl(struct drm_i915_private *i915, + const struct intel_cdclk_config *cdclk_config, + enum pipe pipe) +{ + int cdclk = cdclk_config->cdclk; + int vco = cdclk_config->vco; + int unsquashed_cdclk; + u16 waveform; + u32 val; + + waveform = cdclk_squash_waveform(i915, cdclk); + + unsquashed_cdclk = DIV_ROUND_CLOSEST(cdclk * cdclk_squash_len, + cdclk_squash_divider(waveform)); + + val = bxt_cdclk_cd2x_div_sel(i915, unsquashed_cdclk, vco) | + bxt_cdclk_cd2x_pipe(i915, pipe); + + /* + * Disable SSA Precharge when CD clock frequency < 500 MHz, + * enable otherwise. + */ + if ((IS_GEMINILAKE(i915) || IS_BROXTON(i915)) && + cdclk >= 500000) + val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; + + if (DISPLAY_VER(i915) >= 20) + val |= MDCLK_SOURCE_SEL_CDCLK_PLL; + else + val |= skl_cdclk_decimal(cdclk); + + return val; +} + static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { int cdclk = cdclk_config->cdclk; int vco = cdclk_config->vco; - int unsquashed_cdclk; u16 waveform; - u32 val; if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 && !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { @@ -1925,29 +1957,10 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, waveform = cdclk_squash_waveform(dev_priv, cdclk); - unsquashed_cdclk = DIV_ROUND_CLOSEST(cdclk * cdclk_squash_len, - cdclk_squash_divider(waveform)); - if (HAS_CDCLK_SQUASH(dev_priv)) dg2_cdclk_squash_program(dev_priv, waveform); - val = bxt_cdclk_cd2x_div_sel(dev_priv, unsquashed_cdclk, vco) | - bxt_cdclk_cd2x_pipe(dev_priv, pipe); - - /* - * Disable SSA Precharge when CD clock frequency < 500 MHz, - * enable otherwise. - */ - if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && - cdclk >= 500000) - val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; - - if (DISPLAY_VER(dev_priv) >= 20) - val |= MDCLK_SOURCE_SEL_CDCLK_PLL; - else - val |= skl_cdclk_decimal(cdclk); - - intel_de_write(dev_priv, CDCLK_CTL, val); + intel_de_write(dev_priv, CDCLK_CTL, bxt_cdclk_ctl(dev_priv, cdclk_config, pipe)); if (pipe != INVALID_PIPE) intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe)); From patchwork Thu Jan 4 03:21:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Sousa X-Patchwork-Id: 13510754 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2CE39C47079 for ; Thu, 4 Jan 2024 03:22:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3F44010E373; Thu, 4 Jan 2024 03:22:36 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4D2FC10E373 for ; Thu, 4 Jan 2024 03:22:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704338555; x=1735874555; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xN+WWRdXKJKpYAXhN5QkJKM07ftTfSNzABM6r8mN5NU=; b=HRh3qQZqJiqgLxpE007Nq9N/JpYIwgIrfHB415nbnPyq6dPCFCWDaJpT pBWRqn/QwZPZzzvszeO+quiOO1rrmS2UYd5xBeHV0NY41KRClI0jFFVla 0wcMTFOKyhPrU+F4oyikdF5kcs3tMV95WdyV3Cl60DhMaC7SawTk4/Btu X5VHK09/n0Ok45Wmj5gf3KiREA6MzcexYQUoy7R8n+8QzV0o8+bkrAi7P LTx/2pTwFkSoJFR7MilpeqKGtuS5dS6VNS9h3PJnVckw+edXDxAAsjDYa JdNny0YsZbbaNRy9EBuUY+9Zri7owzHU1EycWzGVJPqN+8SjFyx2ZtjZM Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10942"; a="483295291" X-IronPort-AV: E=Sophos;i="6.04,329,1695711600"; d="scan'208";a="483295291" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2024 19:22:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10942"; a="850623678" X-IronPort-AV: E=Sophos;i="6.04,329,1695711600"; d="scan'208";a="850623678" Received: from rpasham-mobl1.amr.corp.intel.com (HELO gjsousa-mobl2.intel.com) ([10.125.176.66]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2024 19:22:31 -0800 From: Gustavo Sousa To: intel-gfx@lists.freedesktop.org Subject: [PATCH 3/4] drm/i915/cdclk: Reorder bxt_sanitize_cdclk() Date: Thu, 4 Jan 2024 00:21:49 -0300 Message-ID: <20240104032150.118954-4-gustavo.sousa@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240104032150.118954-1-gustavo.sousa@intel.com> References: <20240104032150.118954-1-gustavo.sousa@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make the sequence of steps more logical by grouping things related to the check on the value of CDCLK_CTL into a single "block". Also, this will make an upcoming change replacing that block with a single function call easier to follow. Signed-off-by: Gustavo Sousa Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_cdclk.c | 24 +++++++++++----------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index b9354ad46fee..fbe9aba41c35 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2060,13 +2060,23 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) goto sanitize; - /* DPLL okay; verify the cdclock - * + /* Make sure this is a legal cdclk value for the platform */ + cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); + if (cdclk != dev_priv->display.cdclk.hw.cdclk) + goto sanitize; + + /* Make sure the VCO is correct for the cdclk */ + vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); + if (vco != dev_priv->display.cdclk.hw.vco) + goto sanitize; + + /* * Some BIOS versions leave an incorrect decimal frequency value and * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, * so sanitize this register. */ cdctl = intel_de_read(dev_priv, CDCLK_CTL); + /* * Let's ignore the pipe field, since BIOS could have configured the * dividers both synching to an active pipe, or asynchronously @@ -2074,16 +2084,6 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) */ cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); - /* Make sure this is a legal cdclk value for the platform */ - cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); - if (cdclk != dev_priv->display.cdclk.hw.cdclk) - goto sanitize; - - /* Make sure the VCO is correct for the cdclk */ - vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); - if (vco != dev_priv->display.cdclk.hw.vco) - goto sanitize; - if (DISPLAY_VER(dev_priv) >= 20) expected = MDCLK_SOURCE_SEL_CDCLK_PLL; else From patchwork Thu Jan 4 03:21:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Sousa X-Patchwork-Id: 13510753 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6D918C47073 for ; Thu, 4 Jan 2024 03:22:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 51BF010E376; Thu, 4 Jan 2024 03:22:36 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5AAE710E376 for ; Thu, 4 Jan 2024 03:22:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704338555; x=1735874555; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TOeC0Cx3kqtcBbBsAMoqt23jSD+SeQhTzPLKE3vTxGE=; b=GC0oM6nC4JYFdPPfdFrF9yrr4/YiJt5JutqyzFXWEjR0Sc1tlnNjwU0B TJYacd/MQX8Tc+JQy4xz0IB3eszcmXQCf8ojmrBeShpMSo+T37eH315Xi 52qlum+oe+fXwrkWY7Th05hMG1iKfc7wptK4JECPDK0wlgZE4Q+7bol4o RGNgIX/6SVnD10GqzV72rs2eseZ+P4M0Asy2jNWAj/nrRi8WymkDgm+UD lJ972IN8GjD64++BwJcHQrC++FS+SKeH6oKFcMcd23CSDGCUsfdQU0kED Ymbt3rnv8jpoOIt/gWBApKKdOLLGN5wrYFTI8qLBU8XNIwE4OfSjXwYjB A==; X-IronPort-AV: E=McAfee;i="6600,9927,10942"; a="483295296" X-IronPort-AV: E=Sophos;i="6.04,329,1695711600"; d="scan'208";a="483295296" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2024 19:22:33 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10942"; a="850623685" X-IronPort-AV: E=Sophos;i="6.04,329,1695711600"; d="scan'208";a="850623685" Received: from rpasham-mobl1.amr.corp.intel.com (HELO gjsousa-mobl2.intel.com) ([10.125.176.66]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2024 19:22:32 -0800 From: Gustavo Sousa To: intel-gfx@lists.freedesktop.org Subject: [PATCH 4/4] drm/i915/cdclk: Re-use bxt_cdclk_ctl() when sanitizing Date: Thu, 4 Jan 2024 00:21:50 -0300 Message-ID: <20240104032150.118954-5-gustavo.sousa@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240104032150.118954-1-gustavo.sousa@intel.com> References: <20240104032150.118954-1-gustavo.sousa@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" That's the function responsible for deriving that register's value; use it. Signed-off-by: Gustavo Sousa Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_cdclk.c | 26 +++------------------- 1 file changed, 3 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index fbe9aba41c35..26200ee3e23f 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2051,7 +2051,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) { u32 cdctl, expected; - int cdclk, clock, vco; + int cdclk, vco; intel_update_cdclk(dev_priv); intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); @@ -2076,6 +2076,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) * so sanitize this register. */ cdctl = intel_de_read(dev_priv, CDCLK_CTL); + expected = bxt_cdclk_ctl(dev_priv, &dev_priv->display.cdclk.hw, INVALID_PIPE); /* * Let's ignore the pipe field, since BIOS could have configured the @@ -2083,28 +2084,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) * (PIPE_NONE). */ cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); - - if (DISPLAY_VER(dev_priv) >= 20) - expected = MDCLK_SOURCE_SEL_CDCLK_PLL; - else - expected = skl_cdclk_decimal(cdclk); - - /* Figure out what CD2X divider we should be using for this cdclk */ - if (HAS_CDCLK_SQUASH(dev_priv)) - clock = dev_priv->display.cdclk.hw.vco / 2; - else - clock = dev_priv->display.cdclk.hw.cdclk; - - expected |= bxt_cdclk_cd2x_div_sel(dev_priv, clock, - dev_priv->display.cdclk.hw.vco); - - /* - * Disable SSA Precharge when CD clock frequency < 500 MHz, - * enable otherwise. - */ - if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && - dev_priv->display.cdclk.hw.cdclk >= 500000) - expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; + expected &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); if (cdctl == expected) /* All well; nothing to sanitize */