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pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v3 1/3] xen/arm: Introduce CONFIG_PARTIAL_EMULATION and "partial-emulation" cmd option Date: Fri, 5 Jan 2024 11:21:54 +0000 Message-ID: <20240105112156.154807-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240105112156.154807-1-ayan.kumar.halder@amd.com> References: <20240105112156.154807-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FF:EE_|IA0PR12MB8226:EE_ X-MS-Office365-Filtering-Correlation-Id: 93ef1c4d-3c84-4804-0729-08dc0de09a2f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /cHKAoeBxEBXOczf5GlfLHWLxqr5FPMelFMl0hxq/v6NlsfJm0ntBbrU+j4n5ChrhGT/cQKs0svZGCw5LnDOIHidJaMFuzXeFqHx9PBE65BRJzekdIuAI1ttQ5V57yhP1yMutigS3UXGS22TRYu3HJ9BlrTDKZgnkA+lPnumu7XiI9jXlNn90Rb8d0zSYrX6bXlF0P3LCgojrS8fQLEh2oQi8Gzrzdt/eSpV9aqjQwdnUFv9AslErZC+CrQYz4MWUECE5RGcI8EvImtxxA4he++JZl5426yTQVbOh2mPMPwkDvsYyVcazA7YzIgJ7x2aAn0A/J/a5SwmSROa1LeE03X5/9S4ZnAmf3Z6dMXhLOTM4lRlA9Bp7ZpG0nFVo6aG5Sv0cqRBo6EC1KpsAD5RIYcy89Bd+RFRLES7pGw9CVe8a1lVevksMU1rmlQ6/tPYJLp1NmfW/DVvQTFba5wjWJ7JlmAwTMC8bZFJrOC2fozwwgdX6ctbuNLVpYUjmxbVSEAASxrpY6U45mKdnqkITxfE+6tHf4Wn6GbwPWo+lVDMb+1QUhHPh0nDSh+LoJnzIJ6s4MPrPARt+fh/tW3g2Njk+ZPbvPBcnzDjP9fpVwtRe4MO+cdxfMcYRqFWICBn4sg1TVlAxqB5wYUc9yR5Jog+LoBNGuVsUvfNtK7sx4j3cMI7/NveYGeWY+2SVen/6hhO25cqzfZ4pHPjPXkprV18x4h4TRumyVROBS5W6Z+8uERatDVGIeA8pSvRgK3q7weWQWL1WkQuXcAsWc8qEA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(136003)(346002)(376002)(396003)(230922051799003)(451199024)(64100799003)(1800799012)(82310400011)(186009)(40470700004)(36840700001)(46966006)(41300700001)(36860700001)(83380400001)(47076005)(82740400003)(103116003)(86362001)(356005)(70586007)(4326008)(54906003)(70206006)(81166007)(8676002)(5660300002)(316002)(2906002)(26005)(426003)(1076003)(336012)(8936002)(6666004)(2616005)(6916009)(36756003)(478600001)(40460700003)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2024 11:22:28.9907 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 93ef1c4d-3c84-4804-0729-08dc0de09a2f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8226 There can be situations when the registers cannot be emulated to their full functionality. This can be due to the complexity involved. In such cases, one can emulate those registers as RAZ/WI. We call them as partial emulation. A suitable example of this (as seen in subsequent patches) is emulation of DBGDTRTX_EL0 (on Arm64) and DBGDTRTXINT(on Arm32). These non-optional registers can be partially emulated as RAZ/WI and they can be enclosed within CONFIG_PARTIAL_EMULATION. Further, "partial-emulation" command line option enables us to enable/disable partial emulation at run time. While CONFIG_PARTIAL_EMULATION enables support for partial emulation at compile time (ie adds code for partial emulation), this option may be enabled or disabled by Yocto or other build systems. However if the build system turns this option on, customers can use cripts like Imagebuilder to generate uboot-script which will append "partial-emulation=false" to xen command line to turn off the partial emulation. Thus, it helps to avoid rebuilding xen. By default, "CONFIG_PARTIAL_EMULATION=y" and "partial-emulation=false". This is done so that Xen supports partial emulation. However, customers are fully aware when they enable partial emulation. Signed-off-by: Ayan Kumar Halder --- Changes from v1 :- 1. New patch introduced in v2. v2 :- 1. Reordered the patches so that the config and command line option is introduced in the first patch. docs/misc/xen-command-line.pandoc | 7 +++++++ xen/arch/arm/Kconfig | 8 ++++++++ xen/arch/arm/include/asm/regs.h | 6 ++++++ xen/arch/arm/traps.c | 3 +++ 4 files changed, 24 insertions(+) diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc index 8e65f8bd18..dd2a76fb19 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -1949,6 +1949,13 @@ This option is ignored in **pv-shim** mode. > Default: `on` +### partial-emulation (arm) +> `= ` + +> Default: `false` + +Flag to enable or disable partial emulation of registers + ### pci = List of [ serr=, perr= ] diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 50e9bfae1a..8f25d9cba0 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -225,6 +225,14 @@ config STATIC_EVTCHN This option enables establishing static event channel communication between domains on a dom0less system (domU-domU as well as domU-dom0). +config PARTIAL_EMULATION + bool "Enable partial emulation for registers" + default y + help + This option enabled partial emulation for registers to avoid guests + crashing when accessing registers which are not optional but has not been + emulated to its complete functionality. + endmenu menu "ARM errata workaround via the alternative framework" diff --git a/xen/arch/arm/include/asm/regs.h b/xen/arch/arm/include/asm/regs.h index f998aedff5..b71fa20f91 100644 --- a/xen/arch/arm/include/asm/regs.h +++ b/xen/arch/arm/include/asm/regs.h @@ -13,6 +13,12 @@ #define psr_mode(psr,m) (((psr) & PSR_MODE_MASK) == (m)) +/* + * opt_partial_emulation: If true, partial emulation for registers will be + * enabled. + */ +extern bool opt_partial_emulation; + static inline bool regs_mode_is_32bit(const struct cpu_user_regs *regs) { #ifdef CONFIG_ARM_32 diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 9c10e8f78c..d5fb9c1035 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -42,6 +42,9 @@ #include #include +bool opt_partial_emulation = false; +boolean_param("partial-emulation", opt_partial_emulation); + /* The base of the stack must always be double-word aligned, which means * that both the kernel half of struct cpu_user_regs (which is pushed in * entry.S) and struct cpu_info (which lives at the bottom of a Xen From patchwork Fri Jan 5 11:21:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13511987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 27759C3DA6E for ; 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bh=3vEYAbR5qQnhqgkIaraifN+bUkAXWzEogvZPRK6DI0Q=; b=YmKQd2mOLMqoSZzJs+/HBX7Uih28jQ0BkFKDp7d9mfo+wgvEdf7aMbRLTUJ1G/0dXpewyyZR4LNnq+BC3qA1rjvG78C0poJ53ueXPUhUppGqi+gkSXWVH52+WNERG/lRULNjxteYPddO4DkysZ93jAH0Acn7xvVQ6vsePsWMCQw= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v3 2/3] xen/arm: arm64: Add emulation of Debug Data Transfer Registers Date: Fri, 5 Jan 2024 11:21:55 +0000 Message-ID: <20240105112156.154807-3-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240105112156.154807-1-ayan.kumar.halder@amd.com> References: <20240105112156.154807-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989EB:EE_|DS0PR12MB7581:EE_ X-MS-Office365-Filtering-Correlation-Id: 376ddd6b-b2bc-4c8e-eb23-08dc0de0b3c2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2024 11:23:11.8092 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 376ddd6b-b2bc-4c8e-eb23-08dc0de0b3c2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989EB.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7581 From: Michal Orzel Currently if user enables HVC_DCC config option in Linux, it invokes access to debug data transfer registers (ie DBGDTRTX_EL0 on arm64, DBGDTRTXINT on arm32). As these registers are not emulated, Xen injects an undefined exception to the VM and Linux (running as VM) crashes. We wish to avoid this crash by adding a partial emulation of DBGDTRTX_EL0. MDCCSR_EL0 is emulated as TXfull. Refer ARM DDI 0487J.a ID042523, D19.3.8, DBGDTRTX_EL0 "If TXfull is set to 1, set DTRRX and DTRTX to UNKNOWN". Thus, any OS is expected to read MDCCSR_EL0 and check for TXfull before using DBGDTRTX_EL0. Linux does it via hvc_dcc_init() ---> hvc_dcc_check(), it returns -ENODEV. In this way, we are preventing the VM from accessing DBGDTRTX_EL0 register. We also emulate DBGDTR[TR]X_EL0 as RAZ/WI. Signed-off-by: Michal Orzel Signed-off-by: Ayan Kumar Halder --- Changes from v1 :- 1. DBGDTR_EL0 does not emulate RXfull. This is to avoid giving the OS any indication that the RX buffer is full and is waiting to be read. 2. In Arm32, DBGOSLSR is emulated. Also DBGDTRTXINT is emulated at EL0 only. 3. Fixed the commit message and inline code comments. v2 :- 1. Split the patch into two (separate patches for arm64 and arm32). 2. Removed the "fail" label. 3. Fixed the commit message. xen/arch/arm/arm64/vsysreg.c | 25 +++++++++++++++++++++---- xen/arch/arm/include/asm/arm64/hsr.h | 3 +++ 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index b5d54c569b..2f70eea2e5 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -159,9 +159,6 @@ void do_sysreg(struct cpu_user_regs *regs, * * Unhandled: * MDCCINT_EL1 - * DBGDTR_EL0 - * DBGDTRRX_EL0 - * DBGDTRTX_EL0 * OSDTRRX_EL1 * OSDTRTX_EL1 * OSECCR_EL1 @@ -172,11 +169,31 @@ void do_sysreg(struct cpu_user_regs *regs, case HSR_SYSREG_MDSCR_EL1: return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); case HSR_SYSREG_MDCCSR_EL0: + { /* + * Xen doesn't expose a real (or emulated) Debug Communications Channel + * (DCC) to a domain. Yet the Arm ARM implies this is not an optional + * feature. So some domains may start to probe it. For instance, the + * HVC_DCC driver in Linux (since f377775dc083 and at least up to v6.7), + * will try to write some characters and check if the transmit buffer + * has emptied. By setting TX status bit to indicate the transmit buffer + * is full, we would hint the OS that the DCC is probably not working. + * + * Bit 29: TX full + * * Accessible at EL0 only if MDSCR_EL1.TDCC is set to 0. We emulate that * register as RAZ/WI above. So RO at both EL0 and EL1. */ - return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 0); + return handle_ro_read_val(regs, regidx, hsr.sysreg.read, hsr, 0, + 1U << 29); + } +#ifdef CONFIG_PARTIAL_EMULATION + case HSR_SYSREG_DBGDTR_EL0: + /* DBGDTR[TR]X_EL0 share the same encoding */ + case HSR_SYSREG_DBGDTRTX_EL0: + if ( opt_partial_emulation ) + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 0); +#endif HSR_SYSREG_DBG_CASES(DBGBVR): HSR_SYSREG_DBG_CASES(DBGBCR): HSR_SYSREG_DBG_CASES(DBGWVR): diff --git a/xen/arch/arm/include/asm/arm64/hsr.h b/xen/arch/arm/include/asm/arm64/hsr.h index e691d41c17..1495ccddea 100644 --- a/xen/arch/arm/include/asm/arm64/hsr.h +++ b/xen/arch/arm/include/asm/arm64/hsr.h @@ -47,6 +47,9 @@ #define HSR_SYSREG_OSDLR_EL1 HSR_SYSREG(2,0,c1,c3,4) #define HSR_SYSREG_DBGPRCR_EL1 HSR_SYSREG(2,0,c1,c4,4) #define HSR_SYSREG_MDCCSR_EL0 HSR_SYSREG(2,3,c0,c1,0) +#define HSR_SYSREG_DBGDTR_EL0 HSR_SYSREG(2,3,c0,c4,0) +#define HSR_SYSREG_DBGDTRTX_EL0 HSR_SYSREG(2,3,c0,c5,0) +#define HSR_SYSREG_DBGDTRRX_EL0 HSR_SYSREG(2,3,c0,c5,0) #define HSR_SYSREG_DBGBVRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,4) #define HSR_SYSREG_DBGBCRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,5) From patchwork Fri Jan 5 11:21:56 2024 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v3 3/3] xen/arm: arm32: Add emulation of Debug Data Transfer Registers Date: Fri, 5 Jan 2024 11:21:56 +0000 Message-ID: <20240105112156.154807-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240105112156.154807-1-ayan.kumar.halder@amd.com> References: <20240105112156.154807-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FF:EE_|MN2PR12MB4568:EE_ X-MS-Office365-Filtering-Correlation-Id: a28ecb33-580c-4420-b16d-08dc0de0b67c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: iMc/GfiAlIpa0utVAqG7GskI5g376XoPxRdmFLg5ufxELDp2zH0jDxO/8T8Sj0jKwSDv9+mq5eFQy72A9L3QIof00qJLZDR5n/LIKGSuvqB09ck7S8SHV0mZC4I5u/JiGPSh1Qq7g6p5+9oW0PfKBmgP3fTpE+CAeXkTAveovMVZhVtfdIlDvHngoun1IQZJU6PS9OQurYcmBdufM3C/0NI618Ltgl37eYljGTNV/bT3SPAJN/+eGRE0+MECdm+bmzfyEexHWHNFrzXYWQ7ry/9O6dgAb/2m7XOrb5uUmwDsrfbFc8XFBSU/qcTmzesogFtZUJ59SfEziuyrqdNC9qZQNcnr0CP0u0LTh0GCsN5fE1y0qE+8Rxsat0seGwj4+1HoX0m5ZW5Y5+0ya9lR3pYBZylk9cUJ4pkrhLJFCDBF3FLe0ak5MJA0dsysA2EWOSopEbsNI0CzhYMsNzXNSj1lFbFUQzQ6ABkmA5mMtXJZvHKlkwlHWu0O1MK0hpKAe58hYsPurH6vVZqa0Onr/HmTUz3jfm1G1oJWrWonyKkLuDKGxz0IbxLb4V7tg+SOMxiSAFe6O+5IuM3whzaeJkSJzLgfZu/2EPacCReEe3eEUNkDBpx6FNGXavMx8zbrRx5qpsFlfLgOC6KObXncVS4DPtq6LeejoRWFPSFqQjDQd5TQ/gLX5Btzj9ar1TnYOVpfetsH1bMhPbYuQG2EvP/LNzYYVoC3Nri+UlpUH0bbyYFgzPxbBZBJwZSCZREU+huTsAebsaQNvqKlhOv15RqfXJwIfhQNqCOzZ3u4XaMaTB30i1I/mYo65yrnvcia X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(136003)(376002)(39860400002)(396003)(230922051799003)(230273577357003)(230173577357003)(82310400011)(186009)(451199024)(1800799012)(64100799003)(46966006)(40470700004)(36840700001)(40460700003)(40480700001)(2616005)(426003)(26005)(1076003)(336012)(6666004)(478600001)(82740400003)(103116003)(36756003)(86362001)(81166007)(356005)(2906002)(41300700001)(36860700001)(47076005)(83380400001)(70586007)(6916009)(54906003)(316002)(70206006)(5660300002)(4326008)(8936002)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2024 11:23:16.4759 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a28ecb33-580c-4420-b16d-08dc0de0b67c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4568 DBGOSLSR is emulated in the same way as its AArch64 variant (ie OSLSR_EL1). This is to ensure that DBGOSLSR.OSLK is 0, thus MDSCR_EL1.TXfull is treated as UNK/SBZP. Thus only MDCCSR_EL0 can be emulated (which is DBGDSCRINT on arm32). DBGDSCRINT can be accessed at EL0 as DBGDSCREXT is emulated as RAZ (as DBGOSLSR.OSLK == 0). DBGDSCRINT.TXfull is set to 1. Refer ARM DDI 0487J.a ID042523, G8.3.19, DBGDTRTXint "If TXfull is set to 1, set DTRTX to UNKNOWN". So, DBGDTR[TR]XINT is emulated as RAZ/WI. Signed-off-by: Ayan Kumar Halder --- Changes from v1 :- 1. DBGDTR_EL0 does not emulate RXfull. This is to avoid giving the OS any indication that the RX buffer is full and is waiting to be read. 2. In Arm32, DBGOSLSR is emulated. Also DBGDTRTXINT is emulated at EL0 only. 3. Fixed the commit message and inline code comments. v2 :- 1. Split the patch into two (separate patches for arm64 and arm32). 2. Fixed in line comments and style related issues. 3. Updated commit message to mention DBGDSCRINT handling. xen/arch/arm/include/asm/cpregs.h | 2 ++ xen/arch/arm/vcpreg.c | 36 ++++++++++++++++++++++--------- 2 files changed, 28 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/include/asm/cpregs.h b/xen/arch/arm/include/asm/cpregs.h index 6b083de204..aec9e8f329 100644 --- a/xen/arch/arm/include/asm/cpregs.h +++ b/xen/arch/arm/include/asm/cpregs.h @@ -75,6 +75,8 @@ #define DBGDIDR p14,0,c0,c0,0 /* Debug ID Register */ #define DBGDSCRINT p14,0,c0,c1,0 /* Debug Status and Control Internal */ #define DBGDSCREXT p14,0,c0,c2,2 /* Debug Status and Control External */ +#define DBGDTRRXINT p14,0,c0,c5,0 /* Debug Data Transfer Register, Receive */ +#define DBGDTRTXINT p14,0,c0,c5,0 /* Debug Data Transfer Register, Transmit */ #define DBGVCR p14,0,c0,c7,0 /* Vector Catch */ #define DBGBVR0 p14,0,c0,c0,4 /* Breakpoint Value 0 */ #define DBGBCR0 p14,0,c0,c0,5 /* Breakpoint Control 0 */ diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index a2d0500704..474f872b5f 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -493,11 +493,12 @@ void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr) * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 * * Unhandled: - * DBGOSLSR * DBGPRCR */ case HSR_CPREG32(DBGOSLAR): return handle_wo_wi(regs, regidx, cp32.read, hsr, 1); + case HSR_CPREG32(DBGOSLSR): + return handle_ro_read_val(regs, regidx, cp32.read, hsr, 1, 1U << 3); case HSR_CPREG32(DBGOSDLR): return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); @@ -509,8 +510,6 @@ void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr) * * Unhandled: * DBGDCCINT - * DBGDTRRXint - * DBGDTRTXint * DBGWFAR * DBGDTRTXext * DBGDTRRXext, @@ -549,11 +548,24 @@ void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr) } case HSR_CPREG32(DBGDSCRINT): + { /* - * Read-only register. Accessible by EL0 if DBGDSCRext.UDCCdis - * is set to 0, which we emulated below. + * Xen doesn't expose a real (or emulated) Debug Communications Channel + * (DCC) to a domain. Yet the Arm ARM implies this is not an optional + * feature. So some domains may start to probe it. For instance, the + * HVC_DCC driver in Linux (since f377775dc083 and at least up to v6.7), + * will try to write some characters and check if the transmit buffer + * has emptied. By setting TX status bit to indicate the transmit buffer + * is full. This we would hint the OS that the DCC is probably not + * working. + * + * Bit 29: TX full + * + * Accessible by EL0 if DBGDSCRext.UDCCdis is set to 0, which we emulate + * as RAZ/WI in the next case. */ - return handle_ro_raz(regs, regidx, cp32.read, hsr, 1); + return handle_ro_read_val(regs, regidx, cp32.read, hsr, 0, 1U << 29); + } case HSR_CPREG32(DBGDSCREXT): /* @@ -562,6 +574,13 @@ void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr) */ return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); +#ifdef CONFIG_PARTIAL_EMULATION + /* DBGDTR[TR]XINT share the same encoding */ + case HSR_CPREG32(DBGDTRTXINT): + if ( opt_partial_emulation ) + return handle_raz_wi(regs, regidx, cp32.read, hsr, 0); +#endif + case HSR_CPREG32(DBGVCR): case HSR_CPREG32(DBGBVR0): case HSR_CPREG32(DBGBCR0): @@ -659,10 +678,7 @@ void do_cp14_dbg(struct cpu_user_regs *regs, const union hsr hsr) * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 * * Unhandled: - * DBGDTRTXint - * DBGDTRRXint - * - * And all other unknown registers. + * All unknown registers. */ gdprintk(XENLOG_ERR, "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n",