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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF000252A1.mail.protection.outlook.com (10.167.242.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7181.13 via Frontend Transport; Fri, 12 Jan 2024 23:42:25 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Fri, 12 Jan 2024 17:42:24 -0600 Received: from xsjanatoliy50.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Fri, 12 Jan 2024 17:42:23 -0600 From: Anatoliy Klymenko To: , , , , , , , , , Subject: [PATCH 1/4] drm: xlnx: zynqmp_dpsub: Make drm bridge discoverable Date: Fri, 12 Jan 2024 15:42:19 -0800 Message-ID: <20240112234222.913138-2-anatoliy.klymenko@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240112234222.913138-1-anatoliy.klymenko@amd.com> References: <20240112234222.913138-1-anatoliy.klymenko@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A1:EE_|LV2PR12MB5967:EE_ X-MS-Office365-Filtering-Correlation-Id: d1a85eb4-920f-47ab-7385-08dc13c82133 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Assign device of node to bridge prior registering it. This will make said bridge discoverable by separate crtc driver. Signed-off-by: Anatoliy Klymenko Reviewed-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart --- drivers/gpu/drm/xlnx/zynqmp_dp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c index a0606fab0e22..d60b7431603f 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c @@ -1721,6 +1721,7 @@ int zynqmp_dp_probe(struct zynqmp_dpsub *dpsub) bridge->ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD; bridge->type = DRM_MODE_CONNECTOR_DisplayPort; + bridge->of_node = dp->dev->of_node; dpsub->bridge = bridge; /* From patchwork Fri Jan 12 23:42:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Klymenko, Anatoliy" X-Patchwork-Id: 13518776 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2D46DC4706C for ; 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Signed-off-by: Anatoliy Klymenko Reviewed-by: Tomi Valkeinen --- drivers/gpu/drm/xlnx/zynqmp_disp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c index 407bc07cec69..8a39b3accce5 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c @@ -1166,7 +1166,7 @@ void zynqmp_disp_enable(struct zynqmp_disp *disp) /* Choose clock source based on the DT clock handle. */ zynqmp_disp_avbuf_set_clocks_sources(disp, disp->dpsub->vid_clk_from_ps, disp->dpsub->aud_clk_from_ps, - true); + disp->dpsub->vid_clk_from_ps); zynqmp_disp_avbuf_enable_channels(disp); zynqmp_disp_avbuf_enable_audio(disp); From patchwork Fri Jan 12 23:42:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Klymenko, Anatoliy" X-Patchwork-Id: 13518777 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EA3E7C47422 for ; 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Fri, 12 Jan 2024 17:42:26 -0600 Received: from xsjanatoliy50.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Fri, 12 Jan 2024 17:42:25 -0600 From: Anatoliy Klymenko To: , , , , , , , , , Subject: [PATCH 3/4] drm: xlnx: zynqmp_dpsub: Don't generate vblank in live mode Date: Fri, 12 Jan 2024 15:42:21 -0800 Message-ID: <20240112234222.913138-4-anatoliy.klymenko@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240112234222.913138-1-anatoliy.klymenko@amd.com> References: <20240112234222.913138-1-anatoliy.klymenko@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A1:EE_|MN0PR12MB5858:EE_ X-MS-Office365-Filtering-Correlation-Id: 57ee41d7-6294-49ca-b366-08dc13c82296 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YWpH8F0YFS7fGEAbqYsXLi6PoSPKqgY8Fd1TjA50SzcQ1gd8fOAQXMyfs82QwugRpbE/82FSulZHIuJ0RqBJGTHOs7tr0pFUYuZJ2kJHuxxF9gbKyEDP0ons6wdscVwZvHjJ5MKeMnVXuYuJn7+owvV1npkN/c5ctm+xjt9EFgH+K4XO8nSeJ0fm+gngfW6KpVvmVsTBY3zd1p78mb9g3CkARtBs1j+kRgYCW4zQ3CGXUudFFvqndnsfwsV9m0qJOA/LSr4imGX6YNL3bpkWcCpgD+SPabdvfVDFAHCtDUI2fyNYzgyVXEn4Ae3+F1qUXv9tgTF0bMvEPmwArqNs4KdK9AUm0hvyXJVVPTzuQoke7XC6ocndCcMoh4vFn/QQ4+UtvEHqcOHjcc06zA2nkLrx+sGQnP3/vs0xlHsts6BfBmKk2a7YO2yQaPmuHtSthdWDFB7QX2rskJ2Hjjqyp6TpvZJ5AHr9VUJRSyzYoIx6McI50nd8mFUXhKSve0Bi/zpWqz0R5rQmKm+RK9qWgrbZYWmULMWObaySl0c8kQIx0QcdnP2uR+SGiIlROaSCGchylqZCBzM9BYQdqfT45cP3JSUXPBX2SonoylME+rpj+WdeLXsuMeTDGJP5f79kF+F9UZaAoIAxJ2gzMWaR4UFgNbsTFY2t9M1d+mNIAu8/vwPgpYIENaFx6YLaN5iP0GN9j+n0YnE+mG5PrrlD5mDYt1F/b0gumSvZBbU+7+VrHV4VMFYQllMxRDZFF/3iB4OCDLO6S4HVrG3RKdyg2fd9u2SMdyXL/rqF5dQhMVe8p3W3RTa9Jc3ZRHb6iu0tc/r1WnH9Rap1HOviueBzMQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(136003)(396003)(376002)(346002)(230922051799003)(451199024)(1800799012)(82310400011)(64100799003)(186009)(40470700004)(36840700001)(46966006)(83380400001)(921011)(2906002)(110136005)(2616005)(82740400003)(1076003)(26005)(336012)(5660300002)(8936002)(426003)(81166007)(36860700001)(41300700001)(316002)(356005)(8676002)(44832011)(6666004)(70206006)(47076005)(70586007)(478600001)(86362001)(40460700003)(40480700001)(36756003)(83996005)(2101003)(36900700001);DIR:OUT;SFP:1101; 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Some events are being reported via DP status register, even if corresponding interrupts have been disabled. Avoid processing of such events in interrupt handler context. Signed-off-by: Anatoliy Klymenko --- drivers/gpu/drm/xlnx/zynqmp_dp.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c index d60b7431603f..571c5dbc97e5 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c @@ -1624,8 +1624,16 @@ static irqreturn_t zynqmp_dp_irq_handler(int irq, void *data) u32 status, mask; status = zynqmp_dp_read(dp, ZYNQMP_DP_INT_STATUS); + zynqmp_dp_write(dp, ZYNQMP_DP_INT_STATUS, status); mask = zynqmp_dp_read(dp, ZYNQMP_DP_INT_MASK); - if (!(status & ~mask)) + + /* + * Status register may report some events, which corresponding interrupts + * have been disabled. Filter out those events against interrupts' mask. + */ + status &= ~mask; + + if (!status) return IRQ_NONE; /* dbg for diagnostic, but not much that the driver can do */ @@ -1634,7 +1642,6 @@ static irqreturn_t zynqmp_dp_irq_handler(int irq, void *data) if (status & ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK) dev_dbg_ratelimited(dp->dev, "overflow interrupt\n"); - zynqmp_dp_write(dp, ZYNQMP_DP_INT_STATUS, status); if (status & ZYNQMP_DP_INT_VBLANK_START) zynqmp_dpsub_drm_handle_vblank(dp->dpsub); From patchwork Fri Jan 12 23:42:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Klymenko, Anatoliy" X-Patchwork-Id: 13518780 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3694DC4706C for ; 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Fri, 12 Jan 2024 17:42:27 -0600 Received: from xsjanatoliy50.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Fri, 12 Jan 2024 17:42:26 -0600 From: Anatoliy Klymenko To: , , , , , , , , , Subject: [PATCH 4/4] drm: xlnx: zynqmp_dpsub: Set live video in format Date: Fri, 12 Jan 2024 15:42:22 -0800 Message-ID: <20240112234222.913138-5-anatoliy.klymenko@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240112234222.913138-1-anatoliy.klymenko@amd.com> References: <20240112234222.913138-1-anatoliy.klymenko@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A1:EE_|CH0PR12MB5218:EE_ X-MS-Office365-Filtering-Correlation-Id: 2d1528c3-6861-4456-d660-08dc13c822fa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: iGC4qWbBwyws/+3rpKUGCtNUjMh1gpMnNDThrFhcUwNYrXBhF5uy7B1Gw7HW0k8tN7YqXD+/XCLmlPYzSarwpGwZr6oV+tAFh2Uirp/X+j4IW5Uw5K9rlIxSWDhgx2+S51yH0CK6wqgMG0YG+L+epnnQ+Dy4KS/W0tfGHMmcHxMVc3CObF60gEOB6wOa+4r1LTGSzPHg4I/OLmOnD+9TJmzQf6T/TngDPVZp5kkbRBItU7g63mhns308EE+7qELZt4TpQJQvvCppLSw+cCtMVTUkTkb8q06cm4MI8m/zRkbXpedQEt9aZdJVHrOw1kM5fKBH+H0KrW8Z9OedDtmIF1PE5iAYR5+vYbS1AR0QyDaw98dTclCi9QN53RueuBUckX8VQ94A5cMS3Nll0zD5j0oEmsTaIp+zBHpCxZypovpixItPiuOSVeINa12jHJUZGZdbnhMbIfAkek3Mk2VegEZMJe3FHiOEC0SQ64sKEtDryML6/8eH7NWF336/jp/hnDQzRjouukZWpumLaHkUuVTg/jQGG5O3IudzTXOfslK7VlSNrifusMOANbkb3f4iybzjyCRauxkW/uY3aGgEWvvkjulUpr4r8HRH/Tl/VX1HJ7iwuI1RkQktv5en8Hw97Ghbc4EczjAfA7SkAg6KD8AUYKNXijCZaJs37vfdMJHsvQG6cNERX3Wtin6opIAy9veZZjdSUdSM8Kgtptsf0D+b2XsOlNpHE5oqo17x2l1eTPmZGATgayK977l1OpFXwSvWi3b0eVypiotqJWxTTY+tkf1CUNnUucw5v1ndHkM/8gP8+0LjfjlvtxSuI98TbXSBjD1/dKV0LS5bVJqGEw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(39860400002)(376002)(136003)(346002)(230922051799003)(64100799003)(186009)(451199024)(82310400011)(1800799012)(36840700001)(46966006)(40470700004)(40460700003)(40480700001)(426003)(6666004)(36860700001)(1076003)(2616005)(336012)(26005)(81166007)(36756003)(86362001)(82740400003)(356005)(2906002)(44832011)(8936002)(8676002)(83380400001)(47076005)(5660300002)(921011)(41300700001)(70586007)(316002)(478600001)(70206006)(110136005)(83996005)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jan 2024 23:42:28.0393 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d1528c3-6861-4456-d660-08dc13c822fa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5218 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240112_154240_557371_EB6FCA5B X-CRM114-Status: GOOD ( 23.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Live video input format is expected to be set as "bus-format" property in connected remote endpoint. Program live video input format DPSUB registers. Set display layer mode in layer creation context. Signed-off-by: Anatoliy Klymenko --- drivers/gpu/drm/xlnx/zynqmp_disp.c | 109 ++++++++++++++++++++++-- drivers/gpu/drm/xlnx/zynqmp_disp.h | 3 +- drivers/gpu/drm/xlnx/zynqmp_disp_regs.h | 8 +- drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +- drivers/gpu/drm/xlnx/zynqmp_kms.c | 2 +- 5 files changed, 107 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c index 8a39b3accce5..83af3ad9cdb5 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c @@ -20,8 +20,10 @@ #include #include #include +#include #include #include +#include #include "zynqmp_disp.h" #include "zynqmp_disp_regs.h" @@ -67,12 +69,16 @@ /** * struct zynqmp_disp_format - Display subsystem format information * @drm_fmt: DRM format (4CC) + * @bus_fmt: Live video media bus format * @buf_fmt: AV buffer format * @swap: Flag to swap R & B for RGB formats, and U & V for YUV formats * @sf: Scaling factors for color components */ struct zynqmp_disp_format { - u32 drm_fmt; + union { + u32 drm_fmt; + u32 bus_fmt; + }; u32 buf_fmt; bool swap; const u32 *sf; @@ -354,6 +360,16 @@ static const struct zynqmp_disp_format avbuf_gfx_fmts[] = { }, }; +/* TODO: add support for different formats */ +static const struct zynqmp_disp_format avbuf_live_vid_fmts[] = { + { + .bus_fmt = MEDIA_BUS_FMT_UYVY8_1X16, + .buf_fmt = ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_8 | + ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV422, + .sf = scaling_factors_888, + } +}; + static u32 zynqmp_disp_avbuf_read(struct zynqmp_disp *disp, int reg) { return readl(disp->avbuf.base + reg); @@ -369,6 +385,34 @@ static bool zynqmp_disp_layer_is_video(const struct zynqmp_disp_layer *layer) return layer->id == ZYNQMP_DPSUB_LAYER_VID; } +/** + * zynqmp_disp_avbuf_set_live_format - Set live input format for a layer + * @disp: Display controller + * @layer: The layer + * @fmt: The format information + * + * Set the live video input format for @layer to @fmt. + */ +static void zynqmp_disp_avbuf_set_live_format(struct zynqmp_disp *disp, + struct zynqmp_disp_layer *layer, + const struct zynqmp_disp_format *fmt) +{ + u32 reg, i; + + reg = zynqmp_disp_layer_is_video(layer) + ? ZYNQMP_DISP_AV_BUF_LIVE_VID_CONFIG + : ZYNQMP_DISP_AV_BUF_LIVE_GFX_CONFIG; + zynqmp_disp_avbuf_write(disp, reg, fmt->buf_fmt); + + for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_SF; ++i) { + reg = zynqmp_disp_layer_is_video(layer) + ? ZYNQMP_DISP_AV_BUF_LIVD_VID_COMP_SF(i) + : ZYNQMP_DISP_AV_BUF_LIVD_GFX_COMP_SF(i); + zynqmp_disp_avbuf_write(disp, reg, fmt->sf[i]); + } + layer->disp_fmt = fmt; +} + /** * zynqmp_disp_avbuf_set_format - Set the input format for a layer * @disp: Display controller @@ -902,15 +946,12 @@ u32 *zynqmp_disp_layer_drm_formats(struct zynqmp_disp_layer *layer, /** * zynqmp_disp_layer_enable - Enable a layer * @layer: The layer - * @mode: Operating mode of layer * * Enable the @layer in the audio/video buffer manager and the blender. DMA * channels are started separately by zynqmp_disp_layer_update(). */ -void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer, - enum zynqmp_dpsub_layer_mode mode) +void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer) { - layer->mode = mode; zynqmp_disp_avbuf_enable_video(layer->disp, layer); zynqmp_disp_blend_layer_enable(layer->disp, layer); } @@ -950,11 +991,12 @@ void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer, layer->disp_fmt = zynqmp_disp_layer_find_format(layer, info->format); layer->drm_fmt = info; - zynqmp_disp_avbuf_set_format(layer->disp, layer, layer->disp_fmt); - - if (!layer->disp->dpsub->dma_enabled) + /* Live format set during layer creation */ + if (layer->mode == ZYNQMP_DPSUB_LAYER_LIVE) return; + zynqmp_disp_avbuf_set_format(layer->disp, layer, layer->disp_fmt); + /* * Set pconfig for each DMA channel to indicate they're part of a * video group. @@ -1083,7 +1125,7 @@ static int zynqmp_disp_layer_request_dma(struct zynqmp_disp *disp, unsigned int i; int ret; - if (!disp->dpsub->dma_enabled) + if (layer->mode == ZYNQMP_DPSUB_LAYER_LIVE) return 0; for (i = 0; i < layer->info->num_channels; i++) { @@ -1104,6 +1146,43 @@ static int zynqmp_disp_layer_request_dma(struct zynqmp_disp *disp, return 0; } +/** + * zynqmp_disp_get_live_fmt - Get live video format + * @disp: Display controller + * @layer: Display layer + * + * Parse connected remote endpoint and retrieve configured bus-format + * + * Return: live format pointer on success, NULL otherwise + */ +static const struct zynqmp_disp_format *zynqmp_disp_get_live_fmt(struct zynqmp_disp *disp, + struct zynqmp_disp_layer *layer) +{ + struct device_node *local, *remote, *dpsub = disp->dev->of_node; + int rc, i; + u32 fmt; + + local = of_graph_get_endpoint_by_regs(dpsub, layer->id, -1); + if (!local) + return NULL; + + remote = of_graph_get_remote_endpoint(local); + of_node_put(local); + if (!remote) + return NULL; + + rc = of_property_read_u32_index(remote, "bus-format", 0, &fmt); + of_node_put(remote); + if (rc) + return NULL; + + for (i = 0; i < ARRAY_SIZE(avbuf_live_vid_fmts); ++i) + if (avbuf_live_vid_fmts[i].bus_fmt == fmt) + return &avbuf_live_vid_fmts[i]; + + return NULL; +} + /** * zynqmp_disp_create_layers - Create and initialize all layers * @disp: Display controller @@ -1130,9 +1209,15 @@ static int zynqmp_disp_create_layers(struct zynqmp_disp *disp) for (i = 0; i < ARRAY_SIZE(disp->layers); i++) { struct zynqmp_disp_layer *layer = &disp->layers[i]; + const struct zynqmp_disp_format *disp_fmt; layer->id = i; layer->disp = disp; + /* For now we assume dpsub works in either live or non-live mode for both layers. + * Hybrid mode is not supported yet. + */ + layer->mode = disp->dpsub->dma_enabled ? ZYNQMP_DPSUB_LAYER_NONLIVE + : ZYNQMP_DPSUB_LAYER_LIVE; layer->info = &layer_info[i]; ret = zynqmp_disp_layer_request_dma(disp, layer); @@ -1140,6 +1225,12 @@ static int zynqmp_disp_create_layers(struct zynqmp_disp *disp) goto err; disp->dpsub->layers[i] = layer; + + if (layer->mode == ZYNQMP_DPSUB_LAYER_LIVE) { + disp_fmt = zynqmp_disp_get_live_fmt(disp, layer); + if (disp_fmt) + zynqmp_disp_avbuf_set_live_format(disp, layer, disp_fmt); + } } return 0; diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.h b/drivers/gpu/drm/xlnx/zynqmp_disp.h index 123cffac08be..f3357b2d5c09 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_disp.h +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.h @@ -62,8 +62,7 @@ void zynqmp_disp_blend_set_global_alpha(struct zynqmp_disp *disp, u32 *zynqmp_disp_layer_drm_formats(struct zynqmp_disp_layer *layer, unsigned int *num_formats); -void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer, - enum zynqmp_dpsub_layer_mode mode); +void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer); void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer); void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer, const struct drm_format_info *info); diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp_regs.h b/drivers/gpu/drm/xlnx/zynqmp_disp_regs.h index f92a006d5070..926e07c255bb 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_disp_regs.h +++ b/drivers/gpu/drm/xlnx/zynqmp_disp_regs.h @@ -165,10 +165,10 @@ #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_10 0x2 #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_12 0x3 #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_MASK GENMASK(2, 0) -#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_RGB 0x0 -#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV444 0x1 -#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV422 0x2 -#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YONLY 0x3 +#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_RGB 0x00 +#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV444 0x10 +#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV422 0x20 +#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YONLY 0x30 #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_MASK GENMASK(5, 4) #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_CB_FIRST BIT(8) #define ZYNQMP_DISP_AV_BUF_PALETTE_MEMORY 0x400 diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c index 571c5dbc97e5..59616ed1c3d9 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c @@ -1295,7 +1295,7 @@ static void zynqmp_dp_disp_enable(struct zynqmp_dp *dp, /* TODO: Make the format configurable. */ info = drm_format_info(DRM_FORMAT_YUV422); zynqmp_disp_layer_set_format(layer, info); - zynqmp_disp_layer_enable(layer, ZYNQMP_DPSUB_LAYER_LIVE); + zynqmp_disp_layer_enable(layer); if (layer_id == ZYNQMP_DPSUB_LAYER_GFX) zynqmp_disp_blend_set_global_alpha(dp->dpsub->disp, true, 255); diff --git a/drivers/gpu/drm/xlnx/zynqmp_kms.c b/drivers/gpu/drm/xlnx/zynqmp_kms.c index db3bb4afbfc4..43bf416b33d5 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_kms.c +++ b/drivers/gpu/drm/xlnx/zynqmp_kms.c @@ -122,7 +122,7 @@ static void zynqmp_dpsub_plane_atomic_update(struct drm_plane *plane, /* Enable or re-enable the plane if the format has changed. */ if (format_changed) - zynqmp_disp_layer_enable(layer, ZYNQMP_DPSUB_LAYER_NONLIVE); + zynqmp_disp_layer_enable(layer); } static const struct drm_plane_helper_funcs zynqmp_dpsub_plane_helper_funcs = {