From patchwork Mon Jan 22 16:06:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tangnianyao X-Patchwork-Id: 13524903 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1D5E6C47DAF for ; Mon, 22 Jan 2024 08:08:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=2q1G1JHxNTnHcOQOboxW+Yw+g6E2gATbR4xU9GL4nAg=; b=pf1OWBnDmqVI9j hag0lPnosViVfs8JSktkwuo3K9rVXavog+bzh+YOaZB5hQdT0kxI2GFU2SJfE9mCjvqILCdBIdzi8 rlBbrcBl+1R4CzOeHOlw6NXCd62iJOR39IZLKRYb8jxFYrCUn+DfreGlwoPfW92oXrFhWsR/4zTF+ 73OmOYDuQPjT4cWejTSLzvyaLwtUxtbiQbWwCZS94yCzeAiO1Bvat7C+sR1E082b7EaDnc37n5pcU k0VapM3fSn3gB42E+egu4+yz/xYV7vF9Q/Lh+rYcQAhCkRjNDUtZZSZAFVvwwQ67bMvHAU9CTVn9t E37GW1zkVE+8x8XdVrUg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rRpLY-00Az13-0w; Mon, 22 Jan 2024 08:07:56 +0000 Received: from szxga07-in.huawei.com ([45.249.212.35]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rRpLU-00Ayxg-0g for linux-arm-kernel@lists.infradead.org; Mon, 22 Jan 2024 08:07:54 +0000 Received: from mail.maildlp.com (unknown [172.19.88.234]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4TJN816Rx4z1S5NV; Mon, 22 Jan 2024 16:05:53 +0800 (CST) Received: from kwepemd500003.china.huawei.com (unknown [7.221.188.36]) by mail.maildlp.com (Postfix) with ESMTPS id A2C921400FD; Mon, 22 Jan 2024 16:07:36 +0800 (CST) Received: from 228-1616.huawei.com (10.67.246.68) by kwepemd500003.china.huawei.com (7.221.188.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.1258.28; Mon, 22 Jan 2024 16:07:36 +0800 From: Nianyao Tang To: , , <"linux-kernel@vger.kernel.orgstefanha"@redhat.com>, CC: , , Subject: [PATCH] irqchip/gic-v4.1:Check whether indirect table is supported in allocate_vpe_l1_table Date: Mon, 22 Jan 2024 16:06:07 +0000 Message-ID: <20240122160607.1078960-1-tangnianyao@huawei.com> X-Mailer: git-send-email 2.30.0 MIME-Version: 1.0 X-Originating-IP: [10.67.246.68] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemd500003.china.huawei.com (7.221.188.36) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240122_000752_613900_923B4D46 X-CRM114-Status: GOOD ( 14.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In allocate_vpe_l1_table, when we fail to inherit VPE table from other redistributors or ITSs, and we allocate a new vpe table for current common affinity field without checking whether indirect table is supported. Let's fix it. Signed-off-by: Nianyao Tang --- drivers/irqchip/irq-gic-v3-its.c | 28 ++++++++++++++++++++++------ include/linux/irqchip/arm-gic-v3.h | 1 + 2 files changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index d097001c1e3e..4146d1e285ec 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -2836,6 +2836,7 @@ static int allocate_vpe_l1_table(void) unsigned int psz = SZ_64K; unsigned int np, epp, esz; struct page *page; + bool indirect = false; if (!gic_rdists->has_rvpeid) return 0; @@ -2890,6 +2891,12 @@ static int allocate_vpe_l1_table(void) break; } + /* probe the indirect */ + val = GICR_VPROPBASER_4_1_INDIRECT; + gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER); + val = gicr_read_vpropbaser(vlpi_base + GICR_VPROPBASER); + indirect = !!(val & GICR_VPROPBASER_4_1_INDIRECT); + /* * Start populating the register from scratch, including RO fields * (which we want to print in debug cases...) @@ -2907,15 +2914,24 @@ static int allocate_vpe_l1_table(void) * as indirect and compute the number of required L1 pages. */ if (epp < ITS_MAX_VPEID) { - int nl2; + if (indirect) { + int nl2; - val |= GICR_VPROPBASER_4_1_INDIRECT; + val |= GICR_VPROPBASER_4_1_INDIRECT; - /* Number of L2 pages required to cover the VPEID space */ - nl2 = DIV_ROUND_UP(ITS_MAX_VPEID, epp); + /* Number of L2 pages required to cover the VPEID space */ + nl2 = DIV_ROUND_UP(ITS_MAX_VPEID, epp); - /* Number of L1 pages to point to the L2 pages */ - npg = DIV_ROUND_UP(nl2 * SZ_8, psz); + /* Number of L1 pages to point to the L2 pages */ + npg = DIV_ROUND_UP(nl2 * SZ_8, psz); + } else { + npg = DIV_ROUND_UP(ITS_MAX_VPEID, epp); + if (npg > GICR_VPROPBASER_PAGES_MAX) { + pr_warn("GICR_VPROPBASER pages too large, reduce %llu->%u\n", + npg, GICR_VPROPBASER_PAGES_MAX); + npg = GICR_VPROPBASER_PAGES_MAX; + } + } } else { npg = 1; } diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 728691365464..ace37dfbff20 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -303,6 +303,7 @@ #define GICR_VPROPBASER_4_1_Z (1ULL << 52) #define GICR_VPROPBASER_4_1_ADDR GENMASK_ULL(51, 12) #define GICR_VPROPBASER_4_1_SIZE GENMASK_ULL(6, 0) +#define GICR_VPROPBASER_PAGES_MAX 128 #define GICR_VPENDBASER 0x0078