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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id p21-20020a05600c359500b0040e3488f16dsm42457536wmq.12.2024.01.23.07.34.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 07:34:26 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH 01/21] spi: dt-bindings: samsung: add google,gs101-spi compatible Date: Tue, 23 Jan 2024 15:34:00 +0000 Message-ID: <20240123153421.715951-2-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240123153421.715951-1-tudor.ambarus@linaro.org> References: <20240123153421.715951-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add "google,gs101-spi" dedicated compatible for representing SPI of Google GS101 SoC. Signed-off-by: Tudor Ambarus Reviewed-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski Acked-by: Andi Shyti --- Documentation/devicetree/bindings/spi/samsung,spi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/samsung,spi.yaml b/Documentation/devicetree/bindings/spi/samsung,spi.yaml index 79da99ca0e53..386ea8b23993 100644 --- a/Documentation/devicetree/bindings/spi/samsung,spi.yaml +++ b/Documentation/devicetree/bindings/spi/samsung,spi.yaml @@ -17,6 +17,7 @@ properties: compatible: oneOf: - enum: + - google,gs101-spi - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450 - samsung,s3c6410-spi - samsung,s5pv210-spi # for S5PV210 and S5PC110 From patchwork Tue Jan 23 15:34:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13527671 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 168C15FEF7 for ; Tue, 23 Jan 2024 15:34:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024071; cv=none; b=m88QHYY7u5ET25pyWFOzntRZOxlIIGDPHQySIcpUxCYKm9dm8hOV2Wuop/6SQM1eCkrdd/7mhfUxkpI5CNMBAy8Y9TKpLCW+rs9L6mh8PzVPE38b40iMu4YkboypVVEMugUhfW7ZW213EPWKpbHeY7JGD1APuGQcqf3ZaCQ0EQw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024071; c=relaxed/simple; bh=ElWpxBc+uZ28K/jxG5M5DOmScKkdCa0Y4Qo25bOXlMw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KrG1BeJ3hL9mu/sb8xhNEYUtYpYzcJJJXqiYkBswFRD6/L3mRTW/eegxW1rYl0SLI0ZtZHxy/+iSQ8KE/nCqEKg1wamqCudhIo9WwyaXyfUEYWzAj8twOLx+sZ2QDQr5b7cN9D1V5m7odDUNqfC4wL2qa2yiGvkTEpCh/e99yy0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Y3EnXXao; arc=none smtp.client-ip=209.85.128.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Y3EnXXao" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-40e72a567eeso53432305e9.0 for ; Tue, 23 Jan 2024 07:34:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706024067; x=1706628867; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XigujyuTekxObecLRQT69LgHjYiW1lnxBRIg9BTFsN8=; b=Y3EnXXaormQRU1iecto8ieV9zhbSyWUGlEnfBMk4uZ8bI2ef0++7oA2crp5c32C/Zi Mt7kvW8QRxUfhLzxZLhGFOFY9VcXSYePbygA3czFdEa/6/s3sumxK8hAz8L5NKdj726Y A8urarvzq/GposQfe5625g7+w0jMI2dB9SMIqRGlS3/ODl/spixXLUgbxkmqVHc3Zpmw XGA7QnhInY36MkETvtW++s2MxgK3Uq9hhkbhKv0xkg06UahH9oIJlPCo9JNTFmj/5r4A Xr+X9hI8RTyiOxtDHRsxwuT7vTnrf1uxWw8nlLPM4aHNhumvLCHu12ot6S4gAnF+CgVL wUfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706024067; x=1706628867; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XigujyuTekxObecLRQT69LgHjYiW1lnxBRIg9BTFsN8=; b=gELpO+YEUwYwxdFVSbJ1fOWGLK5e+HotaWrya52BF44Wg3WdDU0FvvgpUxwzSLADMN uI/6Im+3fGGcT/fOK0CQDcfTHogI46ekq14cdtTwxbm95cxkSN/NeJAsuIP0M6k+Plxi u7fsRHmbxuBrLtjo4xoVZ/BoiW+tj9604npd1iAioAsyQEmjQ16rgThB4jWRTFHfyskn SKT+32eOu01FaUamoYtjFSuwVi7/U4q5T9X+Yup/6+gQobupXNEN2u1fMxe+Dd4ymXFa uy1o/rTc/hhbQyulZR2uH5NRPFYq+NEf0Et8NYjGZP+HtOBo1LrQAv+ARGV0DXRx1Jcr KZfg== X-Gm-Message-State: AOJu0YwzwGrl5hQsWJ/ATA35JRxG4rsSsgoExGx9M5HtoAbSBXrjZzz4 oLrgSO3zYpoTb+7ro4qh+HmSIqoAtO5pwV7APwOoUvek5vzPnJ6Ykk2INj1F938= X-Google-Smtp-Source: AGHT+IF1ROX3DbhMGiVBd3XC1sBuhtQqNpsdEmdhphsiT0Bhxh5GRHz0uW02UEB/+wKq7d65pkfsCQ== X-Received: by 2002:a05:600c:3ba2:b0:40e:a328:25ff with SMTP id n34-20020a05600c3ba200b0040ea32825ffmr344127wms.93.1706024067183; Tue, 23 Jan 2024 07:34:27 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id p21-20020a05600c359500b0040e3488f16dsm42457536wmq.12.2024.01.23.07.34.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 07:34:26 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH 02/21] spi: s3c64xx: sort headers alphabetically Date: Tue, 23 Jan 2024 15:34:01 +0000 Message-ID: <20240123153421.715951-3-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240123153421.715951-1-tudor.ambarus@linaro.org> References: <20240123153421.715951-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Sorting headers alphabetically helps locating duplicates, and makes it easier to figure out where to insert new headers. Signed-off-by: Tudor Ambarus Reviewed-by: Andi Shyti --- drivers/spi/spi-s3c64xx.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 432ec60d3568..187b617e3e14 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -3,19 +3,19 @@ // Copyright (c) 2009 Samsung Electronics Co., Ltd. // Jaswinder Singh -#include -#include -#include -#include #include +#include #include #include +#include +#include +#include +#include +#include #include #include #include -#include -#include #define MAX_SPI_PORTS 12 #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) From patchwork Tue Jan 23 15:34:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13527670 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B58D25FF0A for ; Tue, 23 Jan 2024 15:34:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024071; cv=none; b=VLn+nA/iHNTzvBAeYd2ON2VbAuf0NAE20+rxhhfakRrBg6eHcAm6oB6YZN/1eW7fbc3nZqzH2F0jTT5ljLcKVFfp/72CV6MaHTeM8w6ktBf7lCtg8fy2cFs26sb4pFgzc8Yu+tGx37omNgiJPnTAQPnALV0xd8wY4QuwiYSuoy4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024071; c=relaxed/simple; bh=Wu0+yV3u4XzGF+o7kJWaER/58nXttiKzUPsevm54PqQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QbuVVT6XYL5ro5Xs1B5qN6EuaWqllnPEeK1hbZJchz99FcGjsD/VCE7dBzcwouEcWwHkZ4D7auOIptazfXKi0Ahtzvv1SorNuILf8UQo2j0u/JQ2qW4nhmxdiwa0xkIY0D+Hkb66wO2wr/hX84hCoMzqEsD6SB7HvI5TV8Mk86c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=MXnCoeoy; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="MXnCoeoy" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-40eb033c1b0so21746205e9.2 for ; Tue, 23 Jan 2024 07:34:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706024068; x=1706628868; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TlhyzNjFt8B4egY8fYl+NmfB3SAkzLPxUZ0BvmIG80I=; b=MXnCoeoyETLxGk/EiMMpU8Ob7aiPmVQOSyE0OfP9AJiHcezPt7mw26tltJN/sV/FTY Q9KXKDnMiw93aFzVxvuLYA0tBH/iauYyfZ8X2ZSUBi98MPtrx2RjWhHQ/ULYamBXSqIv rx/W+2iYairx5NVICa9cnGD5uQKGnldjVtlyB8MSbDWXyi0B9KQmMMU9oTvyQROGADFH 6M1rWukBEzSbx7Ip+7EyPMrVLd6aE/JqlIV0Wy+WJYSP+v8MJoeRogFgvzN7iN+IBwF3 Wjl4XGAZkKzXe6lzxS5KWqgqZ4wG2eQ1ZPr6KLP1KsrtoPPYPQt+eKyRmTL5K/+BEs2o Wsnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706024068; x=1706628868; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TlhyzNjFt8B4egY8fYl+NmfB3SAkzLPxUZ0BvmIG80I=; b=IfQvGBM2e+ZgL4oUmRps4niJu0sMlQefEa0NwOok4AD2UzX01BB1gK0A/MuCvfOdDO /ngJ6eXouRdr0nzc8SfWtA7kt26SQvaZuj99tNUJfD3GeIFReE+o15A4mnDyIgBMQmUI mQo3tsiRVptVbReyT1wRlMH5R8Y3CkuV60bEItQMKdhaZw8Mj6EVelVlUiFlX+aDP76i 56zrqYVSD35ua+cHQ1/rSLYVkFGR3niOalzbWOYs1fSRHYPgbSWjjaTcbk7ThKOH5opb zsGBF27agacuvbKyYO5FdDYWcLRHLti5Vz/jEP1Oi7Gtn2EIABjm+8nH6u+7MSCrxKhV jfPw== X-Gm-Message-State: AOJu0Yxrhj3K1Nx00wh5JVIABTR2xlR74sTTGa7pZhiZk4b2r3N1tODQ +DtA/mzXhyMi2XzU3XDC27WV1hk0NqT0yuYm6Ua9woDDEchB7FZzcr1Oove5Xa8= X-Google-Smtp-Source: AGHT+IFZYGuih+06B7G1t7JNngFPHTbZIv3BFvbVmmj7HCjRI+QxjvRyDu/w8RFd1+v88GBtB6rn1w== X-Received: by 2002:a05:600c:1f81:b0:40e:a7f0:a0f8 with SMTP id je1-20020a05600c1f8100b0040ea7f0a0f8mr286487wmb.33.1706024067797; Tue, 23 Jan 2024 07:34:27 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. 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Signed-off-by: Tudor Ambarus Reviewed-by: Sam Protsenko Reviewed-by: Andi Shyti --- drivers/spi/spi-s3c64xx.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 187b617e3e14..26d389d95af9 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -16,7 +16,6 @@ #include #include - #define MAX_SPI_PORTS 12 #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) #define AUTOSUSPEND_TIMEOUT 2000 From patchwork Tue Jan 23 15:34:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13527672 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F12915FF1D for ; Tue, 23 Jan 2024 15:34:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024072; cv=none; b=BlXTE1V77e6VAl6iK7Oj82h6FjqtDpZSdM0bOgZyGq31rWE1mBSuRdpCVLZFdOYxlj7HaDcWQu4FMrw3nCzIDZE1phJ5LCave99pECjRuZunUC2rg5eVGHcYKn4A8fhuaAUmwi8J5ViMiQnImgDh6AA2j4MBaeSRZvb7fA5dvMQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024072; c=relaxed/simple; bh=TH1sVFAhrdGV6Yp4bPleYA0ox21IwTqCKXRbqk0AOdM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=K8Hk+VScnSO7XWE2u01RBwFfzvESV6dLmn68LG3uIG7UWaDyLyoAwwv7FQYxRQBu9OEsww93s1THFoScry2C2d1jy/ZREN1vXH9KbVJVHS/WW8luQP3Ii0HhFKQc+aeuGYsv3RwqBRiYlkvrZpbSpciIkXwqM6cKL53xcn7Wjcs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=JDA/xbR6; arc=none smtp.client-ip=209.85.128.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="JDA/xbR6" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-40e5afc18f5so48814265e9.3 for ; Tue, 23 Jan 2024 07:34:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706024068; x=1706628868; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GYolP7qSHiJsNw4Rdgmh202yjvtbAUk4vGAE3cDed4M=; b=JDA/xbR6KvLA8/Z/tWfYjY0wQ7l6LqEZy1svkdh5EQtmC3adowT1kpanGtenap66O+ JtD+9BCDAF6MU2Avl60gOLNVZYIRMnLdzShy18Y0w3oeLBYDGhuj0enDxtfUOgaln8QZ 6uD6assl1guwiG1Ek2XDn+XMRDlgRMR2iF4gERgajaL11C0ZSsY0o3V7rLU58HXqbkEN 2Jl6tcJlMM6cWnmamSCKQpfJqu5qPyMtZ5ItMGBDiu/bwy/kcGhBUXyzqb7ZVXndv92B hxrNfQvXxf/8h+CyzFMFZ71E0iyeqLv1Th0n4o4w5r1JUaK7LCAvx/yFxDOb26741yE4 8b8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706024068; x=1706628868; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GYolP7qSHiJsNw4Rdgmh202yjvtbAUk4vGAE3cDed4M=; b=h+vob6V3/j1tgopDA11kk7r3fcP5on5whVTADZu4qZYOjVnfNUkEAviycIHDOcYedS 52rCp/zVj0BlbQKbBbUVpFiNxJ6GwY+lZGZpNnqMIfUi9LOSGXO9Q0NVnfm1dZxafGV9 Tcchq9gvvixk+NpIk/HJ3FABJcwIhHKb4DeSR/NGjwU/2lfFFPXSsojLws7x0x5mNbAS 0F1Z06nrgY9aDOKzZhEMDt/2XLiMslAKXlbnOkr4xLF1KqeSgAJKovHQpYG/7BGz88c/ yyoi0DjzqvsAad1pMm/KQcP1Wj3FIO9F59Kgxmx8SraGcBieLAi1XU2DvUTZn48pgtl5 a3+w== X-Gm-Message-State: AOJu0YwzP78q89cUn0l4EEV0yE4709y79P4lTNglrHwjy6fsuTKfGI0q QTPGT1JEnJFr9/GBgARS4j+/JPaMpANTweLRDwcYIOgWpdHHKYFCgo1Y1riCC+8= X-Google-Smtp-Source: AGHT+IHWuxpxzMg8g8EGj2cXNPfD+1g/XO+XPmUi/g8fAIxbN4ApYg+KOHjM4WPsFejLGkzpu2Gcog== X-Received: by 2002:a05:600c:2d16:b0:40e:5571:2c6f with SMTP id x22-20020a05600c2d1600b0040e55712c6fmr254080wmf.67.1706024068416; Tue, 23 Jan 2024 07:34:28 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id p21-20020a05600c359500b0040e3488f16dsm42457536wmq.12.2024.01.23.07.34.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 07:34:28 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH 04/21] spi: s3c64xx: remove unneeded (void *) casts in of_match_table Date: Tue, 23 Jan 2024 15:34:03 +0000 Message-ID: <20240123153421.715951-5-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240123153421.715951-1-tudor.ambarus@linaro.org> References: <20240123153421.715951-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 of_device_id::data is an opaque pointer. No explicit cast is needed. Remove unneeded (void *) casts in of_match_table. While here align the compatible and data members. Signed-off-by: Tudor Ambarus Reviewed-by: Andi Shyti --- drivers/spi/spi-s3c64xx.c | 40 +++++++++++++++++++++++---------------- 1 file changed, 24 insertions(+), 16 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 26d389d95af9..b350e70fd179 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1495,29 +1495,37 @@ static const struct platform_device_id s3c64xx_spi_driver_ids[] = { }; static const struct of_device_id s3c64xx_spi_dt_match[] = { - { .compatible = "samsung,s3c2443-spi", - .data = (void *)&s3c2443_spi_port_config, + { + .compatible = "samsung,s3c2443-spi", + .data = &s3c2443_spi_port_config, }, - { .compatible = "samsung,s3c6410-spi", - .data = (void *)&s3c6410_spi_port_config, + { + .compatible = "samsung,s3c6410-spi", + .data = &s3c6410_spi_port_config, }, - { .compatible = "samsung,s5pv210-spi", - .data = (void *)&s5pv210_spi_port_config, + { + .compatible = "samsung,s5pv210-spi", + .data = &s5pv210_spi_port_config, }, - { .compatible = "samsung,exynos4210-spi", - .data = (void *)&exynos4_spi_port_config, + { + .compatible = "samsung,exynos4210-spi", + .data = &exynos4_spi_port_config, }, - { .compatible = "samsung,exynos7-spi", - .data = (void *)&exynos7_spi_port_config, + { + .compatible = "samsung,exynos7-spi", + .data = &exynos7_spi_port_config, }, - { .compatible = "samsung,exynos5433-spi", - .data = (void *)&exynos5433_spi_port_config, + { + .compatible = "samsung,exynos5433-spi", + .data = &exynos5433_spi_port_config, }, - { .compatible = "samsung,exynosautov9-spi", - .data = (void *)&exynosautov9_spi_port_config, + { + .compatible = "samsung,exynosautov9-spi", + .data = &exynosautov9_spi_port_config, }, - { .compatible = "tesla,fsd-spi", - .data = (void *)&fsd_spi_port_config, + { + .compatible = "tesla,fsd-spi", + .data = &fsd_spi_port_config, }, { }, }; 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id p21-20020a05600c359500b0040e3488f16dsm42457536wmq.12.2024.01.23.07.34.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 07:34:28 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH 05/21] spi: s3c64xx: explicitly include Date: Tue, 23 Jan 2024 15:34:04 +0000 Message-ID: <20240123153421.715951-6-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240123153421.715951-1-tudor.ambarus@linaro.org> References: <20240123153421.715951-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The driver uses GENMASK() but does not include . Include the missing header, we shall aim to have the drivers self contained. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index b350e70fd179..9ce56aa792ed 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -3,6 +3,7 @@ // Copyright (c) 2009 Samsung Electronics Co., Ltd. // Jaswinder Singh +#include #include #include #include From patchwork Tue Jan 23 15:34:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13527674 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47610604B7 for ; Tue, 23 Jan 2024 15:34:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024074; cv=none; b=qRxu1isszKLMPoa+18gNUSRKYxVLCwphXT6qX5Wqhhc9GJalMCV4DGSWu3gE8L8shmuqTDx4G5fPijrClr7442nBpJtjtqLjmF1X57UYrjUhLajERyyqQvFmmh1MyfQHm9WFNcmJ9tSb/tyV6rf++t4pNXzOOKeISgP2sIeC8Ro= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024074; c=relaxed/simple; bh=GYq0ktoBx5eIoBEt2IxaK7Hm43PmKkluplSV8nDXwcE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ms/heSq7eTlPwLU1QelLCWf3buFb2cp9PJF9tjDktSPgp562L5T00+KZCZrJnYJ3rsjGeGcQ6DB3/FD5q4XnIjo2UYdUM0xhGYYcXUwjgw6Cca2s5sHEmCNszB6u26L+DJ8twahTcczoSclHstxfnmKuXEl3TQo4bcJXmxjYDA0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=i4ivwGI7; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="i4ivwGI7" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-40e800461baso53221975e9.3 for ; Tue, 23 Jan 2024 07:34:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706024070; x=1706628870; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RUhqsvib/uXsB8/ZG1ztFE4b7a6LgsyBrst5iQF/X8M=; b=i4ivwGI7zKVr1oTIleGQIJnnF1kdVhXVV/rkyReyZhIQukxApgt3GNfs4V0UO9scKA +vPl5R7cW+wPzMkrww5KU0NOZNR4nVDBeNvKywezW/ZAoDqWqdjewE44sQiWaph8kkzv GyFg/YGsUAxFTxyg2pw9KlKWYnegzpyDto9Fvk6AxwJ6PgQSNY/UEsHtzs+NdvfQehTE dEcdSr/Jii59uml0+n8iAkKLfBYA0+o6Yk3Q1PdrKkj8+wCSYjxOJ7SBwaAg7EYnj6uX S7G07WcLGHQaa4WdtD7rsx5hxCldV3pc1WyHDCGxgJYZ56oPFOjdxp3zOWoWPwxUwxf2 dBXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706024070; x=1706628870; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RUhqsvib/uXsB8/ZG1ztFE4b7a6LgsyBrst5iQF/X8M=; b=ekBcmqsw2BGZ0WvFhEYkFv+YeFPZ1+5VytsozN1vNIKhnH33+DoYHD9OkHN8QYsQ8Q izYBMDURJ3UqnIPePXCjzt20tBQjpL6aMTl5JzUf+0fKHvV/Xwv/YBXVlNXbthfzq9ic iG8wEFCqpRm6Im37+OX3BOtDheJuFNEAeZyQ1q0S7z+RIjdMhy9pgDStXUqapBGRDBy5 aLC+prpL6nK/j/aU9kNPMynbNuP1+oEIgoLRc3DWsRtSfdiFhW6E9Jr8/omIExkZHqhl JzxooIF06IYMyfIS0B0RKhe7DiGVqZ/K7xU3RLPNKM397TgZTPnb0Zzq3/oNx9UHIg5b RXfw== X-Gm-Message-State: AOJu0YzSp/22QBirET2joxjcd8T6YKVURh2MEDyFzIemxw11Ljc3GOlu E4LWyBKZ9jvNs06uyilHv4Kz4HViIVa/9Oahv3piovUDG5j690vtSB9hWAJQh7g= X-Google-Smtp-Source: AGHT+IEUQRFIekgMzpx0cR8sCCVG3w5xgk2OePoUsW4Y1C3evA/H4sd/SqXvBEWXjsocAfm8duQg6A== X-Received: by 2002:a05:600c:1f8e:b0:40e:50c6:3b88 with SMTP id je14-20020a05600c1f8e00b0040e50c63b88mr370700wmb.142.1706024070623; Tue, 23 Jan 2024 07:34:30 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id p21-20020a05600c359500b0040e3488f16dsm42457536wmq.12.2024.01.23.07.34.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 07:34:29 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH 06/21] spi: s3c64xx: remove else after return Date: Tue, 23 Jan 2024 15:34:05 +0000 Message-ID: <20240123153421.715951-7-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240123153421.715951-1-tudor.ambarus@linaro.org> References: <20240123153421.715951-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Else case is not needed after a return, remove it. Signed-off-by: Tudor Ambarus Reviewed-by: Sam Protsenko Reviewed-by: Andi Shyti --- drivers/spi/spi-s3c64xx.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 9ce56aa792ed..db1e1d6ee732 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -406,12 +406,10 @@ static bool s3c64xx_spi_can_dma(struct spi_controller *host, { struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); - if (sdd->rx_dma.ch && sdd->tx_dma.ch) { + if (sdd->rx_dma.ch && sdd->tx_dma.ch) return xfer->len > FIFO_DEPTH(sdd); - } else { - return false; - } + return false; } static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, From patchwork Tue Jan 23 15:34:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13527675 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60EFD60261 for ; Tue, 23 Jan 2024 15:34:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024076; cv=none; b=Qsu0O7zZbthEvFF/F6Vo+Xi2afxpQzDWo8C18M3qYoMieqnAlgy3DNKOYmSNjXIq0hREYhRrfv68/weA4Vfp3SwqYYwcs3FZlvoavNLSi7V177ow3Zb2vG3cO9Tka8MTIfLXSNG929XrfFGdY/l2LZ0qHSdKpn37RoOzuTGXgEI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024076; c=relaxed/simple; bh=eNztj8TcyTgv1CSN254XQrBbZBMIjnXnj81xPzvJpqA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kv9BVQ9euLmd7cFOwmC7RkT2UsLhYiY9KeOmPqOCeXoATQP1Lbe18ZpRpquPmdUAsjTpN8grW8rgOdnZWlwgeeoKCDXW1W10OoJ083tUXPW8sdbfN9BYH5wiTmZRWAC7tAhqxwWpF1UqJ8+3ke2aTYtXZTu4t+ErtqLO1llq+RE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=VmOXjpHI; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="VmOXjpHI" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-40eb2f392f0so12141305e9.1 for ; Tue, 23 Jan 2024 07:34:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706024071; x=1706628871; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TOeaP+uQvqY+z2mWaYRhy1CLD5dZOaOwjcdl9nFCka0=; b=VmOXjpHIyPfLuexvCWMSBTGyl5mbVvLAnXbiW7Q0fOijVsEzCEhBhhQhr9/u7/SsQL H3fxfA335RBQ+jhOsC2LFT4XVZ5DUT25jCUnHILzu+Zwl8EhBYsfND9WnEY7ROWPcKur poqXVMVrqdW272y4sXoqQm8C4ZxtWfLYvkxBBo1iawE5m7o0oxNxswvCnsklHvdmZH+3 voS5ItMUZl1G6IxaVYtaALQ/Yk/pa2ftnDOu6FO98VGI9lp/8scfmAWQBZkYDchEZhsO HoOA15O7tdZXxDpIyRP76MGfUG8BTPx4bKkLrSO/axrxk1eE0xp9GIofX4g62VArLHGy QndA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706024071; x=1706628871; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TOeaP+uQvqY+z2mWaYRhy1CLD5dZOaOwjcdl9nFCka0=; b=ZC04T4/xB/WjKmp3a/pkZoDOAqnkoV4fClL+KAoyM4GYDhkxNp+ixaf7B6iv9GF+ix stz0/2Vpk8aprwO9KDDx4+ziLkZ09ejMMQ7XuPHlX6M002vbUyJMRy5dhwS/ukt6hf/9 Jj3vqfpYYNfDhYDWPervnzLVA0LhXeFztVDYMz4+RFq9oZH7ktr63IeS1EUOoO0MJGQX NXZYqUMDzqGOrEiYzvSS3Ug7syMyaG2Lt+UnglXmuefnMsC4juctVYucDl07b081gDkx N2XVws7e4w+FE5qLbug3FImXe5g+g8u35L4/Q2soBPIOZn+XfAUcoLdG+ONvxAV62MS/ t1jw== X-Gm-Message-State: AOJu0Yz0iW4E02VbXDplSbosfiKfqwD8voi1GhRCqN2Npd+uEHvezE1+ b9p6avOTeNH93ZT5wtX3tnyyOW8urz6MNbJxbu/zim7ARTYGTdK/PsrJu6alZFo= X-Google-Smtp-Source: AGHT+IGkWbV55/MmrTK57oh/po/OTjbqpTK3Dx13U0dgMMaMNXEqC0k6UPb8hTivxpsDPwAhpDNUeQ== X-Received: by 2002:a05:600c:538e:b0:40e:6d7a:f9dd with SMTP id hg14-20020a05600c538e00b0040e6d7af9ddmr275420wmb.47.1706024071685; Tue, 23 Jan 2024 07:34:31 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id p21-20020a05600c359500b0040e3488f16dsm42457536wmq.12.2024.01.23.07.34.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 07:34:30 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH 07/21] spi: s3c64xx: use bitfield access macros Date: Tue, 23 Jan 2024 15:34:06 +0000 Message-ID: <20240123153421.715951-8-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240123153421.715951-1-tudor.ambarus@linaro.org> References: <20240123153421.715951-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use the bitfield access macros in order to clean and to make the driver easier to read. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 196 +++++++++++++++++++------------------- 1 file changed, 99 insertions(+), 97 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index db1e1d6ee732..16eea56892a2 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -4,6 +4,7 @@ // Jaswinder Singh #include +#include #include #include #include @@ -17,91 +18,91 @@ #include #include -#define MAX_SPI_PORTS 12 -#define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) -#define AUTOSUSPEND_TIMEOUT 2000 +#define MAX_SPI_PORTS 12 +#define S3C64XX_SPI_QUIRK_CS_AUTO BIT(1) +#define AUTOSUSPEND_TIMEOUT 2000 /* Registers and bit-fields */ -#define S3C64XX_SPI_CH_CFG 0x00 -#define S3C64XX_SPI_CLK_CFG 0x04 -#define S3C64XX_SPI_MODE_CFG 0x08 -#define S3C64XX_SPI_CS_REG 0x0C -#define S3C64XX_SPI_INT_EN 0x10 -#define S3C64XX_SPI_STATUS 0x14 -#define S3C64XX_SPI_TX_DATA 0x18 -#define S3C64XX_SPI_RX_DATA 0x1C -#define S3C64XX_SPI_PACKET_CNT 0x20 -#define S3C64XX_SPI_PENDING_CLR 0x24 -#define S3C64XX_SPI_SWAP_CFG 0x28 -#define S3C64XX_SPI_FB_CLK 0x2C - -#define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ -#define S3C64XX_SPI_CH_SW_RST (1<<5) -#define S3C64XX_SPI_CH_SLAVE (1<<4) -#define S3C64XX_SPI_CPOL_L (1<<3) -#define S3C64XX_SPI_CPHA_B (1<<2) -#define S3C64XX_SPI_CH_RXCH_ON (1<<1) -#define S3C64XX_SPI_CH_TXCH_ON (1<<0) - -#define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) -#define S3C64XX_SPI_CLKSEL_SRCSHFT 9 -#define S3C64XX_SPI_ENCLK_ENABLE (1<<8) -#define S3C64XX_SPI_PSR_MASK 0xff - -#define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) -#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) -#define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) -#define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) -#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) -#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) -#define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) -#define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) +#define S3C64XX_SPI_CH_CFG 0x00 +#define S3C64XX_SPI_CLK_CFG 0x04 +#define S3C64XX_SPI_MODE_CFG 0x08 +#define S3C64XX_SPI_CS_REG 0x0C +#define S3C64XX_SPI_INT_EN 0x10 +#define S3C64XX_SPI_STATUS 0x14 +#define S3C64XX_SPI_TX_DATA 0x18 +#define S3C64XX_SPI_RX_DATA 0x1C +#define S3C64XX_SPI_PACKET_CNT 0x20 +#define S3C64XX_SPI_PENDING_CLR 0x24 +#define S3C64XX_SPI_SWAP_CFG 0x28 +#define S3C64XX_SPI_FB_CLK 0x2C + +#define S3C64XX_SPI_CH_HS_EN BIT(6) /* High Speed Enable */ +#define S3C64XX_SPI_CH_SW_RST BIT(5) +#define S3C64XX_SPI_CH_SLAVE BIT(4) +#define S3C64XX_SPI_CPOL_L BIT(3) +#define S3C64XX_SPI_CPHA_B BIT(2) +#define S3C64XX_SPI_CH_RXCH_ON BIT(1) +#define S3C64XX_SPI_CH_TXCH_ON BIT(0) + +#define S3C64XX_SPI_CLKSEL_SRCMSK GENMASK(10, 9) +#define S3C64XX_SPI_ENCLK_ENABLE BIT(8) +#define S3C64XX_SPI_PSR_MASK GENMASK(15, 0) + +#define S3C64XX_SPI_MODE_CH_TSZ_MASK GENMASK(30, 29) +#define S3C64XX_SPI_MODE_CH_TSZ_BYTE 0 +#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD 1 +#define S3C64XX_SPI_MODE_CH_TSZ_WORD 2 +#define S3C64XX_SPI_MAX_TRAILCNT_MASK GENMASK(28, 19) +#define S3C64XX_SPI_MODE_BUS_TSZ_MASK GENMASK(18, 17) +#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE 0 +#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD 1 +#define S3C64XX_SPI_MODE_BUS_TSZ_WORD 2 #define S3C64XX_SPI_MODE_RX_RDY_LVL GENMASK(16, 11) -#define S3C64XX_SPI_MODE_RX_RDY_LVL_SHIFT 11 -#define S3C64XX_SPI_MODE_SELF_LOOPBACK (1<<3) -#define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) -#define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) -#define S3C64XX_SPI_MODE_4BURST (1<<0) - -#define S3C64XX_SPI_CS_NSC_CNT_2 (2<<4) -#define S3C64XX_SPI_CS_AUTO (1<<1) -#define S3C64XX_SPI_CS_SIG_INACT (1<<0) - -#define S3C64XX_SPI_INT_TRAILING_EN (1<<6) -#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) -#define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) -#define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) -#define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) -#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) -#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) - -#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) -#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) -#define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) -#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) -#define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) -#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) - -#define S3C64XX_SPI_PACKET_CNT_EN (1<<16) +#define S3C64XX_SPI_MODE_SELF_LOOPBACK BIT(3) +#define S3C64XX_SPI_MODE_RXDMA_ON BIT(2) +#define S3C64XX_SPI_MODE_TXDMA_ON BIT(1) +#define S3C64XX_SPI_MODE_4BURST BIT(0) + +#define S3C64XX_SPI_CS_NSC_CNT_MASK GENMASK(9, 4) +#define S3C64XX_SPI_CS_NSC_CNT_2 2 +#define S3C64XX_SPI_CS_AUTO BIT(1) +#define S3C64XX_SPI_CS_SIG_INACT BIT(0) + +#define S3C64XX_SPI_INT_TRAILING_EN BIT(6) +#define S3C64XX_SPI_INT_RX_OVERRUN_EN BIT(5) +#define S3C64XX_SPI_INT_RX_UNDERRUN_EN BIT(4) +#define S3C64XX_SPI_INT_TX_OVERRUN_EN BIT(3) +#define S3C64XX_SPI_INT_TX_UNDERRUN_EN BIT(2) +#define S3C64XX_SPI_INT_RX_FIFORDY_EN BIT(1) +#define S3C64XX_SPI_INT_TX_FIFORDY_EN BIT(0) + +#define S3C64XX_SPI_ST_RX_OVERRUN_ERR BIT(5) +#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR BIT(4) +#define S3C64XX_SPI_ST_TX_OVERRUN_ERR BIT(3) +#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR BIT(2) +#define S3C64XX_SPI_ST_RX_FIFORDY BIT(1) +#define S3C64XX_SPI_ST_TX_FIFORDY BIT(0) + +#define S3C64XX_SPI_PACKET_CNT_EN BIT(16) #define S3C64XX_SPI_PACKET_CNT_MASK GENMASK(15, 0) -#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) -#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) -#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) -#define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) -#define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) +#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR BIT(4) +#define S3C64XX_SPI_PND_TX_OVERRUN_CLR BIT(3) +#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR BIT(2) +#define S3C64XX_SPI_PND_RX_OVERRUN_CLR BIT(1) +#define S3C64XX_SPI_PND_TRAILING_CLR BIT(0) -#define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) -#define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) -#define S3C64XX_SPI_SWAP_RX_BIT (1<<5) -#define S3C64XX_SPI_SWAP_RX_EN (1<<4) -#define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) -#define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) -#define S3C64XX_SPI_SWAP_TX_BIT (1<<1) -#define S3C64XX_SPI_SWAP_TX_EN (1<<0) +#define S3C64XX_SPI_SWAP_RX_HALF_WORD BIT(7) +#define S3C64XX_SPI_SWAP_RX_BYTE BIT(6) +#define S3C64XX_SPI_SWAP_RX_BIT BIT(5) +#define S3C64XX_SPI_SWAP_RX_EN BIT(4) +#define S3C64XX_SPI_SWAP_TX_HALF_WORD BIT(3) +#define S3C64XX_SPI_SWAP_TX_BYTE BIT(2) +#define S3C64XX_SPI_SWAP_TX_BIT BIT(1) +#define S3C64XX_SPI_SWAP_TX_EN BIT(0) -#define S3C64XX_SPI_FBCLK_MSK (3<<0) +#define S3C64XX_SPI_FBCLK_MASK GENMASK(1, 0) #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ @@ -111,18 +112,13 @@ FIFO_LVL_MASK(i)) #define FIFO_DEPTH(i) ((FIFO_LVL_MASK(i) >> 1) + 1) -#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff -#define S3C64XX_SPI_TRAILCNT_OFF 19 - -#define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT - #define S3C64XX_SPI_POLLING_SIZE 32 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) #define is_polling(x) (x->cntrlr_info->polling) -#define RXBUSY (1<<2) -#define TXBUSY (1<<3) +#define RXBUSY BIT(2) +#define TXBUSY BIT(3) struct s3c64xx_spi_dma_data { struct dma_chan *ch; @@ -341,8 +337,9 @@ static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable) } else { u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG); - ssel |= (S3C64XX_SPI_CS_AUTO | - S3C64XX_SPI_CS_NSC_CNT_2); + ssel |= S3C64XX_SPI_CS_AUTO | + FIELD_PREP(S3C64XX_SPI_CS_NSC_CNT_MASK, + S3C64XX_SPI_CS_NSC_CNT_2); writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG); } } else { @@ -665,16 +662,22 @@ static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) switch (sdd->cur_bpw) { case 32: - val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; - val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; + val |= FIELD_PREP(S3C64XX_SPI_MODE_BUS_TSZ_MASK, + S3C64XX_SPI_MODE_BUS_TSZ_WORD) | + FIELD_PREP(S3C64XX_SPI_MODE_CH_TSZ_MASK, + S3C64XX_SPI_MODE_CH_TSZ_WORD); break; case 16: - val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; - val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; + val |= FIELD_PREP(S3C64XX_SPI_MODE_BUS_TSZ_MASK, + S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD) | + FIELD_PREP(S3C64XX_SPI_MODE_CH_TSZ_MASK, + S3C64XX_SPI_MODE_CH_TSZ_HALFWORD); break; default: - val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; - val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; + val |= FIELD_PREP(S3C64XX_SPI_MODE_BUS_TSZ_MASK, + S3C64XX_SPI_MODE_BUS_TSZ_BYTE) | + FIELD_PREP(S3C64XX_SPI_MODE_CH_TSZ_MASK, + S3C64XX_SPI_MODE_CH_TSZ_BYTE); break; } @@ -800,7 +803,7 @@ static int s3c64xx_spi_transfer_one(struct spi_controller *host, val = readl(sdd->regs + S3C64XX_SPI_MODE_CFG); val &= ~S3C64XX_SPI_MODE_RX_RDY_LVL; - val |= (rdy_lv << S3C64XX_SPI_MODE_RX_RDY_LVL_SHIFT); + val |= FIELD_PREP(S3C64XX_SPI_MODE_RX_RDY_LVL, rdy_lv); writel(val, sdd->regs + S3C64XX_SPI_MODE_CFG); /* Enable FIFO_RDY_EN IRQ */ @@ -1073,8 +1076,8 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd) writel(0, regs + S3C64XX_SPI_INT_EN); if (!sdd->port_conf->clk_from_cmu) - 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id p21-20020a05600c359500b0040e3488f16dsm42457536wmq.12.2024.01.23.07.34.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 07:34:32 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH 08/21] spi: s3c64xx: move error check up to avoid rechecking Date: Tue, 23 Jan 2024 15:34:07 +0000 Message-ID: <20240123153421.715951-9-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240123153421.715951-1-tudor.ambarus@linaro.org> References: <20240123153421.715951-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Check the return value of wait_for_completion_timeout() immediately after the call so that we avoid checking the return value twice. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 16eea56892a2..128c3b8211ce 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -519,17 +519,17 @@ static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, val = msecs_to_jiffies(ms) + 10; val = wait_for_completion_timeout(&sdd->xfer_completion, val); - + if (!val) + return -EIO; /* - * If the previous xfer was completed within timeout, then - * proceed further else return -EIO. + * If the previous xfer was completed within timeout proceed further. * DmaTx returns after simply writing data in the FIFO, * w/o waiting for real transmission on the bus to finish. * DmaRx returns only after Dma read data from FIFO which * needs bus transmission to finish, so we don't worry if * Xfer involved Rx(with or without Tx). */ - if (val && !xfer->rx_buf) { + if (!xfer->rx_buf) { val = msecs_to_loops(10); status = readl(regs + S3C64XX_SPI_STATUS); while ((TX_FIFO_LVL(status, sdd) @@ -538,13 +538,8 @@ static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, cpu_relax(); status = readl(regs + S3C64XX_SPI_STATUS); } - } - /* If timed out while checking rx/tx status return error */ - if (!val) - return -EIO; - return 0; } From patchwork Tue Jan 23 15:34:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13527677 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C8DC60884 for ; Tue, 23 Jan 2024 15:34:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024078; cv=none; b=HPOK3JSo/IGs0mPb3h6F770gyDROOF13XZd7KWbAt6ykDKNapWDIbI/jSOWQ0zw3sD+dXQqH7qZCaJF1YxMXQjfrW0sxQuT6zUZLLvNy7mJx5kGgQYGuU4FChYZ7Q3toYLP723uHMyHmifwS98jv/k3gRRrUkQNj3kg81nC7Rvw= ARC-Message-Signature: i=1; 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id p21-20020a05600c359500b0040e3488f16dsm42457536wmq.12.2024.01.23.07.34.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 07:34:32 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH 09/21] spi: s3c64xx: use full mask for {RX, TX}_FIFO_LVL Date: Tue, 23 Jan 2024 15:34:08 +0000 Message-ID: <20240123153421.715951-10-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240123153421.715951-1-tudor.ambarus@linaro.org> References: <20240123153421.715951-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 SPI_STATUSn.{RX, TX}_FIFO_LVL fields show the data level in the RX and TX FIFOs. The IP supports FIFOs from 8 to 256 bytes, but apart from the MODE_CFG.{RX, TX}_RDY_LVL fields that configure the {RX, TX} FIFO trigger level in the interrupt mode, there's nothing in the registers that configure the FIFOs depth. Is the responsibility of the SoC that integrates the IP to dictate the FIFO depth and of the SPI driver to make sure it doesn't bypass the FIFO length. {RX, TX}_FIFO_LVL was used to pass the FIFO length information based on the IP configuration in the SoC. Its value was defined so that it includes the entire FIFO length. For example, if one wanted to specify a 64 FIFO length (0x40), it wold configure the FIFO level to 127 (0x7f). This is not only wrong, because it doesn't respect the IP's register fields, it's also misleading. Use the full mask for the SPI_STATUSn.{RX, TX}_FIFO_LVL fields. No change in functionality is expected. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 128c3b8211ce..a06b83b952c6 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -77,6 +77,8 @@ #define S3C64XX_SPI_INT_RX_FIFORDY_EN BIT(1) #define S3C64XX_SPI_INT_TX_FIFORDY_EN BIT(0) +#define S3C64XX_SPI_ST_RX_FIFO_LVL GENMASK(23, 15) +#define S3C64XX_SPI_ST_TX_FIFO_LVL GENMASK(14, 6) #define S3C64XX_SPI_ST_RX_OVERRUN_ERR BIT(5) #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR BIT(4) #define S3C64XX_SPI_ST_TX_OVERRUN_ERR BIT(3) @@ -107,9 +109,6 @@ #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) -#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) -#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ - FIFO_LVL_MASK(i)) #define FIFO_DEPTH(i) ((FIFO_LVL_MASK(i) >> 1) + 1) #define S3C64XX_SPI_POLLING_SIZE 32 @@ -218,7 +217,7 @@ static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd) loops = msecs_to_loops(1); do { val = readl(regs + S3C64XX_SPI_STATUS); - } while (TX_FIFO_LVL(val, sdd) && loops--); + } while (FIELD_GET(S3C64XX_SPI_ST_TX_FIFO_LVL, val) && loops--); if (loops == 0) dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); @@ -227,7 +226,7 @@ static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd) loops = msecs_to_loops(1); do { val = readl(regs + S3C64XX_SPI_STATUS); - if (RX_FIFO_LVL(val, sdd)) + if (FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, val)) readl(regs + S3C64XX_SPI_RX_DATA); else break; @@ -498,10 +497,11 @@ static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, do { status = readl(regs + S3C64XX_SPI_STATUS); - } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); + } while (FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, status) < max_fifo && + --val); /* return the actual received data length */ - return RX_FIFO_LVL(status, sdd); + return FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, status); } static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, @@ -532,7 +532,7 @@ static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, if (!xfer->rx_buf) { val = msecs_to_loops(10); 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id p21-20020a05600c359500b0040e3488f16dsm42457536wmq.12.2024.01.23.07.34.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 07:34:33 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH 10/21] spi: s3c64xx: move common code outside if else Date: Tue, 23 Jan 2024 15:34:09 +0000 Message-ID: <20240123153421.715951-11-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240123153421.715951-1-tudor.ambarus@linaro.org> References: <20240123153421.715951-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Move common code outside if else to avoid code duplication. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index a06b83b952c6..4b13252da8b8 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -285,20 +285,18 @@ static int prepare_dma(struct s3c64xx_spi_dma_data *dma, if (dma->direction == DMA_DEV_TO_MEM) { sdd = container_of((void *)dma, struct s3c64xx_spi_driver_data, rx_dma); - config.direction = dma->direction; config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; config.src_addr_width = sdd->cur_bpw / 8; config.src_maxburst = 1; - dmaengine_slave_config(dma->ch, &config); } else { sdd = container_of((void *)dma, struct s3c64xx_spi_driver_data, tx_dma); - config.direction = dma->direction; config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; config.dst_addr_width = sdd->cur_bpw / 8; config.dst_maxburst = 1; - dmaengine_slave_config(dma->ch, &config); } + config.direction = dma->direction; + dmaengine_slave_config(dma->ch, &config); desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, dma->direction, DMA_PREP_INTERRUPT); From patchwork Tue Jan 23 15:34:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13527679 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A54860BB8 for ; Tue, 23 Jan 2024 15:34:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024080; cv=none; b=bjrsdOu+0sy3BdrMjLmJVJvvjiFgx/m+a5tdyrxEblfnhnMNzrKCHrAHOVAQHGikupPtHK6HJW23JJo+gk/CFB47QsAnLO835/f/d2SwTaUmW6DCgm2YqOSpQU/AiQ7cRJN2LyqxgLlpKsI6/Q9k58JLmrVvwNYPAIdSLcsB+nA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024080; c=relaxed/simple; bh=ABSBo8ChnyWfSDmKV7SkQrHMoHBUlI2Sroam7dwUzCg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YdfxBu6LwUhNqccq59oda1K/W1tfIJUn+lBh5hJxfmh0rdx/yT2egzRTPcPp7g9s4Afdma13vidtIJh12Z4gg4aNNJ4OKb8SpwAI8CcnUrHapw9wZQuDsq2W1n1BLNpmLPb+v/kYHQYKSqVdRyJXMfrSyaihApbJIvmjiXIRTP0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=ioSmhcqz; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ioSmhcqz" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-40eb0836f8dso17924675e9.2 for ; Tue, 23 Jan 2024 07:34:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706024075; x=1706628875; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BB2Xa0B54slaxQ4TFzJZkt9rUGgpa6L4k5N0BA4Wago=; b=ioSmhcqzk9xBOnliJ7fe26EMcL/uk3BWE065odkQ3uhog+Hdo+usdhF6y+om+3azGz 8ghhpKTmxwmwXkFR7D2YMYeg2+zJI6O3Ku+8PAQIgqsXuAe4YKV126pqFHCzAr9ettA4 aiO+PVbRxZzFd2Arip+1QZcw1gpI/TJOk+wmoSFpKKAnCriPuts+P+TeKxfQtb9/HEBC i1nBcLeHA3BFpsoFgK9wKMDdRMz7/wt1AAElxC5dpebnVsg/qS3S+7u2NsVmd8lGguvn ZLAT/RrOqe03noggtPYV2klFHpdn/ISZRQbmsy7OIy+O/ZjcsOtaTPes70WOByUPBHth 2Ztw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706024075; x=1706628875; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BB2Xa0B54slaxQ4TFzJZkt9rUGgpa6L4k5N0BA4Wago=; b=N+xhzz8C1zwx9CWQdUtdB9M6DjChE01cd5njnkNyTZEMb2ZvsmIgEEQE4NJHWD9AjN CD9vVt4gkatYWzC/yJW1JXDEwbHItPdA/XZ7gcOCvbhmGFDVyXdB5ter+5XpUZSZNxST Gka5aJ2eg0UqwZUSf/oFBdxiJLImIJYf78d+QaQS9rOmp70dGWV9KOAqxHu3tlgLzA/r jSTVVSzjyVGC2VE0AIL7FlW4gSRdhQPZbu8HyeEQ4uu+eNz8cvyXGXNujInCZi8dYfxD 9P7Y80PeEqmDScTkLP4lHCp5nbbb21sErZTCbuEB1PTOVEI9PxT+OQt7V+KICzVzc9yr NHIA== X-Gm-Message-State: AOJu0YzAqzMaluvekT9wCGKeNInfwViJr/lzjEo78fskTGmFWsyfyyW+ MpHkbSWYgrBzBkMVSLrRlAZtr94uyclUjy3gGFyhrapblMM/jyXd7fYoT1MPL4o= X-Google-Smtp-Source: AGHT+IEp2Ri4s9MSjNV1VlE0RaiDM1zebT1VTZlSVw5LZqKCz7pZak2vpPPA7KZ21bzUs72y5miHDg== X-Received: by 2002:a05:600c:2108:b0:40e:62c9:9e6f with SMTP id u8-20020a05600c210800b0040e62c99e6fmr241876wml.184.1706024075595; Tue, 23 Jan 2024 07:34:35 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id p21-20020a05600c359500b0040e3488f16dsm42457536wmq.12.2024.01.23.07.34.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 07:34:34 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH 11/21] spi: s3c64xx: check return code of dmaengine_slave_config() Date: Tue, 23 Jan 2024 15:34:10 +0000 Message-ID: <20240123153421.715951-12-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240123153421.715951-1-tudor.ambarus@linaro.org> References: <20240123153421.715951-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Check the return code of dmaengine_slave_config(). Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 4b13252da8b8..cc33647eab14 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -296,7 +296,9 @@ static int prepare_dma(struct s3c64xx_spi_dma_data *dma, config.dst_maxburst = 1; } config.direction = dma->direction; - dmaengine_slave_config(dma->ch, &config); + ret = dmaengine_slave_config(dma->ch, &config); + if (ret) + return ret; desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, dma->direction, DMA_PREP_INTERRUPT); From patchwork Tue Jan 23 15:34:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13527680 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BE1260DCF for ; Tue, 23 Jan 2024 15:34:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024080; cv=none; b=gg8eiTHeKAEXctvLTqxlAjEFVKJvKLtlvmTb/3NgAIRVfSQOjbd9bTNHmHgPDhCLJHbzyqTiHJaWU1vTBbOi0+UdRPutc1PwiqAeV2HzpqOT3R0LnykMeUZIwdtTztIvpFEYNGw4NdAb+2jK9SJSo04YiwlRS+WJaBw3d+7DwUE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024080; c=relaxed/simple; bh=azFcV/mgHmxVyLvuazK3I1eqSDB4DgGiyfhf9SMqDgs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ggvi5rYRkLcpMyFRFBTkRUQHSxJgluDSIItv4nI/AO7mZtGWPoDMuSKoakqYHjVXbpbSbY8E4o5S4MW+QFMNgJ+Y3IGFsPvQ2A6g0Cdx3QgLJUSDLrhnEXwa+PujwI6hziQPfE1KXcJUJods0O+ME2rFRnuH0/7s4oroWWjswpc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=mpekW4G5; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="mpekW4G5" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-40eb033c1b0so21748225e9.2 for ; Tue, 23 Jan 2024 07:34:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706024076; x=1706628876; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e+YMzDyGNc/zXRSdUvNiD+W2fMYH+c8kFJSxO3iDixs=; b=mpekW4G5d289qPbVUvpkAx8dBz1CQgT4/WEtGZYW7xdwyvJSb9jRMGSPwByj1kCtgF 2LdcPLya6CDBrGEfsyh2EV/dJdPCVn3YQ4C0xEOFDCy/Eu6OUXZu27B5pyfGy8fcYsxl 52TuZpwdJlbRz88Wyc/Ou58kG9b70Oelvt32wxIZ05LGnT1mK/egInn2APLvu4brVNQN 3enQu9MxqjIZoVvFdlZw86KAQJKCbxWuDeZ7sJC6cNQQDqkgGPK2RO8uOH1CWZiuP7NY Z37j4r6HSoQyIzT1xgKfjEDPcNlSJuJAT3JTstiqQAWY0E88S3MLVMrBB7NTP54WiSj1 S0ZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706024076; x=1706628876; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e+YMzDyGNc/zXRSdUvNiD+W2fMYH+c8kFJSxO3iDixs=; b=vVf5k7m4H1UzA0I/7WCMuYOyYrGCBoxveyxxnWyYurW+QFEsgKr9/8/EKfQkUz0BO5 lZuVdCxS4lveYgcJlbQg61AxPCvTJtJBN3YkBJy5yH44JYes9hr3rspuLK1IioLLDENx S4+a3ONLEYe8KyNmMwsJseemZU4XUjcwwfIyq99p0GtdXFElJybRYspvFWFoZcqWYCfh Vfgzk6ZtHCe8Iy603uTfi/+YdfjOIZ0GVyzfGU9Lue2axwOi48oXD9exzM4cYfHfeggF rK4eTVeVUolUyrIZwytQKbzMiNVW9nwnZ3FW28F/nYtfHaeGFGaRd++KEZAlQKGzmt0h WjtQ== X-Gm-Message-State: AOJu0YwCbDziZq9luK2fyye8KAmQZbsj0yCpqmt+nYXf1GAV95+Ivko9 w+7zJkLMB0ru8+B32mBMWHrxslT1xeLnd0rj7ZkmFY2pcwQMXJjMejzEuDgPmjA= X-Google-Smtp-Source: AGHT+IHzfN1qnVR4UVsM9mJTMqExDKUWTqRX/JTb9E8bTyCwoGow8h3nokE07jWiTAJ313YlGKAHHw== X-Received: by 2002:a05:600c:12cb:b0:40e:4179:d060 with SMTP id v11-20020a05600c12cb00b0040e4179d060mr280263wmd.65.1706024076431; Tue, 23 Jan 2024 07:34:36 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id p21-20020a05600c359500b0040e3488f16dsm42457536wmq.12.2024.01.23.07.34.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 07:34:35 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH 12/21] spi: s3c64xx: propagate the dma_submit_error() error code Date: Tue, 23 Jan 2024 15:34:11 +0000 Message-ID: <20240123153421.715951-13-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240123153421.715951-1-tudor.ambarus@linaro.org> References: <20240123153421.715951-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Propagate the dma_submit_error() error code, don't overwrite it. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index cc33647eab14..2b088a190ab9 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -315,7 +315,7 @@ static int prepare_dma(struct s3c64xx_spi_dma_data *dma, ret = dma_submit_error(dma->cookie); if (ret) { dev_err(&sdd->pdev->dev, "DMA submission failed"); - return -EIO; + return ret; } dma_async_issue_pending(dma->ch); From patchwork Tue Jan 23 15:34:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13527681 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2DA9860EC9 for ; Tue, 23 Jan 2024 15:34:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024081; cv=none; b=D2lTtdbSytvWSkZRFmek9JGC+hMksrHJQA7pKfmljeZRrWDP/PaCusWTfn+jqfSRlwEQE8ipbrg8ds51NI735YLkPHJ9pd5Mua/LR86ALhlUaR8/KWRLEEvlCWIzeS/fuplz8xh71ZAVTvlPxQ5TvRzTGqnlMvi2X1zPaiFHkSc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024081; c=relaxed/simple; bh=MM8h/S9zhmJXxlI1gWjw0PgXgsMVTe/E1qBEBZIGhCw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jrriZMzKHZaHxiliPOPOIKAPeVPHctnmMEVwVrBiUOhN3Czun6++iHko06bRPfFQbbTLTcqJJr8dj5SqD2a4/taS52gy7fO2RwFtlqNyRn0eMhdcWGvlocjLIuCEnYaTRkWKZDBGsBOXLRVW3/tjwvRn1RRoM+wZ+9f0X60yxyw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=zo5S7x7f; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="zo5S7x7f" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-40eacb4bfa0so24559045e9.1 for ; Tue, 23 Jan 2024 07:34:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706024077; x=1706628877; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Kxj/GKivy8KHz8wlyYVu9rRfrbEmnmhas4Q7ujviZXU=; b=zo5S7x7fXsE2/iibwqDoFYX/xn2PrzwJxfuQDTlsEBvEadeSWOgaudyzBXBz1h5kQp z/jGMd9AGwKZJVdOlR0NOrRxmNlyPLLxWVUxjwyRlVWhtp8w4U52FKDqnj1VJjAB+5Sl EaLQDpGKXRRv+qgVPSOIK3ZLmnagb01AhkHgMVTKfa1i/o/+snmhB/36DFH2hzXtYjLt yU7AWIwDH73zMb2H757hwoeHEZpGqzJBtqf+ro7lLTF4jKUknGdI7FKxLcZvtWs7KUXw yAmPrpm/K2kI5DwCTmUefLJgNHU/Lgo6NFSQNPKsYx+O+3nP7M5yTJLYclGx4mbXw3/5 qPVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706024077; x=1706628877; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Kxj/GKivy8KHz8wlyYVu9rRfrbEmnmhas4Q7ujviZXU=; b=HKD8nVjGw24NahZmumO6hhomkYkYBlaZEKD85hJBmQ5GIp9CDPWH52a4brHjrIHuZP snxPVtxwPoYCyrMCX8g+e3uxlIf7HLt3llgshqWeuKCVepmMoRv8uY07t5apdXEksc1g fIKZvFU4GVcVmir3N0nb2cfYS7ndZtyDXD4j9S30i7d8EMhcygqzq18sVJHkrq4GN7p4 BWKsQZ96n7QsjGO7YkPiJ0QXNA74apnwp7k7w5w6/zL1pWWKZiQZjl4ctJamw8fgm+SB nFV5gZWWWTG8njFMlB7Cw1RrMkxm+cBvL7IcBovQZ31rNHguMNYyIPzRWht+YiMnljmb pTjw== X-Gm-Message-State: AOJu0YwpQtcsvMCxRYRs4I+w64urvbMG4ZzH5thfkgv4MZa/5HcvFu+b TyZeLLqU5J0FYSWne9cFS7eOnDwSLjtQHXpAisC27UIPplzTgNAyShvDU26a3Rw= X-Google-Smtp-Source: AGHT+IFcab2zDsD9I27H2KBoICJD/fGV5rpgJVASWI6Q+u5HNWTcCrDWfrf1zCUTug9AMM0BIJrhgw== X-Received: by 2002:a7b:cd8f:0:b0:40e:b505:5581 with SMTP id y15-20020a7bcd8f000000b0040eb5055581mr265504wmj.60.1706024077455; Tue, 23 Jan 2024 07:34:37 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id p21-20020a05600c359500b0040e3488f16dsm42457536wmq.12.2024.01.23.07.34.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 07:34:36 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH 13/21] spi: s3c64xx: rename prepare_dma() to s3c64xx_prepare_dma() Date: Tue, 23 Jan 2024 15:34:12 +0000 Message-ID: <20240123153421.715951-14-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240123153421.715951-1-tudor.ambarus@linaro.org> References: <20240123153421.715951-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Don't monopolize the name. Prepend the driver prefix to the function name. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 2b088a190ab9..8897b5895cde 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -272,8 +272,8 @@ static void s3c64xx_spi_dmacb(void *data) spin_unlock_irqrestore(&sdd->lock, flags); } -static int prepare_dma(struct s3c64xx_spi_dma_data *dma, - struct sg_table *sgt) +static int s3c64xx_prepare_dma(struct s3c64xx_spi_dma_data *dma, + struct sg_table *sgt) { struct s3c64xx_spi_driver_data *sdd; struct dma_slave_config config; @@ -439,7 +439,7 @@ static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, chcfg |= S3C64XX_SPI_CH_TXCH_ON; if (dma_mode) { modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; - ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg); + ret = s3c64xx_prepare_dma(&sdd->tx_dma, &xfer->tx_sg); } else { switch (sdd->cur_bpw) { case 32: @@ -471,7 +471,7 @@ static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) | S3C64XX_SPI_PACKET_CNT_EN, regs + S3C64XX_SPI_PACKET_CNT); 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id p21-20020a05600c359500b0040e3488f16dsm42457536wmq.12.2024.01.23.07.34.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 07:34:37 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH 14/21] spi: s3c64xx: return ETIMEDOUT for wait_for_completion_timeout() Date: Tue, 23 Jan 2024 15:34:13 +0000 Message-ID: <20240123153421.715951-15-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240123153421.715951-1-tudor.ambarus@linaro.org> References: <20240123153421.715951-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 ETIMEDOUT is more specific than EIO, use it for wait_for_completion_timeout(). Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 8897b5895cde..fd0e62ff8968 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -520,7 +520,7 @@ static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, val = msecs_to_jiffies(ms) + 10; val = wait_for_completion_timeout(&sdd->xfer_completion, val); if (!val) - return -EIO; + return -ETIMEDOUT; /* * If the previous xfer was completed within timeout proceed further. * DmaTx returns after simply writing data in the FIFO, @@ -568,7 +568,7 @@ static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd, if (use_irq) { val = msecs_to_jiffies(ms); if (!wait_for_completion_timeout(&sdd->xfer_completion, val)) - return -EIO; + return -ETIMEDOUT; } val = msecs_to_loops(ms); From patchwork Tue Jan 23 15:34:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13527683 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE0A8612FF for ; Tue, 23 Jan 2024 15:34:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024083; cv=none; b=JZ2mT7GzvKR6gOMWvzlNCk0we3OkhnWWxB/mF9zGxSh83K7xw+/Jp3aWXiPqd7oWL+ZCm+5ht8zKUsFDTgOKrNIOZG/yCB5Z79UE9Sxwqxluf0q7rdT/IC1KZ1WKiOQYN62tglUMLUYW6OSaRflRHPXUcIgFAqANXnMgGh3tUfE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024083; c=relaxed/simple; bh=0jefaH/X2bYazIxd0tEnmAOi/YD0WkwHPNe0EjJYDl8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lqkdjihGdKaFgkZf7xEo7sK4ZJj1QEnj6iuaCgu//6cQUjRScGQBt2z7G+YvSupS/5AePsdpFiec7NnP/UC+LlPjjwXNC98TvpAYQNEhnrgppBmWhefp5p6UoY0vjt6Ggn2BgyuIjXlsfhNXuVa01yujTxLLW2N2qDCy4K597IM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=R1IHuyV6; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="R1IHuyV6" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-40eb2f392f0so12142665e9.1 for ; Tue, 23 Jan 2024 07:34:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706024079; x=1706628879; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2fDM9KTVN+TskU9fbko0BxYR8hTUuEx0IDlypoaNnK8=; b=R1IHuyV6sLW+L72bW++AHL9U0m+KPlVx3OENxfejCAQEbc9ExLHTViHVhwpkkQym2G goqdnS9rYWj6lZUBLOJamen8+5R+YvgUVtyU7ct6ifde1IeNOTrXOAHUmNKjrP4cbtl9 s+VFPpXuDJXSdkyETjkHAkhncRd4qu0xRc3eo1O3QfDnPZJl3pMrgg6Y8ZOiXyQoqFIJ gLpgILqzL6bTXcA1PLwaE0SNkNidA/9GqeY4JwXgMVW03pUcBUOCp/VF4uQ/311RPHEx sA3wV1OkC2QGo80uLM2URAIPkQEKXOHvY8F6vPpzZCxPgnN0Na1XeJrIshb3m8Bnn7Ax BppQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706024079; x=1706628879; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2fDM9KTVN+TskU9fbko0BxYR8hTUuEx0IDlypoaNnK8=; b=AW1+NjnHRIFihL1lI8412EZY8BNDx0R18piCX5P7EoDK7JNkVSTUXrBMQRBUHVlJ12 2QDrayYnrVT9CW1A1g3uZWvJkeuyPsov/bwrqjXH8uaOJDS3MXzN+33f1a6sxMzSOp/Q lAEBJHwYZJi0F5z+gGgUNvQIMr/ptnNEfI/kNyoEJ9USh733p3xvCXGqUuGOcmTvq9Zl 5lik82xc8NKo9u3yCbQ/C1bm9Fk/4OieUhFeGVzbys0kN201r49vg6Rjs367G4d8CJfu E7G9t2xOuY/7ShSeD5bDpezTPcl0VIT9BU3H6tzVoNN1W11pld6SXzl9oCQqDAgTKMO4 Hn/Q== X-Gm-Message-State: AOJu0Yx9Uu0DTsSDqKCckLqZxu0u9uR42k9cWG6V6/Ch9Cshh0rpAxWY 4bzaHNf0AQk5D6C1ya1oplYkrsTwF6s4s4QMcbX7DdmZ2m1lZmxaFNmTiPC0z+A= X-Google-Smtp-Source: AGHT+IG7MEG80tjOklkuIf4WBsSG8lL2BEyEh1zV2JV31IyAf2q0kQ4mEQdrihuSIxu+3aeBuTvWIQ== X-Received: by 2002:a05:600c:4e87:b0:40e:c23f:8784 with SMTP id f7-20020a05600c4e8700b0040ec23f8784mr262957wmq.111.1706024079161; Tue, 23 Jan 2024 07:34:39 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id p21-20020a05600c359500b0040e3488f16dsm42457536wmq.12.2024.01.23.07.34.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 07:34:38 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH 15/21] spi: s3c64xx: simplify s3c64xx_wait_for_pio() Date: Tue, 23 Jan 2024 15:34:14 +0000 Message-ID: <20240123153421.715951-16-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240123153421.715951-1-tudor.ambarus@linaro.org> References: <20240123153421.715951-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 s3c64xx_spi_transfer_one() makes sure that for PIO the xfer->len is always smaller than the fifo size. Clean s3c64xx_wait_for_pio() and emphasize that it works with lengths smaller than the fifo size. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 75 +++++++++------------------------------ 1 file changed, 17 insertions(+), 58 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index fd0e62ff8968..f5474f3b3920 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -484,26 +484,6 @@ static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, return 0; } -static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, - int timeout_ms) -{ - void __iomem *regs = sdd->regs; - unsigned long val = 1; - u32 status; - u32 max_fifo = FIFO_DEPTH(sdd); - - if (timeout_ms) - val = msecs_to_loops(timeout_ms); - - do { - status = readl(regs + S3C64XX_SPI_STATUS); - } while (FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, status) < max_fifo && - --val); - - /* return the actual received data length */ - return FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, status); -} - static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, struct spi_transfer *xfer) { @@ -547,13 +527,11 @@ static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd, struct spi_transfer *xfer, bool use_irq) { void __iomem *regs = sdd->regs; + u8 *buf = xfer->rx_buf; + unsigned long time_us; unsigned long val; - u32 status; - int loops; - u32 cpy_len; - u8 *buf; + u32 status, len; int ms; - unsigned long time_us; /* microsecs to xfer 'len' bytes @ 'cur_speed' */ time_us = (xfer->len * 8 * 1000 * 1000) / sdd->cur_speed; @@ -576,48 +554,29 @@ static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd, status = readl(regs + S3C64XX_SPI_STATUS); } while (FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, status) < xfer->len && --val); - if (!val) return -EIO; /* If it was only Tx */ - if (!xfer->rx_buf) { + if (!buf) { sdd->state &= ~TXBUSY; return 0; } - /* - * If the receive length is bigger than the controller fifo - * size, calculate the loops and read the fifo as many times. - * loops = length / max fifo size (calculated by using the - * fifo mask). - * For any size less than the fifo size the below code is - * executed atleast once. - */ - loops = xfer->len / FIFO_DEPTH(sdd); - buf = xfer->rx_buf; - do { - /* wait for data to be received in the fifo */ - cpy_len = s3c64xx_spi_wait_for_timeout(sdd, - (loops ? ms : 0)); - - switch (sdd->cur_bpw) { - case 32: - ioread32_rep(regs + S3C64XX_SPI_RX_DATA, - buf, cpy_len / 4); - break; - case 16: - ioread16_rep(regs + S3C64XX_SPI_RX_DATA, - buf, cpy_len / 2); - break; - default: - ioread8_rep(regs + S3C64XX_SPI_RX_DATA, - buf, cpy_len); - break; - } + len = FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, status); + + switch (sdd->cur_bpw) { + case 32: + ioread32_rep(regs + S3C64XX_SPI_RX_DATA, buf, len / 4); + break; + case 16: + ioread16_rep(regs + S3C64XX_SPI_RX_DATA, buf, len / 2); + break; + default: + ioread8_rep(regs + S3C64XX_SPI_RX_DATA, buf, len); + break; + } - buf = buf + cpy_len; - } while (loops--); sdd->state &= ~RXBUSY; return 0; From patchwork Tue Jan 23 15:34:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13527684 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6A866168E for ; Tue, 23 Jan 2024 15:34:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024084; cv=none; b=fMdeVi3VLpF0rtbIiTlkTlhWMN+9f4t3kgjEZ/wzfk/DIv7y12N/g5UhnpnhcNGsizBRHTddrNzj/m6ss40WzQY1ANPjDcE5OgzYnxA9dIdIJaTCKYO4guBSjxBO6HWqWkOVyRP+992RizqfxOASIA8hFMnRtSKggWR3c4C1eF0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024084; c=relaxed/simple; bh=11eqkgJUjNPy5+qS5uzzo4B6y2Q0KQYSVIT5ixBCL68=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qzNj9J4ex2IsrTppT1U8rv/Q1qNHPB2R6Ew+FzIze8/X/amJwbRseRvPN3trZ0dos3t0bhzXIC/RDc/+JwAJwk1l7l4QxSiI6wm56x5fD0wCNdf7Y6jDho5nfutAHdU5FJGsgeJfk6FlQywDOsvPblNrx/xl9BrvyBwfzKWhPzY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=cowR9q1N; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="cowR9q1N" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-40e86a9fc4bso57490715e9.2 for ; Tue, 23 Jan 2024 07:34:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706024080; x=1706628880; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2ut/OStyJerEIXwncXZj/mTgjprtvHDvTLoi9wIIiA8=; b=cowR9q1N5OOb/8+IF+LIstEKqYRcfVHg78yhtiu0hKtUqRL8sQfv1AoVZObXOXlKQ2 RvPFYrHyQenWZfr0jxv/AyEYTiGXdzMrpa+PvVB4sGdEDi29AQGaUDw6kShcCqGbMqLm p6ddUcRtUPK9g+ILTY0nb+C5BR3GUmBfMxKF2r1w2ZaNT36edvNaSP8mfpxv0Rl/bTvI ybq0biSfkhq0oMW/eYFzDI8jjH+/smOGNJc1uCIBZqKHMOOpSAFmgr/vucQxTFvnKSo0 RgI2jSit5PjXoLhiUaoRidnQbAheLM2FgHYWdo0HsWuqz3cb1kJxtMO2J2Lr5Qpn3J83 rssw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706024080; x=1706628880; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2ut/OStyJerEIXwncXZj/mTgjprtvHDvTLoi9wIIiA8=; b=vpRSvoGEqbU/asqyi6sz5TGur8M9UvzUcyVO6rB1dfEIglWy/nm5r7EFJl23dNKfLt Xy873XuPKVpuF2ck3yysFy5hlILwbVwwe3vo4wNE12PHdsbSOkxYJiHE2dB0BCRc29A9 FNyQ+QM9Z+Pt1DLExgmcY47h9+hqPw5I5OANpqgcl6S9PqSshMActeqqtexEyHwpi8DB CAT68uFABY4cvzHpnf6RC/MT4PSyUDG898uUpBmxhCju4lMnpatzGWE3+iY4YMcxpCda trc/SIt1M5mY7pO/KkzXcptDXVc8SMB67ciAB6Zo9UEMtRsbnjFdz50YqTsjCsKyqh3R 7gXA== X-Gm-Message-State: AOJu0Yykknr3eeyVzRhx3wEbI4ppi3SD3GchjuJfH3bU/qUIusTGzvDP TSVyoDh2srzHdMmEEv2PiKrGCRp4O80w+InQtB0CJH3CVtF4njrbiRFb39av/nw= X-Google-Smtp-Source: AGHT+IFy5hVqPrTc2wq6yQNAZyI/n9eio2xmFflp5WDTVB2OCH4vhagDSKA9/oRlBzXDGVqen8YdpQ== X-Received: by 2002:a05:600c:3f97:b0:40e:5263:28a3 with SMTP id fs23-20020a05600c3f9700b0040e526328a3mr258912wmb.52.1706024080218; Tue, 23 Jan 2024 07:34:40 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id p21-20020a05600c359500b0040e3488f16dsm42457536wmq.12.2024.01.23.07.34.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 07:34:39 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH 16/21] spi: s3c64xx: add missing blank line after declaration Date: Tue, 23 Jan 2024 15:34:15 +0000 Message-ID: <20240123153421.715951-17-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240123153421.715951-1-tudor.ambarus@linaro.org> References: <20240123153421.715951-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add missing blank line after declaration. Move initialization in the body of the function. Signed-off-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- drivers/spi/spi-s3c64xx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index f5474f3b3920..2abf5994080a 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1273,8 +1273,9 @@ static int s3c64xx_spi_suspend(struct device *dev) { struct spi_controller *host = dev_get_drvdata(dev); struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); + int ret; - int ret = spi_controller_suspend(host); + ret = spi_controller_suspend(host); if (ret) return ret; From patchwork Tue Jan 23 15:34:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13527685 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCE5A627FD for ; Tue, 23 Jan 2024 15:34:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024085; cv=none; b=Nvj3z60S7gT7+x15QYs4QhLFA2+8sDrMswHbYbsPIA5IyYCZeQA9wMpg16N8hFp+9PPmG+1HphncgMry5+DF0D/xa3qRTT/IakqyTTbqlYkPPJuj2ifJPJkupLsRUiPsLPqBCp21Gf56i8/dWPa33aCCtzNnX3xbZkR56eNB7tU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024085; c=relaxed/simple; bh=uyvoI3Eakfsm5uU2bBBf4GNvp+1Z30veFit2CgoNzVA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=k4OYA5bX1eE4Ke13jkQW6VVezcD7TTn7HbQqR84J1cjnyIXWNFAbU8glr7TptOsmCXLk8eGW0Qq5FUgQIIU9nO5kzz9QJTts3rK1ZPLuE92GfFnvMe6PUtDXbOfpGvw0T3vCiouOxJvr0uJVs37lf/qwHeZ45ln3brglZkpv9AI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=i8fBUW1U; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="i8fBUW1U" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-40eb95bd2c6so10518085e9.0 for ; Tue, 23 Jan 2024 07:34:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706024081; x=1706628881; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/irE8ZyZqV8JPqhFZspW4QvYBkIBZkdLqpFIYT3Nu0M=; b=i8fBUW1UXBpq+PbgE7s23N2jq6m/LbjqqPK0i2O9xePJco/GU3g/VZcytc9uNerkf9 fTEvnqqngkKLHvaBCvqJS+BnAR+xOxFJpz/3s3YPZAFa4ZIkvgRqb/XMHbUy557Mu4ku G13Sa3nBf/oO4VkVyu80eu7jPLVtyaAOzjEJS0Gxg7/AsxUaaG92sHzLU+L3cyx2hFP+ vKCBy2DQUynstj8/IQ530U3ghycbE4H6ZxLDfUH6S8FVLqaSvshP3+ROBzCR4KK+QjMS CiOVb4aHlNjY5xjRs1K5ffbzs/SiAmscV8FYOmScbGMIIV7WjyHPnLgalZ546hc0K/lg uWEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706024081; x=1706628881; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/irE8ZyZqV8JPqhFZspW4QvYBkIBZkdLqpFIYT3Nu0M=; b=avUAF8j14ygnWreQIyayubPMcvb+lLLZF9yI9DNX7KaAqHzquJ3q9DAA+a+f9Uc1qr f/27MBox8BwW4NvjZSgfKAUvMr8WIS62/iS/TgdwUShFNelnxUjVLuozl9Y6g7W2bAn3 V4njDGv7X4a8BHBgLgjVRBmZEkqs8zUDyph6xXWmDk89lrfEMn/Cv9k3XKDOyBB52VZH Wwt3oBYtRrNfJt2R8d1+DoR9bgdhXzUTlIIhAdf6853u4MhsEyYmJX/i6LZJoMd6h5UE DlLSNJOOroct4I6yqUeJ4344Dtre3Jxr32S8hAtHcFPHZqUV4/DZ5F0UfpHlfd8UZW79 TVdA== X-Gm-Message-State: AOJu0YwwBPeQPwqp5Yf5wq8JZC4dUyrVjx1lq3TO/5Id/e9O+3gtMUx7 KA0aZzyoZAhQH2n5JwHrR2PgpX7grv6oNlf1C2vlY0cGi29JA/wTGX9nph+xrFw= X-Google-Smtp-Source: AGHT+IFnQUAOFj2XlDJpBxTuWZdr7PkB/FRu7Br6988kcrenHLZAgS6ZvP6iNS1JTyl+7ezr01rrMA== X-Received: by 2002:a05:600c:46ce:b0:40e:b036:d92e with SMTP id q14-20020a05600c46ce00b0040eb036d92emr249779wmo.144.1706024081101; Tue, 23 Jan 2024 07:34:41 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id p21-20020a05600c359500b0040e3488f16dsm42457536wmq.12.2024.01.23.07.34.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 07:34:40 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH 17/21] spi: s3c64xx: downgrade dev_warn to dev_dbg for optional dt props Date: Tue, 23 Jan 2024 15:34:16 +0000 Message-ID: <20240123153421.715951-18-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240123153421.715951-1-tudor.ambarus@linaro.org> References: <20240123153421.715951-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 "samsung,spi-src-clk" and "num-cs" are optional dt properties. Downgrade the message from warning to debug message. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 2abf5994080a..62671b2d594a 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1065,14 +1065,14 @@ static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) return ERR_PTR(-ENOMEM); if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { - dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); + dev_dbg(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); sci->src_clk_nr = 0; } else { sci->src_clk_nr = temp; } if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { - dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n"); + dev_dbg(dev, "number of chip select lines not specified, assuming 1 chip select line\n"); sci->num_cs = 1; } else { sci->num_cs = temp; From patchwork Tue Jan 23 15:34:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13527686 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C48F3629E9 for ; Tue, 23 Jan 2024 15:34:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024086; cv=none; b=ohTq5l1QsYtGJ5AL4Okf/RoQI8s8Dxo7HDOOAP7nwEWi09KNm+dVKWUJESKXPObIBc9/18IjvBHtS8EcwOu0b7WdBsCkX+KlcCu1FM5yArRK871ndcACA18oduU51fPCICEQkXSOYiX0zfSDIFIoQZDoI1kSs0BkPdRCMMeWIqE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706024086; c=relaxed/simple; bh=+FEK7zXvkUNPYoloHVBKujmewWPaUNrgkfydcuviAQc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=V6G5EGnwxStf3qsXOqu48OAk2HwauzNBjHlBne2E8NPFyr8DTgqcQLupUzJv/sYdcgi+11UcU+G27qa68U4W7RqaoIvz0PBhpPhpim/vAdQaUjJVJazdyhsZmoOO4YpdReD7gkwfl58WrM+LfsPyk4wjY54TJkQJzMTULSjRJ6k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=k9HzX+fx; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="k9HzX+fx" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-40ec048e0c1so4721755e9.2 for ; Tue, 23 Jan 2024 07:34:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706024082; x=1706628882; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2H+4vxpbUIDd45rCzEN2Z22Mxunqggm4pG1DkoeAKqY=; b=k9HzX+fxGHGhBRM9HiG54NpzC/9HNYzRkNHrf6ZjAql/yvsfySr+xVSx3aCiLlgjI6 u1dVoIxstQCKfMqWKLqehMp9f+myUe5OXqS92n1D77Gd0prCXiu32uBSWxLw+/XGGgj3 ADk3gPSFOdL8XCK9+GVhqZrHVHEHbQvCPgBQ26coqOv71awO50TrdYLu24Vx7LMwbPOM Du4m/a0xywWE36l3pCXeKYRrQAsQCgkwjqwmvKQfWL4foXcXm2GolIxVN+N5RkKkqwiY i2twN279l6iyqRlgJXJ/WO5lp9hkB54nLLzH63OXUUfuE3ervksl9Le6ZMf9c2VG48Pu dqwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706024082; x=1706628882; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2H+4vxpbUIDd45rCzEN2Z22Mxunqggm4pG1DkoeAKqY=; b=Ugp0yEJ2ZTnvgYFPU/ckJe8URW4/pxbAlLwF2ZK2bRJ/KhiKMmWgSFrp9mnNDFzPF1 W5mPtz8b5niLu6npjiqg1NaI+9Hy5u0y6E2NCFIkLz8YKksaKj72xKghFAZ0SpvrnT8L gLOq+1TIm4gdJYL41/bl+L/VnCBx5b0OeB3q212xtW/VZ8yJ1r8gk7DanU/hRPEFnwPj 1+NAF9hcNuDCU92/tCyVv7g8Y4u6nnfI5XZjt7OFXj+ZWwcP9GJD5jZ3UiLvWF+9F/3M qmEsbswvLhKiJIGAxwkysRjG5UHrMFuyCAwIq4/OHqjpYJNHDG4FCEOMHiyn5bXOxqw6 fhKQ== X-Gm-Message-State: AOJu0YxjlJ1GVlO0rtaMc6l9LbuYtVEQGMy5NMEwBVCcBFRMWVkZoj81 Lae8UY3+BYoYEqz79BKtHq9hAOx1poYSI+Q+IF6nFKp0bIf1QQksSNsawlROKEo= X-Google-Smtp-Source: AGHT+IEdhulGHnMoRApGote5ScptZ0DoCltZHEA7gddglwiHhXxlIDhI6CN7Ov1Zuk+CJc7AAijQ6g== X-Received: by 2002:a05:600c:4448:b0:40e:937f:16dc with SMTP id v8-20020a05600c444800b0040e937f16dcmr707423wmn.17.1706024082130; Tue, 23 Jan 2024 07:34:42 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id p21-20020a05600c359500b0040e3488f16dsm42457536wmq.12.2024.01.23.07.34.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 07:34:41 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH 18/21] asm-generic/io.h: add iowrite{8,16}_32 accessors Date: Tue, 23 Jan 2024 15:34:17 +0000 Message-ID: <20240123153421.715951-19-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240123153421.715951-1-tudor.ambarus@linaro.org> References: <20240123153421.715951-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This will allow devices that require 32 bits register accesses to write data in chunks of 8 or 16 bits. One SoC that requires 32 bit register accesses is the google gs101. A typical use case is SPI, where the clients can request transfers in words of 8 bits. Signed-off-by: Tudor Ambarus --- include/asm-generic/io.h | 50 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index bac63e874c7b..1e224d1ccc98 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -476,6 +476,21 @@ static inline void writesb(volatile void __iomem *addr, const void *buffer, } #endif +#ifndef writesb_l +#define writesb_l writesb_l +static inline void writesb_l(volatile void __iomem *addr, const void *buffer, + unsigned int count) +{ + if (count) { + const u8 *buf = buffer; + + do { + __raw_writel(*buf++, addr); + } while (--count); + } +} +#endif + #ifndef writesw #define writesw writesw static inline void writesw(volatile void __iomem *addr, const void *buffer, @@ -491,6 +506,21 @@ static inline void writesw(volatile void __iomem *addr, const void *buffer, } #endif +#ifndef writesw_l +#define writesw_l writesw_l +static inline void writesw_l(volatile void __iomem *addr, const void *buffer, + unsigned int count) +{ + if (count) { + const u16 *buf = buffer; + + do { + __raw_writel(*buf++, addr); + } while (--count); + } +} +#endif + #ifndef writesl #define writesl writesl static inline void writesl(volatile void __iomem *addr, const void *buffer, @@ -956,6 +986,16 @@ static inline void iowrite8_rep(volatile void __iomem *addr, } #endif +#ifndef iowrite8_32_rep +#define iowrite8_32_rep iowrite8_32_rep +static inline void iowrite8_32_rep(volatile void __iomem *addr, + const void *buffer, + unsigned int count) +{ + writesb_l(addr, buffer, count); +} +#endif + #ifndef iowrite16_rep #define iowrite16_rep iowrite16_rep static inline void iowrite16_rep(volatile void __iomem *addr, @@ -966,6 +1006,16 @@ static inline void iowrite16_rep(volatile void __iomem *addr, } #endif +#ifndef iowrite16_32_rep +#define iowrite16_32_rep iowrite16_32_rep +static inline void iowrite16_32_rep(volatile void __iomem *addr, + const void *buffer, + unsigned int count) +{ + writesw_l(addr, buffer, count); +} +#endif + #ifndef iowrite32_rep #define iowrite32_rep iowrite32_rep static inline void iowrite32_rep(volatile void __iomem *addr, From patchwork Tue Jan 23 15:34:18 2024 Content-Type: text/plain; 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id p21-20020a05600c359500b0040e3488f16dsm42457536wmq.12.2024.01.23.07.34.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 07:34:42 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH 19/21] spi: s3c64xx: add support for google,gs101-spi Date: Tue, 23 Jan 2024 15:34:18 +0000 Message-ID: <20240123153421.715951-20-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240123153421.715951-1-tudor.ambarus@linaro.org> References: <20240123153421.715951-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for GS101 SPI. All the SPI nodes on GS101 have 64 bytes FIFOs, infer the FIFO size from the compatible. GS101 allows just 32bit register accesses, otherwise a Serror Interrupt is raised. Do the write reg accesses in 32 bits. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 50 +++++++++++++++++++++++++++++++++------ 1 file changed, 43 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 62671b2d594a..c4ddd2859ba4 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -20,6 +20,7 @@ #define MAX_SPI_PORTS 12 #define S3C64XX_SPI_QUIRK_CS_AUTO BIT(1) +#define S3C64XX_SPI_GS1O1_32BIT_REG_IO_WIDTH BIT(2) #define AUTOSUSPEND_TIMEOUT 2000 /* Registers and bit-fields */ @@ -131,6 +132,7 @@ struct s3c64xx_spi_dma_data { * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. * @clk_div: Internal clock divider + * @fifosize: size of the FIFO * @quirks: Bitmask of known quirks * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. * @clk_from_cmu: True, if the controller does not include a clock mux and @@ -149,6 +151,7 @@ struct s3c64xx_spi_port_config { int tx_st_done; int quirks; int clk_div; + unsigned int fifosize; bool high_speed; bool clk_from_cmu; bool clk_ioclk; @@ -175,6 +178,7 @@ struct s3c64xx_spi_port_config { * @tx_dma: Local transmit DMA data (e.g. chan and direction) * @port_conf: Local SPI port configuartion data * @port_id: Port identification number + * @fifosize: size of the FIFO for this port */ struct s3c64xx_spi_driver_data { void __iomem *regs; @@ -194,6 +198,7 @@ struct s3c64xx_spi_driver_data { struct s3c64xx_spi_dma_data tx_dma; const struct s3c64xx_spi_port_config *port_conf; unsigned int port_id; + unsigned int fifosize; }; static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd) @@ -403,7 +408,7 @@ static bool s3c64xx_spi_can_dma(struct spi_controller *host, struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); if (sdd->rx_dma.ch && sdd->tx_dma.ch) - return xfer->len > FIFO_DEPTH(sdd); + return xfer->len > sdd->fifosize; return false; } @@ -447,12 +452,22 @@ static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, xfer->tx_buf, xfer->len / 4); break; case 16: - iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, - xfer->tx_buf, xfer->len / 2); + if (sdd->port_conf->quirks & + S3C64XX_SPI_GS1O1_32BIT_REG_IO_WIDTH) + iowrite16_32_rep(regs + S3C64XX_SPI_TX_DATA, + xfer->tx_buf, xfer->len / 2); + else + iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, + xfer->tx_buf, xfer->len / 2); break; default: - iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, - xfer->tx_buf, xfer->len); + if (sdd->port_conf->quirks & + S3C64XX_SPI_GS1O1_32BIT_REG_IO_WIDTH) + iowrite8_32_rep(regs + S3C64XX_SPI_TX_DATA, + xfer->tx_buf, xfer->len); + else + iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, + xfer->tx_buf, xfer->len); break; } } @@ -696,7 +711,7 @@ static int s3c64xx_spi_transfer_one(struct spi_controller *host, struct spi_transfer *xfer) { struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); - const unsigned int fifo_len = FIFO_DEPTH(sdd); + const unsigned int fifo_len = sdd->fifosize; const void *tx_buf = NULL; void *rx_buf = NULL; int target_len = 0, origin_len = 0; @@ -1145,6 +1160,11 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd->port_id = pdev->id; } + if (sdd->port_conf->fifosize) + sdd->fifosize = sdd->port_conf->fifosize; + else + sdd->fifosize = FIFO_DEPTH(sdd); + sdd->cur_bpw = 8; sdd->tx_dma.direction = DMA_MEM_TO_DEV; @@ -1234,7 +1254,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Targets attached\n", sdd->port_id, host->num_chipselect); dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n", - mem_res, FIFO_DEPTH(sdd)); + mem_res, sdd->fifosize); pm_runtime_mark_last_busy(&pdev->dev); pm_runtime_put_autosuspend(&pdev->dev); @@ -1362,6 +1382,18 @@ static const struct dev_pm_ops s3c64xx_spi_pm = { s3c64xx_spi_runtime_resume, NULL) }; +static const struct s3c64xx_spi_port_config gs101_spi_port_config = { + .fifosize = 64, + .rx_lvl_offset = 15, + .tx_st_done = 25, + .clk_div = 4, + .high_speed = true, + .clk_from_cmu = true, + .has_loopback = true, + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO | + S3C64XX_SPI_GS1O1_32BIT_REG_IO_WIDTH, +}; + static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = { .fifo_lvl_mask = { 0x7f }, .rx_lvl_offset = 13, @@ -1452,6 +1484,10 @@ static const struct platform_device_id s3c64xx_spi_driver_ids[] = { }; static const struct of_device_id s3c64xx_spi_dt_match[] = { + { + .compatible = "google,gs101-spi", + .data = &gs101_spi_port_config, + }, { .compatible = "samsung,s3c2443-spi", .data = &s3c2443_spi_port_config, From patchwork Tue Jan 23 15:34:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13527688 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BDDA463400 for ; Tue, 23 Jan 2024 15:34:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id p21-20020a05600c359500b0040e3488f16dsm42457536wmq.12.2024.01.23.07.34.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 07:34:44 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH 20/21] spi: s3c64xx: make the SPI alias optional for newer SoCs Date: Tue, 23 Jan 2024 15:34:19 +0000 Message-ID: <20240123153421.715951-21-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240123153421.715951-1-tudor.ambarus@linaro.org> References: <20240123153421.715951-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The alias was used to initialize the port_id, which unfortunately is used for older SoCs to determine the FIFO size from ``s3c64xx_spi_port_config.fifo_lvl_mask``. This is wrong all the way as we shouldn't make a driver dependable of an alias, or the order of probe. If multiple FIFO sizes are supported across the SPI IPs, one shall instead introduce a fifosize device tree property. Make the SPI alias optional for the newer SoCs and mark the ``port_id`` and ``fifo_lvl_mask`` as deprecated. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index c4ddd2859ba4..9cd64fd3058a 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -128,7 +128,8 @@ struct s3c64xx_spi_dma_data { /** * struct s3c64xx_spi_port_config - SPI Controller hardware info - * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. + * @fifo_lvl_mask: [DEPRECATED] Bit-mask for {TX|RX}_FIFO_LVL bits in + * SPI_STATUS register. * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. * @clk_div: Internal clock divider @@ -177,7 +178,7 @@ struct s3c64xx_spi_port_config { * @rx_dma: Local receive DMA data (e.g. chan and direction) * @tx_dma: Local transmit DMA data (e.g. chan and direction) * @port_conf: Local SPI port configuartion data - * @port_id: Port identification number + * @port_id: [DEPRECATED] Port identification number * @fifosize: size of the FIFO for this port */ struct s3c64xx_spi_driver_data { @@ -1152,7 +1153,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd->pdev = pdev; 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id p21-20020a05600c359500b0040e3488f16dsm42457536wmq.12.2024.01.23.07.34.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 07:34:45 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH 21/21] MAINTAINERS: add Tudor Ambarus as R for the samsung SPI driver Date: Tue, 23 Jan 2024 15:34:20 +0000 Message-ID: <20240123153421.715951-22-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240123153421.715951-1-tudor.ambarus@linaro.org> References: <20240123153421.715951-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 I'm working with the samsung SPI driver and I'd like to review further patches on this driver. Add myself as reviewer. Signed-off-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8d1052fa6a69..b9cde7ed8489 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19404,6 +19404,7 @@ F: include/linux/clk/samsung.h SAMSUNG SPI DRIVERS M: Andi Shyti +R: Tudor Ambarus L: linux-spi@vger.kernel.org L: linux-samsung-soc@vger.kernel.org S: Maintained