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Allow this to be described in the GPU clock controller binding. Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/clock/qcom,gpucc.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index f369fa34e00c..c0dd24c9dcb3 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -53,6 +53,9 @@ properties: power-domains: maxItems: 1 + vdd-gfx-supply: + description: Regulator supply for the VDD_GFX pads + '#clock-cells': const: 1 @@ -74,6 +77,19 @@ required: - '#reset-cells' - '#power-domain-cells' +# Allow either power-domains or vdd-gfx-supply, not both +oneOf: + - required: + - power-domains + - required: + - vdd-gfx-supply + - not: + anyOf: + - required: + - power-domains + - required: + - vdd-gfx-supply + additionalProperties: false examples: From patchwork Wed Jan 24 04:25:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 13528505 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05C60BE74; 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Wed, 24 Jan 2024 04:25:17 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 40O4PGQe030413 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 24 Jan 2024 04:25:16 GMT Received: from [169.254.0.1] (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 23 Jan 2024 20:25:16 -0800 From: Bjorn Andersson Date: Tue, 23 Jan 2024 20:25:16 -0800 Subject: [PATCH v3 2/8] clk: qcom: gdsc: Enable supply reglator in GPU GX handler Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240123-sa8295p-gpu-v3-2-d5b4474c8f33@quicinc.com> References: <20240123-sa8295p-gpu-v3-0-d5b4474c8f33@quicinc.com> In-Reply-To: <20240123-sa8295p-gpu-v3-0-d5b4474c8f33@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Taniya Das , Johan Hovold CC: , , , , , , "Bjorn Andersson" X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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But in the event that the power-domain is supplied through a dedicated regulator (in contrast to being a subdomin of another power-domain), something needs to turn that regulator on, both to make sure things are powered and to match the operation in gdsc_disable(). Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gdsc.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 5358e28122ab..e7a4068b9f39 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -557,7 +557,15 @@ void gdsc_unregister(struct gdsc_desc *desc) */ int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain) { - /* Do nothing but give genpd the impression that we were successful */ - return 0; + struct gdsc *sc = domain_to_gdsc(domain); + int ret = 0; + + /* Enable the parent supply, when controlled through the regulator framework. */ + if (sc->rsupply) + ret = regulator_enable(sc->rsupply); + + /* Do nothing with the GDSC itself */ + + return ret; } EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable); From patchwork Wed Jan 24 04:25:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 13528503 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2CA8BE5C; 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Wed, 24 Jan 2024 04:25:17 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 40O4PHLf030418 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 24 Jan 2024 04:25:17 GMT Received: from [169.254.0.1] (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 23 Jan 2024 20:25:16 -0800 From: Bjorn Andersson Date: Tue, 23 Jan 2024 20:25:17 -0800 Subject: [PATCH v3 3/8] clk: qcom: gpucc-sc8280xp: Add external supply for GX gdsc Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240123-sa8295p-gpu-v3-3-d5b4474c8f33@quicinc.com> References: <20240123-sa8295p-gpu-v3-0-d5b4474c8f33@quicinc.com> In-Reply-To: <20240123-sa8295p-gpu-v3-0-d5b4474c8f33@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Taniya Das , Johan Hovold CC: , , , , , , "Bjorn Andersson" , Dmitry Baryshkov X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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Define the "vdd-gfx" as the supply regulator for the GDSC, to cause the gdsc logic to look for, and control, this external power supply. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gpucc-sc8280xp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gpucc-sc8280xp.c b/drivers/clk/qcom/gpucc-sc8280xp.c index 8e147ee294ee..e2b3bc000c71 100644 --- a/drivers/clk/qcom/gpucc-sc8280xp.c +++ b/drivers/clk/qcom/gpucc-sc8280xp.c @@ -399,6 +399,7 @@ static struct gdsc gx_gdsc = { }, .pwrsts = PWRSTS_OFF_ON, .flags = CLAMP_IO | RETAIN_FF_ENABLE, + .supply = "vdd-gfx", }; static struct gdsc *gpu_cc_sc8280xp_gdscs[] = { From patchwork Wed Jan 24 04:25:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 13528499 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6B64BE45; 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Drop gfx.lvl from the list of power-domains exposed on this platform. Fixes: f68f1cb3437d ("soc: qcom: rpmhpd: add sc8280xp & sa8540p rpmh power-domains") Reviewed-by: Dmitry Baryshkov Acked-by: Ulf Hansson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson --- drivers/pmdomain/qcom/rpmhpd.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pmdomain/qcom/rpmhpd.c b/drivers/pmdomain/qcom/rpmhpd.c index 3078896b1300..27a73ff72614 100644 --- a/drivers/pmdomain/qcom/rpmhpd.c +++ b/drivers/pmdomain/qcom/rpmhpd.c @@ -217,7 +217,6 @@ static struct rpmhpd *sa8540p_rpmhpds[] = { [SC8280XP_CX] = &cx, [SC8280XP_CX_AO] = &cx_ao, [SC8280XP_EBI] = &ebi, - [SC8280XP_GFX] = &gfx, [SC8280XP_LCX] = &lcx, [SC8280XP_LMX] = &lmx, [SC8280XP_MMCX] = &mmcx, From patchwork Wed Jan 24 04:25:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 13528502 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A819FBE59; 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Drop the power-domains property of the gpucc node to reflect this. Fixes: eec51ab2fd6f ("arm64: dts: qcom: sc8280xp: Add GPU related nodes") Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8540p.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qcom/sa8540p.dtsi index 96b2c59ad02b..23888029cc11 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi @@ -168,6 +168,9 @@ opp-2592000000 { }; &gpucc { + /* SA8295P and SA8540P doesn't provide gfx.lvl */ + /delete-property/ power-domains; + status = "disabled"; }; From patchwork Wed Jan 24 04:25:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 13528504 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C94CD514; 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Wed, 24 Jan 2024 04:25:18 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 40O4PIKg025235 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 24 Jan 2024 04:25:18 GMT Received: from [169.254.0.1] (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 23 Jan 2024 20:25:17 -0800 From: Bjorn Andersson Date: Tue, 23 Jan 2024 20:25:20 -0800 Subject: [PATCH v3 6/8] arm64: dts: qcom: sa8295p-adp: add max20411 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240123-sa8295p-gpu-v3-6-d5b4474c8f33@quicinc.com> References: <20240123-sa8295p-gpu-v3-0-d5b4474c8f33@quicinc.com> In-Reply-To: <20240123-sa8295p-gpu-v3-0-d5b4474c8f33@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Taniya Das , Johan Hovold CC: , , , , , , "Bjorn Andersson" , Bjorn Andersson X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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Enable the bus and add the maxim,max20411 device on the bus. Signed-off-by: Bjorn Andersson Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 39 ++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index fd253942e5e5..bd0962f39fc5 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -266,6 +266,26 @@ &dispcc1 { status = "okay"; }; +&i2c12 { + pinctrl-0 = <&qup1_i2c4_state>; + pinctrl-names = "default"; + + status = "okay"; + + vdd_gfx: regulator@39 { + compatible = "maxim,max20411"; + reg = <0x39>; + + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + + enable-gpios = <&pmm8540a_gpios 2 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&max20411_en>; + pinctrl-names = "default"; + }; +}; + &mdss0 { status = "okay"; }; @@ -476,6 +496,10 @@ &pcie4_phy { status = "okay"; }; +&qup1 { + status = "okay"; +}; + &qup2 { status = "okay"; }; @@ -636,6 +660,14 @@ &xo_board_clk { /* PINCTRL */ +&pmm8540a_gpios { + max20411_en: max20411-en-state { + pins = "gpio2"; + function = "normal"; + output-enable; + }; +}; + &tlmm { pcie2a_default: pcie2a-default-state { clkreq-n-pins { @@ -728,4 +760,11 @@ wake-n-pins { bias-pull-up; }; }; + + qup1_i2c4_state: qup1-i2c4-state { + pins = "gpio0", "gpio1"; + function = "qup12"; + drive-strength = <2>; + bias-pull-up; + }; }; From patchwork Wed Jan 24 04:25:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 13528500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B430BBE61; Wed, 24 Jan 2024 04:25:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706070330; cv=none; b=byG8xyvPB6UtX5oafPBYhwcZzIWy6yXtfnJ5xfvB1Wo4DIMhKOCTzQTVyeultLt8DUAX8yubRDH+mdcXu0DPwhZ56RJLNjc55kVPUxsFoQPFh4q40b385IptMH4yQxpoiOEcENUtRJaqpSHpJGSLEoL533gr3qDBgwAHd6tpR08= ARC-Message-Signature: i=1; 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Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index bd0962f39fc5..78e933c42c31 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -108,6 +108,13 @@ edp3_connector_in: endpoint { }; }; }; + + reserved-memory { + gpu_mem: gpu-mem@8bf00000 { + reg = <0 0x8bf00000 0 0x2000>; + no-map; + }; + }; }; &apps_rsc { @@ -286,6 +293,28 @@ vdd_gfx: regulator@39 { }; }; +&gpucc { + vdd-gfx-supply = <&vdd_gfx>; + status = "okay"; +}; + +&gmu { + status = "okay"; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sa8295p/a690_zap.mbn"; + }; +}; + +&gpu_smmu { + status = "okay"; +}; + &mdss0 { status = "okay"; }; From patchwork Wed Jan 24 04:25:22 2024 Content-Type: text/plain; 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Signed-off-by: Bjorn Andersson Reviewed-by: Konrad Dybcio --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index e6cf3e5d63c3..43cd31f30fd2 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -752,6 +752,7 @@ CONFIG_REGULATOR_HI6421V530=y CONFIG_REGULATOR_HI655X=y CONFIG_REGULATOR_MAX77620=y CONFIG_REGULATOR_MAX8973=y +CONFIG_REGULATOR_MAX20411=m CONFIG_REGULATOR_MP8859=y CONFIG_REGULATOR_MT6315=m CONFIG_REGULATOR_MT6357=y