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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org In the RISC-V specification, the stimecmp register doesn't have a default value. To prevent the timer interrupt from being triggered during timer initialization, clear the timer interrupt by writing stimecmp with a maximum value. Signed-off-by: Ley Foon Tan --- drivers/clocksource/timer-riscv.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index e66dcbd66566..a75a74647344 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -172,6 +172,9 @@ static int __init riscv_timer_init_common(void) sched_clock_register(riscv_sched_clock, 64, riscv_timebase); + /* Clear timer interrupt */ + riscv_clock_event_stop(); + error = request_percpu_irq(riscv_clock_event_irq, riscv_timer_interrupt, "riscv-timer", &riscv_clock_event);