From patchwork Fri Jan 26 08:54:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532225 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8324B22EE3; Fri, 26 Jan 2024 08:55:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259341; cv=none; b=t6eLtmOhEGCZq8jJ50tSF9Xsnp5pVPDwoO/n91QYXARy0NGbm77AU307jjIJ9BU4uSbdVQQEE1IeVlJ17fTHGhl5p8RzrYAWs0wUs+qeAUpT6A/w4JF+Q5VzpUL1tnMvD01acwuXEezas+FklPrlrdN5pBSUwHusF7jd6W4lNGY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259341; c=relaxed/simple; bh=1r9bMkN+DuC7eFrI9IMK6ih6tNqjKLC/zGVRio9Us8k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nW2V9evEm99t9YYdoiLbJnmUmVnaTP0Bpqyg98BKsY/6/b3YeJDOJSyvpGjZsw8Dd7uvuk4GbJRMTDT0Dyv7f7wXGjwAvp20dAnySXN+m0ZPPJ/tI+HXfhVShaSs/d4UucuRBo0/yiXPVN/Q0DCKpdjlBFXIxRjSAG2297oK9s0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=SJU5vNT/; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="SJU5vNT/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706259340; x=1737795340; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1r9bMkN+DuC7eFrI9IMK6ih6tNqjKLC/zGVRio9Us8k=; b=SJU5vNT/x77p5DRNOlDKjAC3KeBXzPzWnNIfUlA0LvFY9bdqCs7t+oNS v5o6ixc8vZ1hI2V8xXYojfKu5wyv1KK/QYOugUV4x90mjOIgVn/E8sv9Z iAJLYipnD64TtHjJCNCkR7uUW/dfm7szllrdrOtMLtlqFk9WI7hZbQ/gL KyijfmySl1RSFs5GZlZ1CmyXvJ97yExfwP8wwZ/c3J2rRQxHjOD/DcHUh B2z10NlWN67qF1QB1nh21EzzZMgQZIhEy1hAzgBK3F8s7p+0INMnsLNiM ywijPjJuYCi5sAMdRWrz68j2KMzJOjhX+1w3YaSq0N/jG+fIUpQKHEu8W A==; X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9792030" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9792030" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:55:39 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930309778" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930309778" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:55:34 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com, Kan Liang Subject: [RFC PATCH 01/41] perf: x86/intel: Support PERF_PMU_CAP_VPMU_PASSTHROUGH Date: Fri, 26 Jan 2024 16:54:04 +0800 Message-Id: <20240126085444.324918-2-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Kan Liang Define and apply the PERF_PMU_CAP_VPMU_PASSTHROUGH flag for the version 4 and later PMUs, which includes the improvements for virtualization. Signed-off-by: Kan Liang Signed-off-by: Mingwei Zhang --- arch/x86/events/intel/core.c | 6 ++++++ include/linux/perf_event.h | 1 + 2 files changed, 7 insertions(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index a08f794a0e79..cf790c37757a 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4662,6 +4662,9 @@ static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu) else pmu->pmu.capabilities |= ~PERF_PMU_CAP_AUX_OUTPUT; + if (x86_pmu.version >= 4) + pmu->pmu.capabilities |= PERF_PMU_CAP_VPMU_PASSTHROUGH; + intel_pmu_check_event_constraints(pmu->event_constraints, pmu->num_counters, pmu->num_counters_fixed, @@ -6137,6 +6140,9 @@ __init int intel_pmu_init(void) pr_cont(" AnyThread deprecated, "); } + if (version >= 4) + x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_VPMU_PASSTHROUGH; + /* * Install the hw-cache-events table: */ diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index afb028c54f33..60eff413dbba 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -291,6 +291,7 @@ struct perf_event_pmu_context; #define PERF_PMU_CAP_NO_EXCLUDE 0x0040 #define PERF_PMU_CAP_AUX_OUTPUT 0x0080 #define PERF_PMU_CAP_EXTENDED_HW_TYPE 0x0100 +#define PERF_PMU_CAP_VPMU_PASSTHROUGH 0x0200 struct perf_output_handle; From patchwork Fri Jan 26 08:54:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532226 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 575CF12CDBB; Fri, 26 Jan 2024 08:55:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259347; cv=none; b=WRFOgiEd6EXZVL02zR+b1fU9O1Pt1gx2q2lC36ba/xmiwwIDqEYIMfM0KSsvIXFqJi7y57yl8W31bTkfpSCnCI+m+IRY+JIqvhVW0frabBpLDBTLLTe25VLWTt8HtVjv7bSFbXzgqv0IU7xfdiyTy1bCC5Ie2iYySpiG86d1j8Y= ARC-Message-Signature: i=1; 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d="scan'208";a="930309794" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:55:39 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com, Kan Liang Subject: [RFC PATCH 02/41] perf: Support guest enter/exit interfaces Date: Fri, 26 Jan 2024 16:54:05 +0800 Message-Id: <20240126085444.324918-3-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Kan Liang Currently, the guest and host share the PMU resources when a guest is running. KVM has to create an extra virtual event to simulate the guest's event, which brings several issues, e.g., high overhead, not accuracy and etc. A new pass-through method is proposed to address the issue. It requires that the PMU resources can be fully occupied by the guest while it's running. Two new interfaces are implemented to fulfill the requirement. The hypervisor should invoke the interface while entering/exiting a guest which wants the pass-through PMU capability. The PMU resources should only be temporarily occupied when a guest is running. When the guest is out, the PMU resources are still shared among different users. The exclude_guest event modifier is used to guarantee the exclusive occupation of the PMU resources. When a guest enters, perf forces the exclude_guest capability. If the pre-existing events with !exclude_guest, the events are moved to the error state. The new event-creation of the !exclude_guest event will error out during the period. So the PMU resources can be safely accessed by the guest directly. https://lore.kernel.org/lkml/20231002204017.GB27267@noisy.programming.kicks-ass.net/ Not all PMUs support exclude_guest and vPMU pass-through, e.g., uncore PMU and SW PMU. The guest enter/exit interfaces should only impact the supported PMUs. Add a new PERF_PMU_CAP_VPMU_PASSTHROUGH flag to indicate the PMUs that support the feature. Signed-off-by: Kan Liang Signed-off-by: Mingwei Zhang --- include/linux/perf_event.h | 9 ++ kernel/events/core.c | 174 +++++++++++++++++++++++++++++++++++++ 2 files changed, 183 insertions(+) diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 60eff413dbba..9912d1112371 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -1392,6 +1392,11 @@ static inline int is_exclusive_pmu(struct pmu *pmu) return pmu->capabilities & PERF_PMU_CAP_EXCLUSIVE; } +static inline int has_vpmu_passthrough_cap(struct pmu *pmu) +{ + return pmu->capabilities & PERF_PMU_CAP_VPMU_PASSTHROUGH; +} + extern struct static_key perf_swevent_enabled[PERF_COUNT_SW_MAX]; extern void ___perf_sw_event(u32, u64, struct pt_regs *, u64); @@ -1709,6 +1714,8 @@ extern void perf_event_task_tick(void); extern int perf_event_account_interrupt(struct perf_event *event); extern int perf_event_period(struct perf_event *event, u64 value); extern u64 perf_event_pause(struct perf_event *event, bool reset); +extern void perf_guest_enter(void); +extern void perf_guest_exit(void); #else /* !CONFIG_PERF_EVENTS: */ static inline void * perf_aux_output_begin(struct perf_output_handle *handle, @@ -1795,6 +1802,8 @@ static inline u64 perf_event_pause(struct perf_event *event, bool reset) { return 0; } +static inline void perf_guest_enter(void) { } +static inline void perf_guest_exit(void) { } #endif #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL) diff --git a/kernel/events/core.c b/kernel/events/core.c index 683dc086ef10..59471eeec7e4 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -3803,6 +3803,8 @@ static inline void group_update_userpage(struct perf_event *group_event) event_update_userpage(event); } +static DEFINE_PER_CPU(bool, __perf_force_exclude_guest); + static int merge_sched_in(struct perf_event *event, void *data) { struct perf_event_context *ctx = event->ctx; @@ -3814,6 +3816,14 @@ static int merge_sched_in(struct perf_event *event, void *data) if (!event_filter_match(event)) return 0; + /* + * The __perf_force_exclude_guest indicates entering the guest. + * No events of the passthrough PMU should be scheduled. + */ + if (__this_cpu_read(__perf_force_exclude_guest) && + has_vpmu_passthrough_cap(event->pmu)) + return 0; + if (group_can_go_on(event, *can_add_hw)) { if (!group_sched_in(event, ctx)) list_add_tail(&event->active_list, get_event_list(event)); @@ -5707,6 +5717,165 @@ u64 perf_event_pause(struct perf_event *event, bool reset) } EXPORT_SYMBOL_GPL(perf_event_pause); +static void __perf_force_exclude_guest_pmu(struct perf_event_pmu_context *pmu_ctx, + struct perf_event *event) +{ + struct perf_event_context *ctx = pmu_ctx->ctx; + struct perf_event *sibling; + bool include_guest = false; + + event_sched_out(event, ctx); + if (!event->attr.exclude_guest) + include_guest = true; + for_each_sibling_event(sibling, event) { + event_sched_out(sibling, ctx); + if (!sibling->attr.exclude_guest) + include_guest = true; + } + if (include_guest) { + perf_event_set_state(event, PERF_EVENT_STATE_ERROR); + for_each_sibling_event(sibling, event) + perf_event_set_state(event, PERF_EVENT_STATE_ERROR); + } +} + +static void perf_force_exclude_guest_pmu(struct perf_event_pmu_context *pmu_ctx) +{ + struct perf_event *event, *tmp; + struct pmu *pmu = pmu_ctx->pmu; + + perf_pmu_disable(pmu); + + /* + * Sched out all active events. + * For the !exclude_guest events, they are forced to be sched out and + * moved to the error state. + * For the exclude_guest events, they should be scheduled out anyway + * when the guest is running. + */ + list_for_each_entry_safe(event, tmp, &pmu_ctx->pinned_active, active_list) + __perf_force_exclude_guest_pmu(pmu_ctx, event); + + list_for_each_entry_safe(event, tmp, &pmu_ctx->flexible_active, active_list) + __perf_force_exclude_guest_pmu(pmu_ctx, event); + + pmu_ctx->rotate_necessary = 0; + + perf_pmu_enable(pmu); +} + +static void perf_force_exclude_guest_enter(struct perf_event_context *ctx) +{ + struct perf_event_pmu_context *pmu_ctx; + + update_context_time(ctx); + list_for_each_entry(pmu_ctx, &ctx->pmu_ctx_list, pmu_ctx_entry) { + /* + * The PMU, which doesn't have the capability of excluding guest + * e.g., uncore PMU, is not impacted. + */ + if (!has_vpmu_passthrough_cap(pmu_ctx->pmu)) + continue; + perf_force_exclude_guest_pmu(pmu_ctx); + } +} + +/* + * When a guest enters, force all active events of the PMU, which supports + * the VPMU_PASSTHROUGH feature, to be scheduled out. The events of other + * PMUs, such as uncore PMU, should not be impacted. The guest can + * temporarily own all counters of the PMU. + * During the period, all the creation of the new event of the PMU with + * !exclude_guest are error out. + */ +void perf_guest_enter(void) +{ + struct perf_cpu_context *cpuctx = this_cpu_ptr(&perf_cpu_context); + + lockdep_assert_irqs_disabled(); + + if (__this_cpu_read(__perf_force_exclude_guest)) + return; + + perf_ctx_lock(cpuctx, cpuctx->task_ctx); + + perf_force_exclude_guest_enter(&cpuctx->ctx); + if (cpuctx->task_ctx) + perf_force_exclude_guest_enter(cpuctx->task_ctx); + + perf_ctx_unlock(cpuctx, cpuctx->task_ctx); + + __this_cpu_write(__perf_force_exclude_guest, true); +} +EXPORT_SYMBOL_GPL(perf_guest_enter); + +static void perf_force_exclude_guest_exit(struct perf_event_context *ctx) +{ + struct perf_event_pmu_context *pmu_ctx; + struct pmu *pmu; + + update_context_time(ctx); + list_for_each_entry(pmu_ctx, &ctx->pmu_ctx_list, pmu_ctx_entry) { + pmu = pmu_ctx->pmu; + if (!has_vpmu_passthrough_cap(pmu)) + continue; + + perf_pmu_disable(pmu); + pmu_groups_sched_in(ctx, &ctx->pinned_groups, pmu); + pmu_groups_sched_in(ctx, &ctx->flexible_groups, pmu); + perf_pmu_enable(pmu); + } +} + +void perf_guest_exit(void) +{ + struct perf_cpu_context *cpuctx = this_cpu_ptr(&perf_cpu_context); + + lockdep_assert_irqs_disabled(); + + if (!__this_cpu_read(__perf_force_exclude_guest)) + return; + + __this_cpu_write(__perf_force_exclude_guest, false); + + perf_ctx_lock(cpuctx, cpuctx->task_ctx); + + perf_force_exclude_guest_exit(&cpuctx->ctx); + if (cpuctx->task_ctx) + perf_force_exclude_guest_exit(cpuctx->task_ctx); + + perf_ctx_unlock(cpuctx, cpuctx->task_ctx); +} +EXPORT_SYMBOL_GPL(perf_guest_exit); + +static inline int perf_force_exclude_guest_check(struct perf_event *event, + int cpu, struct task_struct *task) +{ + bool *force_exclude_guest = NULL; + + if (!has_vpmu_passthrough_cap(event->pmu)) + return 0; + + if (event->attr.exclude_guest) + return 0; + + if (cpu != -1) { + force_exclude_guest = per_cpu_ptr(&__perf_force_exclude_guest, cpu); + } else if (task && (task->flags & PF_VCPU)) { + /* + * Just need to check the running CPU in the event creation. If the + * task is moved to another CPU which supports the force_exclude_guest. + * The event will filtered out and be moved to the error stage. See + * merge_sched_in(). + */ + force_exclude_guest = per_cpu_ptr(&__perf_force_exclude_guest, task_cpu(task)); + } + + if (force_exclude_guest && *force_exclude_guest) + return -EBUSY; + return 0; +} + /* * Holding the top-level event's child_mutex means that any * descendant process that has inherited this event will block @@ -11973,6 +12142,11 @@ perf_event_alloc(struct perf_event_attr *attr, int cpu, goto err_ns; } + if (perf_force_exclude_guest_check(event, cpu, task)) { + err = -EBUSY; + goto err_pmu; + } + /* * Disallow uncore-task events. Similarly, disallow uncore-cgroup * events (they don't make sense as the cgroup will be different From patchwork Fri Jan 26 08:54:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532227 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 327A612DD99; Fri, 26 Jan 2024 08:55:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259351; cv=none; b=PIb/nEbXblJIeLdTY6DiQ8gzJUW8NeFZpr0vgANDZrLlZKuTpc4TTMVDig7moRMvqjcnCVvgMEE8CEajarVC8txOiM5M3tpOSN01+mfp3PjSuQcif5AMJ7H3/f0t1B1v3ZmeKwPGa9hnPAfaF0SogEHOhEJm6QE+y8D8Q2/4eWI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259351; c=relaxed/simple; bh=j+/uxe8eBjcxhFKmmV+TNL3Gnvy6/jWawY4A6DrZz/I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=blrLtUXYi9NxA2pLkhfQi2QVImbujXf49bmZuhKrU6iUVMuwRnIDCmXDdxc77DTfngr6o88gEL+x5C7Gh2IX+iZCWY6hY8yvekwCSaXeKdbTw8nSzFFvnmYhQqjQBCNtW28SZusIQel1hKxU1kalT2VIHPDCvxyfM5Gm/E4yhZE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=I6uZZ9jo; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="I6uZZ9jo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706259350; x=1737795350; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=j+/uxe8eBjcxhFKmmV+TNL3Gnvy6/jWawY4A6DrZz/I=; b=I6uZZ9jooCMeYjMCVqPzsdoILxcvguc4p5jjXPeF8TEnpm7RAnt1OH71 YPETNQqpqcCLxY+F+6dfOJWrHG/ZkIqlDMHtGhji4XCqyEADsv+R/OfEB 0d/x+V356ZdJJsM+5dRzQ8sYnXjAhbupZKfx1jzZQ+qGhUW/hmKUAe4Te CyqDjejELDTc1BlwkUgZf5Z2LGxdS9s0kVGamyZaJyoPAPJVBpWwheP8P I1vF04JXeHvF/A9RjFpe0Y6u/TymfYaV2hi4/p5NbHXOZinnUjhvgv4BQ SMjhfzCK/ejkMXTQyFH+Payb1hmYKBEdWHKigQfwLM+Kc1M6AXqEu/JRv Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9792066" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9792066" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:55:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930309817" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930309817" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:55:44 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com, Xiong Zhang Subject: [RFC PATCH 03/41] perf: Set exclude_guest onto nmi_watchdog Date: Fri, 26 Jan 2024 16:54:06 +0800 Message-Id: <20240126085444.324918-4-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Xiong Zhang The perf event for NMI watchdog is per cpu pinned system wide event, if such event doesn't have exclude_guest flag, it will be put into error state once guest with passthrough PMU starts, this breaks NMI watchdog function totally. This commit adds exclude_guest flag for this perf event, so this perf event is stopped during VM running, but it will continue working after VM exit. In this way the NMI watchdog can not detect hardlockups during VM running, it still breaks NMI watchdog function a bit. But host perf event must be stopped during VM with passthrough PMU running, current no other reliable method can be used to replace perf event for NMI watchdog. Signed-off-by: Xiong Zhang Signed-off-by: Mingwei Zhang --- kernel/watchdog_perf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/watchdog_perf.c b/kernel/watchdog_perf.c index 8ea00c4a24b2..c8ba656ff674 100644 --- a/kernel/watchdog_perf.c +++ b/kernel/watchdog_perf.c @@ -88,6 +88,7 @@ static struct perf_event_attr wd_hw_attr = { .size = sizeof(struct perf_event_attr), .pinned = 1, .disabled = 1, + .exclude_guest = 1, }; /* Callback function for perf event subsystem */ From patchwork Fri Jan 26 08:54:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532228 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DFFB24A13; Fri, 26 Jan 2024 08:55:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259357; cv=none; b=AT5vE/6+uCnYDcFptXotY4A2a8rO6k6J+0sLX2agnh/2HrdokHpAxVwL2acMEZ+0gjFOjp360l8aukPBKAPuJPqEZ8nTOOt3yo9ovvUHf6BO+Wk4k3yKEzrAef/qDVRCLnIN0YOZz9Lpp5PsHkYZZrPrMNZff2kEBt6AxeMhF6k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259357; c=relaxed/simple; bh=vQKsd3FKHlP9/WxLnOHpK3oqY7sIOL0lcUsvNFfgQE0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=O6o8QIShn6itGCX544Sg48vZwq4dPRf1Skd1iHXqDDf+g0Q1fdNRGKgCwqZyVYxQyHBsZE94M+hivgO/nHqrDOL1GucDKitok7s9PMPSeMpKhh0GESeC8fNhrHInDDpj7ujnIVgx1A0U9xj+v5+4JJLNIzLlt2/HLbjnixiscqE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=d/u2KDQK; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="d/u2KDQK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706259356; x=1737795356; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vQKsd3FKHlP9/WxLnOHpK3oqY7sIOL0lcUsvNFfgQE0=; b=d/u2KDQKjFo7OJ4Z0VqSxU6dvk5BTUXIM7VWK9OSERsIVL6vcFgq0ERL 5nX5Sdn/RA0CAc0Pwke0cMPgQLZOm+WIj/iBt9pw9BdBwJtX5gnoqma0i aSss9gH0K1PrHQQbVP0Rxq/bXUbtDVUZtKLsq1J+Cn9KT/Sf90rkCg5oY F2tp3gMfQb7/NZmsg1uGzRuKFXEzCDk8pv0lB3EUhdubMVrUldIhb323L ec5lOF2BRClFdKnl5GjROdELmrrXKk4oFKyc4CtFId7xYn4oXG3AU8AYs fYbhnq1Xumbym3Wpam+j8bc1m+YzeHdTxXlE7Y81gXTOxbHz6DWvRWFK1 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9792085" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9792085" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:55:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930309830" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930309830" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:55:49 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com, Xiong Zhang Subject: [RFC PATCH 04/41] perf: core/x86: Add support to register a new vector for PMI handling Date: Fri, 26 Jan 2024 16:54:07 +0800 Message-Id: <20240126085444.324918-5-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Xiong Zhang Create a new vector in the host IDT for PMI handling within a passthrough vPMU implementation. In addition, add a function to allow the registration of the handler and a function to switch the PMI handler. This is the preparation work to support KVM passthrough vPMU to handle its own PMIs without interference from PMI handler of the host PMU. Signed-off-by: Xiong Zhang Signed-off-by: Mingwei Zhang --- arch/x86/include/asm/hardirq.h | 1 + arch/x86/include/asm/idtentry.h | 1 + arch/x86/include/asm/irq.h | 1 + arch/x86/include/asm/irq_vectors.h | 2 +- arch/x86/kernel/idt.c | 1 + arch/x86/kernel/irq.c | 29 ++++++++++++++++++++++++ tools/arch/x86/include/asm/irq_vectors.h | 1 + 7 files changed, 35 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/hardirq.h b/arch/x86/include/asm/hardirq.h index 66837b8c67f1..c1e2c1a480bf 100644 --- a/arch/x86/include/asm/hardirq.h +++ b/arch/x86/include/asm/hardirq.h @@ -19,6 +19,7 @@ typedef struct { unsigned int kvm_posted_intr_ipis; unsigned int kvm_posted_intr_wakeup_ipis; unsigned int kvm_posted_intr_nested_ipis; + unsigned int kvm_vpmu_pmis; #endif unsigned int x86_platform_ipis; /* arch dependent */ unsigned int apic_perf_irqs; diff --git a/arch/x86/include/asm/idtentry.h b/arch/x86/include/asm/idtentry.h index 05fd175cec7d..d1b58366bc21 100644 --- a/arch/x86/include/asm/idtentry.h +++ b/arch/x86/include/asm/idtentry.h @@ -675,6 +675,7 @@ DECLARE_IDTENTRY_SYSVEC(IRQ_WORK_VECTOR, sysvec_irq_work); DECLARE_IDTENTRY_SYSVEC(POSTED_INTR_VECTOR, sysvec_kvm_posted_intr_ipi); DECLARE_IDTENTRY_SYSVEC(POSTED_INTR_WAKEUP_VECTOR, sysvec_kvm_posted_intr_wakeup_ipi); DECLARE_IDTENTRY_SYSVEC(POSTED_INTR_NESTED_VECTOR, sysvec_kvm_posted_intr_nested_ipi); +DECLARE_IDTENTRY_SYSVEC(KVM_VPMU_VECTOR, sysvec_kvm_vpmu_handler); #endif #if IS_ENABLED(CONFIG_HYPERV) diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index 836c170d3087..ee268f42d04a 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h @@ -31,6 +31,7 @@ extern void fixup_irqs(void); #ifdef CONFIG_HAVE_KVM extern void kvm_set_posted_intr_wakeup_handler(void (*handler)(void)); +extern void kvm_set_vpmu_handler(void (*handler)(void)); #endif extern void (*x86_platform_ipi_callback)(void); diff --git a/arch/x86/include/asm/irq_vectors.h b/arch/x86/include/asm/irq_vectors.h index 3a19904c2db6..120403572307 100644 --- a/arch/x86/include/asm/irq_vectors.h +++ b/arch/x86/include/asm/irq_vectors.h @@ -77,7 +77,7 @@ */ #define IRQ_WORK_VECTOR 0xf6 -/* 0xf5 - unused, was UV_BAU_MESSAGE */ +#define KVM_VPMU_VECTOR 0xf5 #define DEFERRED_ERROR_VECTOR 0xf4 /* Vector on which hypervisor callbacks will be delivered */ diff --git a/arch/x86/kernel/idt.c b/arch/x86/kernel/idt.c index 8857abc706e4..6944eec251f4 100644 --- a/arch/x86/kernel/idt.c +++ b/arch/x86/kernel/idt.c @@ -157,6 +157,7 @@ static const __initconst struct idt_data apic_idts[] = { INTG(POSTED_INTR_VECTOR, asm_sysvec_kvm_posted_intr_ipi), INTG(POSTED_INTR_WAKEUP_VECTOR, asm_sysvec_kvm_posted_intr_wakeup_ipi), INTG(POSTED_INTR_NESTED_VECTOR, asm_sysvec_kvm_posted_intr_nested_ipi), + INTG(KVM_VPMU_VECTOR, asm_sysvec_kvm_vpmu_handler), # endif # ifdef CONFIG_IRQ_WORK INTG(IRQ_WORK_VECTOR, asm_sysvec_irq_work), diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c index 11761c124545..c6cffb34191b 100644 --- a/arch/x86/kernel/irq.c +++ b/arch/x86/kernel/irq.c @@ -181,6 +181,13 @@ int arch_show_interrupts(struct seq_file *p, int prec) seq_printf(p, "%10u ", irq_stats(j)->kvm_posted_intr_wakeup_ipis); seq_puts(p, " Posted-interrupt wakeup event\n"); + + seq_printf(p, "%*s: ", prec, "VPMU"); + for_each_online_cpu(j) + seq_printf(p, "%10u ", + irq_stats(j)->kvm_vpmu_pmis); + seq_puts(p, " PT PMU PMI\n"); + #endif return 0; } @@ -293,6 +300,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_x86_platform_ipi) #ifdef CONFIG_HAVE_KVM static void dummy_handler(void) {} static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler; +static void (*kvm_vpmu_handler)(void) = dummy_handler; void kvm_set_posted_intr_wakeup_handler(void (*handler)(void)) { @@ -305,6 +313,17 @@ void kvm_set_posted_intr_wakeup_handler(void (*handler)(void)) } EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wakeup_handler); +void kvm_set_vpmu_handler(void (*handler)(void)) +{ + if (handler) + kvm_vpmu_handler = handler; + else { + kvm_vpmu_handler = dummy_handler; + synchronize_rcu(); + } +} +EXPORT_SYMBOL_GPL(kvm_set_vpmu_handler); + /* * Handler for POSTED_INTERRUPT_VECTOR. */ @@ -332,6 +351,16 @@ DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm_posted_intr_nested_ipi) apic_eoi(); inc_irq_stat(kvm_posted_intr_nested_ipis); } + +/* + * Handler for KVM_PT_PMU_VECTOR. + */ +DEFINE_IDTENTRY_SYSVEC(sysvec_kvm_vpmu_handler) +{ + apic_eoi(); + inc_irq_stat(kvm_vpmu_pmis); + kvm_vpmu_handler(); +} #endif diff --git a/tools/arch/x86/include/asm/irq_vectors.h b/tools/arch/x86/include/asm/irq_vectors.h index 3a19904c2db6..3773e60f1af8 100644 --- a/tools/arch/x86/include/asm/irq_vectors.h +++ b/tools/arch/x86/include/asm/irq_vectors.h @@ -85,6 +85,7 @@ /* Vector for KVM to deliver posted interrupt IPI */ #ifdef CONFIG_HAVE_KVM +#define KVM_VPMU_VECTOR 0xf5 #define POSTED_INTR_VECTOR 0xf2 #define POSTED_INTR_WAKEUP_VECTOR 0xf1 #define POSTED_INTR_NESTED_VECTOR 0xf0 From patchwork Fri Jan 26 08:54:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532229 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52B8912FF79; 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X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9792098" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9792098" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:56:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930309850" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930309850" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:55:55 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com, Xiong Zhang Subject: [RFC PATCH 05/41] KVM: x86/pmu: Register PMI handler for passthrough PMU Date: Fri, 26 Jan 2024 16:54:08 +0800 Message-Id: <20240126085444.324918-6-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Xiong Zhang Add function to register/unregister PMI handler at KVM module initialization and destroy time. This allows the host PMU with passthough capability enabled switch PMI handler at PMU context switch time. Signed-off-by: Xiong Zhang Signed-off-by: Mingwei Zhang --- arch/x86/kvm/x86.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 2c924075f6f1..4432e736129f 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -10611,6 +10611,18 @@ void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) } EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); +void kvm_passthrough_pmu_handler(void) +{ + struct kvm_vcpu *vcpu = kvm_get_running_vcpu(); + + if (!vcpu) { + pr_warn_once("%s: no running vcpu found!\n", __func__); + return; + } + + kvm_make_request(KVM_REQ_PMI, vcpu); +} + /* * Called within kvm->srcu read side. * Returns 1 to let vcpu_run() continue the guest execution loop without @@ -13815,6 +13827,7 @@ static int __init kvm_x86_init(void) { kvm_mmu_x86_module_init(); mitigate_smt_rsb &= boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible(); + kvm_set_vpmu_handler(kvm_passthrough_pmu_handler); return 0; } module_init(kvm_x86_init); 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d="scan'208";a="930309897" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:56:00 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com, Xiong Zhang Subject: [RFC PATCH 06/41] perf: x86: Add function to switch PMI handler Date: Fri, 26 Jan 2024 16:54:09 +0800 Message-Id: <20240126085444.324918-7-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Xiong Zhang Add function to switch PMI handler since passthrough PMU and host PMU will use different interrupt vectors. Signed-off-by: Xiong Zhang Signed-off-by: Mingwei Zhang --- arch/x86/events/core.c | 15 +++++++++++++++ arch/x86/include/asm/perf_event.h | 3 +++ 2 files changed, 18 insertions(+) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 40ad1425ffa2..3f87894d8c8e 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -701,6 +701,21 @@ struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data) } EXPORT_SYMBOL_GPL(perf_guest_get_msrs); +void perf_guest_switch_to_host_pmi_vector(void) +{ + lockdep_assert_irqs_disabled(); + + apic_write(APIC_LVTPC, APIC_DM_NMI); +} +EXPORT_SYMBOL_GPL(perf_guest_switch_to_host_pmi_vector); + +void perf_guest_switch_to_kvm_pmi_vector(void) +{ + lockdep_assert_irqs_disabled(); + + apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_VPMU_VECTOR); +} +EXPORT_SYMBOL_GPL(perf_guest_switch_to_kvm_pmi_vector); /* * There may be PMI landing after enabled=0. The PMI hitting could be before or * after disable_all. diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 2618ec7c3d1d..021ab362a061 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -573,6 +573,9 @@ static inline void perf_events_lapic_init(void) { } static inline void perf_check_microcode(void) { } #endif +extern void perf_guest_switch_to_host_pmi_vector(void); +extern void perf_guest_switch_to_kvm_pmi_vector(void); + #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL) extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data); extern void x86_perf_get_lbr(struct x86_pmu_lbr *lbr); From patchwork Fri Jan 26 08:54:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532231 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 802EC137C42; Fri, 26 Jan 2024 08:56:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259373; cv=none; b=hcHKQF2SIbi26xtb+7ZXGvSl3+hZdRyzuSrMkoMdObVQWm4/iKzbof0sSVDemMkXFoNCAWZ31cFPIcGD6xehDvM51W/2STNcN76xM0St5YWMq1xdSNxuDjhF60fx6fC9IkqSPhJ+1k9UFM0hUazGZ4p/VZnc971f72f5xMZ0MGE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259373; c=relaxed/simple; bh=54n0IWcah7YMnjD6TUF3R2BJoZpEbfLCDMdkjoA+y3o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=g6B8LmW2oSZabohaH8WPF/ktZT4iCnlt1USw4erPwjD9q6xpIr0d73L2+EToQm8WoRCg9uYVm9NG/novJmUla/OxcRUEdinZXsuAvgXDKaBPbOAL8bXwnbapOg1dBXeghD9YcwrxskICC/tF3g7gA23IbLdziY9w71Ishj9pMw4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=GLIs00vw; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="GLIs00vw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706259372; x=1737795372; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=54n0IWcah7YMnjD6TUF3R2BJoZpEbfLCDMdkjoA+y3o=; b=GLIs00vwmZUqDp1H2fIi9xNFQkkw8Ixd8rr6zySyQDtiZJJOeRSpJa8Y bWeymP8+ZzhHs1ZcOG7n6aEOjMpSOnyg/TtmR/EcluP9teRxZn1zLFQvP fq4pWyDjCF9m4/PXfUbZmNYi/+3bO1O16SbRF2/N6VCDeLN4DmRkrnsxh 5Q122Jrowq/+YTrtdjnpmmb+jmXVAXKGfpQ32nXQmtRZCYnAGagopf+4J czdgoS1uDIFdVvW9U2bZtTsm9PY1xc5NZNSzCCTqwcHY3HdNdtOSlp6Nh MzRinM2TjcCPcRcqHxEpEdbh5XGlHxZM1oXyAMU9sgtYPj2iOJqDUaMYa Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9792118" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9792118" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:56:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930309918" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930309918" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:56:06 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com, Xiong Zhang Subject: [RFC PATCH 07/41] perf/x86: Add interface to reflect virtual LVTPC_MASK bit onto HW Date: Fri, 26 Jan 2024 16:54:10 +0800 Message-Id: <20240126085444.324918-8-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Xiong Zhang When guest clear LVTPC_MASK bit in guest PMI handler at PMU passthrough mode, this bit should be reflected onto HW, otherwise HW couldn't generate PMI again during VM running until it is cleared. This commit set HW LVTPC_MASK bit at PMU vecctor switching to KVM PMI vector. Signed-off-by: Xiong Zhang Signed-off-by: Mingwei Zhang --- arch/x86/events/core.c | 9 +++++++-- arch/x86/include/asm/perf_event.h | 2 +- arch/x86/kvm/lapic.h | 1 - 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 3f87894d8c8e..ece042cfb470 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -709,13 +709,18 @@ void perf_guest_switch_to_host_pmi_vector(void) } EXPORT_SYMBOL_GPL(perf_guest_switch_to_host_pmi_vector); -void perf_guest_switch_to_kvm_pmi_vector(void) +void perf_guest_switch_to_kvm_pmi_vector(bool mask) { lockdep_assert_irqs_disabled(); - apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_VPMU_VECTOR); + if (mask) + apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_VPMU_VECTOR | + APIC_LVT_MASKED); + else + apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_VPMU_VECTOR); } EXPORT_SYMBOL_GPL(perf_guest_switch_to_kvm_pmi_vector); + /* * There may be PMI landing after enabled=0. The PMI hitting could be before or * after disable_all. diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 021ab362a061..180d63ba2f46 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -574,7 +574,7 @@ static inline void perf_check_microcode(void) { } #endif extern void perf_guest_switch_to_host_pmi_vector(void); -extern void perf_guest_switch_to_kvm_pmi_vector(void); +extern void perf_guest_switch_to_kvm_pmi_vector(bool mask); #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL) extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data); diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h index 0a0ea4b5dd8c..e30641d5ac90 100644 --- a/arch/x86/kvm/lapic.h +++ b/arch/x86/kvm/lapic.h @@ -277,5 +277,4 @@ static inline u8 kvm_xapic_id(struct kvm_lapic *apic) { return kvm_lapic_get_reg(apic, APIC_ID) >> 24; } - #endif From patchwork Fri Jan 26 08:54:11 2024 Content-Type: text/plain; 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X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9792137" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9792137" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:56:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930309950" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930309950" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:56:11 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com, Xiong Zhang Subject: [RFC PATCH 08/41] KVM: x86/pmu: Add get virtual LVTPC_MASK bit function Date: Fri, 26 Jan 2024 16:54:11 +0800 Message-Id: <20240126085444.324918-9-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Xiong Zhang On PMU passthrough mode, guest virtual LVTPC_MASK bit must be reflected onto HW, especially when guest clear it, the HW bit should be cleared also. Otherwise processor can't generate PMI until the HW mask bit is cleared. This commit add a function to get virtual LVTPC_MASK bit, so that it can be set onto HW later. Signed-off-by: Xiong Zhang --- arch/x86/kvm/lapic.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h index e30641d5ac90..dafae44325d1 100644 --- a/arch/x86/kvm/lapic.h +++ b/arch/x86/kvm/lapic.h @@ -277,4 +277,10 @@ static inline u8 kvm_xapic_id(struct kvm_lapic *apic) { return kvm_lapic_get_reg(apic, APIC_ID) >> 24; } + +static inline bool kvm_lapic_get_lvtpc_mask(struct kvm_vcpu *vcpu) +{ + return lapic_in_kernel(vcpu) && + (kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVTPC) & APIC_LVT_MASKED); +} #endif From patchwork Fri Jan 26 08:54:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532233 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC77713B793; Fri, 26 Jan 2024 08:56:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259383; cv=none; b=XjAMgP8CAlyKXI687umrdMeSWDw4/OzDCY+sOfHlPAGeuXKYMYzSBgKwHjPHRBOxFvXTbL2w6LXO0Wx/XfIOua8pocVJR+fj4rp/2epG9ujwWki73sU+gDak3sEaQ741F2IC60lTQw/LKWZOdCSQp/QSLU3sUM+jC53Msk5DZpo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259383; c=relaxed/simple; bh=FNmnze51sS7ZRAsHO2TuBSH6BpqRtE5lEtl2KmvnGcA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qjF9+q535UMfVj7grO69igtWyJfPTrli6INiwMG8tvliz6G+gvjOsG2cusFmrH1OOExDXEtJWlMC5bwX/qM5rxOOfqsRfOCAJBID57wJVsEYs9+HB4B3XMS77HTVEtjHQ8XCnKMji3pVEdmrlfi+ChWyN0YtsRJyXyQkWa81ors= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=g7EmKPeY; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="g7EmKPeY" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706259382; x=1737795382; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FNmnze51sS7ZRAsHO2TuBSH6BpqRtE5lEtl2KmvnGcA=; b=g7EmKPeYYSDTkZ4GwviWXzK949kai9aDfRm7jnXcPzSGhi3o8ppL0I7O oUwkiaKvGdVQo2O50EEIRFzuax6aPSDZDN56RQLK6FGdZ+lmN5VXTi8bK FMHwSlqTTD3dptqanwfKHFTPOxYtSHzqWN3+vGAuLB4QH3zdXYlqUFQC5 wI0ZviRvEQqJVpXHPlbu45hU3C8yiwnWlDXMuubCbkhNHZSpB5sZa8KBk rHguxyo8QeAC2u4wFJCs9/sXmCUFekqOPMkV71JFvs9cf9YSgl1Argjn9 cPRVNu/Xbywq+pvUfyWjdr3lRJOhIcGgZs97M6YYJyj75YvxbE00rLBVf g==; X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9792154" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9792154" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:56:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930309964" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930309964" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:56:16 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com Subject: [RFC PATCH 09/41] perf: core/x86: Forbid PMI handler when guest own PMU Date: Fri, 26 Jan 2024 16:54:12 +0800 Message-Id: <20240126085444.324918-10-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mingwei Zhang If a guest PMI is delivered after VM-exit, the KVM maskable interrupt will be held pending until EFLAGS.IF is set. In the meantime, if the logical processor receives an NMI for any reason at all, perf_event_nmi_handler() will be invoked. If there is any active perf event anywhere on the system, x86_pmu_handle_irq() will be invoked, and it will clear IA32_PERF_GLOBAL_STATUS. By the time KVM's PMI handler is invoked, it will be a mystery which counter(s) overflowed. When LVTPC is using KVM PMI vecotr, PMU is owned by guest, Host NMI let x86_pmu_handle_irq() run, x86_pmu_handle_irq() restore PMU vector to NMI and clear IA32_PERF_GLOBAL_STATUS, this breaks guest vPMU passthrough environment. So modify perf_event_nmi_handler() to check perf_is_in_guest_pasthrough(), and if so, to simply return without calling x86_pmu_handle_irq(). Suggested-by: Jim Mattson Signed-off-by: Mingwei Zhang --- arch/x86/events/core.c | 17 +++++++++++++++++ include/linux/perf_event.h | 1 + kernel/events/core.c | 5 +++++ 3 files changed, 23 insertions(+) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index ece042cfb470..20a5ccc641b9 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -1752,6 +1752,23 @@ perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) u64 finish_clock; int ret; + /* + * When PMU is pass-through into guest, this handler should be forbidden from + * running, the reasons are: + * 1. After perf_guest_switch_to_kvm_pmi_vector() is called, and before cpu + * enter into non-root mode, NMI could happen, but x86_pmu_handle_irq() + * restore PMU to use NMI vector, which destroy KVM PMI vector setting. + * 2. When VM is running, host NMI other than PMI causes VM exit, KVM will + * call host NMI handler (vmx_vcpu_enter_exit()) first before KVM save + * guest PMU context (kvm_pmu_save_pmu_context()), as x86_pmu_handle_irq() + * clear global_status MSR which has guest status now, then this destroy + * guest PMU status. + * 3. After VM exit, but before KVM save guest PMU context, host NMI other + * than PMI could happen, x86_pmu_handle_irq() clear global_status MSR + * which has guest status now, then this destroy guest PMU status. + */ + if (perf_is_in_guest_passthrough()) + return 0; /* * All PMUs/events that share this PMI handler should make sure to * increment active_events for their events. diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 9912d1112371..6cfa0f5ac120 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -1716,6 +1716,7 @@ extern int perf_event_period(struct perf_event *event, u64 value); extern u64 perf_event_pause(struct perf_event *event, bool reset); extern void perf_guest_enter(void); extern void perf_guest_exit(void); +extern bool perf_is_in_guest_passthrough(void); #else /* !CONFIG_PERF_EVENTS: */ static inline void * perf_aux_output_begin(struct perf_output_handle *handle, diff --git a/kernel/events/core.c b/kernel/events/core.c index 59471eeec7e4..00ea2705444e 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -5848,6 +5848,11 @@ void perf_guest_exit(void) } EXPORT_SYMBOL_GPL(perf_guest_exit); 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d="scan'208";a="930309979" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:56:21 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com Subject: [RFC PATCH 10/41] perf: core/x86: Plumb passthrough PMU capability from x86_pmu to x86_pmu_cap Date: Fri, 26 Jan 2024 16:54:13 +0800 Message-Id: <20240126085444.324918-11-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mingwei Zhang Plumb passthrough PMU capability to x86_pmu_cap in order to let any kernel entity such as KVM know that host PMU support passthrough PMU mode and has the implementation. Signed-off-by: Mingwei Zhang --- arch/x86/events/core.c | 1 + arch/x86/events/intel/core.c | 4 +++- arch/x86/events/perf_event.h | 1 + arch/x86/include/asm/perf_event.h | 1 + 4 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 20a5ccc641b9..d2b7aa5b7876 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -3026,6 +3026,7 @@ void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) cap->events_mask = (unsigned int)x86_pmu.events_maskl; cap->events_mask_len = x86_pmu.events_mask_len; cap->pebs_ept = x86_pmu.pebs_ept; + cap->passthrough = !!(x86_pmu.flags & PMU_FL_PASSTHROUGH); } EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index cf790c37757a..727ee64bb566 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -6140,8 +6140,10 @@ __init int intel_pmu_init(void) pr_cont(" AnyThread deprecated, "); } - if (version >= 4) + if (version >= 4) { + x86_pmu.flags |= PMU_FL_PASSTHROUGH; x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_VPMU_PASSTHROUGH; + } /* * Install the hw-cache-events table: diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 53dd5d495ba6..39c58a3f5a6b 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -1012,6 +1012,7 @@ do { \ #define PMU_FL_INSTR_LATENCY 0x80 /* Support Instruction Latency in PEBS Memory Info Record */ #define PMU_FL_MEM_LOADS_AUX 0x100 /* Require an auxiliary event for the complete memory info */ #define PMU_FL_RETIRE_LATENCY 0x200 /* Support Retire Latency in PEBS */ +#define PMU_FL_PASSTHROUGH 0x400 /* Support passthrough mode */ #define EVENT_VAR(_id) event_attr_##_id #define EVENT_PTR(_id) &event_attr_##_id.attr.attr diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 180d63ba2f46..400727b27634 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -254,6 +254,7 @@ struct x86_pmu_capability { unsigned int events_mask; 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26 Jan 2024 00:56:26 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com, Xiong Zhang Subject: [RFC PATCH 11/41] KVM: x86/pmu: Introduce enable_passthrough_pmu module parameter and propage to KVM instance Date: Fri, 26 Jan 2024 16:54:14 +0800 Message-Id: <20240126085444.324918-12-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mingwei Zhang Introduce enable_passthrough_pmu as a RO KVM kernel module parameter. This variable is true only when the following conditions satisfies: - set to true when module loaded. - enable_pmu is true. - is running on Intel CPU. - supports PerfMon v4. - host PMU supports passthrough mode. The value is always read-only because passthrough PMU currently does not support features like LBR and PEBS, while emualted PMU does. This will end up with two different values for kvm_cap.supported_perf_cap, which is initialized at module load time. Maintaining two different perf capabilities will add complexity. Further, there is not enough motivation to support running two types of PMU implementations at the same time, although it is possible/feasible in reality. Finally, always propagate enable_passthrough_pmu and perf_capabilities into kvm->arch for each KVM instance. Co-developed-by: Xiong Zhang Signed-off-by: Xiong Zhang Signed-off-by: Mingwei Zhang --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/pmu.h | 14 ++++++++++++++ arch/x86/kvm/vmx/vmx.c | 5 +++-- arch/x86/kvm/x86.c | 9 +++++++++ arch/x86/kvm/x86.h | 1 + 5 files changed, 28 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index d7036982332e..f2e73e6830a3 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1371,6 +1371,7 @@ struct kvm_arch { bool bus_lock_detection_enabled; bool enable_pmu; + bool enable_passthrough_pmu; u32 notify_window; u32 notify_vmexit_flags; diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 1d64113de488..51011603c799 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -208,6 +208,20 @@ static inline void kvm_init_pmu_capability(const struct kvm_pmu_ops *pmu_ops) enable_pmu = false; } + /* Pass-through vPMU is only supported in Intel CPUs. */ + if (!is_intel) + enable_passthrough_pmu = false; + + /* + * Pass-through vPMU requires at least PerfMon version 4 because the + * implementation requires the usage of MSR_CORE_PERF_GLOBAL_STATUS_SET + * for counter emulation as well as PMU context switch. In addition, it + * requires host PMU support on passthrough mode. Disable pass-through + * vPMU if any condition fails. + */ + if (!enable_pmu || kvm_pmu_cap.version < 4 || !kvm_pmu_cap.passthrough) + enable_passthrough_pmu = false; + if (!enable_pmu) { memset(&kvm_pmu_cap, 0, sizeof(kvm_pmu_cap)); return; diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index be20a60047b1..e4610b80e519 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7835,13 +7835,14 @@ static u64 vmx_get_perf_capabilities(void) if (boot_cpu_has(X86_FEATURE_PDCM)) rdmsrl(MSR_IA32_PERF_CAPABILITIES, host_perf_cap); - if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR)) { + if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR) && + !enable_passthrough_pmu) { x86_perf_get_lbr(&lbr); if (lbr.nr) perf_cap |= host_perf_cap & PMU_CAP_LBR_FMT; } - if (vmx_pebs_supported()) { + if (vmx_pebs_supported() && !enable_passthrough_pmu) { perf_cap |= host_perf_cap & PERF_CAP_PEBS_MASK; if ((perf_cap & PERF_CAP_PEBS_FORMAT) < 4) perf_cap &= ~PERF_CAP_PEBS_BASELINE; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 4432e736129f..074452aa700d 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -193,6 +193,11 @@ bool __read_mostly enable_pmu = true; EXPORT_SYMBOL_GPL(enable_pmu); module_param(enable_pmu, bool, 0444); +/* Enable/disable PMU virtualization */ +bool __read_mostly enable_passthrough_pmu = true; +EXPORT_SYMBOL_GPL(enable_passthrough_pmu); +module_param(enable_passthrough_pmu, bool, 0444); + bool __read_mostly eager_page_split = true; module_param(eager_page_split, bool, 0644); @@ -6553,6 +6558,9 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm, mutex_lock(&kvm->lock); if (!kvm->created_vcpus) { kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE); + /* Disable passthrough PMU if enable_pmu is false. */ + if (!kvm->arch.enable_pmu) + kvm->arch.enable_passthrough_pmu = false; r = 0; } mutex_unlock(&kvm->lock); @@ -12480,6 +12488,7 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) kvm->arch.default_tsc_khz = max_tsc_khz ? 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Note that enabling PMU is decided by VMM when it sets the CPUID bits exposed to guest VM. So plumb through the enabling for each pmu in intel_pmu_refresh(). Co-developed-by: Xiong Zhang Signed-off-by: Xiong Zhang Signed-off-by: Mingwei Zhang --- arch/x86/include/asm/kvm_host.h | 2 ++ arch/x86/kvm/pmu.c | 1 + arch/x86/kvm/vmx/pmu_intel.c | 10 ++++++++-- 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index f2e73e6830a3..ede45c923089 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -575,6 +575,8 @@ struct kvm_pmu { * redundant check before cleanup if guest don't use vPMU at all. */ u8 event_count; + + bool passthrough; }; struct kvm_pmu_ops; diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 9ae07db6f0f6..1853739a59bf 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -665,6 +665,7 @@ void kvm_pmu_init(struct kvm_vcpu *vcpu) static_call(kvm_x86_pmu_init)(vcpu); pmu->event_count = 0; pmu->need_cleanup = false; + pmu->passthrough = false; kvm_pmu_refresh(vcpu); } diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 820d3e1f6b4f..15cc107ed573 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -517,14 +517,20 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) return; 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d="scan'208";a="9792254" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:56:42 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930310035" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930310035" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:56:36 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com Subject: [RFC PATCH 13/41] KVM: x86/pmu: Add a helper to check if passthrough PMU is enabled Date: Fri, 26 Jan 2024 16:54:16 +0800 Message-Id: <20240126085444.324918-14-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mingwei Zhang Add a helper to check if passthrough PMU is enabled for convenience as it is vendor neutral. Signed-off-by: Mingwei Zhang --- arch/x86/kvm/pmu.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 51011603c799..28beae0f9209 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -267,6 +267,11 @@ static inline bool pmc_is_globally_enabled(struct kvm_pmc *pmc) return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl); } +static inline bool is_passthrough_pmu_enabled(struct kvm_vcpu *vcpu) +{ + return vcpu_to_pmu(vcpu)->passthrough; +} + void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu); void kvm_pmu_handle_event(struct kvm_vcpu *vcpu); int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); From patchwork Fri Jan 26 08:54:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532238 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23BA910A0F; Fri, 26 Jan 2024 08:56:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259412; cv=none; b=TB8PJLWiqjwseo736AK/haPzw++RBu0x/uWcm9p1Q+MydzdURLhRl0m/Ci9xu9E38beVFHqvTpOahLLFSz6IfX2DYSxhyxPWeEzjnzLh6prErdL7t1BR5l4M4gzMfWg6G+ZWGHJA7uDkzWBGN2hJseng6zWoG0MrgVaM6lfhsqM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259412; c=relaxed/simple; bh=QglvaqOiccK1QoUItcblJF4VkLMkGcShw3WGx+q7c0A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=g3zcOGotuFu8ibhhmCj1myU5tFVqxOC1A6GooKeHDozh4MiWbo7Fxh8LYwrnh2fVBWbljuFiWKnL7OX5pOjwx9oxP/bWNPQeQtStqPRrLvV99Pv2ojI8PLsR2uaM9kHbRCiusf46nxzP6MMg8l0Z0/NdYi161OqsObr7di6avSQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ZDZEQGzx; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ZDZEQGzx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706259411; x=1737795411; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QglvaqOiccK1QoUItcblJF4VkLMkGcShw3WGx+q7c0A=; b=ZDZEQGzxB+DwqHhS/sTqW3jq9MTYXu33vQCrVeR4jMhp8b5VOGKQ2jgO ZtAQH+nGl0189cdIphReGwB66YfMjoG9pUUeA+uXG26tDoRofOheNWy1C IoWuW50m0ntHr/9cf5fxXYR79whdfi5OY3z0s9/2p2hOHb5PcdNCXYkcI YpnQJ+WrJ+m/OrVa8BxkbAW792gxrBJL/Edi1HuDwyCk3eOtsuX6vCyKN IZyYvQCVsMblvmCU88iL8K703xXWbWaPyRTzjC7lCUKZUmp4ddDIEl6Or 7zqzsETNOWxzaZMLKIVoBSWY0VNvQjh6Iyw0yplyCrBa3CAVlmgBeTmfE w==; X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9792278" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9792278" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:56:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930310047" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930310047" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:56:41 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com, Xiong Zhang Subject: [RFC PATCH 14/41] KVM: x86/pmu: Allow RDPMC pass through Date: Fri, 26 Jan 2024 16:54:17 +0800 Message-Id: <20240126085444.324918-15-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mingwei Zhang Clear RDPMC_EXITING in vmcs cpu based execution control to allow rdpmc instruction to proceed without VMEXIT. This gives performance to passthrough PMU. Clear RDPMC in vmx_vcpu_after_set_cpuid() when guest enables PMU and passthrough PMU is allowed. The passthrough RDPMC allows guest to read several PMU MSRs including unexposed counters like fixed counter 3 as well as IA32_PERF_METRICS. To cope with this issue, these MSRs will be cleared in later commits when context switching to VM guest. Co-developed-by: Xiong Zhang Signed-off-by: Xiong Zhang Signed-off-by: Mingwei Zhang --- arch/x86/kvm/vmx/vmx.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index e4610b80e519..33cb69ff0804 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7819,6 +7819,9 @@ static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) vmx->msr_ia32_feature_control_valid_bits &= ~FEAT_CTL_SGX_LC_ENABLED; + if (is_passthrough_pmu_enabled(&vmx->vcpu)) + exec_controls_clearbit(vmx, CPU_BASED_RDPMC_EXITING); + /* Refresh #PF interception to account for MAXPHYADDR changes. */ vmx_update_exception_bitmap(vcpu); } From patchwork Fri Jan 26 08:54:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532239 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99DB525633; 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X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9792346" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9792346" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:56:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930310057" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930310057" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:56:47 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com, Xiong Zhang Subject: [RFC PATCH 15/41] KVM: x86/pmu: Manage MSR interception for IA32_PERF_GLOBAL_CTRL Date: Fri, 26 Jan 2024 16:54:18 +0800 Message-Id: <20240126085444.324918-16-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Xiong Zhang In PMU passthrough mode, there are three requirements to manage IA32_PERF_GLOBAL_CTRL: - guest IA32_PERF_GLOBAL_CTRL MSR must be saved at vm exit. - IA32_PERF_GLOBAL_CTRL MSR must be cleared at vm exit to avoid any counter of running within KVM runloop. - guest IA32_PERF_GLOBAL_CTRL MSR must be restored at vm entry. Introduce vmx_set_perf_global_ctrl() function to auto switching IA32_PERF_GLOBAL_CTR and invoke it after the VMM finishes setting up the CPUID bits. Signed-off-by: Xiong Zhang Signed-off-by: Mingwei Zhang --- arch/x86/include/asm/vmx.h | 1 + arch/x86/kvm/vmx/vmx.c | 89 ++++++++++++++++++++++++++++++++------ arch/x86/kvm/vmx/vmx.h | 3 +- 3 files changed, 78 insertions(+), 15 deletions(-) diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h index 0e73616b82f3..f574e7b429a3 100644 --- a/arch/x86/include/asm/vmx.h +++ b/arch/x86/include/asm/vmx.h @@ -104,6 +104,7 @@ #define VM_EXIT_CLEAR_BNDCFGS 0x00800000 #define VM_EXIT_PT_CONCEAL_PIP 0x01000000 #define VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 +#define VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL 0x40000000 #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 33cb69ff0804..8ab266e1e2a7 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -4387,6 +4387,74 @@ static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) return pin_based_exec_ctrl; } +static void vmx_set_perf_global_ctrl(struct vcpu_vmx *vmx) +{ + u32 vmentry_ctrl = vm_entry_controls_get(vmx); + u32 vmexit_ctrl = vm_exit_controls_get(vmx); + int i; + + /* + * PERF_GLOBAL_CTRL is toggled dynamically in emulated vPMU. + */ + if (cpu_has_perf_global_ctrl_bug() || + !is_passthrough_pmu_enabled(&vmx->vcpu)) { + vmentry_ctrl &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; + vmexit_ctrl &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; + vmexit_ctrl &= ~VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL; + } + + if (is_passthrough_pmu_enabled(&vmx->vcpu)) { + /* + * Setup auto restore guest PERF_GLOBAL_CTRL MSR at vm entry. + */ + if (vmentry_ctrl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) + vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL, 0); + else { + i = vmx_find_loadstore_msr_slot(&vmx->msr_autoload.guest, + MSR_CORE_PERF_GLOBAL_CTRL); + if (i < 0) { + i = vmx->msr_autoload.guest.nr++; + vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, + vmx->msr_autoload.guest.nr); + } + vmx->msr_autoload.guest.val[i].index = MSR_CORE_PERF_GLOBAL_CTRL; + vmx->msr_autoload.guest.val[i].value = 0; + } + /* + * Setup auto clear host PERF_GLOBAL_CTRL msr at vm exit. + */ + if (vmexit_ctrl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) + vmcs_write64(HOST_IA32_PERF_GLOBAL_CTRL, 0); + else { + i = vmx_find_loadstore_msr_slot(&vmx->msr_autoload.host, + MSR_CORE_PERF_GLOBAL_CTRL); + if (i < 0) { + i = vmx->msr_autoload.host.nr++; + vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, + vmx->msr_autoload.host.nr); + } + vmx->msr_autoload.host.val[i].index = MSR_CORE_PERF_GLOBAL_CTRL; + vmx->msr_autoload.host.val[i].value = 0; + } + /* + * Setup auto save guest PERF_GLOBAL_CTRL msr at vm exit + */ + if (!(vmexit_ctrl & VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL)) { + i = vmx_find_loadstore_msr_slot(&vmx->msr_autostore.guest, + MSR_CORE_PERF_GLOBAL_CTRL); + if (i < 0) { + i = vmx->msr_autostore.guest.nr++; + vmcs_write32(VM_EXIT_MSR_STORE_COUNT, + vmx->msr_autostore.guest.nr); + } + vmx->msr_autostore.guest.val[i].index = MSR_CORE_PERF_GLOBAL_CTRL; + } + } + + vm_entry_controls_set(vmx, vmentry_ctrl); + vm_exit_controls_set(vmx, vmexit_ctrl); +} + static u32 vmx_vmentry_ctrl(void) { u32 vmentry_ctrl = vmcs_config.vmentry_ctrl; @@ -4394,15 +4462,9 @@ static u32 vmx_vmentry_ctrl(void) if (vmx_pt_mode_is_system()) vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP | VM_ENTRY_LOAD_IA32_RTIT_CTL); - /* - * IA32e mode, and loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically. - */ - vmentry_ctrl &= ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | - VM_ENTRY_LOAD_IA32_EFER | - VM_ENTRY_IA32E_MODE); - if (cpu_has_perf_global_ctrl_bug()) - vmentry_ctrl &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; + /* IA32e mode, and loading of EFER is toggled dynamically. */ + vmentry_ctrl &= ~(VM_ENTRY_LOAD_IA32_EFER | VM_ENTRY_IA32E_MODE); return vmentry_ctrl; } @@ -4422,12 +4484,8 @@ static u32 vmx_vmexit_ctrl(void) vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP | VM_EXIT_CLEAR_IA32_RTIT_CTL); - if (cpu_has_perf_global_ctrl_bug()) - vmexit_ctrl &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; - - /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */ - return vmexit_ctrl & - ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER); + /* Loading of EFER is toggled dynamically */ + return vmexit_ctrl & ~VM_EXIT_LOAD_IA32_EFER; } static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) @@ -4765,6 +4823,7 @@ static void init_vmcs(struct vcpu_vmx *vmx) vmcs_write64(VM_FUNCTION_CONTROL, 0); vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); + vmcs_write64(VM_EXIT_MSR_STORE_ADDR, __pa(vmx->msr_autostore.guest.val)); vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); @@ -7822,6 +7881,8 @@ static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) if (is_passthrough_pmu_enabled(&vmx->vcpu)) exec_controls_clearbit(vmx, CPU_BASED_RDPMC_EXITING); + vmx_set_perf_global_ctrl(vmx); + /* Refresh #PF interception to account for MAXPHYADDR changes. */ vmx_update_exception_bitmap(vcpu); } diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index c2130d2c8e24..c89db35e1de8 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -502,7 +502,8 @@ static inline u8 vmx_get_rvi(void) VM_EXIT_LOAD_IA32_EFER | \ VM_EXIT_CLEAR_BNDCFGS | \ VM_EXIT_PT_CONCEAL_PIP | \ - VM_EXIT_CLEAR_IA32_RTIT_CTL) + VM_EXIT_CLEAR_IA32_RTIT_CTL | \ + VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL) #define KVM_REQUIRED_VMX_PIN_BASED_VM_EXEC_CONTROL \ (PIN_BASED_EXT_INTR_MASK | \ From patchwork Fri Jan 26 08:54:19 2024 Content-Type: text/plain; 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X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9792463" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9792463" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:56:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930310069" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930310069" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:56:52 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com Subject: [RFC PATCH 16/41] KVM: x86/pmu: Create a function prototype to disable MSR interception Date: Fri, 26 Jan 2024 16:54:19 +0800 Message-Id: <20240126085444.324918-17-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mingwei Zhang Add one extra pmu function prototype in kvm_pmu_ops to disable PMU MSR interception. Signed-off-by: Mingwei Zhang --- arch/x86/include/asm/kvm-x86-pmu-ops.h | 1 + arch/x86/kvm/cpuid.c | 4 ++++ arch/x86/kvm/pmu.c | 5 +++++ arch/x86/kvm/pmu.h | 2 ++ 4 files changed, 12 insertions(+) diff --git a/arch/x86/include/asm/kvm-x86-pmu-ops.h b/arch/x86/include/asm/kvm-x86-pmu-ops.h index 6c98f4bb4228..a2acf0afee5d 100644 --- a/arch/x86/include/asm/kvm-x86-pmu-ops.h +++ b/arch/x86/include/asm/kvm-x86-pmu-ops.h @@ -25,6 +25,7 @@ KVM_X86_PMU_OP(init) KVM_X86_PMU_OP(reset) KVM_X86_PMU_OP_OPTIONAL(deliver_pmi) KVM_X86_PMU_OP_OPTIONAL(cleanup) +KVM_X86_PMU_OP_OPTIONAL(passthrough_pmu_msrs) #undef KVM_X86_PMU_OP #undef KVM_X86_PMU_OP_OPTIONAL diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index dda6fc4cfae8..ab9e47ba8b6a 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -366,6 +366,10 @@ static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); kvm_pmu_refresh(vcpu); + + if (is_passthrough_pmu_enabled(vcpu)) + kvm_pmu_passthrough_pmu_msrs(vcpu); + vcpu->arch.cr4_guest_rsvd_bits = __cr4_reserved_bits(guest_cpuid_has, vcpu); diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 1853739a59bf..d83746f93392 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -893,3 +893,8 @@ int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp) kfree(filter); return r; } + +void kvm_pmu_passthrough_pmu_msrs(struct kvm_vcpu *vcpu) +{ + static_call_cond(kvm_x86_pmu_passthrough_pmu_msrs)(vcpu); +} diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 28beae0f9209..d575808c7258 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -33,6 +33,7 @@ struct kvm_pmu_ops { void (*reset)(struct kvm_vcpu *vcpu); void (*deliver_pmi)(struct kvm_vcpu *vcpu); void (*cleanup)(struct kvm_vcpu *vcpu); + void (*passthrough_pmu_msrs)(struct kvm_vcpu *vcpu); const u64 EVENTSEL_EVENT; const int MAX_NR_GP_COUNTERS; @@ -286,6 +287,7 @@ void kvm_pmu_cleanup(struct kvm_vcpu *vcpu); void kvm_pmu_destroy(struct kvm_vcpu *vcpu); int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp); 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d="scan'208";a="930310087" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:56:57 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com Subject: [RFC PATCH 17/41] KVM: x86/pmu: Implement pmu function for Intel CPU to disable MSR interception Date: Fri, 26 Jan 2024 16:54:20 +0800 Message-Id: <20240126085444.324918-18-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mingwei Zhang Disable PMU MSRs interception, these MSRs are defined in Architectural Performance Monitoring from SDM, so that guest can access them without VM-exit. Signed-off-by: Mingwei Zhang --- arch/x86/kvm/vmx/pmu_intel.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 15cc107ed573..7f6cabb2c378 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -794,6 +794,25 @@ void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu) } } +void intel_passthrough_pmu_msrs(struct kvm_vcpu *vcpu) +{ + int i; + + for (i = 0; i < vcpu_to_pmu(vcpu)->nr_arch_gp_counters; i++) { + vmx_set_intercept_for_msr(vcpu, MSR_ARCH_PERFMON_EVENTSEL0 + i, MSR_TYPE_RW, false); + vmx_set_intercept_for_msr(vcpu, MSR_IA32_PERFCTR0 + i, MSR_TYPE_RW, false); + vmx_set_intercept_for_msr(vcpu, MSR_IA32_PMC0 + i, MSR_TYPE_RW, false); + } + + vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_TYPE_RW, false); + for (i = 0; i < vcpu_to_pmu(vcpu)->nr_arch_fixed_counters; i++) + vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_FIXED_CTR0 + i, MSR_TYPE_RW, false); + + vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_GLOBAL_STATUS, MSR_TYPE_RW, false); + vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL, MSR_TYPE_RW, false); + vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, MSR_TYPE_RW, false); +} + struct kvm_pmu_ops intel_pmu_ops __initdata = { .hw_event_available = intel_hw_event_available, .pmc_idx_to_pmc = intel_pmc_idx_to_pmc, @@ -808,6 +827,7 @@ struct kvm_pmu_ops intel_pmu_ops __initdata = { .reset = intel_pmu_reset, .deliver_pmi = intel_pmu_deliver_pmi, .cleanup = intel_pmu_cleanup, + .passthrough_pmu_msrs = intel_passthrough_pmu_msrs, .EVENTSEL_EVENT = ARCH_PERFMON_EVENTSEL_EVENT, .MAX_NR_GP_COUNTERS = KVM_INTEL_PMC_MAX_GENERIC, .MIN_NR_GP_COUNTERS = 1, From patchwork Fri Jan 26 08:54:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532242 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEFF5144628; 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X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9792596" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9792596" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:57:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930310100" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930310100" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:57:02 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com, Xiong Zhang Subject: [RFC PATCH 18/41] KVM: x86/pmu: Intercept full-width GP counter MSRs by checking with perf capabilities Date: Fri, 26 Jan 2024 16:54:21 +0800 Message-Id: <20240126085444.324918-19-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mingwei Zhang Intercept full-width GP counter MSRs in passthrough PMU if guest does not have the capability to write in full-width. In addition, opportunistically add a warning if non-full-width counter MSRs are also intercepted, in which case it is a clear mistake. Co-developed-by: Xiong Zhang Signed-off-by: Xiong Zhang Signed-off-by: Mingwei Zhang --- arch/x86/kvm/vmx/pmu_intel.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 7f6cabb2c378..49df154fbb5b 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -429,6 +429,13 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) default: if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) || (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) { + if (is_passthrough_pmu_enabled(vcpu) && + !(msr & MSR_PMC_FULL_WIDTH_BIT) && + !msr_info->host_initiated) { + pr_warn_once("passthrough PMU never intercepts non-full-width PMU counters\n"); + return 1; + } + if ((msr & MSR_PMC_FULL_WIDTH_BIT) && (data & ~pmu->counter_bitmask[KVM_PMC_GP])) return 1; @@ -801,7 +808,8 @@ void intel_passthrough_pmu_msrs(struct kvm_vcpu *vcpu) for (i = 0; i < vcpu_to_pmu(vcpu)->nr_arch_gp_counters; i++) { vmx_set_intercept_for_msr(vcpu, MSR_ARCH_PERFMON_EVENTSEL0 + i, MSR_TYPE_RW, false); vmx_set_intercept_for_msr(vcpu, MSR_IA32_PERFCTR0 + i, MSR_TYPE_RW, false); - vmx_set_intercept_for_msr(vcpu, MSR_IA32_PMC0 + i, MSR_TYPE_RW, false); + if (fw_writes_is_enabled(vcpu)) + vmx_set_intercept_for_msr(vcpu, MSR_IA32_PMC0 + i, MSR_TYPE_RW, false); } vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_TYPE_RW, false); From patchwork Fri Jan 26 08:54:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532243 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9D0E145B18; Fri, 26 Jan 2024 08:57:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; 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26 Jan 2024 00:57:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930310107" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930310107" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:57:07 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com Subject: [RFC PATCH 19/41] KVM: x86/pmu: Whitelist PMU MSRs for passthrough PMU Date: Fri, 26 Jan 2024 16:54:22 +0800 Message-Id: <20240126085444.324918-20-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mingwei Zhang Whitelist PMU MSRs is_valid_passthrough_msr() to avoid warnings in kernel message. In addition add comments in vmx_possible_passthrough_msrs() to specify that interception of PMU MSRs are specially handled in intel_passthrough_pmu_msrs(). Signed-off-by: Mingwei Zhang --- arch/x86/kvm/vmx/vmx.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 8ab266e1e2a7..349954f90fe9 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -158,7 +158,7 @@ module_param(allow_smaller_maxphyaddr, bool, S_IRUGO); /* * List of MSRs that can be directly passed to the guest. - * In addition to these x2apic and PT MSRs are handled specially. + * In addition to these x2apic, PMU and PT MSRs are handled specially. */ static u32 vmx_possible_passthrough_msrs[MAX_POSSIBLE_PASSTHROUGH_MSRS] = { MSR_IA32_SPEC_CTRL, @@ -698,6 +698,15 @@ static bool is_valid_passthrough_msr(u32 msr) case MSR_LBR_CORE_FROM ... MSR_LBR_CORE_FROM + 8: case MSR_LBR_CORE_TO ... MSR_LBR_CORE_TO + 8: /* LBR MSRs. These are handled in vmx_update_intercept_for_lbr_msrs() */ + case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 7: + case MSR_IA32_PMC0 ... MSR_IA32_PMC0 + 7: + case MSR_IA32_PERFCTR0 ... MSR_IA32_PERFCTR0 + 7: + case MSR_CORE_PERF_FIXED_CTR_CTRL: + case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + 2: + case MSR_CORE_PERF_GLOBAL_STATUS: + case MSR_CORE_PERF_GLOBAL_CTRL: + case MSR_CORE_PERF_GLOBAL_OVF_CTRL: + /* PMU MSRs. These are handled in intel_passthrough_pmu_msrs() */ return true; } From patchwork Fri Jan 26 08:54:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532244 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B10412CCBA; Fri, 26 Jan 2024 08:57:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259439; cv=none; b=nmJIWJc+CQ8QIPJZ0IzJ+0qbvQH8lPxMS/kBSde531IENXWSobvuRMrxdwO5yezJg+TqDUNtdte+HAp2QMBw64kafGBImyBjU0vU+vti5kJzkxkmV7oAl1MRsF+80pdgkjjrw6fhloQBashU+SQ3IIKkOkM12pg99Ri4Fc75NI8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259439; c=relaxed/simple; bh=n7VLnKBVL7xRAaVFEomROGAnaAnnwE6pOBxo0lUgP7k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pFNlhehUZidhvE5lSTRTliOuOs0rNh12p7VS9lGjqBl4/1XtUMXwfmg2NzdIWmtRoS9bo8axBty06R8YZKS62j5SSgHODaDhOct/nXTupXiqlE4CVZPAVDWtffoFb5qjvr3zftS01hcQ680xt3Xc8auayjvcy5GKdye1xcJ2Ghc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=BxXu+7Dd; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="BxXu+7Dd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706259438; x=1737795438; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=n7VLnKBVL7xRAaVFEomROGAnaAnnwE6pOBxo0lUgP7k=; b=BxXu+7DdeRHvRviwoxC4mlxNtbXqJ0y4acTyf8ENVeHELfQwie0ygTCj YQuZwqthDt6LjDlf5DHXG8O1qfZ45qzdnAdlLxYyl7xbEGCc6ePkBlq1t KDGHTRryis/EGMyjDB1m7G6F27wCEIEUE9ZJgSKCUieZrKzSwgQr2I5et XqGIyxYowiOddUVvauOpyziN0X1ztgYRAcbjAaWFDPsxRy0Cab9mBYLh2 ClwpjHYKREYBsmNMm9aRK6OFLzp2peml3nkfO/KsNPoaMhbVJUrtlGdsD 6K2dKywLsDhFDqfyVD6DbWyMy6dynuihTbIGxEgPUurNo4YxtcTzbH35o Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9792632" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9792632" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:57:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930310111" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930310111" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:57:12 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com Subject: [RFC PATCH 20/41] KVM: x86/pmu: Introduce PMU operation prototypes for save/restore PMU context Date: Fri, 26 Jan 2024 16:54:23 +0800 Message-Id: <20240126085444.324918-21-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mingwei Zhang Plumb through kvm_pmu_ops with these two extra functions to allow pmu context switch. Signed-off-by: Mingwei Zhang --- arch/x86/include/asm/kvm-x86-pmu-ops.h | 2 ++ arch/x86/kvm/pmu.c | 14 ++++++++++++++ arch/x86/kvm/pmu.h | 4 ++++ 3 files changed, 20 insertions(+) diff --git a/arch/x86/include/asm/kvm-x86-pmu-ops.h b/arch/x86/include/asm/kvm-x86-pmu-ops.h index a2acf0afee5d..ee201ac95f57 100644 --- a/arch/x86/include/asm/kvm-x86-pmu-ops.h +++ b/arch/x86/include/asm/kvm-x86-pmu-ops.h @@ -26,6 +26,8 @@ KVM_X86_PMU_OP(reset) KVM_X86_PMU_OP_OPTIONAL(deliver_pmi) KVM_X86_PMU_OP_OPTIONAL(cleanup) KVM_X86_PMU_OP_OPTIONAL(passthrough_pmu_msrs) +KVM_X86_PMU_OP_OPTIONAL(save_pmu_context) +KVM_X86_PMU_OP_OPTIONAL(restore_pmu_context) #undef KVM_X86_PMU_OP #undef KVM_X86_PMU_OP_OPTIONAL diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index d83746f93392..9d737f5b96bf 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -898,3 +898,17 @@ void kvm_pmu_passthrough_pmu_msrs(struct kvm_vcpu *vcpu) { static_call_cond(kvm_x86_pmu_passthrough_pmu_msrs)(vcpu); } + +void kvm_pmu_save_pmu_context(struct kvm_vcpu *vcpu) +{ + lockdep_assert_irqs_disabled(); + + static_call_cond(kvm_x86_pmu_save_pmu_context)(vcpu); +} + +void kvm_pmu_restore_pmu_context(struct kvm_vcpu *vcpu) +{ + lockdep_assert_irqs_disabled(); + + static_call_cond(kvm_x86_pmu_restore_pmu_context)(vcpu); +} diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index d575808c7258..a4c0b2e2c24b 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -34,6 +34,8 @@ struct kvm_pmu_ops { void (*deliver_pmi)(struct kvm_vcpu *vcpu); void (*cleanup)(struct kvm_vcpu *vcpu); void (*passthrough_pmu_msrs)(struct kvm_vcpu *vcpu); + void (*save_pmu_context)(struct kvm_vcpu *vcpu); + void (*restore_pmu_context)(struct kvm_vcpu *vcpu); const u64 EVENTSEL_EVENT; const int MAX_NR_GP_COUNTERS; @@ -288,6 +290,8 @@ void kvm_pmu_destroy(struct kvm_vcpu *vcpu); int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp); void kvm_pmu_trigger_event(struct kvm_vcpu *vcpu, u64 perf_hw_id); void kvm_pmu_passthrough_pmu_msrs(struct kvm_vcpu *vcpu); +void kvm_pmu_save_pmu_context(struct kvm_vcpu *vcpu); +void kvm_pmu_restore_pmu_context(struct kvm_vcpu *vcpu); bool is_vmware_backdoor_pmc(u32 pmc_idx); From patchwork Fri Jan 26 08:54:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532245 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A590F2CCBA; Fri, 26 Jan 2024 08:57:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259443; cv=none; b=EDcB2aDflmrmz1EQQeqVydv+dm792GUXP/kdJHFLr/oGfnArGeWqnVkfDCUqpPB0s+I7mIOKoQ2oFOCBApZhjBpfYvpJHk+4EnE30C5vi9LgWOx8pr831PvXtYSzb/1dxtkpeSoTUoT4m2B6CdNEdJILQJEXlR+mJFXOcEI2050= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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26 Jan 2024 00:57:17 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com Subject: [RFC PATCH 21/41] KVM: x86/pmu: Introduce function prototype for Intel CPU to save/restore PMU context Date: Fri, 26 Jan 2024 16:54:24 +0800 Message-Id: <20240126085444.324918-22-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mingwei Zhang Implement a PMU function prototype for Intel CPU. Signed-off-by: Mingwei Zhang --- arch/x86/kvm/vmx/pmu_intel.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 49df154fbb5b..0d58fe7d243e 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -821,6 +821,14 @@ void intel_passthrough_pmu_msrs(struct kvm_vcpu *vcpu) vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, MSR_TYPE_RW, false); } +static void intel_save_pmu_context(struct kvm_vcpu *vcpu) +{ +} + +static void intel_restore_pmu_context(struct kvm_vcpu *vcpu) +{ +} + struct kvm_pmu_ops intel_pmu_ops __initdata = { .hw_event_available = intel_hw_event_available, .pmc_idx_to_pmc = intel_pmc_idx_to_pmc, @@ -836,6 +844,8 @@ struct kvm_pmu_ops intel_pmu_ops __initdata = { .deliver_pmi = intel_pmu_deliver_pmi, .cleanup = intel_pmu_cleanup, .passthrough_pmu_msrs = intel_passthrough_pmu_msrs, + .save_pmu_context = intel_save_pmu_context, + .restore_pmu_context = intel_restore_pmu_context, .EVENTSEL_EVENT = ARCH_PERFMON_EVENTSEL_EVENT, .MAX_NR_GP_COUNTERS = KVM_INTEL_PMC_MAX_GENERIC, .MIN_NR_GP_COUNTERS = 1, From patchwork Fri Jan 26 08:54:25 2024 Content-Type: text/plain; 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X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9792656" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9792656" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:57:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930310132" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930310132" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:57:22 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com Subject: [RFC PATCH 22/41] x86: Introduce MSR_CORE_PERF_GLOBAL_STATUS_SET for passthrough PMU Date: Fri, 26 Jan 2024 16:54:25 +0800 Message-Id: <20240126085444.324918-23-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Dapeng Mi Add additional PMU MSRs MSR_CORE_PERF_GLOBAL_STATUS_SET to allow passthrough PMU operation on the read-only MSR IA32_PERF_GLOBAL_STATUS. Signed-off-by: Dapeng Mi Signed-off-by: Mingwei Zhang --- arch/x86/include/asm/msr-index.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 1d51e1850ed0..270f4f420801 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1059,6 +1059,7 @@ #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 +#define MSR_CORE_PERF_GLOBAL_STATUS_SET 0x00000391 #define MSR_PERF_METRICS 0x00000329 From patchwork Fri Jan 26 08:54:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532247 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B77CF33CF7; Fri, 26 Jan 2024 08:57:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259454; cv=none; b=ulB4MJD60A/2yYTYJXcT/NWQroeNnHgVWUQEcHg4Ow6FCxTDWhrAmKJUfCiWmU79CmCbbFabVWi3N5ijJABpXc6SVf0Utjufr2ui+IFIYsjxGkhLIsJVbiij9jWxwVKyj2ryHDzQZvtesUfAwCATPSHufkzUla+M46FOFHqZ9lU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259454; c=relaxed/simple; bh=aqXZtsYM8yBxMah4+UqygYn+me8SEAHU5KBDJu/R31g=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=h4XC1z2bAquftol1QzZ9dEqFRk6dTQi4rwn2iPygR63NrkgF+wmB7XeOA4K67E9GWgOiXXDnkyYvelS/Xeg2HlLi5dW6giftC6ksx2khc9BE3QRG/hmPD0nCm2m7GJljI3iw1JZNURzumjv0WWfYMSzM9xBI5o+XeXwRPyvfVgs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Pj+X4SWu; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Pj+X4SWu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706259453; x=1737795453; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aqXZtsYM8yBxMah4+UqygYn+me8SEAHU5KBDJu/R31g=; b=Pj+X4SWupkwYi1e8NlXB8tgFTm4+TBb2gO0OzvTamuNZYmCCP/TpDDNG IlvqnKcv3GVWTkP9V34rWnRN/tigrBXy6mN06sLYPjmAlUcPE2K5fmrSJ AYTXaTEOsvUxtNLRki1sOYFHmh01l89EYfWxLbVxC/S7h5827PdsErW68 ZZFOMRpkIVv16MHz6fzvibQjTp9R0DzfKKYRavt25hoATk6BAF9y823Sg VKATE++Jn1mo5EAsRYy9dE8J6FfB6fDDBGzqcL1WNTknlPOlElDPZljTT ZBAlQYF5Nz+dan7Oy7zbkUo0DGLqUMxV87XOxuW9SRiaSgp0B4gizG/yz g==; X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9792668" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9792668" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:57:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930310191" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930310191" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:57:27 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com Subject: [RFC PATCH 23/41] KVM: x86/pmu: Implement the save/restore of PMU state for Intel CPU Date: Fri, 26 Jan 2024 16:54:26 +0800 Message-Id: <20240126085444.324918-24-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Dapeng Mi Implement the save/restore of PMU state for pasthrough PMU in Intel. In passthrough mode, KVM owns exclusively the PMU HW when control flow goes to the scope of passthrough PMU. Thus, KVM needs to save the host PMU state and gains the full HW PMU ownership. On the contrary, host regains the ownership of PMU HW from KVM when control flow leaves the scope of passthrough PMU. Implement PMU context switches for Intel CPUs and opptunistically use rdpmcl() instead of rdmsrl() when reading counters since the former has lower latency in Intel CPUs. Co-developed-by: Mingwei Zhang Signed-off-by: Mingwei Zhang Signed-off-by: Dapeng Mi --- arch/x86/kvm/vmx/pmu_intel.c | 73 ++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 0d58fe7d243e..f79bebe7093d 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -823,10 +823,83 @@ void intel_passthrough_pmu_msrs(struct kvm_vcpu *vcpu) static void intel_save_pmu_context(struct kvm_vcpu *vcpu) { + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + struct kvm_pmc *pmc; + u32 i; + + if (pmu->version != 2) { + pr_warn("only PerfMon v2 is supported for passthrough PMU"); + return; + } + + /* Global ctrl register is already saved at VM-exit. */ + rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, pmu->global_status); + /* Clear hardware MSR_CORE_PERF_GLOBAL_STATUS MSR, if non-zero. */ + if (pmu->global_status) + wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, pmu->global_status); + + for (i = 0; i < pmu->nr_arch_gp_counters; i++) { + pmc = &pmu->gp_counters[i]; + rdpmcl(i, pmc->counter); + rdmsrl(i + MSR_ARCH_PERFMON_EVENTSEL0, pmc->eventsel); + /* + * Clear hardware PERFMON_EVENTSELx and its counter to avoid + * leakage and also avoid this guest GP counter get accidentally + * enabled during host running when host enable global ctrl. + */ + if (pmc->eventsel) + wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0); + if (pmc->counter) + wrmsrl(MSR_IA32_PMC0 + i, 0); + } + + rdmsrl(MSR_CORE_PERF_FIXED_CTR_CTRL, pmu->fixed_ctr_ctrl); + /* + * Clear hardware FIXED_CTR_CTRL MSR to avoid information leakage and + * also avoid these guest fixed counters get accidentially enabled + * during host running when host enable global ctrl. + */ + if (pmu->fixed_ctr_ctrl) + wrmsrl(MSR_CORE_PERF_FIXED_CTR_CTRL, 0); + for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { + pmc = &pmu->fixed_counters[i]; + rdpmcl(INTEL_PMC_FIXED_RDPMC_BASE | i, pmc->counter); + if (pmc->counter) + wrmsrl(MSR_CORE_PERF_FIXED_CTR0 + i, 0); + } } static void intel_restore_pmu_context(struct kvm_vcpu *vcpu) { + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + struct kvm_pmc *pmc; + u64 global_status; + int i; + + if (pmu->version != 2) { + pr_warn("only PerfMon v2 is supported for passthrough PMU"); + return; + } + + /* Clear host global_ctrl and global_status MSR if non-zero. */ + wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); + rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, global_status); + if (global_status) + wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, global_status); + + wrmsrl(MSR_CORE_PERF_GLOBAL_STATUS_SET, pmu->global_status); + + for (i = 0; i < pmu->nr_arch_gp_counters; i++) { + pmc = &pmu->gp_counters[i]; + wrmsrl(MSR_IA32_PMC0 + i, pmc->counter); + wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, pmc->eventsel); + } + + wrmsrl(MSR_CORE_PERF_FIXED_CTR_CTRL, pmu->fixed_ctr_ctrl); + for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { + pmc = &pmu->fixed_counters[i]; + wrmsrl(MSR_CORE_PERF_FIXED_CTR0 + i, pmc->counter); + } } struct kvm_pmu_ops intel_pmu_ops __initdata = { From patchwork Fri Jan 26 08:54:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532248 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A43629CFD; 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X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9792686" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9792686" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:57:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930310204" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930310204" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:57:32 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com Subject: [RFC PATCH 24/41] KVM: x86/pmu: Zero out unexposed Counters/Selectors to avoid information leakage Date: Fri, 26 Jan 2024 16:54:27 +0800 Message-Id: <20240126085444.324918-25-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mingwei Zhang Zero out unexposed counters/selectors because even though KVM intercepts all accesses to unexposed PMU MSRs, it does pass through RDPMC instruction which allows guest to read all GP counters and fixed counters. So, zero out unexposed counter values which might contain critical information for the host. Signed-off-by: Mingwei Zhang --- arch/x86/kvm/vmx/pmu_intel.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index f79bebe7093d..4b4da7f17895 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -895,11 +895,27 @@ static void intel_restore_pmu_context(struct kvm_vcpu *vcpu) wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, pmc->eventsel); } + /* + * Zero out unexposed GP counters/selectors to avoid information leakage + * since passthrough PMU does not intercept RDPMC. + */ + for (i = pmu->nr_arch_gp_counters; i < kvm_pmu_cap.num_counters_gp; i++) { + wrmsrl(MSR_IA32_PMC0 + i, 0); + wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0); + } + wrmsrl(MSR_CORE_PERF_FIXED_CTR_CTRL, pmu->fixed_ctr_ctrl); for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { pmc = &pmu->fixed_counters[i]; wrmsrl(MSR_CORE_PERF_FIXED_CTR0 + i, pmc->counter); } + + /* + * Zero out unexposed fixed counters to avoid information leakage + * since passthrough PMU does not intercept RDPMC. + */ + for (i = pmu->nr_arch_fixed_counters; i < kvm_pmu_cap.num_counters_fixed; i++) + wrmsrl(MSR_CORE_PERF_FIXED_CTR0 + i, 0); } struct kvm_pmu_ops intel_pmu_ops __initdata = { From patchwork Fri Jan 26 08:54:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532249 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF61B148319; Fri, 26 Jan 2024 08:57:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259464; cv=none; b=Qf8VfxcDWResXfhVOpPzsMHvAMTM6QEfn9ULsY5Hc0nhGKgMwIkb3yIspVayd8BUDUQzU5PlR8C8DN8+vWQ70PfcpDiV46+okqt7sFngaXF+FUzuF0tEmnt32rTtQOSzS0F0Z0UoeOq3MaYLWs1MTjURMHqenORowf8yiOXfQkk= ARC-Message-Signature: i=1; a=rsa-sha256; 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d="scan'208";a="930310216" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:57:37 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com Subject: [RFC PATCH 25/41] KVM: x86/pmu: Introduce macro PMU_CAP_PERF_METRICS Date: Fri, 26 Jan 2024 16:54:28 +0800 Message-Id: <20240126085444.324918-26-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Dapeng Mi Define macro PMU_CAP_PERF_METRICS to represent bit[15] of MSR_IA32_PERF_CAPABILITIES MSR. This bit is used to represent whether perf metrics feature is enabled. Signed-off-by: Dapeng Mi --- arch/x86/kvm/vmx/capabilities.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilities.h index 41a4533f9989..d8317552b634 100644 --- a/arch/x86/kvm/vmx/capabilities.h +++ b/arch/x86/kvm/vmx/capabilities.h @@ -22,6 +22,7 @@ extern int __read_mostly pt_mode; #define PT_MODE_HOST_GUEST 1 #define PMU_CAP_FW_WRITES (1ULL << 13) +#define PMU_CAP_PERF_METRICS BIT_ULL(15) #define PMU_CAP_LBR_FMT 0x3f struct nested_vmx_msrs { From patchwork Fri Jan 26 08:54:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532250 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6C5014A096; Fri, 26 Jan 2024 08:57:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259469; cv=none; b=UJgX1HBnKczReskb7JgrzDNGS0mRr/pmt04sc/jtvj2lVruHgaiX7S2QhqzZxFlBfRpxGnv9jg5x7lRqAvkjpdX/dYtW3rJEDlPiexzNmfx5Lbgd/7HoM0hN+QfAOKjyyelFhFSR6LpqwXNYUwcXABQWDhTRg26oAAq2UggKxSc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259469; c=relaxed/simple; bh=IbYfCxqPksLaeoFkdiGUr44Kkbsmws1IykdSnPTgst4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Q16m865Fm+NTVv6nsbPFk5x/Qn6J7BgT4AmFEBXWtwk4Qu29wI/HLsf6b6LJvEmsgqeieDeasYpQrLp+2o1GvL1chAWUlegBMPGjenqSBtRe6qn1ugfwTz5fAKslb6drUzKQaMDH++4DQZWlwtRiAo0RbBArYz3S0+0LekpYXAQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=E8o/GLhe; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="E8o/GLhe" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706259468; x=1737795468; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IbYfCxqPksLaeoFkdiGUr44Kkbsmws1IykdSnPTgst4=; b=E8o/GLheeUlyXIaZ4eDYq0uBGnHuCsMCUgwgw64auF1sYjpxZLyGlUZL pdWT5TYpS5p9A+PqoF1duUDXxnuTgXmjThsH8TMpdV2b441S06RyGOYp0 3G/8NxDS+t/N7zO8VvODRBOTiudQV2M0Y/RvLbLieU8LR/rGSlIkrGJZ9 7IQvE6dJ+82FPvz2b2bk36mvZA8LhEd1w/6/Q+Y0TWjycEpIpbOS7qaH2 R8uFIxbrCOtQNaRQDfQdDQfrMh1f8v/0G3Ah41CRW1IAYADT++VDTE9/Z aGDsUUqF+8SZ890bszhxVZ0Oxf0HAeZYAn2ltJdr8Bd9tDbSbSsxO3LKc Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9792724" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9792724" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:57:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930310246" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930310246" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:57:42 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com Subject: [RFC PATCH 26/41] KVM: x86/pmu: Add host_perf_cap field in kvm_caps to record host PMU capability Date: Fri, 26 Jan 2024 16:54:29 +0800 Message-Id: <20240126085444.324918-27-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mingwei Zhang Add host_perf_cap field in kvm_caps to record host PMU capability. This helps KVM recognize the PMU capability difference between host and guest. This awareness improves performance in PMU context switch. In particular, KVM will need to zero out all MSRs that guest PMU does not use but host PMU does use. Having the host PMU feature set cached in host_perf_cap in kvm_caps structure saves a rdmsrl() to IA32_PERF_CAPABILITY MSR on each PMU context switch. In addition, this is more convenient approach than open another API on the host perf subsystem side. Signed-off-by: Mingwei Zhang --- arch/x86/kvm/vmx/vmx.c | 17 +++++++++-------- arch/x86/kvm/x86.h | 1 + 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 349954f90fe9..50100954cd92 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7896,32 +7896,33 @@ static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) vmx_update_exception_bitmap(vcpu); } -static u64 vmx_get_perf_capabilities(void) +static void vmx_get_perf_capabilities(void) { u64 perf_cap = PMU_CAP_FW_WRITES; struct x86_pmu_lbr lbr; - u64 host_perf_cap = 0; + + kvm_caps.host_perf_cap = 0; if (!enable_pmu) - return 0; + return; if (boot_cpu_has(X86_FEATURE_PDCM)) - rdmsrl(MSR_IA32_PERF_CAPABILITIES, host_perf_cap); + rdmsrl(MSR_IA32_PERF_CAPABILITIES, kvm_caps.host_perf_cap); if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR) && !enable_passthrough_pmu) { x86_perf_get_lbr(&lbr); if (lbr.nr) - perf_cap |= host_perf_cap & PMU_CAP_LBR_FMT; + perf_cap |= kvm_caps.host_perf_cap & PMU_CAP_LBR_FMT; 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X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9792757" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9792757" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:57:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930310275" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930310275" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:57:47 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com Subject: [RFC PATCH 27/41] KVM: x86/pmu: Clear PERF_METRICS MSR for guest Date: Fri, 26 Jan 2024 16:54:30 +0800 Message-Id: <20240126085444.324918-28-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Dapeng Mi Since perf topdown metrics feature is not supported yet, clear PERF_METRICS MSR for guest. Signed-off-by: Dapeng Mi --- arch/x86/kvm/vmx/pmu_intel.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 4b4da7f17895..ad0434646a29 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -916,6 +916,10 @@ static void intel_restore_pmu_context(struct kvm_vcpu *vcpu) */ for (i = pmu->nr_arch_fixed_counters; i < kvm_pmu_cap.num_counters_fixed; i++) wrmsrl(MSR_CORE_PERF_FIXED_CTR0 + i, 0); + + /* Clear PERF_METRICS MSR since guest topdown metrics is not supported yet. */ + if (kvm_caps.host_perf_cap & PMU_CAP_PERF_METRICS) + wrmsrl(MSR_PERF_METRICS, 0); } struct kvm_pmu_ops intel_pmu_ops __initdata = { From patchwork Fri Jan 26 08:54:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532252 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C381814AD17; Fri, 26 Jan 2024 08:57:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259480; cv=none; b=gpYbhXY8W/niohkQ8M5/xeHDGCBTWVe+gevEk1w/k3OjrmBn4f8DflGyHC75bctCFwhDQtqD7ln+s7oDgstF68VH7eDhG3Cuidfxl8J3sfeJLq7z7ztXOZLoGLgfgpjPeuQMI0PsQFZ6noK4dpyHfGnN0EMFHAE0TX8jcroQpYs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259480; c=relaxed/simple; bh=Pl83DMZ20U/aWXgf0PpwHCQnMJZPTtvWBj5drnp1+m8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tPK5FkkTHzjFgyMU2yPZWQ1mdJth3hEzWvp5rMIkBewE+RZAFyBzQtfDKHVPJgyLmf+KzH4+ZwFGw5oJK6cLVSzxkFtNDsIC3Yt1hhutokfPHnYDNaMefyARN1Ljuc7kSbKyPF4jQC2McLSabxCnu2pxBwxK/uvDU85IM6GX2xk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hzDtdLuM; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hzDtdLuM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706259479; x=1737795479; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Pl83DMZ20U/aWXgf0PpwHCQnMJZPTtvWBj5drnp1+m8=; b=hzDtdLuMFYG/b2DWLZbkcouV6c12uzZusBe3TzIUZXebtmjG+pdMoXl3 NeCPRXYNQREhs0tBh3OR0Epc0XIvcl4AbQ5UhpDIsgysVdF3qqUBUMxLX PXl82S4n4WlVtvFsogNocfrkJ/tyaBjyjKLa4IVH6wUdxVKdUgHPzwSF0 ANTvqnPSfAi9yPrA+f1VHx3lprCFeG7fGWIuf588g1vS3Mn+BmJVQqxVk pQ6qDRRvJKDNklAq6DCb0KKLAyEY3pnhN7RknEeDfNDhuExBOLooye7Y2 4o+w3LK2RJaE2JsIpRpbEVpT/v1pfspMKED6Kot7xMU4bjWc3zQwWhRw+ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9792783" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9792783" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:57:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930310306" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930310306" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:57:52 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com, Xiong Zhang Subject: [RFC PATCH 28/41] KVM: x86/pmu: Switch IA32_PERF_GLOBAL_CTRL at VM boundary Date: Fri, 26 Jan 2024 16:54:31 +0800 Message-Id: <20240126085444.324918-29-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Xiong Zhang In PMU passthrough mode, use global_ctrl field in struct kvm_pmu as the cached value. This is convenient for KVM to set and get the value from the host side. In addition, load and save the value across VM enter/exit boundary in the following way: - At VM exit, if processor supports GUEST_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL, read guest IA32_PERF_GLOBAL_CTRL GUEST_IA32_PERF_GLOBAL_CTRL VMCS field, else read it from VM-exit MSR-stroe array in VMCS. The value is then assigned to global_ctrl. - At VM Entry, if processor supports GUEST_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, read guest IA32_PERF_GLOBAL_CTRL from GUEST_IA32_PERF_GLOBAL_CTRL VMCS field, else read it from VM-entry MSR-load array in VMCS. The value is then assigned to global ctrl. Implement the above logic into two helper functions and invoke them around VM Enter/exit boundary. Co-developed-by: Mingwei Zhang Signed-off-by: Mingwei Zhang Signed-off-by: Xiong Zhang --- arch/x86/kvm/vmx/vmx.c | 51 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 50100954cd92..a9623351eafe 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7193,7 +7193,7 @@ static void vmx_cancel_injection(struct kvm_vcpu *vcpu) vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); } -static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) +static void __atomic_switch_perf_msrs(struct vcpu_vmx *vmx) { int i, nr_msrs; struct perf_guest_switch_msr *msrs; @@ -7216,6 +7216,52 @@ static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) msrs[i].host, false); } +static void save_perf_global_ctrl_in_passthrough_pmu(struct vcpu_vmx *vmx) +{ + struct kvm_pmu *pmu = vcpu_to_pmu(&vmx->vcpu); + int i; + + if (vm_exit_controls_get(vmx) & VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL) { + pmu->global_ctrl = vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL); + } else { + i = vmx_find_loadstore_msr_slot(&vmx->msr_autostore.guest, + MSR_CORE_PERF_GLOBAL_CTRL); + if (i < 0) + return; + pmu->global_ctrl = vmx->msr_autostore.guest.val[i].value; + } +} + +static void load_perf_global_ctrl_in_passthrough_pmu(struct vcpu_vmx *vmx) +{ + u64 global_ctrl = vcpu_to_pmu(&vmx->vcpu)->global_ctrl; + int i; + + if (vm_entry_controls_get(vmx) & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) { + vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL, global_ctrl); + } else { + i = vmx_find_loadstore_msr_slot(&vmx->msr_autoload.guest, + MSR_CORE_PERF_GLOBAL_CTRL); + if (i < 0) + return; + + vmx->msr_autoload.guest.val[i].value = global_ctrl; + } +} + +static void __atomic_switch_perf_msrs_in_passthrough_pmu(struct vcpu_vmx *vmx) +{ + load_perf_global_ctrl_in_passthrough_pmu(vmx); +} + +static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) +{ + if (is_passthrough_pmu_enabled(&vmx->vcpu)) + __atomic_switch_perf_msrs_in_passthrough_pmu(vmx); + else + __atomic_switch_perf_msrs(vmx); +} + static void vmx_update_hv_timer(struct kvm_vcpu *vcpu) { struct vcpu_vmx *vmx = to_vmx(vcpu); @@ -7314,6 +7360,9 @@ static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu, vcpu->arch.cr2 = native_read_cr2(); vcpu->arch.regs_avail &= ~VMX_REGS_LAZY_LOAD_SET; + if (is_passthrough_pmu_enabled(vcpu)) + save_perf_global_ctrl_in_passthrough_pmu(vmx); + vmx->idt_vectoring_info = 0; vmx_enable_fb_clear(vmx); From patchwork Fri Jan 26 08:54:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532253 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4648B14C585; Fri, 26 Jan 2024 08:58:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; 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26 Jan 2024 00:58:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930310337" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930310337" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:57:58 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com Subject: [RFC PATCH 29/41] KVM: x86/pmu: Exclude existing vLBR logic from the passthrough PMU Date: Fri, 26 Jan 2024 16:54:32 +0800 Message-Id: <20240126085444.324918-30-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mingwei Zhang Excluding existing vLBR logic from the passthrough PMU because the it does not support LBR related MSRs. So to avoid any side effect, do not call vLBR related code in both vcpu_enter_guest() and pmi injection function. Signed-off-by: Mingwei Zhang --- arch/x86/kvm/vmx/pmu_intel.c | 13 ++++++++----- arch/x86/kvm/vmx/vmx.c | 2 +- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index ad0434646a29..9bbd5084a766 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -688,13 +688,16 @@ static void intel_pmu_legacy_freezing_lbrs_on_pmi(struct kvm_vcpu *vcpu) static void intel_pmu_deliver_pmi(struct kvm_vcpu *vcpu) { - u8 version = vcpu_to_pmu(vcpu)->version; + u8 version; - if (!intel_pmu_lbr_is_enabled(vcpu)) - return; + if (!is_passthrough_pmu_enabled(vcpu)) { + if (!intel_pmu_lbr_is_enabled(vcpu)) + return; - if (version > 1 && version < 4) - intel_pmu_legacy_freezing_lbrs_on_pmi(vcpu); + version = vcpu_to_pmu(vcpu)->version; + if (version > 1 && version < 4) + intel_pmu_legacy_freezing_lbrs_on_pmi(vcpu); + } } static void vmx_update_intercept_for_lbr_msrs(struct kvm_vcpu *vcpu, bool set) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index a9623351eafe..d28afa87be70 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7469,7 +7469,7 @@ static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu) pt_guest_enter(vmx); atomic_switch_perf_msrs(vmx); - if (intel_pmu_lbr_is_enabled(vcpu)) + if (!is_passthrough_pmu_enabled(&vmx->vcpu) && intel_pmu_lbr_is_enabled(vcpu)) vmx_passthrough_lbr_msrs(vcpu); if (enable_preemption_timer) From patchwork Fri Jan 26 08:54:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532254 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F80314C5AE; Fri, 26 Jan 2024 08:58:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259489; cv=none; b=dlZbobPNs7K1iXg4awUad2LsQKXSRW3kaFY9H/RZGdNcGwnv72ih94aV1otvxNS+79qkvYAVLlLUboSdOgwBm8xJqKY/BxK4ls1Sn4ReI0necVhJb8XPwnWONpLmefXkV0t9SOn+187zSKSwA7FrOidU2JjORWHrNegqdUUKO0k= ARC-Message-Signature: i=1; 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d="scan'208";a="930310377" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:58:03 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com, Xiong Zhang Subject: [RFC PATCH 30/41] KVM: x86/pmu: Switch PMI handler at KVM context switch boundary Date: Fri, 26 Jan 2024 16:54:33 +0800 Message-Id: <20240126085444.324918-31-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Xiong Zhang Switch PMI handler at KVM context switch boundary because KVM uses a separate maskable interrupt vector other than the NMI handler for the host PMU to process its own PMIs. So invoke the perf API that allows registration of the PMI handler. Signed-off-by: Xiong Zhang Signed-off-by: Mingwei Zhang --- arch/x86/kvm/pmu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 9d737f5b96bf..cd559fd74f65 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -904,11 +904,15 @@ void kvm_pmu_save_pmu_context(struct kvm_vcpu *vcpu) lockdep_assert_irqs_disabled(); static_call_cond(kvm_x86_pmu_save_pmu_context)(vcpu); + + perf_guest_switch_to_host_pmi_vector(); } void kvm_pmu_restore_pmu_context(struct kvm_vcpu *vcpu) { lockdep_assert_irqs_disabled(); + perf_guest_switch_to_kvm_pmi_vector(kvm_lapic_get_lvtpc_mask(vcpu)); + static_call_cond(kvm_x86_pmu_restore_pmu_context)(vcpu); } From patchwork Fri Jan 26 08:54:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532268 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9ED5D14C5AE; Fri, 26 Jan 2024 08:58:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259494; cv=none; b=S7+Wedwg5/txyCBRC/Mc+LV0Fwf+dN0gfBZC2azIzhlxe/93OrBI3woV3yQDCIqbXGYixj369GFs9REgO/QKs9LQJT5N42pC931JthalTT1FcDytux1qQQLlUvoav/U8YVfBR1YxhfINV6XwZA5Hs+D5NnJGEjbEhapuj+zsHow= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259494; c=relaxed/simple; bh=LCLMFfglJdBAlQ+bO08mPrCWqyX9JhAyfb9lgPMTV8w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=A+mgtlWqg8cV1lnVOQqKvAZvTWeUiOU78PUEwFiu/LTQw7xyH8abqgVoJqBYIlEMzCUqVjbVBpqB8C0f6LyViTnhszNcdblLrt4mOBTJ5uhhowxq/YL5VHG8/Do8Ag7+Uv6dwyvL9fsLjyYpwE+dOJXwya/WochfVkrXGVAnRW0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=BVADkwOz; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="BVADkwOz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706259494; x=1737795494; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LCLMFfglJdBAlQ+bO08mPrCWqyX9JhAyfb9lgPMTV8w=; b=BVADkwOzbWObRoh2JHCaGaw/q8w8iY0ASsfaS2iPrfBHStWAJa+mMaiE wIpyqdhQHX/rGDvOW5rws3ZqoNxkqJJWgHSwA6SZX92hVtnUBm1opcJVv PNggp7ZJAlkSJyS8R9mtTXv33NXtt0CLYeqMFijuOIRPNVZUNANurYqy2 oAR/EGK94ekErGvhiJcDIlAIGLW1XwfrE/8HAdrjr8hvmxCRajggXEHO0 WCHeAzArpwgt2GHGiGEtMA1QmYmY4hQWidDmBJ+4FFHBi0Hm+LMtrxVbk p11pqqur3aj1v3/vMqWKMuZFoKajcxI9bpfTndvAjKWLusowdKM3IfrHi w==; X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9792859" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9792859" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:58:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930310401" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930310401" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:58:08 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com, Xiong Zhang Subject: [RFC PATCH 31/41] KVM: x86/pmu: Call perf_guest_enter() at PMU context switch Date: Fri, 26 Jan 2024 16:54:34 +0800 Message-Id: <20240126085444.324918-32-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Xiong Zhang perf subsystem should stop and restart all the perf events at the host level when entering and leaving the passthrough PMU respectively. So invoke the perf API at PMU context switch functions. Signed-off-by: Xiong Zhang Signed-off-by: Mingwei Zhang --- arch/x86/kvm/pmu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index cd559fd74f65..afc9f7eb3a6b 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -906,12 +906,16 @@ void kvm_pmu_save_pmu_context(struct kvm_vcpu *vcpu) static_call_cond(kvm_x86_pmu_save_pmu_context)(vcpu); perf_guest_switch_to_host_pmi_vector(); + + perf_guest_exit(); } void kvm_pmu_restore_pmu_context(struct kvm_vcpu *vcpu) { lockdep_assert_irqs_disabled(); + perf_guest_enter(); + perf_guest_switch_to_kvm_pmi_vector(kvm_lapic_get_lvtpc_mask(vcpu)); static_call_cond(kvm_x86_pmu_restore_pmu_context)(vcpu); From patchwork Fri Jan 26 08:54:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532269 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9EBC44C78; Fri, 26 Jan 2024 08:58:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259500; cv=none; b=HYFnAXrXHy54TZudiY0byakOfvMJ4TmMa3nic5thSvB2vwtJG/QUkg173K87GI6ZuneEq+Fqdv9JTzhiL6TfV3C7lKCxz+qKjo3lz7y+bHaPLSVFYb9Xe0HDQus2tk52g9Tpv0Y2RxlyLmXd3Odt5/nCnJ+RAUGx0YsRrPSL0fQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259500; c=relaxed/simple; bh=DJFzjL1uqbqtFpO07Bney0dZeYiSOvnd7xtSkhQaCpM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FC4JDmgwUdOH7sVNzDvm7Xh24kwNdLPY9ylYwRv6fdzabowWlanZiKgewPme6qpUFrI3WlBB7GsDeTPp3ijsTbY2+JoY8kD5quKw3NrbQwc1sezbd0xrg79ZDdY3rgx5k/5qbD0rBo/8pWq1Y30hYlXEgPWYXD1JXkaOsNyw6T8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=A4IhCEFW; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="A4IhCEFW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706259499; x=1737795499; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DJFzjL1uqbqtFpO07Bney0dZeYiSOvnd7xtSkhQaCpM=; b=A4IhCEFWX5t7TRs6NydvdsqBBpw8UAzOBZkqDXEGlXCDzWPnvDiZ8YsX CAjPh0GUeETVywKhGYJL/y1bkOVPECy1/i+rvcIglxv4jjsO0yiZUA0q7 yoc71J/HrnzbsKFL/BKWFt49UVKelmowSLZ/71kKl6eGEmrTofGkrMyPX Je+ATi4Ru7MO8+i/Ww8vsJVLgDFl2TCHFq6P+I03nCVZLN0SueCg66kT9 lDF/+2TVDXa8u5K89XIN0D/wlhfgKYzQdQ9Nr0adaelTqyyQsRdA14ewK EOpuMVs0gnPOPpxofrQXS8jJCCKOPXm/TJU5WI/CoFmFEA8BrfbKUI7pg w==; X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9792895" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9792895" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:58:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930310409" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930310409" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:58:13 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com, Xiong Zhang Subject: [RFC PATCH 32/41] KVM: x86/pmu: Add support for PMU context switch at VM-exit/enter Date: Fri, 26 Jan 2024 16:54:35 +0800 Message-Id: <20240126085444.324918-33-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Xiong Zhang Add correct PMU context switch at VM_entry/exit boundary. Signed-off-by: Xiong Zhang Signed-off-by: Mingwei Zhang --- arch/x86/kvm/x86.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 074452aa700d..fe7da1a16c3b 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -10898,6 +10898,9 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) set_debugreg(0, 7); } + if (is_passthrough_pmu_enabled(vcpu)) + kvm_pmu_restore_pmu_context(vcpu); + guest_timing_enter_irqoff(); for (;;) { @@ -10926,6 +10929,9 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) ++vcpu->stat.exits; } + if (is_passthrough_pmu_enabled(vcpu)) + kvm_pmu_save_pmu_context(vcpu); + /* * Do this here before restoring debug registers on the host. And * since we do this before handling the vmexit, a DR access vmexit From patchwork Fri Jan 26 08:54:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532270 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C353744C91; Fri, 26 Jan 2024 08:58:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259505; cv=none; b=Ccb7XzzImUjnUINKaTg/gEnAHrgyaFunxEOizYjNA1M22CIZl10yRbxhrXt2jTa9bMMRdTfT2TBr1n3I/Oe+ZbrkU2+FVrPJTpBWdoTBZI1/RuKNObjlGy1A0UW5sxMk7VPPh63LWbAo9VfY6IIIEf7KIlxHRLQsutlKVOYbCXo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259505; c=relaxed/simple; bh=ddpAkYf+SFjOXBfQ8YDzS6ORpXllmgKkQ9QvOpiV49E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=n1vr1KN/+rr9N37147WCCfEjeB4II3Hs5cRpEbA1tFklSMKwwBwkHodaIxWqwNPfKHT/GKWAWuK3ip1690NCMFder4HetPcZe+hhqT88H1JdxI3baB8w5h8rYmgM7aBDVH6U5rMCnpA0+TUbU4NSKMvIAqz3OpOVQd/5rWOSEqc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XGQ0/Pw4; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XGQ0/Pw4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706259504; x=1737795504; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ddpAkYf+SFjOXBfQ8YDzS6ORpXllmgKkQ9QvOpiV49E=; b=XGQ0/Pw4JBjsshYnqZaj+QvA4kGdI5hfLF7MHOrzX4+/6suY4AJ116bx 8lNV+1ERElEMyntt3LeLNQiy0JO55KbbX79wxxhmRla2a6tPuHbirMH7G SwVOKEu2bSiKxIdDBMMDTwrbOdvE40NlTV7bX0OrfGBA0pONVyC1vCbUl 9uKVMVzjN7mTl0IjHI/TlSP5+l2nTCMgSieEItzoF1CyQ84j+rcBx1Slf MnlnI/B87BHpPbMhGs7QaUiBhS+Nn9+xyoUWcgMaut3stibfcsZJ4p9i/ NAC2Oiy2xmg9VdRsprjunw9gH3efdiRTW8Jqqo66vmEewTWPU2htBbRQm Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9792941" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9792941" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:58:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930310415" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930310415" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:58:18 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com Subject: [RFC PATCH 33/41] KVM: x86/pmu: Make check_pmu_event_filter() an exported function Date: Fri, 26 Jan 2024 16:54:36 +0800 Message-Id: <20240126085444.324918-34-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mingwei Zhang Make check_pmu_event_filter() exported to usable by vendor modules like kvm_intel. This is because passthrough PMU intercept the guest writes to event selectors and directly do the event filter checking inside the vendor specific set_msr() instead of deferring to the KVM_REQ_PMU handler. Signed-off-by: Mingwei Zhang --- arch/x86/kvm/pmu.c | 3 ++- arch/x86/kvm/pmu.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index afc9f7eb3a6b..e7ad97734705 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -356,7 +356,7 @@ static bool is_fixed_event_allowed(struct kvm_x86_pmu_event_filter *filter, return true; } -static bool check_pmu_event_filter(struct kvm_pmc *pmc) +bool check_pmu_event_filter(struct kvm_pmc *pmc) { struct kvm_x86_pmu_event_filter *filter; struct kvm *kvm = pmc->vcpu->kvm; @@ -370,6 +370,7 @@ static bool check_pmu_event_filter(struct kvm_pmc *pmc) return is_fixed_event_allowed(filter, pmc->idx); } +EXPORT_SYMBOL_GPL(check_pmu_event_filter); static bool pmc_event_is_allowed(struct kvm_pmc *pmc) { diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index a4c0b2e2c24b..6f44fe056368 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -292,6 +292,7 @@ void kvm_pmu_trigger_event(struct kvm_vcpu *vcpu, u64 perf_hw_id); void kvm_pmu_passthrough_pmu_msrs(struct kvm_vcpu *vcpu); void kvm_pmu_save_pmu_context(struct kvm_vcpu *vcpu); void kvm_pmu_restore_pmu_context(struct kvm_vcpu *vcpu); +bool check_pmu_event_filter(struct kvm_pmc *pmc); bool is_vmware_backdoor_pmc(u32 pmc_idx); From patchwork Fri Jan 26 08:54:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532271 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 505BA14F522; Fri, 26 Jan 2024 08:58:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259510; cv=none; b=N5fO1D5w2UYpBWA4Kau7P9lweL1y8LQ9TNesS5V4Kvp96R5M2rcYH46oCSgQlZKHHG9AL6+oRX33cQ6iUFVFgtKrsm12MnvEgnVPTjJowbkqyLxPflp8XI8Mrx+q7oqT+9F2rWljxRB9hZVcwIi/jaVbVE4bWxIQ9Fr3OxMepvk= ARC-Message-Signature: i=1; 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d="scan'208";a="930310425" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:58:23 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com, Xiong Zhang Subject: [RFC PATCH 34/41] KVM: x86/pmu: Intercept EVENT_SELECT MSR Date: Fri, 26 Jan 2024 16:54:37 +0800 Message-Id: <20240126085444.324918-35-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Xiong Zhang Event selectors for GP counters are still intercepted for the purpose of security, i.e., preventing guest from using unallowed events to steal information or take advantages of any CPU errata. Signed-off-by: Xiong Zhang Signed-off-by: Mingwei Zhang --- arch/x86/kvm/vmx/pmu_intel.c | 1 - arch/x86/kvm/vmx/vmx.c | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 9bbd5084a766..621922005184 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -809,7 +809,6 @@ void intel_passthrough_pmu_msrs(struct kvm_vcpu *vcpu) int i; for (i = 0; i < vcpu_to_pmu(vcpu)->nr_arch_gp_counters; i++) { - vmx_set_intercept_for_msr(vcpu, MSR_ARCH_PERFMON_EVENTSEL0 + i, MSR_TYPE_RW, false); vmx_set_intercept_for_msr(vcpu, MSR_IA32_PERFCTR0 + i, MSR_TYPE_RW, false); if (fw_writes_is_enabled(vcpu)) vmx_set_intercept_for_msr(vcpu, MSR_IA32_PMC0 + i, MSR_TYPE_RW, false); diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index d28afa87be70..1a518800d154 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -698,7 +698,6 @@ static bool is_valid_passthrough_msr(u32 msr) case MSR_LBR_CORE_FROM ... MSR_LBR_CORE_FROM + 8: case MSR_LBR_CORE_TO ... MSR_LBR_CORE_TO + 8: /* LBR MSRs. These are handled in vmx_update_intercept_for_lbr_msrs() */ - case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 7: case MSR_IA32_PMC0 ... MSR_IA32_PMC0 + 7: case MSR_IA32_PERFCTR0 ... MSR_IA32_PERFCTR0 + 7: case MSR_CORE_PERF_FIXED_CTR_CTRL: From patchwork Fri Jan 26 08:54:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532272 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75FB514F547; Fri, 26 Jan 2024 08:58:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259519; cv=none; b=RXJP5dkVDfBvtRpeVm4rDZ+eGvFjkES9Qapq+97cZMiG91/JHirBle1hEgP87+/cHtFPK67cJxl3kKKAJMOJsWrKKeJCAN0hrZjuBYmRXHL6OFliiYT8gwjytDxTFKCDMg2p+ThNvSozKQ62DOb+LAYQV/NsfoeYnK08TkNhhv4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259519; c=relaxed/simple; bh=Ljh9yt1ZTZazh8g8HMDGH1EBGrH5rCz+avVoyaVnQW0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=h7FckSGJ45OuwP1N29hFRYhOGNsybCPeQcZr+j8MYd5zi6xtBmqfYNdzOzSXAlNTchch31cGaP/g+XCWz+LZNZUX8yYxSWIUVgXT5vqb/5bjTiBZ1kmX4gpSlehUH6VxkvMAlbWPINfZimW86j+5Cg1Z5EExlXkJTcMrPy+TDr8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=B6N9e6bh; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="B6N9e6bh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706259519; x=1737795519; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ljh9yt1ZTZazh8g8HMDGH1EBGrH5rCz+avVoyaVnQW0=; b=B6N9e6bhNtLqJSDKICtGGx0xZuhj2Sv4Lx9oP5e0L0yiMa/uoQF4CqFq BP/qZFV8iXvC+4csqJfYVj020yBu13qsFWK0faaKI+3fblCfYV+WD8oba QNS4eGcsMklNln0ndpS0K5X2U4+PXhKvwlwuAk7vX55V9zMB0qO0SJyAm zlQ0phnECrXLnK18QyZDf1GGua1BEDcPswts8BSDY+xh7fa5UlYLnxNkQ YQZF6XcDVvEFl5iXue33CPLbtok/jAPgmSeCCvf32lWGtSYm1Vsp+Tmgk uWre2CUogfjpMTwG+gDHtAoL3gbRiq/e7vCoi6eZOL1/OdavQI/fwc66I Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9792988" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9792988" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:58:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930310443" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930310443" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:58:28 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com, Xiong Zhang Subject: [RFC PATCH 35/41] KVM: x86/pmu: Allow writing to event selector for GP counters if event is allowed Date: Fri, 26 Jan 2024 16:54:38 +0800 Message-Id: <20240126085444.324918-36-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mingwei Zhang Only allow writing to event selector if event is allowed in filter. Since passthrough PMU implementation does the PMU context switch at VM Enter/Exit boudary, even if the value of event selector passes the checking, it cannot be written directly to HW since PMU HW is owned by the host PMU at the moment. Because of that, introduce eventsel_hw to cache that value which will be assigned into HW just before VM entry. Note that regardless of whether an event value is allowed, the value will be cached in pmc->eventsel and guest VM can always read the cached value back. This implementation is consistent with the HW CPU design. Signed-off-by: Xiong Zhang Signed-off-by: Mingwei Zhang --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/vmx/pmu_intel.c | 18 ++++++++++++++---- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index ede45c923089..fd1c69371dbf 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -503,6 +503,7 @@ struct kvm_pmc { u64 counter; u64 prev_counter; u64 eventsel; + u64 eventsel_hw; struct perf_event *perf_event; struct kvm_vcpu *vcpu; /* diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 621922005184..92c5baed8d36 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -458,7 +458,18 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) if (data & reserved_bits) return 1; - if (data != pmc->eventsel) { + if (is_passthrough_pmu_enabled(vcpu)) { + pmc->eventsel = data; + if (!check_pmu_event_filter(pmc)) { + /* When guest request an invalid event, + * stop the counter by clearing the + * event selector MSR. + */ + pmc->eventsel_hw = 0; + return 0; + } + pmc->eventsel_hw = data; + } else if (data != pmc->eventsel) { pmc->eventsel = data; kvm_pmu_request_counter_reprogram(pmc); } @@ -843,13 +854,12 @@ static void intel_save_pmu_context(struct kvm_vcpu *vcpu) for (i = 0; i < pmu->nr_arch_gp_counters; i++) { pmc = &pmu->gp_counters[i]; rdpmcl(i, pmc->counter); - rdmsrl(i + MSR_ARCH_PERFMON_EVENTSEL0, pmc->eventsel); /* * Clear hardware PERFMON_EVENTSELx and its counter to avoid * leakage and also avoid this guest GP counter get accidentally * enabled during host running when host enable global ctrl. */ - if (pmc->eventsel) + if (pmc->eventsel_hw) wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0); if (pmc->counter) wrmsrl(MSR_IA32_PMC0 + i, 0); @@ -894,7 +904,7 @@ static void intel_restore_pmu_context(struct kvm_vcpu *vcpu) for (i = 0; i < pmu->nr_arch_gp_counters; i++) { pmc = &pmu->gp_counters[i]; wrmsrl(MSR_IA32_PMC0 + i, pmc->counter); - wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, pmc->eventsel); + wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, pmc->eventsel_hw); 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26 Jan 2024 00:58:34 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com, Xiong Zhang Subject: [RFC PATCH 36/41] KVM: x86/pmu: Intercept FIXED_CTR_CTRL MSR Date: Fri, 26 Jan 2024 16:54:39 +0800 Message-Id: <20240126085444.324918-37-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Xiong Zhang Fixed counters control MSR are still intercepted for the purpose of security, i.e., preventing guest from using unallowed Fixed Counter to steal information or take advantages of any CPU errata. Signed-off-by: Xiong Zhang Signed-off-by: Mingwei Zhang --- arch/x86/kvm/vmx/pmu_intel.c | 1 - arch/x86/kvm/vmx/vmx.c | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 92c5baed8d36..713c2a7c7f07 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -825,7 +825,6 @@ void intel_passthrough_pmu_msrs(struct kvm_vcpu *vcpu) vmx_set_intercept_for_msr(vcpu, MSR_IA32_PMC0 + i, MSR_TYPE_RW, false); } - vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_TYPE_RW, false); for (i = 0; i < vcpu_to_pmu(vcpu)->nr_arch_fixed_counters; i++) vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_FIXED_CTR0 + i, MSR_TYPE_RW, false); diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 1a518800d154..7c4e1feb589b 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -700,7 +700,6 @@ static bool is_valid_passthrough_msr(u32 msr) /* LBR MSRs. These are handled in vmx_update_intercept_for_lbr_msrs() */ case MSR_IA32_PMC0 ... MSR_IA32_PMC0 + 7: case MSR_IA32_PERFCTR0 ... MSR_IA32_PERFCTR0 + 7: - case MSR_CORE_PERF_FIXED_CTR_CTRL: case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + 2: case MSR_CORE_PERF_GLOBAL_STATUS: case MSR_CORE_PERF_GLOBAL_CTRL: From patchwork Fri Jan 26 08:54:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532274 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 007544595F; Fri, 26 Jan 2024 08:58:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259526; cv=none; b=pscJeA3C+k5/tDj/DphuC0q6Jyn++RPyhOTQonHAU6wo3igDMYoHRnUl4QQ8R19bsOVk0dxuc5wzmFeiJ3nSd3N8LQXtGVk1qhTITe3uD3Qnxzkact7+KA5OL3sxO/wASuALLRfJcajLeqFc+2deTXmCU+4XQwPc+w9sn7pjFEE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259526; c=relaxed/simple; bh=x5C5Od06oBAnqpreQLTjGicQhvVIOtKOokF+NlLLHQY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SjmzZ15Hisqro4E56jGHAoPkwm4G8IFyqD4iPttW9urllIFpkF2HZ/9AOnEj9mYErmcfVv/gTWrI7a9zhT0cX8lLi6PAuXM4JNmBHg4KZ8qnVgiL5GYfvxAM7hq6EopnyVccTVKXBEnuSlqIIeFucFcDY0oVhKIE+2sjo8MTF9o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nMi0Gc4A; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nMi0Gc4A" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706259525; x=1737795525; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=x5C5Od06oBAnqpreQLTjGicQhvVIOtKOokF+NlLLHQY=; b=nMi0Gc4ADYFhJTLRcbfAXIXn1gdiQxEBQ1guAHIbRNTx46mNJ4bDBNG/ RwlqMRzOak4zYcRTYTd7/fWzeNDoVQgIvzIMu7vmRBSoNrCBXYuFQbp8W E0heKRz/XWJiEgWKh/V5EqU3ubcyMkgzfg/0a9nk1bX+RWyU7szyzVAlo A/x9v54YtEecH4MvnhqzxhJN0btVqFL8pkV9e9WaySD2gB9FcmBoT6lYw sh4zNDLYhIN3neLUmR+6TwZavGDVnQSmEiRcM4gtUWXpJEw+/HRb67ebK P9Ci+/PdQByC9EAoa/dKy61GNd3hpePGNQjmfLiXfPx6S5XUZJVC8e1ij g==; X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9793046" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9793046" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:58:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930310478" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930310478" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:58:39 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com Subject: [RFC PATCH 37/41] KVM: x86/pmu: Allow writing to fixed counter selector if counter is exposed Date: Fri, 26 Jan 2024 16:54:40 +0800 Message-Id: <20240126085444.324918-38-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mingwei Zhang Allow writing to fixed counter selector if counter is exposed. If this fixed counter is filtered out, this counter won't be enabled on HW. Passthrough PMU implements the context switch at VM Enter/Exit boundary the guest value cannot be directly written to HW since the HW PMU is owned by the host. Introduce a new field fixed_ctr_ctrl_hw in kvm_pmu to cache the guest value. which will be assigne to HW at PMU context restore. Since passthrough PMU intercept writes to fixed counter selector, there is no need to read the value at pmu context save, but still clear the fix counter ctrl MSR and counters when switching out to host PMU. Signed-off-by: Mingwei Zhang --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/vmx/pmu_intel.c | 28 ++++++++++++++++++++++++---- 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index fd1c69371dbf..b02688ed74f7 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -527,6 +527,7 @@ struct kvm_pmu { unsigned nr_arch_fixed_counters; unsigned available_event_types; u64 fixed_ctr_ctrl; + u64 fixed_ctr_ctrl_hw; u64 fixed_ctr_ctrl_mask; u64 global_ctrl; u64 global_status; diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 713c2a7c7f07..93cfb86c1292 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -68,6 +68,25 @@ static int fixed_pmc_events[] = { [2] = PSEUDO_ARCH_REFERENCE_CYCLES, }; +static void reprogram_fixed_counters_in_passthrough_pmu(struct kvm_pmu *pmu, u64 data) +{ + struct kvm_pmc *pmc; + u64 new_data = 0; + int i; + + for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { + pmc = get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i); + if (check_pmu_event_filter(pmc)) { + pmc->current_config = fixed_ctrl_field(data, i); + new_data |= intel_fixed_bits_by_idx(i, pmc->current_config); + } else { + pmc->counter = 0; + } + } + pmu->fixed_ctr_ctrl_hw = new_data; + pmu->fixed_ctr_ctrl = data; +} + static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data) { struct kvm_pmc *pmc; @@ -401,7 +420,9 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) if (data & pmu->fixed_ctr_ctrl_mask) return 1; - if (pmu->fixed_ctr_ctrl != data) + if (is_passthrough_pmu_enabled(vcpu)) + reprogram_fixed_counters_in_passthrough_pmu(pmu, data); + else if (pmu->fixed_ctr_ctrl != data) reprogram_fixed_counters(pmu, data); break; case MSR_IA32_PEBS_ENABLE: @@ -864,13 +885,12 @@ static void intel_save_pmu_context(struct kvm_vcpu *vcpu) wrmsrl(MSR_IA32_PMC0 + i, 0); } - rdmsrl(MSR_CORE_PERF_FIXED_CTR_CTRL, pmu->fixed_ctr_ctrl); /* * Clear hardware FIXED_CTR_CTRL MSR to avoid information leakage and * also avoid these guest fixed counters get accidentially enabled * during host running when host enable global ctrl. */ - if (pmu->fixed_ctr_ctrl) + if (pmu->fixed_ctr_ctrl_hw) wrmsrl(MSR_CORE_PERF_FIXED_CTR_CTRL, 0); for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { pmc = &pmu->fixed_counters[i]; @@ -915,7 +935,7 @@ static void intel_restore_pmu_context(struct kvm_vcpu *vcpu) wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0); } - wrmsrl(MSR_CORE_PERF_FIXED_CTR_CTRL, pmu->fixed_ctr_ctrl); + wrmsrl(MSR_CORE_PERF_FIXED_CTR_CTRL, pmu->fixed_ctr_ctrl_hw); for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { pmc = &pmu->fixed_counters[i]; wrmsrl(MSR_CORE_PERF_FIXED_CTR0 + i, pmc->counter); From patchwork Fri Jan 26 08:54:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Zhang X-Patchwork-Id: 13532275 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D64145C1F; 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X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="9793069" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9793069" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:58:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930310492" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930310492" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:58:44 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com Subject: [RFC PATCH 38/41] KVM: x86/pmu: Introduce PMU helper to increment counter Date: Fri, 26 Jan 2024 16:54:41 +0800 Message-Id: <20240126085444.324918-39-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mingwei Zhang Introduce PMU helper to increment counter for passthrough PMU because it is able to conveniently return the overflow condition instead of deferring the overflow check to KVM_REQ_PMU in original implementation. In addition, this helper function can hide architecture details. Signed-off-by: Mingwei Zhang --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/pmu.c | 15 +++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index b02688ed74f7..869de0d81055 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -501,6 +501,7 @@ struct kvm_pmc { bool is_paused; bool intr; u64 counter; + u64 emulated_counter; u64 prev_counter; u64 eventsel; u64 eventsel_hw; diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index e7ad97734705..7b0bac1ac4bf 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -434,6 +434,21 @@ static void reprogram_counter(struct kvm_pmc *pmc) pmc->prev_counter = 0; } +static bool kvm_passthrough_pmu_incr_counter(struct kvm_pmc *pmc) +{ + if (!pmc->emulated_counter) + return false; + + pmc->counter += pmc->emulated_counter; + pmc->emulated_counter = 0; + pmc->counter &= pmc_bitmask(pmc); + + if (!pmc->counter) + return true; + + return false; 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26 Jan 2024 00:58:49 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com Subject: [RFC PATCH 39/41] KVM: x86/pmu: Implement emulated counter increment for passthrough PMU Date: Fri, 26 Jan 2024 16:54:42 +0800 Message-Id: <20240126085444.324918-40-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mingwei Zhang Implement emulated counter increment for passthrough PMU under KVM_REQ_PMU. Defer the counter increment to KVM_REQ_PMU handler because counter increment requests come from kvm_pmu_trigger_event() which can be triggered within the KVM_RUN inner loop or outside of the inner loop. This means the counter increment could happen before or after PMU context switch. So process counter increment in one place makes the implementation simple. Signed-off-by: Mingwei Zhang --- arch/x86/include/asm/kvm_host.h | 2 ++ arch/x86/kvm/pmu.c | 52 ++++++++++++++++++++++++++++++++- arch/x86/kvm/pmu.h | 1 + arch/x86/kvm/x86.c | 8 +++-- 4 files changed, 60 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 869de0d81055..9080319751de 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -532,6 +532,7 @@ struct kvm_pmu { u64 fixed_ctr_ctrl_mask; u64 global_ctrl; u64 global_status; + u64 synthesized_overflow; u64 counter_bitmask[2]; u64 global_ctrl_mask; u64 global_status_mask; @@ -550,6 +551,7 @@ struct kvm_pmu { atomic64_t __reprogram_pmi; }; DECLARE_BITMAP(all_valid_pmc_idx, X86_PMC_IDX_MAX); + DECLARE_BITMAP(incremented_pmc_idx, X86_PMC_IDX_MAX); DECLARE_BITMAP(pmc_in_use, X86_PMC_IDX_MAX); u64 ds_area; diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 7b0bac1ac4bf..9e62e96fe48a 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -449,6 +449,26 @@ static bool kvm_passthrough_pmu_incr_counter(struct kvm_pmc *pmc) return false; } +void kvm_passthrough_pmu_handle_event(struct kvm_vcpu *vcpu) +{ + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + int bit; + + for_each_set_bit(bit, pmu->incremented_pmc_idx, X86_PMC_IDX_MAX) { + struct kvm_pmc *pmc = static_call(kvm_x86_pmu_pmc_idx_to_pmc)(pmu, bit); + + if (kvm_passthrough_pmu_incr_counter(pmc)) { + __set_bit(pmc->idx, (unsigned long *)&pmc_to_pmu(pmc)->synthesized_overflow); + + if (pmc->eventsel & ARCH_PERFMON_EVENTSEL_INT) + kvm_make_request(KVM_REQ_PMI, vcpu); + } + } + bitmap_zero(pmu->incremented_pmc_idx, X86_PMC_IDX_MAX); + pmu->global_status |= pmu->synthesized_overflow; + pmu->synthesized_overflow = 0; +} + void kvm_pmu_handle_event(struct kvm_vcpu *vcpu) { struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); @@ -748,7 +768,29 @@ static inline bool cpl_is_matched(struct kvm_pmc *pmc) return (static_call(kvm_x86_get_cpl)(pmc->vcpu) == 0) ? select_os : select_user; } -void kvm_pmu_trigger_event(struct kvm_vcpu *vcpu, u64 perf_hw_id) +static void __kvm_passthrough_pmu_trigger_event(struct kvm_vcpu *vcpu, u64 perf_hw_id) +{ + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + struct kvm_pmc *pmc; + int i; + + for_each_set_bit(i, pmu->all_valid_pmc_idx, X86_PMC_IDX_MAX) { + pmc = static_call(kvm_x86_pmu_pmc_idx_to_pmc)(pmu, i); + + if (!pmc || !pmc_speculative_in_use(pmc) || + !check_pmu_event_filter(pmc)) + continue; + + /* Ignore checks for edge detect, pin control, invert and CMASK bits */ + if (eventsel_match_perf_hw_id(pmc, perf_hw_id) && cpl_is_matched(pmc)) { + pmc->emulated_counter += 1; + __set_bit(pmc->idx, pmu->incremented_pmc_idx); + kvm_make_request(KVM_REQ_PMU, vcpu); + } + } +} + +static void __kvm_pmu_trigger_event(struct kvm_vcpu *vcpu, u64 perf_hw_id) { struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); struct kvm_pmc *pmc; @@ -765,6 +807,14 @@ void kvm_pmu_trigger_event(struct kvm_vcpu *vcpu, u64 perf_hw_id) kvm_pmu_incr_counter(pmc); } } + +void kvm_pmu_trigger_event(struct kvm_vcpu *vcpu, u64 perf_hw_id) +{ + if (is_passthrough_pmu_enabled(vcpu)) + __kvm_passthrough_pmu_trigger_event(vcpu, perf_hw_id); + else + __kvm_pmu_trigger_event(vcpu, perf_hw_id); +} EXPORT_SYMBOL_GPL(kvm_pmu_trigger_event); static bool is_masked_filter_valid(const struct kvm_x86_pmu_event_filter *filter) diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 6f44fe056368..0fc37a06fe48 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -277,6 +277,7 @@ static inline bool is_passthrough_pmu_enabled(struct kvm_vcpu *vcpu) void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu); void kvm_pmu_handle_event(struct kvm_vcpu *vcpu); +void kvm_passthrough_pmu_handle_event(struct kvm_vcpu *vcpu); int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); bool kvm_pmu_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx); bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index fe7da1a16c3b..1bbf312cbd73 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -10726,8 +10726,12 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) } if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) record_steal_time(vcpu); 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d="scan'208";a="930310561" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:58:54 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com Subject: [RFC PATCH 40/41] KVM: x86/pmu: Separate passthrough PMU logic in set/get_msr() from non-passthrough vPMU Date: Fri, 26 Jan 2024 16:54:43 +0800 Message-Id: <20240126085444.324918-41-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mingwei Zhang Separate passthrough PMU logic from non-passthrough vPMU code. There are two places in passthrough vPMU when set/get_msr() may call into the existing non-passthrough vPMU code: 1) set/get counters; 2) set global_ctrl MSR. In the former case, non-passthrough vPMU will call into pmc_{read,write}_counter() which wires to the perf API. Update these functions to avoid the perf API invocation. The 2nd case is where global_ctrl MSR writes invokes reprogram_counters() which will invokes the non-passthrough PMU logic. So use pmu->passthrough flag to wrap out the call. Signed-off-by: Mingwei Zhang --- arch/x86/kvm/pmu.c | 4 +++- arch/x86/kvm/pmu.h | 10 +++++++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 9e62e96fe48a..de653a67ba93 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -652,7 +652,9 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) if (pmu->global_ctrl != data) { diff = pmu->global_ctrl ^ data; pmu->global_ctrl = data; - reprogram_counters(pmu, diff); + /* Passthrough vPMU never reprogram counters. */ + if (!pmu->passthrough) + reprogram_counters(pmu, diff); } break; case MSR_CORE_PERF_GLOBAL_OVF_CTRL: diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 0fc37a06fe48..ab8d4a8e58a8 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -70,6 +70,9 @@ static inline u64 pmc_read_counter(struct kvm_pmc *pmc) u64 counter, enabled, running; counter = pmc->counter; + if (pmc_to_pmu(pmc)->passthrough) + return counter & pmc_bitmask(pmc); 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d="scan'208";a="9793186" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:59:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930310591" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930310591" Received: from yanli3-mobl.ccr.corp.intel.com (HELO xiongzha-desk1.ccr.corp.intel.com) ([10.254.213.178]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 00:59:00 -0800 From: Xiong Zhang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com Subject: [RFC PATCH 41/41] KVM: nVMX: Add nested virtualization support for passthrough PMU Date: Fri, 26 Jan 2024 16:54:44 +0800 Message-Id: <20240126085444.324918-42-xiong.y.zhang@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mingwei Zhang Add nested virtualization support for passthrough PMU by combining the MSR interception bitmaps of vmcs01 and vmcs12. Readers may argue even without this patch, nested virtualization works for passthrough PMU because L1 will see Perfmon v2 and will have to use legacy vPMU implementation if it is Linux. However, any assumption made on L1 may be invalid, e.g., L1 may not even be Linux. If both L0 and L1 pass through PMU MSRs, the correct behavior is to allow MSR access from L2 directly touch HW MSRs, since both L0 and L1 passthrough the access. However, in current implementation, if without adding anything for nested, KVM always set MSR interception bits in vmcs02. This leads to the fact that L0 will emulate all MSR read/writes for L2, leading to errors, since the current passthrough vPMU never implements set_msr() and get_msr() for any counter access except counter accesses from the VMM side. So fix the issue by setting up the correct MSR interception for PMU MSRs. Signed-off-by: Mingwei Zhang --- arch/x86/kvm/vmx/nested.c | 52 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index c5ec0ef51ff7..95e1c78152da 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -561,6 +561,55 @@ static inline void nested_vmx_set_intercept_for_msr(struct vcpu_vmx *vmx, msr_bitmap_l0, msr); } +/* Pass PMU MSRs to nested VM if L0 and L1 are set to passthrough. */ +static void nested_vmx_set_passthru_pmu_intercept_for_msr(struct kvm_vcpu *vcpu, + unsigned long *msr_bitmap_l1, + unsigned long *msr_bitmap_l0) +{ + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + struct vcpu_vmx *vmx = to_vmx(vcpu); + int i; + + for (i = 0; i < pmu->nr_arch_gp_counters; i++) { + nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, + msr_bitmap_l0, + MSR_ARCH_PERFMON_EVENTSEL0 + i, + MSR_TYPE_RW); + nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, + msr_bitmap_l0, + MSR_IA32_PERFCTR0 + i, + MSR_TYPE_RW); + nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, + msr_bitmap_l0, + MSR_IA32_PMC0 + i, + MSR_TYPE_RW); + } + + for (i = 0; i < vcpu_to_pmu(vcpu)->nr_arch_fixed_counters; i++) { + nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, + msr_bitmap_l0, + MSR_CORE_PERF_FIXED_CTR0 + i, + MSR_TYPE_RW); + } + nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, + msr_bitmap_l0, + MSR_CORE_PERF_FIXED_CTR_CTRL, + MSR_TYPE_RW); + + nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, + msr_bitmap_l0, + MSR_CORE_PERF_GLOBAL_STATUS, + MSR_TYPE_RW); + nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, + msr_bitmap_l0, + MSR_CORE_PERF_GLOBAL_CTRL, + MSR_TYPE_RW); + nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, + msr_bitmap_l0, + MSR_CORE_PERF_GLOBAL_OVF_CTRL, + MSR_TYPE_RW); +} + /* * Merge L0's and L1's MSR bitmap, return false to indicate that * we do not use the hardware. @@ -660,6 +709,9 @@ static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu, nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0, MSR_IA32_FLUSH_CMD, MSR_TYPE_W); + if (is_passthrough_pmu_enabled(vcpu)) + nested_vmx_set_passthru_pmu_intercept_for_msr(vcpu, msr_bitmap_l1, msr_bitmap_l0); + kvm_vcpu_unmap(vcpu, &vmx->nested.msr_bitmap_map, false); vmx->nested.force_msr_bitmap_recalc = false;