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Mon, 29 Jan 2024 07:26:42 +0000 Received: from ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn ([fe80::8de6:348f:764f:293d]) by ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn ([fe80::8de6:348f:764f:293d%4]) with mapi id 15.20.7249.015; Mon, 29 Jan 2024 07:26:42 +0000 From: Ley Foon Tan To: Daniel Lezcano , Thomas Gleixner , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: atishp@rivosinc.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Ley Foon Tan , stable@vger.kernel.org Subject: [PATCH v2] clocksource: timer-riscv: Clear timer interrupt on timer initialization Date: Mon, 29 Jan 2024 15:26:25 +0800 Message-ID: <20240129072625.2837771-1-leyfoon.tan@starfivetech.com> X-Mailer: git-send-email 2.43.0 X-ClientProxiedBy: SH0PR01CA0007.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:5::19) To ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:f::12) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQZPR01MB0979:EE_|ZQZPR01MB0961:EE_ X-MS-Office365-Filtering-Correlation-Id: ef82b62c-f28c-4d35-f8a4-08dc209ba3e6 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; 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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org In the RISC-V specification, the stimecmp register doesn't have a default value. To prevent the timer interrupt from being triggered during timer initialization, clear the timer interrupt by writing stimecmp with a maximum value. Fixes: 9f7a8ff6391f ("RISC-V: Prefer sstc extension if available") Cc: Signed-off-by: Ley Foon Tan Reviewed-by: Anup Patel --- v2: Resolved comments from Anup. - Moved riscv_clock_event_stop() to riscv_timer_starting_cpu(). - Added Fixes tag --- drivers/clocksource/timer-riscv.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index e66dcbd66566..672669eb7281 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -116,6 +116,9 @@ static int riscv_timer_starting_cpu(unsigned int cpu) ce->rating = 450; clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff); + /* Clear timer interrupt */ + riscv_clock_event_stop(); + enable_percpu_irq(riscv_clock_event_irq, irq_get_trigger_type(riscv_clock_event_irq)); return 0;