From patchwork Mon Jan 29 17:55:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13536162 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B0C4C47DB3 for ; Mon, 29 Jan 2024 17:55:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B5E2D112A51; Mon, 29 Jan 2024 17:55:31 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id B1357112A51 for ; Mon, 29 Jan 2024 17:55:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706550931; x=1738086931; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=qZ/SZIBrHeXAxbyp6/bE6FZgOSL6XPfz3Ds/QWV37Nc=; b=kSDvre5bbYKhJSJoYe+Ue13YAM1fK9olLplDsqhBTOT7iWeKEESVcMwW fwUiYyf0LsN3PM76JFYi1L7x4rhGDaGxfgHTiBlS6fPBto7QnAQLYkmnT S6fdImUb/Gg54PVWdYL0msNWU7SJnZ+80/A1znmrw8dulOr2Z3HPI4sdL WBm8orPSpzNe2aH3ZxIe8tJ528zYQc9+f/NXb+KeOvBRbbQK5XF9ejubb K/g4u6gyD2gAtKww2+5mIzrM4TMsoDlt0JCx8Ux5ZAqSU3bpwYZzPVC3J Uu1V3R3y1wbHEvuz7CQYmOQuk4RG2MeNpioQtkLmmVISe3YMMRT03R1ob w==; X-IronPort-AV: E=McAfee;i="6600,9927,10968"; a="10407773" X-IronPort-AV: E=Sophos;i="6.05,227,1701158400"; d="scan'208";a="10407773" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2024 09:55:18 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10968"; a="931157877" X-IronPort-AV: E=Sophos;i="6.05,227,1701158400"; d="scan'208";a="931157877" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2024 09:55:17 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 1/6] drm/i915/adlp: Add MST FEC BS jitter WA (Wa_14013163432) Date: Mon, 29 Jan 2024 19:55:28 +0200 Message-Id: <20240129175533.904590-2-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240129175533.904590-1-imre.deak@intel.com> References: <20240129175533.904590-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a workaround to fix BS (blank start) to BS jitter issues on MST links when FEC is enabled. Neither Bspec requires this nor Windows clears the WA when disabling the output - presumedly because CHICKEN_MISC_3 gets reset after disabling the pipe/transcoder - so follow suit. Bspec: 50050, 55424 Signed-off-by: Imre Deak Reviewed-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 24 +++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 5fa25a5a36b55..22c1759f912db 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1106,6 +1106,28 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, intel_ddi_set_dp_msa(pipe_config, conn_state); } +static void enable_bs_jitter_was(const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + u32 clear = 0; + u32 set = 0; + + if (!IS_ALDERLAKE_P(i915)) + return; + + if (!IS_DISPLAY_STEP(i915, STEP_D0, STEP_FOREVER)) + return; + + /* Wa_14013163432:adlp */ + if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state)) + set |= DP_MST_FEC_BS_JITTER_WA(crtc_state->cpu_transcoder); + + if (!clear && !set) + return; + + intel_de_rmw(i915, CHICKEN_MISC_3, clear, set); +} + static void intel_mst_enable_dp(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, @@ -1134,6 +1156,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); } + enable_bs_jitter_was(pipe_config); + intel_ddi_enable_transcoder_func(encoder, pipe_config); clear_act_sent(encoder, pipe_config); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 75bc08081fce9..67b7d02ea37bf 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4555,6 +4555,9 @@ #define GLK_CL1_PWR_DOWN REG_BIT(11) #define GLK_CL0_PWR_DOWN REG_BIT(10) +#define CHICKEN_MISC_3 _MMIO(0x42088) +#define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A) + #define CHICKEN_MISC_4 _MMIO(0x4208c) #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13) #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0) From patchwork Mon Jan 29 17:55:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13536163 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3179BC48285 for ; Mon, 29 Jan 2024 17:55:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E5EE0112A5B; Mon, 29 Jan 2024 17:55:31 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id EBB09112A51 for ; Mon, 29 Jan 2024 17:55:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706550931; x=1738086931; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=YPi19jVfe7jo8mwLLgxMxlpxZfcWUXm4qU1Ce2LZKJ8=; b=Vi9NHDA8yWZ3Baov67nydCZ+GH4m/6RkzmAeMwGnGL0eWKLYJufxD7KX jUNR5HL3Z5Lq8EjSWK4t2a3nir4QUENBbG8wx1Be5SSEGaJYpZ6hLBDfI KljnJLAHC3Haoge5CJF2r1SBtVe49t3kL4LZs1PaIlzhF5Ysw3IYocqWm nLznfYINZnDQf5bmdziOzSw6KRY6pxzFZDWnNW/nwSRmEG0cctLkF8NTC GnghEZML3y4OSmFT1aLay6gRvUKErfVUgW/ww1J7Qc00hsdXbjZzG4RKG 4lNxOaMCzAht3DCDoWG2qu5I+hHfFmy79z5h+dYMmZVzkoSNaBJuKA46f A==; X-IronPort-AV: E=McAfee;i="6600,9927,10968"; a="10407778" X-IronPort-AV: E=Sophos;i="6.05,227,1701158400"; d="scan'208";a="10407778" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2024 09:55:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10968"; a="931157881" X-IronPort-AV: E=Sophos;i="6.05,227,1701158400"; d="scan'208";a="931157881" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2024 09:55:18 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 2/6] drm/i915/adlp: Add MST short HBlank WA (Wa_14014143976) Date: Mon, 29 Jan 2024 19:55:29 +0200 Message-Id: <20240129175533.904590-3-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240129175533.904590-1-imre.deak@intel.com> References: <20240129175533.904590-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a workaround to fix BS jitter issues on MST links if the HBLANK period is less than 1 MTP. The WA applies only to UHBR rates while on non-UHBR the specification requires disabling it explicitly - presumedly because the register's reset value has the WA enabled. Bspec: 50050, 55424 Signed-off-by: Imre Deak Reviewed-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++++++++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 22c1759f912db..23f3f7fab9d0b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1122,6 +1122,14 @@ static void enable_bs_jitter_was(const struct intel_crtc_state *crtc_state) if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state)) set |= DP_MST_FEC_BS_JITTER_WA(crtc_state->cpu_transcoder); + /* Wa_14014143976:adlp */ + if (IS_DISPLAY_STEP(i915, STEP_E0, STEP_FOREVER)) { + if (intel_dp_is_uhbr(crtc_state)) + set |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder); + else if (crtc_state->fec_enable) + clear |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder); + } + if (!clear && !set) return; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 67b7d02ea37bf..091edc1071e0e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4556,6 +4556,7 @@ #define GLK_CL0_PWR_DOWN REG_BIT(10) #define CHICKEN_MISC_3 _MMIO(0x42088) +#define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A) #define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A) #define CHICKEN_MISC_4 _MMIO(0x4208c) From patchwork Mon Jan 29 17:55:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13536166 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2D9EAC48286 for ; Mon, 29 Jan 2024 17:55:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8D177112A66; Mon, 29 Jan 2024 17:55:40 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4E8C5112A51 for ; Mon, 29 Jan 2024 17:55:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706550931; x=1738086931; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=n0++DhuNpJoy/zBYCTAI/EcSjxqDWc9WHs44kb0A8V4=; b=YvciegQZFztmUMQEnxgEIWyUwGw6jwaHvMkRvqjoAfbS7uJgB7Hn9e1L gn0axuPDXjuxs9pSvlpxCtaIYmBAXnw5cv0hU2aEWstf3LURB6tU0xabO X7ZMYLUok5VnVhmuLS0AzTh3oonhXbNlYM+MlxoAvTGFxZv61o+beU60X 2pektjPLMFcGBRrt4zuBCqtQcMmP8OicOvTtl2eZT07sAjt/qTE8Wjqnd ODOgC5O7R89qYUHjAco91vTd3qvgpRUvduSOht/SoKRqvFttIEeExGDrJ Tr8/6CbVCfXEYg/3XHnmvUP8FSqGEdgvHIE+7iQP6e7e/SIUFkDk3DphJ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10968"; a="10407789" X-IronPort-AV: E=Sophos;i="6.05,227,1701158400"; d="scan'208";a="10407789" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2024 09:55:20 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10968"; a="931157883" X-IronPort-AV: E=Sophos;i="6.05,227,1701158400"; d="scan'208";a="931157883" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2024 09:55:19 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 3/6] drm/i915/adlp: Add DP MST DPT/DPTP alignment WA (Wa_14014143976) Date: Mon, 29 Jan 2024 19:55:30 +0200 Message-Id: <20240129175533.904590-4-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240129175533.904590-1-imre.deak@intel.com> References: <20240129175533.904590-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a workaround to fix BS-BS jitter issues on MST links, aligning DPT/DPTP MTPs. Bspec: 50050, 55424 Signed-off-by: Imre Deak Reviewed-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 23f3f7fab9d0b..26c838ac9e411 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1128,6 +1128,9 @@ static void enable_bs_jitter_was(const struct intel_crtc_state *crtc_state) set |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder); else if (crtc_state->fec_enable) clear |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder); + + if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state)) + set |= DP_MST_DPT_DPTP_ALIGN_WA(crtc_state->cpu_transcoder); } if (!clear && !set) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 091edc1071e0e..eecbdecb8ed40 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4556,6 +4556,7 @@ #define GLK_CL0_PWR_DOWN REG_BIT(10) #define CHICKEN_MISC_3 _MMIO(0x42088) +#define DP_MST_DPT_DPTP_ALIGN_WA(trans) REG_BIT(9 + (trans) - TRANSCODER_A) #define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A) #define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A) From patchwork Mon Jan 29 17:55:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13536164 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4ADEFC47DB3 for ; Mon, 29 Jan 2024 17:55:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 839BE112A48; Mon, 29 Jan 2024 17:55:36 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 89EFE112A51 for ; Mon, 29 Jan 2024 17:55:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706550932; x=1738086932; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=SGmrjdQjqkX7Wr12Cdv8h5xWfSzYHeNQsbsYQnouFJA=; b=EVYKDTACQ1UIte27eNdvF2QcU0UQIpsqg3Oy76E2IKCDh10Yu5pGB4ye //wBf7JtUmtX32Sc17Nadaloh3MFjERhRd1dbA8aXMGd1KmHdmgyDGmJg HLAU7T9qfuv5fgxTfecWWpcXbnwobYaqcJ5inJRIvEJZu/W/9WtUSiu+h nWDfWBJcr/E8Ma4ueTFA5UF5CcqCcMuiGbLuegzfnsl1t34rMd/r+fKyS DSLlc4zCWcEls1jm0XXRBUJJpJP9nc+kIjNbBwOlRhReGGGbL/GuR3+AY y3tYRkq0NhB5xbogVbvRu5YXjqphPOB30sjd6lbVWLTy9wQgmS1gJWsOu Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10968"; a="10407795" X-IronPort-AV: E=Sophos;i="6.05,227,1701158400"; d="scan'208";a="10407795" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2024 09:55:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10968"; a="931157886" X-IronPort-AV: E=Sophos;i="6.05,227,1701158400"; d="scan'208";a="931157886" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2024 09:55:20 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 4/6] drm/i915/adlp+: Add DSC early pixel count scaling WA (Wa_1409098942) Date: Mon, 29 Jan 2024 19:55:31 +0200 Message-Id: <20240129175533.904590-5-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240129175533.904590-1-imre.deak@intel.com> References: <20240129175533.904590-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a workaround to fix timing issues on links with DSC enabled - presumedly related to the audio functionality. Bspec requires enabling this workaround if audio is enabled on ADLP, however Windows enables it whenever DSC is enabled ADLP onwards; follow Windows. Bspec: 50490, 55424 Signed-off-by: Imre Deak Reviewed-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a92e959c8ac7b..0f4cd634d7dce 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -435,6 +435,14 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) return; } + /* Wa_1409098942: adlp+ */ + if (DISPLAY_VER(dev_priv) >= 13 && + new_crtc_state->dsc.compression_enable) { + val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK; + val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK, + TRANSCONF_PIXEL_COUNT_SCALING_X4); + } + intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val | TRANSCONF_ENABLE); intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); @@ -481,6 +489,11 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) if (!IS_I830(dev_priv)) val &= ~TRANSCONF_ENABLE; + /* Wa_1409098942: adlp+ */ + if (DISPLAY_VER(dev_priv) >= 13 && + old_crtc_state->dsc.compression_enable) + val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK; + intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); if (DISPLAY_VER(dev_priv) >= 12) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index eecbdecb8ed40..b43d1145fa22f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2588,6 +2588,9 @@ #define TRANSCONF_DITHER_TYPE_ST1 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1) #define TRANSCONF_DITHER_TYPE_ST2 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2) #define TRANSCONF_DITHER_TYPE_TEMP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3) +#define TRANSCONF_PIXEL_COUNT_SCALING_MASK REG_GENMASK(1, 0) +#define TRANSCONF_PIXEL_COUNT_SCALING_X4 1 + #define _PIPEASTAT 0x70024 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) From patchwork Mon Jan 29 17:55:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13536167 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0F3ECC47DB3 for ; Mon, 29 Jan 2024 17:55:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E72A4112A6B; Mon, 29 Jan 2024 17:55:40 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 092B3112A62 for ; Mon, 29 Jan 2024 17:55:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706550932; x=1738086932; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=zv8S0p5juj9Ckv9dhV/2P1eTcAzFQH3I+1COUqWcEDk=; b=R7jZWLHQrgYOlTyLgUiiPeDBqfRCG0UT7Er2a/LH4wdIFQuXTWP1RuZg 0PdsXzjjKIiLLOkTyfYUWDqB9sIsOWt9DPYaebVCu4uZc/DG5S9W6ntva MK7chMc9luRs8kgtE5T6hPqNsEXyyhPTYe1adfqaNz8R6EAFeHX7Dqx3W KO6rEfVg1+akKnWwSmzS877BAr8nEZbhNmgEcNUeBmB3ddlcEUwrstRGl /9ZmQtbP17NSTiz2SRGy+NzLfENoE+R0hqXmqGxPfi56vm62MOX2GH820 Xbfs3K2Cwdd8ortOJCcODftxZzrNL73J/S8Idz1DDfwdujmhPAUYWL1zi Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10968"; a="10407809" X-IronPort-AV: E=Sophos;i="6.05,227,1701158400"; d="scan'208";a="10407809" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2024 09:55:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10968"; a="931157890" X-IronPort-AV: E=Sophos;i="6.05,227,1701158400"; d="scan'208";a="931157890" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2024 09:55:21 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 5/6] drm/i915/mtl+: Disable DP/DSC SF insertion at EOL WA Date: Mon, 29 Jan 2024 19:55:32 +0200 Message-Id: <20240129175533.904590-6-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240129175533.904590-1-imre.deak@intel.com> References: <20240129175533.904590-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Disable the workaround inserting an SF symbol between the last DSC EOC symbol and the subsequent BS symbol. The WA is enabled by default - based on the register's reset value - and Bspec requires disabling it explicitly. Bspec doesn't provide an actual WA ID for this. Bspec: 50054, 65448, 68849 Signed-off-by: Imre Deak Reviewed-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0f4cd634d7dce..e0b75aa18ae33 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -428,6 +428,15 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 0, PIPE_ARB_USE_PROG_SLOTS); + if (DISPLAY_VER(dev_priv) >= 14) { + u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA; + u32 set = 0; + + intel_de_rmw(dev_priv, + hsw_chicken_trans_reg(dev_priv, cpu_transcoder), + clear, set); + } + val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); if (val & TRANSCONF_ENABLE) { /* we keep both pipes enabled on 830 */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b43d1145fa22f..9873daa16c6a1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4620,6 +4620,7 @@ #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */ #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15) #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) +#define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4) #define DISP_ARB_CTL _MMIO(0x45000) #define DISP_FBC_MEMORY_WAKE REG_BIT(31) From patchwork Mon Jan 29 17:55:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13536165 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9715C48285 for ; Mon, 29 Jan 2024 17:55:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 048A1112A52; Mon, 29 Jan 2024 17:55:37 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5C0B4112A62 for ; Mon, 29 Jan 2024 17:55:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706550932; x=1738086932; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=P/CDwbETja9AvT67wFsZ5rTxa3bYhHCuCTgU4WjZUPE=; b=nRqkS3qevCUuTGvCk2WAE+P5sbeH4IymUZVzdK6mhk0NQ94Og4DZAbWa rfrOGASIkxOpvHg13LegoI0icF4Unz+3Ryk6mFS39LFFCqAtcQ2ngSsYd NN21QAsLKKcM6FNCbOA+UVwJ24QxqNyXuLCqQlgWKNln192WQfDGP/+ym HY3JtELoD0oD3aUJdtsshKkXMOCBHYjmNwz1iBSo9xCUQSN62RUX9NMDr Sitq+BwD3kXnxihYaTu31JqaFBJbITHyPl6FWnBuqT/IGjoiU2wNp5U1V C4eDKNDYt4G8S70uWRpbYSRlqdcVE2MLGs1QjrG8LhhogV2bd2/8CT42J g==; X-IronPort-AV: E=McAfee;i="6600,9927,10968"; a="10407811" X-IronPort-AV: E=Sophos;i="6.05,227,1701158400"; d="scan'208";a="10407811" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2024 09:55:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10968"; a="931157894" X-IronPort-AV: E=Sophos;i="6.05,227,1701158400"; d="scan'208";a="931157894" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2024 09:55:22 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 6/6] drm/i915/mtl: Add DP FEC BS jitter WA Date: Mon, 29 Jan 2024 19:55:33 +0200 Message-Id: <20240129175533.904590-7-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240129175533.904590-1-imre.deak@intel.com> References: <20240129175533.904590-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a workaround to fix BS (blank start) to BS jitter fixes on non-UHBR MST/FEC and UHBR links. Bspec doesn't provide an actual WA ID for this. Bspec: 65448, 50054 Signed-off-by: Imre Deak Reviewed-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index e0b75aa18ae33..72a852cccd3f3 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -432,6 +432,9 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA; u32 set = 0; + if (DISPLAY_VER(dev_priv) == 14) + set |= DP_FEC_BS_JITTER_WA; + intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder), clear, set); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9873daa16c6a1..d86e904ffe893 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4619,6 +4619,7 @@ #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */ #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */ #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15) +#define DP_FEC_BS_JITTER_WA REG_BIT(15) #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) #define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4)