From patchwork Wed Jan 31 00:37:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 13538434 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F69417F8; Wed, 31 Jan 2024 00:37:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661445; cv=none; b=GRgmAsEDp/3msDXY3bvjF5u6jskYmn4qfcREXBxik/7bp9JJyUBRPPludpbr6mxj0haA+1mX7S6aFo0kvKc/kyPtrxf5ZEmzoAdaABvJqkQsGVLa67Z5Fe5XovSE3ywjVj7qQkTqKSgVH9Khu/renRF40VoHsmchpooY6G5vot8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661445; c=relaxed/simple; bh=EnOc0EzSAzYuA0nYU+KTduJT+7wxBgmYtycNXpZ9rVc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HgD/7e/dZ9/Wsy92cOY4IFXtrL8VWkyUXLe0gyg8y2klPclsjVBYCIp6fHJrlyOJMmT1ubONcIAv/xIBJbQq6De9n8kAA86RnqkF+JGf8ciykdz3bMGcuOnj4eFjWx/i9hjjPiy6d4walI5afWMJ5WG6A4n5DS9NZ3s6nFSREU4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=JJSX43b5; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="JJSX43b5" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bF3I121335; Tue, 30 Jan 2024 18:37:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706661435; bh=Kb1YRhHFElMz/np+okVMEjKtBNYvxamj0d8EUV8sUyk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=JJSX43b5zabhLTokflNZYxifWRyKrvbuK1ZxkbVYh1arSapC/1WagZfg92ZkNvdH8 l+GszLIx+ZTS0he8mjrp81VtMrMdc7GGPKwEDaWuRIUHNGsa4XPp8Kh/mQjf4dzwt3 Pl7fzlKN2X5xcrweDhwtb02hNU1DE/GtAJO7jDvw= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40V0bFeQ007816 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Jan 2024 18:37:15 -0600 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 30 Jan 2024 18:37:15 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 30 Jan 2024 18:37:15 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bEw8026520; Tue, 30 Jan 2024 18:37:14 -0600 From: Judith Mendez To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Adrian Hunter , , , Nishanth Menon , Vignesh Raghavendra , Andrew Davis , Udit Kumar , Roger Quadros , , Randolph Sapp Subject: [RFC PATCH 01/13] drivers: mmc: host: sdhci_am654: Add tuning algorithm for delay chain Date: Tue, 30 Jan 2024 18:37:02 -0600 Message-ID: <20240131003714.2779593-2-jm@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131003714.2779593-1-jm@ti.com> References: <20240131003714.2779593-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Currently the sdhci_am654 driver only supports one tuning algorithm which should be used only when DLL is enabled. The ITAPDLY is selected from the largest passing window and the buffer is viewed as a circular buffer. The new algorithm should be used when the delay chain is enabled. The ITAPDLY is selected from the largest passing window and the buffer is not viewed as a circular buffer. This implementation is based off of the following paper: [1]. Also add support for multiple failing windows. [1] https://www.ti.com/lit/an/spract9/spract9.pdf Signed-off-by: Judith Mendez --- drivers/mmc/host/sdhci_am654.c | 128 +++++++++++++++++++++++++++------ 1 file changed, 108 insertions(+), 20 deletions(-) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index d659c59422e1..59d205511312 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -149,10 +149,17 @@ struct sdhci_am654_data { int strb_sel; u32 flags; u32 quirks; + bool dll_enable; #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0) }; +struct window { + u8 start; + u8 end; + u8 length; +}; + struct sdhci_am654_driver_data { const struct sdhci_pltfm_data *pdata; u32 flags; @@ -290,10 +297,13 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); - if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) + if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) { sdhci_am654_setup_dll(host, clock); - else + sdhci_am654->dll_enable = true; + } else { sdhci_am654_setup_delay_chain(sdhci_am654, timing); + sdhci_am654->dll_enable = false; + } regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, sdhci_am654->clkbuf_sel); @@ -408,39 +418,117 @@ static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) return 0; } -#define ITAP_MAX 32 +#define ITAPDLY_LENGTH 32 +#define ITAPDLY_LAST_INDEX 31 +static u32 calculate_itap(struct sdhci_host *host, struct window *fail_window, + u8 num_fails, bool circular_buffer) +{ + struct device *dev = mmc_dev(host->mmc); + struct window pass_window, first_fail, last_fail; + u8 itap = 0, start_fail = 0, end_fail = 0, pass_length = 0; + int prev_end_fail = -1; + + memset(&pass_window, 0, sizeof(pass_window)); + memset(&first_fail, 0, sizeof(first_fail)); + memset(&last_fail, 0, sizeof(last_fail)); + + if (!num_fails) { + return ITAPDLY_LAST_INDEX >> 1; + } else if (fail_window->length == ITAPDLY_LENGTH) { + dev_warn(dev, "No passing ITAPDLY, return 0\n"); + return 0; + } else { + for (int i = 0; i < num_fails; i++) { + start_fail = fail_window[i].start; + end_fail = fail_window[i].end; + + if (i == 0) { + first_fail.start = start_fail; + first_fail.end = end_fail; + first_fail.length = fail_window[0].length; + } + + if (i == num_fails - 1) { + last_fail.start = start_fail; + last_fail.end = end_fail; + last_fail.length = fail_window[i].length; + } + + pass_length = start_fail - (prev_end_fail + 1); + if (pass_length > pass_window.length) { + pass_window.start = prev_end_fail + 1; + pass_window.length = pass_length; + } + prev_end_fail = end_fail; + } + + if (!circular_buffer) { + if (ITAPDLY_LAST_INDEX - end_fail > pass_window.length) { + pass_window.start = end_fail + 1; + pass_window.length = ITAPDLY_LAST_INDEX - end_fail; + } + } else { + pass_length = ITAPDLY_LAST_INDEX - end_fail + first_fail.start; + if (pass_length > pass_window.length) { + pass_window.start = last_fail.end + 1; + pass_window.length = pass_length; + } + } + } + + if (!circular_buffer) + itap = pass_window.start + (pass_window.length >> 1); + else + itap = (pass_window.start + (pass_window.length >> 1)) % ITAPDLY_LENGTH; + + if (itap < 0 || itap > ITAPDLY_LAST_INDEX) + itap = 0; + + return itap; +} + static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, u32 opcode) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); - int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len; - u32 itap; + struct window fail_window[ITAPDLY_LENGTH]; + u8 prev_pass = 1; + u8 fail_index = 0; + u8 curr_pass, itap, i; + + for (i = 0; i < ITAPDLY_LENGTH; i++) + memset(&fail_window[i], 0, sizeof(fail_window[0])); /* Enable ITAPDLY */ regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, 1 << ITAPDLYENA_SHIFT); - for (itap = 0; itap < ITAP_MAX; itap++) { + for (itap = 0; itap < ITAPDLY_LENGTH; itap++) { sdhci_am654_write_itapdly(sdhci_am654, itap); - cur_val = !mmc_send_tuning(host->mmc, opcode, NULL); - if (cur_val && !prev_val) - pass_window = itap; + curr_pass = !mmc_send_tuning(host->mmc, opcode, NULL); - if (!cur_val) - fail_len++; + if (!curr_pass && prev_pass) + fail_window[fail_index].start = itap; - prev_val = cur_val; + if (!curr_pass) { + fail_window[fail_index].end = itap; + fail_window[fail_index].length++; + } + + if (curr_pass && !prev_pass) + fail_index++; + + prev_pass = curr_pass; } - /* - * Having determined the length of the failing window and start of - * the passing window calculate the length of the passing window and - * set the final value halfway through it considering the range as a - * circular buffer - */ - pass_len = ITAP_MAX - fail_len; - itap = (pass_window + (pass_len >> 1)) % ITAP_MAX; + + if (fail_window[fail_index].length != 0) + fail_index++; + + itap = calculate_itap(host, &fail_window[0], fail_index, + (sdhci_am654->dll_enable ? true : false)); + sdhci_am654_write_itapdly(sdhci_am654, itap); return 0; From patchwork Wed Jan 31 00:37:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 13538430 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6CE41368; Wed, 31 Jan 2024 00:37:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661444; cv=none; b=o842fCKefa0RlYGqthzDqOR8aXNicUTEIR3MkE9EOSqGNFBEC1DeD2+GZjHtOJ5Uk+y8r6nsSP+lGjxUVsBkyi1NJGLCyuCazTKu9xba1WHI8e9qTrqHAeOiylFePZNPivhSwYxKi+9yBj3+IQRe69xJWLSFqeAmYWrqpr3jNn4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661444; c=relaxed/simple; bh=N/wvgqoLvx08bPoO9QmgamH9P2amkLRca7A2GlFK1g4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LhX5XFcJA32/urd8sPIvHop+OuEZVcs664qys79Dhpznbv9XR0Oy8COBvuI2KfEBsaedoUNVpMHPyOuP0dWShwm/dFH8PcPbCN+wdHOo4cRce/Ris+yNO6wMamJYy7MmZelEZne5/8bSRBJHFaupemVQKXEmQoFDUjCrZ0o/B1M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=mNAgkY2s; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="mNAgkY2s" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bFux121327; Tue, 30 Jan 2024 18:37:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706661435; bh=dB3vWg8oNKa63KPtTWaKYFvtzzmYzuSTHHI9s9R+/6E=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mNAgkY2sOL+C9Mc8OMMV6BY57CYy8knr+5MscEpRcfS1eAF74FbM4C0kvHB73+Jyc nednmbvGt3CvFkhVxJJLmtmmqpISf+wTUjtSmzQa+zzr3OvAS5hT+DXVzdF+lTqCGS bpn9HYMFR5OfJZAqm99qlj0/E+sVZHEfeGgX9n0M= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40V0bFuk007810 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Jan 2024 18:37:15 -0600 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 30 Jan 2024 18:37:15 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 30 Jan 2024 18:37:14 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bEw9026520; Tue, 30 Jan 2024 18:37:15 -0600 From: Judith Mendez To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Adrian Hunter , , , Nishanth Menon , Vignesh Raghavendra , Andrew Davis , Udit Kumar , Roger Quadros , , Randolph Sapp Subject: [RFC PATCH 02/13] drivers: mmc: host: sdhci_am654: Write ITAPDLY for DDR52 timing Date: Tue, 30 Jan 2024 18:37:03 -0600 Message-ID: <20240131003714.2779593-3-jm@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131003714.2779593-1-jm@ti.com> References: <20240131003714.2779593-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 For DDR52 timing, DLL is enabled but tuning is not carried out, therefore the ITAPDLY value in PHY CTRL 4 register is not correct. Fix this by writing ITAPDLY after enabling DLL. Signed-off-by: Judith Mendez --- drivers/mmc/host/sdhci_am654.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index 59d205511312..0a1ed2ae2eef 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -170,7 +170,19 @@ struct sdhci_am654_driver_data { #define DLL_CALIB (1 << 4) }; -static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) +static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, + u32 itapdly) +{ + /* Set ITAPCHGWIN before writing to ITAPDLY */ + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, + 0x1 << ITAPCHGWIN_SHIFT); + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, + itapdly << ITAPDLYSEL_SHIFT); + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); +} + +static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock, + unsigned char timing) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); @@ -236,17 +248,8 @@ static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); return; } -} -static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, - u32 itapdly) -{ - /* Set ITAPCHGWIN before writing to ITAPDLY */ - regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, - 1 << ITAPCHGWIN_SHIFT); - regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, - itapdly << ITAPDLYSEL_SHIFT); - regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); + sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing]); } static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, @@ -298,7 +301,7 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) { - sdhci_am654_setup_dll(host, clock); + sdhci_am654_setup_dll(host, clock, timing); sdhci_am654->dll_enable = true; } else { sdhci_am654_setup_delay_chain(sdhci_am654, timing); From patchwork Wed Jan 31 00:37:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 13538440 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C07167EEF0; Wed, 31 Jan 2024 00:37:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661447; cv=none; b=N4v0pVrZ7fDA5DTB2RY9LI0K9IHnD+e8GfEJdYaGabeTpm2l3uUzL/SRxXqpsmW5frKhJEEAtA8QYa3KoIerOx9WXSjqYhA4lYTXRTIAZl5w7XJKNZoCC1B0rjeb/ljJK4QI69XApQNZnmKEnEz3COoPSp93eusPc1DEgtZxIqc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661447; c=relaxed/simple; bh=uSIQxp/yvzhc4Y6WNYcSagG5vH1bZ4d9JfIO8bJaTNU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=imc3c+Q3fajbf0TC+uS2lOKEct3FIIqP4009hybRt2jkDmXVPcH0qjB1/qkL34l/EfCODFvQekVFyugjsbUI6Bs/P5BLiMYa0Q9uk4sndZceGDF9JGxZMbseT99arks+raG8flB/O1xaM8TGfN8/SFfEByODTjB02kn2Sy/FMls= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=KqybR8sm; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="KqybR8sm" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bFBZ038162; Tue, 30 Jan 2024 18:37:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706661435; bh=eAvv0aSOJvvajgLl06cW3GQaJE/fjuUjp+24JiWk/9A=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=KqybR8smJ/p/0H7qKnezMcn8VadlHDXJutLpExO+9kejCmWDXpdjaSTFytXseRfkS +yOnnoQ3vwy6M8w04s/b4O4DwfBKpGvgJi/cDcflBLv7R8dET/doSPzP9lq+BShT2m gsENvXJmzcTzMPKJ++8w7UYXemzd6XmAl0a0kkD4= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40V0bFe5030604 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Jan 2024 18:37:15 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 30 Jan 2024 18:37:15 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 30 Jan 2024 18:37:15 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bEwA026520; Tue, 30 Jan 2024 18:37:15 -0600 From: Judith Mendez To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Adrian Hunter , , , Nishanth Menon , Vignesh Raghavendra , Andrew Davis , Udit Kumar , Roger Quadros , , Randolph Sapp Subject: [RFC PATCH 03/13] drivers: mmc: host: sdhci_am654: Add missing OTAP/ITAP enable Date: Tue, 30 Jan 2024 18:37:04 -0600 Message-ID: <20240131003714.2779593-4-jm@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131003714.2779593-1-jm@ti.com> References: <20240131003714.2779593-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Currently the OTAP/ITAP delay enable functionality is missing in the am654_set_clock function which is used for MMC0 on AM62p and AM64x devices. The OTAP delay is not enabled when timing < SDR25 bus speed mode. The ITAP delay is not enabled for all bus speed modes. Add this OTAP/ITAP delay functionality according to the datasheet [1] OTAPDLYENA and ITAPDLYENA for MMC0. [1] https://www.ti.com/lit/ds/symlink/am62p.pdf Signed-off-by: Judith Mendez --- drivers/mmc/host/sdhci_am654.c | 48 +++++++++++++++++++--------------- 1 file changed, 27 insertions(+), 21 deletions(-) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index 0a1ed2ae2eef..35e02f4128a7 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -143,6 +143,7 @@ struct sdhci_am654_data { struct regmap *base; int otap_del_sel[ARRAY_SIZE(td)]; int itap_del_sel[ARRAY_SIZE(td)]; + u8 itap_del_ena[ARRAY_SIZE(td)]; int clkbuf_sel; int trm_icp; int drv_strength; @@ -171,11 +172,13 @@ struct sdhci_am654_driver_data { }; static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, - u32 itapdly) + u32 itapdly, u32 enable) { /* Set ITAPCHGWIN before writing to ITAPDLY */ regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0x1 << ITAPCHGWIN_SHIFT); + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, + enable << ITAPDLYENA_SHIFT); regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, itapdly << ITAPDLYSEL_SHIFT); regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); @@ -249,7 +252,8 @@ static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock, return; } - sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing]); + sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing], + sdhci_am654->itap_del_ena[timing]); } static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, @@ -263,8 +267,8 @@ static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK; regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); - sdhci_am654_write_itapdly(sdhci_am654, - sdhci_am654->itap_del_sel[timing]); + sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing], + sdhci_am654->itap_del_ena[timing]); } static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) @@ -273,20 +277,17 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); unsigned char timing = host->mmc->ios.timing; u32 otap_del_sel; - u32 otap_del_ena; u32 mask, val; regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); sdhci_set_clock(host, clock); - /* Setup DLL Output TAP delay */ + /* Setup Output TAP delay */ otap_del_sel = sdhci_am654->otap_del_sel[timing]; - otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; - val = (otap_del_ena << OTAPDLYENA_SHIFT) | - (otap_del_sel << OTAPDLYSEL_SHIFT); + val = (0x1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT); /* Write to STRBSEL for HS400 speed mode */ if (timing == MMC_TIMING_MMC_HS400) { @@ -319,14 +320,20 @@ static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); unsigned char timing = host->mmc->ios.timing; u32 otap_del_sel; + u32 itap_del_ena; u32 mask, val; - /* Setup DLL Output TAP delay */ + /* Setup Output TAP delay */ otap_del_sel = sdhci_am654->otap_del_sel[timing]; mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; - val = (0x1 << OTAPDLYENA_SHIFT) | - (otap_del_sel << OTAPDLYSEL_SHIFT); + val = (0x1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT); + + itap_del_ena = sdhci_am654->itap_del_ena[timing]; + + mask |= ITAPDLYENA_MASK; + val |= (itap_del_ena << ITAPDLYENA_SHIFT); + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, @@ -503,12 +510,8 @@ static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, for (i = 0; i < ITAPDLY_LENGTH; i++) memset(&fail_window[i], 0, sizeof(fail_window[0])); - /* Enable ITAPDLY */ - regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, - 1 << ITAPDLYENA_SHIFT); - for (itap = 0; itap < ITAPDLY_LENGTH; itap++) { - sdhci_am654_write_itapdly(sdhci_am654, itap); + sdhci_am654_write_itapdly(sdhci_am654, itap, 1); curr_pass = !mmc_send_tuning(host->mmc, opcode, NULL); @@ -532,7 +535,7 @@ static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, itap = calculate_itap(host, &fail_window[0], fail_index, (sdhci_am654->dll_enable ? true : false)); - sdhci_am654_write_itapdly(sdhci_am654, itap); + sdhci_am654_write_itapdly(sdhci_am654, itap, 1); return 0; } @@ -681,9 +684,12 @@ static int sdhci_am654_get_otap_delay(struct sdhci_host *host, host->mmc->caps2 &= ~td[i].capability; } - if (td[i].itap_binding) - device_property_read_u32(dev, td[i].itap_binding, - &sdhci_am654->itap_del_sel[i]); + if (td[i].itap_binding) { + ret = device_property_read_u32(dev, td[i].itap_binding, + &sdhci_am654->itap_del_sel[i]); + if (!ret) + sdhci_am654->itap_del_ena[i] = 0x1; + } } return 0; From patchwork Wed Jan 31 00:37:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 13538439 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 802C123A3; Wed, 31 Jan 2024 00:37:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661446; cv=none; b=uSdemH2FvOv2/VRSTM6EiD9vps3Btx3dePoVRB61UCgmBCHFvfQNLUtrQ7IpcTuxlVBugqiU4IuWTTLPmprTicoulTlA2hQXHsWKkUZmq3LmeTNjSD6qTEmnXfyEuR1VWEmbA87TKF1n1S8d7EBgI180WvlNQfYxeJWZOhLsXuk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661446; c=relaxed/simple; bh=BOIMfpJd4wjoTPa05l1nYj4kGi90/ceQ2kjZ91/SPNc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Xth93IyuNTsge4h98FMXEe6Nt8lUOeaU0VaKH8gIysu65HtDsVY5NaLN7YsX0OcrsJgddwO3S292XOGuNOcKbhYsNz2x37f6AyEy5NwONH4Fq6q3vGTmmZny01YVFW4HY/IetOcdI3J2CDYuO/J0gXPbxub8nSJR2pGQX4au7CE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Kr591s/Y; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Kr591s/Y" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bF9O034651; Tue, 30 Jan 2024 18:37:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706661435; bh=QWigbctVlzjkxsBbZQ1Y47XS9owR9Y5JqOgjf+q4VGI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Kr591s/Y+VWQxGZjMzjiDsejRTtZiCsN9wHN/Sawlxg/NnFFu0Tvfrq0dShEUxZfq NpOIZAOtGwK9aL+PUZJyBypSS5SwxJuXMMTJVezt+12iWr5n3PU4AP3ZluVcXI9O8x Aq8iWnc0eQl/58P78xQ7FqyOxzB8qzHLJxSoULEg= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40V0bFe4030604 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Jan 2024 18:37:15 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 30 Jan 2024 18:37:15 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 30 Jan 2024 18:37:15 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bEwB026520; Tue, 30 Jan 2024 18:37:15 -0600 From: Judith Mendez To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Adrian Hunter , , , Nishanth Menon , Vignesh Raghavendra , Andrew Davis , Udit Kumar , Roger Quadros , , Randolph Sapp Subject: [RFC PATCH 04/13] drivers: mmc: host: sdhci_am654: Add ITAPDLYSEL in sdhci_j721e_4bit_set_clock Date: Tue, 30 Jan 2024 18:37:05 -0600 Message-ID: <20240131003714.2779593-5-jm@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131003714.2779593-1-jm@ti.com> References: <20240131003714.2779593-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Add ITAPDLYSEL to sdhci_j721e_4bit_set_clock function. This allows to set the correct ITAPDLY for timings that do not carry out tuning. Signed-off-by: Judith Mendez --- drivers/mmc/host/sdhci_am654.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index 35e02f4128a7..61f95aad3f80 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -321,6 +321,7 @@ static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, unsigned char timing = host->mmc->ios.timing; u32 otap_del_sel; u32 itap_del_ena; + u32 itap_del_sel; u32 mask, val; /* Setup Output TAP delay */ @@ -329,12 +330,17 @@ static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; val = (0x1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT); + /* Setup Input TAP delay */ itap_del_ena = sdhci_am654->itap_del_ena[timing]; + itap_del_sel = sdhci_am654->itap_del_sel[timing]; - mask |= ITAPDLYENA_MASK; - val |= (itap_del_ena << ITAPDLYENA_SHIFT); + mask |= ITAPDLYENA_MASK | ITAPDLYSEL_MASK; + val |= (itap_del_ena << ITAPDLYENA_SHIFT) | (itap_del_sel << ITAPDLYSEL_SHIFT); + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, + 1 << ITAPCHGWIN_SHIFT); regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, sdhci_am654->clkbuf_sel); From patchwork Wed Jan 31 00:37:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 13538429 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CF35367; Wed, 31 Jan 2024 00:37:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661442; cv=none; b=EICZcNDLhe8u4QoFT+IUskIVLpJYGGrEl7O3d9TDVi991OHPYMILgzEXvvMiPz2RhUsyDKcl6fvkXixFOcCo2DT/Pv9YFJEIiYBB+IO1mm5ITCekclk+7uTzqBnVskRaivM7e8N+plv2M0Y93d1azg1SKedYaVa048wnpcwRyh8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661442; c=relaxed/simple; bh=Yde+/v/+AnUplfQUwrwsE7yIYWSZYjR61zlCFeX+dks=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=s5tyKGujdtc1/7wCRyRkIqz7O+43bYxHlPgV4etTp17O+IQjsG1wtrn/6AM+GeB3ZU939H2Ayv45y38NDaxeXXeubS4LX5emf6BZZ5wz9giKyY4ZKYEIbdv8+Ctvk3URamnpnnSiDnd/Ht/TqILrjy81EKT/V/cdZPOGSURGbXg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=W6UwvpBD; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="W6UwvpBD" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bFhi038158; Tue, 30 Jan 2024 18:37:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706661435; bh=RHyTtzIAoeUMLOJFOBHlD1R5jRaYgsYXm6fuzcPyioU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=W6UwvpBDROaTTwQ3dE2R9wx30n4qWHX/EUnYgs4ftSdmTgC/60KaI6veo3Q9UV/5I pkRQO+Pw2w4LCp0KPvwGw37NoQr2mdV/+Pg1whUh4etDdvZlADIzEOsFRhzS3rxi12 a0l27FeozYKkxMsTkiG+Pu0VyNl8Mrjp/+oFf4WA= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40V0bFHI007806 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Jan 2024 18:37:15 -0600 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 30 Jan 2024 18:37:15 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 30 Jan 2024 18:37:15 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bEwC026520; Tue, 30 Jan 2024 18:37:15 -0600 From: Judith Mendez To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Adrian Hunter , , , Nishanth Menon , Vignesh Raghavendra , Andrew Davis , Udit Kumar , Roger Quadros , , Randolph Sapp Subject: [RFC PATCH 05/13] drivers: mmc: host: sdhci_am654: Fix ITAPDLY for HS400 timing Date: Tue, 30 Jan 2024 18:37:06 -0600 Message-ID: <20240131003714.2779593-6-jm@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131003714.2779593-1-jm@ti.com> References: <20240131003714.2779593-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 While STRB is currently used for DATA and CRC responses, the CMD responses from the device to the host still require ITAPDLY for HS400 timing. Currently what is stored for HS400 is the ITAPDLY from High Speed mode which is incorrect. The ITAPDLY for HS400 speed mode should be the same as ITAPDLY as HS200 timing after tuning is executed. Add the functionality to save ITAPDLY from HS200 tuning and save as HS400 ITAPDLY. Signed-off-by: Judith Mendez --- drivers/mmc/host/sdhci_am654.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index 61f95aad3f80..0f0178936a6d 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -151,6 +151,7 @@ struct sdhci_am654_data { u32 flags; u32 quirks; bool dll_enable; + bool hs200_tunning; #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0) }; @@ -252,6 +253,10 @@ static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock, return; } + /* HS400 ITAPDLY should be the same as HS200 ITAPDLY*/ + if (timing == MMC_TIMING_MMC_HS400) + sdhci_am654->itap_del_sel[timing] = sdhci_am654->itap_del_sel[timing - 1]; + sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing], sdhci_am654->itap_del_ena[timing]); } @@ -311,6 +316,9 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, sdhci_am654->clkbuf_sel); + + if (timing == MMC_TIMING_MMC_HS200 && sdhci_am654->dll_enable) + sdhci_am654->hs200_tunning = true; } static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, @@ -543,6 +551,10 @@ static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, sdhci_am654_write_itapdly(sdhci_am654, itap, 1); + /* Save ITAPDLY for HS200 */ + if (sdhci_am654->hs200_tunning) + sdhci_am654->itap_del_sel[MMC_TIMING_MMC_HS200] = itap; + return 0; } From patchwork Wed Jan 31 00:37:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 13538438 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F03736D; Wed, 31 Jan 2024 00:37:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661446; cv=none; b=Xxt9Wqb0QM3nzssrREZ/eQKrUR/B9fkBZga5L18694H1W1FLN87+kzje49s245LpHh1nz5b1HLFalaE5bGf9Vl2/FpfgbRTgf3vKu+AvZEyRtrQXCEztaGovo1lci5IqHbOdgRG7jHVAP5PZik6+IyAPBp26E/lRn0WSR7M6pAA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661446; c=relaxed/simple; bh=fbGnNeYHC8zY3a1uoZmwZ/hqQ7K+FI4IQ3ndJ0elgpg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=V6SnuMKPPEnPLcP89HSXstvHv/j+D185yVR6UyoOCYKOKeLXwo/Q4q3if40rwV0UifyeoZPuGu2dFjkae7avgsNj0uEFmVL96Hb+MEGwqxQLbJoLzLf5k9nz1CMGsFScxC43r5iNhAr4beQL/70nWucWDo3UgvMELeOgUIlVOu0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=W8eqpP1v; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="W8eqpP1v" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bFsk121331; Tue, 30 Jan 2024 18:37:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706661435; bh=xxI57RFhA7r8bRyDm0k+ooGHxeLdKBscUR5KUmBLBy4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=W8eqpP1vqt/01If1kWf0TL6/kyi7kEcCm9cy1B0g+mzGSfa65kdreCDC5qrPEjsWI rR9/8aO10PMpbxzNWDq676WA2QiEZ+gm/WuWY8hPqZiFxDFVO7g0TNUUz+iWO577HX bX2Wivjx9NqFssYid3pAnTIh+v01MxZa2xZY7DEc= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40V0bFRU045571 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Jan 2024 18:37:15 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 30 Jan 2024 18:37:15 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 30 Jan 2024 18:37:15 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bEwD026520; Tue, 30 Jan 2024 18:37:15 -0600 From: Judith Mendez To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Adrian Hunter , , , Nishanth Menon , Vignesh Raghavendra , Andrew Davis , Udit Kumar , Roger Quadros , , Randolph Sapp Subject: [RFC PATCH 06/13] arm64: dts: ti: k3-am62a-main: Add sdhci0 instance Date: Tue, 30 Jan 2024 18:37:07 -0600 Message-ID: <20240131003714.2779593-7-jm@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131003714.2779593-1-jm@ti.com> References: <20240131003714.2779593-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 From: Nitin Yadav Add sdhci0 DT node in k3-am62a-main for eMMC support. Add otap/itap values according to the datasheet[0], Refer to Table 7-79. [0] https://www.ti.com/lit/ds/symlink/am62a3.pdf Signed-off-by: Judith Mendez Signed-off-by: Nitin Yadav --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index f0b8c9ab1459..523dee78123a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -536,6 +536,24 @@ main_gpio1: gpio@601000 { status = "disabled"; }; + sdhci0: mmc@fa10000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; + interrupts = ; + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&k3_clks 57 6>; + assigned-clock-parents = <&k3_clks 57 8>; + bus-width = <8>; + mmc-hs200-1_8v; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-hs200 = <0x6>; + status = "disabled"; + }; + sdhci1: mmc@fa00000 { compatible = "ti,am62-sdhci"; reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; From patchwork Wed Jan 31 00:37:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 13538436 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40C461FBA; Wed, 31 Jan 2024 00:37:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661446; cv=none; b=XzunxncAkKJlnoXWamRIIh9NfEL2aHNuPKWR14xo5iMNRV2YSSiUoRyM1dvtcZnSkxk2P05qd7q+kAQlTFVzvelVlwvaAjIQnFI7lOchrTYBa3mrFYbk8ufn5uPm/OF6IYmgJfqN5uY2ge1YfJJq04XCN/D5krw6xrGxSCQI8ao= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661446; c=relaxed/simple; bh=BaJ+2pN6/A+fuLA4/j8U/u2l/DCl6yBJ76g7kV3qe+I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=C8kS1IsabY18p6kWJZN7qg3pwVc78VSyNoDwfX5AOr3ON/LgethONO8kVOkVw55UL2qpTMzJ7YXpECQgNEoIlzXca9JrRF90pv4LIJeNu0SkfAAVSQLhyFDzka7bLd+vVVdZFKoPZKT9p6YaIBu7xEr/S9/4B0ItIoBVZu5zSSU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=U+93OxQn; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="U+93OxQn" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bFfu031424; Tue, 30 Jan 2024 18:37:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706661435; bh=zkwcrne0XbKEdytWqRh3uctBmYEsUgvOo74fiuH10tc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=U+93OxQnFYfXp6bS+nzW4mNXgE8deqHaDK3AtDZmleAXKR0qgXmx99GBMblzV/VgV Y2RQtKn117zzWYH6JO1KF5FPWRnGCzg57t3g6EKBJg1WnkajMjOgBjmMgVfwTTGsK9 j814DUUKyDSDdrEgkdNm9i2DitnFlC8/Sv+YwFtA= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40V0bF5u030616 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Jan 2024 18:37:15 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 30 Jan 2024 18:37:15 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 30 Jan 2024 18:37:15 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bEwE026520; Tue, 30 Jan 2024 18:37:15 -0600 From: Judith Mendez To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Adrian Hunter , , , Nishanth Menon , Vignesh Raghavendra , Andrew Davis , Udit Kumar , Roger Quadros , , Randolph Sapp Subject: [RFC PATCH 07/13] arm64: dts: ti: k3-am62a7-sk: Enable eMMC support Date: Tue, 30 Jan 2024 18:37:08 -0600 Message-ID: <20240131003714.2779593-8-jm@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131003714.2779593-1-jm@ti.com> References: <20240131003714.2779593-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 From: Nitin Yadav Add support for 32GB eMMC card on AM62A7 SK. Includes adding mmc0 pins settings. Add mmc0 alias for sdhci0 in k3-am62a7-sk.dts. Signed-off-by: Judith Mendez Signed-off-by: Nitin Yadav --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 26 +++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index 7b7142586295..2497acc0dd60 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -20,6 +20,7 @@ aliases { serial0 = &wkup_uart0; serial2 = &main_uart0; serial3 = &main_uart1; + mmc0 = &sdhci0; mmc1 = &sdhci1; }; @@ -218,6 +219,22 @@ AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ >; }; + main_mmc0_pins_default: main-mmc0-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62AX_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLKLB */ + AM62AX_IOPAD(0x21c, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62AX_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ + AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ + AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ + AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ + AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ + AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ + AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ @@ -475,6 +492,15 @@ &main_i2c2 { clock-frequency = <400000>; }; +&sdhci0 { + /* eMMC */ + status = "okay"; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + disable-wp; +}; + &sdhci1 { /* SD/MMC */ status = "okay"; From patchwork Wed Jan 31 00:37:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 13538435 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED917139E; Wed, 31 Jan 2024 00:37:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661445; cv=none; b=O0oPZjx7L7iY/k5QAJlmTKDJCrRRL90z04rbHXKLZTxp0/RXdi2SkqS6Q9+rq02FDRbewA/PVkWEqkZW4JprmFHbXaEB5BMJI8ezrV2DA855gxDonD4f/BNLQsTOuqulR9in8sgHorJ5Us7A5KBq58qakncmdhG8PrL1ze4KO8k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661445; c=relaxed/simple; bh=VoaHMnbiB4InY0n1diaV3Seie5O8+ODnxvi4wD3A9AY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TmhBSrZci6nDa/383EdP4PvrPy29tqulABTW9/r+Rw7OcbcJggYAo9wJz25DiBbs0RwOEkGnpZ3m/a823fYy5VrftsDXfAWl7F9nGXPhk5FMC6p69FgN7fb4NOWX83cvqh3/sEc/bRoZYaN6fQX56vadOz+mlGRvJokGjj7x4pA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=zTUWQw30; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="zTUWQw30" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bF8j031408; Tue, 30 Jan 2024 18:37:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706661435; bh=u/6Pxik58VJUCHSPJKRuRr57oOiGRkcoH1Dp3zB/20s=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=zTUWQw304cPdc6IpAYO/VoL0qHN8LsP/25j/oORRNbC4BCBJ0v8s3zAu0uZo6JgtY c080UhCcFJ0zlg57Z1rkOY/VqAENp3C09ms9UqYUOq7YwvwpPw2Kx8niRWbvDKB3Zj 8ALBTWreCzcS5LkwmfOQb5cnFmhn7DdCQO0jv3PU= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40V0bFip045574 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Jan 2024 18:37:15 -0600 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 30 Jan 2024 18:37:15 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 30 Jan 2024 18:37:15 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bEwF026520; Tue, 30 Jan 2024 18:37:15 -0600 From: Judith Mendez To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Adrian Hunter , , , Nishanth Menon , Vignesh Raghavendra , Andrew Davis , Udit Kumar , Roger Quadros , , Randolph Sapp Subject: [RFC PATCH 08/13] arm64: dts: ti: k3-am62a-main: Add sdhci2 instance Date: Tue, 30 Jan 2024 18:37:09 -0600 Message-ID: <20240131003714.2779593-9-jm@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131003714.2779593-1-jm@ti.com> References: <20240131003714.2779593-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Add sdhci2 DT node in k3-am62a-main for mmc2. Add otap/itap values according to the datasheet[0], Refer to Table 7-97. [0] https://www.ti.com/lit/ds/symlink/am62a3.pdf Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 24 +++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index 523dee78123a..227e7fb3e5bb 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -579,6 +579,30 @@ sdhci1: mmc@fa00000 { status = "disabled"; }; + sdhci2: mmc@fa00000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0xfa20000 0x00 0x260>, <0x00 0xfa28000 0x00 0x134>; + interrupts = ; + power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; + clock-names = "clk_ahb", "clk_xin"; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + no-1-8-v; + status = "disabled"; + }; + usbss0: dwc3-usb@f900000 { compatible = "ti,am62-usb"; reg = <0x00 0x0f900000 0x00 0x800>; From patchwork Wed Jan 31 00:37:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 13538428 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A96A363; Wed, 31 Jan 2024 00:37:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661442; cv=none; b=aHrZotXivh9ktC2uKO27t6pnPbnf4iDnkley/+GntWl5Z149cwScBhwjB1NBx82tpDNrgsVl9XdqAqCTzKU18f/P4QTmuutpZI7pAf07bR/6ZVEruF3SFe+35qJHeG2f0zUmlJJpy3mmPg4t8+4d75m2BxhHqdgXF2h6ASBL0L4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661442; c=relaxed/simple; bh=TRI76dxKaAg21+XKMTz2eTHyC73X3AcSx+5xJSrO0Q4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gVnlLLBFSoWvXhpAQS7fASmNyj/APv0EXff6SXjPWDDNQfJq65Ipr3wsxy6PM8NY/JzGCw8WvYYRl3s+xAOuc8bcHLyKo9HnTo79zUYzd1lVZ8rHOtqRbMC62yY7TRZ9OYWPT/mFrZdCb3xBJYoUc8HU7/uHkmH04Rk69ZggH/g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=t6VENNGx; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="t6VENNGx" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bFKP038166; Tue, 30 Jan 2024 18:37:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706661435; bh=KX5ixSYuqhTJGTqFFZNAXHuik1i9Vu58r7YXwjkwNqk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=t6VENNGxZ+4kVYI48GV/LXaMQVqkGjNUXHqffkGA4nMUzMf+Pu7hJI1++OyJjKTOG AiNhNCHJ7k2zyPs6kTgZVRxHzzqbUyUj9jCJaqIy4oM16tuH0JN0l1/Vn0T4yeRKlw +9Ej71sxLvOc8yxAM0gBRhZqCX3X5SJ4hcMFFo3w= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40V0bFio045574 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Jan 2024 18:37:15 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 30 Jan 2024 18:37:15 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 30 Jan 2024 18:37:15 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bEwG026520; Tue, 30 Jan 2024 18:37:15 -0600 From: Judith Mendez To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Adrian Hunter , , , Nishanth Menon , Vignesh Raghavendra , Andrew Davis , Udit Kumar , Roger Quadros , , Randolph Sapp Subject: [RFC PATCH 09/13] arm64: dts: ti: k3-am64-main: Update ITAP/OTAP values for MMC Date: Tue, 30 Jan 2024 18:37:10 -0600 Message-ID: <20240131003714.2779593-10-jm@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131003714.2779593-1-jm@ti.com> References: <20240131003714.2779593-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Update MMC0/MMC1 OTAP/ITAP values according to the datasheet [0], refer to Table 7-68 for MMC0 and Table 7-77 for MMC1. [0] https://www.ti.com/lit/ds/symlink/am6442.pdf Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index e348114f42e0..b355d0a715a9 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -633,6 +633,9 @@ sdhci0: mmc@fa10000 { ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x6>; ti,otap-del-sel-hs200 = <0x7>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-mmc-hs = <0xa>; + ti,itap-del-sel-ddr52 = <0x3>; status = "disabled"; }; @@ -645,13 +648,17 @@ sdhci1: mmc@fa00000 { clock-names = "clk_ahb", "clk_xin"; ti,trm-icp = <0x2>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-sdr104 = <0x6>; ti,otap-del-sel-ddr50 = <0x9>; ti,clkbuf-sel = <0x7>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; status = "disabled"; }; From patchwork Wed Jan 31 00:37:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 13538431 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEF291103; Wed, 31 Jan 2024 00:37:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661444; cv=none; b=PmKU/JpTOhZk4r88xoed0guMYB0npwEzgHnCdYyrsR6//SaY2NSiKoSpeHkrUey1ResFM1/U/ZuFybZIE3D+DL4Qg718KJA1AKXemNVgOaDYhmbuyvu3ibKI5bpBhJ5ONeQuWNP5Q1zjdgjEZCLrSK9LUojfHgbWb6fL3SNR0r8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661444; c=relaxed/simple; bh=bigE3EepV9sNoml2beOok0eVzDwugI7z/SxMEMH6kyk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=D10svgBjvPx5xQt1a/OhroSgApPKJl+6w8iNY7GiopB7PXm3c1tg79KjiXRIG71lZ4eqyUn31qlIx9YZ387vy9ewole/mndTePQ7aK0aogScC6+UmcKmaPr5jKgzWPRB2SlQwq4WrUwk7EcKQUb9h+8ROKPC0EA+2p2T+sCCywA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=N5dfAM8L; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="N5dfAM8L" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bFI5038170; Tue, 30 Jan 2024 18:37:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706661435; bh=BkvyuZpDxRgCi61BEcqjXTvloaPaLWpET4daXVO+ju0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=N5dfAM8Lhx8x+LRogl4T5Iw8MHkf5QROXb1IwJA3dc3/uQXn39bjRWgGDxRrM4F4U mX4oP8mTbuSXx3sbGRDBKjSg3clJQMwQrujb3Qw+t5MiROvieM1Gnayag8CJIOM7zk wP5sETEOlSiqTFRaVGhZTHlrvhsURC1UIcjPz7Gw= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40V0bFCB071564 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Jan 2024 18:37:15 -0600 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 30 Jan 2024 18:37:15 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 30 Jan 2024 18:37:15 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bEwH026520; Tue, 30 Jan 2024 18:37:15 -0600 From: Judith Mendez To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Adrian Hunter , , , Nishanth Menon , Vignesh Raghavendra , Andrew Davis , Udit Kumar , Roger Quadros , , Randolph Sapp Subject: [RFC PATCH 10/13] arm64: dts: ti: k3-am62-main: Update ITAP/OTAP values for MMC Date: Tue, 30 Jan 2024 18:37:11 -0600 Message-ID: <20240131003714.2779593-11-jm@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131003714.2779593-1-jm@ti.com> References: <20240131003714.2779593-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Update MMC0/MMC1 OTAP/ITAP values according to the datasheet [0], refer to Table 7-79 for MMC0 and Table 7-97 for MMC1. [0] https://www.ti.com/lit/ds/symlink/am625.pdf Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 49 +++++++++++------------- 1 file changed, 23 insertions(+), 26 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 464b7565d085..d10a02ede06c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -566,10 +566,7 @@ sdhci0: mmc@fa10000 { ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-ddr52 = <0x5>; - ti,otap-del-sel-hs200 = <0x5>; - ti,itap-del-sel-legacy = <0xa>; - ti,itap-del-sel-mmc-hs = <0x1>; + ti,otap-del-sel-hs200 = <0x6>; status = "disabled"; }; @@ -581,19 +578,19 @@ sdhci1: mmc@fa00000 { clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; ti,trm-icp = <0x2>; - ti,otap-del-sel-legacy = <0x8>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0x0>; - ti,otap-del-sel-sdr25 = <0x0>; - ti,otap-del-sel-sdr50 = <0x8>; - ti,otap-del-sel-sdr104 = <0x7>; - ti,otap-del-sel-ddr50 = <0x4>; - ti,itap-del-sel-legacy = <0xa>; - ti,itap-del-sel-sd-hs = <0x1>; - ti,itap-del-sel-sdr12 = <0xa>; - ti,itap-del-sel-sdr25 = <0x1>; ti,clkbuf-sel = <0x7>; bus-width = <4>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; status = "disabled"; }; @@ -605,18 +602,18 @@ sdhci2: mmc@fa20000 { clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; clock-names = "clk_ahb", "clk_xin"; ti,trm-icp = <0x2>; - ti,otap-del-sel-legacy = <0x8>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0x0>; - ti,otap-del-sel-sdr25 = <0x0>; - ti,otap-del-sel-sdr50 = <0x8>; - ti,otap-del-sel-sdr104 = <0x7>; - ti,otap-del-sel-ddr50 = <0x8>; - ti,itap-del-sel-legacy = <0xa>; - ti,itap-del-sel-sd-hs = <0xa>; - ti,itap-del-sel-sdr12 = <0xa>; - ti,itap-del-sel-sdr25 = <0x1>; ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; status = "disabled"; }; From patchwork Wed Jan 31 00:37:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 13538437 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F3F91FB3; Wed, 31 Jan 2024 00:37:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661446; cv=none; b=NY4NAhOMJif68AwgfjFp803H0I2HRiuINNexCOx7m0ebfGegqK6I49jGxbPynYYAagLNdOBrvgzDd5icYAMflfUBQKpbON7vzlPIooWSpUzgG5MuFsXp8NNLtntZhQO/sBxC9Mmp6HWG2PzDpOvG7efBMBZdaZQDmCxWve9BWTs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661446; c=relaxed/simple; bh=qBnBVr+aLoSqcfjfTdT+YAbFQ5Tgjn3lSVio74wtNeU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pKC6IDHsfZuuOYq18vPr7Q0D9T0WGACQyCqJVdgULQOYgt1yaUWDNz5+5W9UE8AV+Yi7Qd7dJnQIke0IoXJN8Z1lor/rOdrFYLLw6e3T6KAL/c0lhuobZ0SdFozv7E4hmTGwS4PUJX+XtEbqmUsDgsbtmtlo+RtytQ418OC71fo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=HkhKtVrH; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="HkhKtVrH" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bFVa031412; Tue, 30 Jan 2024 18:37:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706661435; bh=D/3ZeQt/EO5BG2rjHHm795CMpkA3j3QkXj6n+muBwvo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=HkhKtVrHiByde5TvuwCf8mCYvIkEYDT1jfssNQMolulBHi/6dSqA1Zebz6Eg7R7z3 CVEZde+BsdHrSVfR/rkHvQGUhJqkt+2UiH0v6QO7BMlM3PckeMVc8rJQeuutZbbGyC gfTbMyGwC4LGBx8qNB7If1Wyr/CYAZmXXeOClDBQ= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40V0bFIN030610 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Jan 2024 18:37:15 -0600 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 30 Jan 2024 18:37:15 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 30 Jan 2024 18:37:15 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bEwI026520; Tue, 30 Jan 2024 18:37:15 -0600 From: Judith Mendez To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Adrian Hunter , , , Nishanth Menon , Vignesh Raghavendra , Andrew Davis , Udit Kumar , Roger Quadros , , Randolph Sapp Subject: [RFC PATCH 11/13] arm64: dts: ti: k3-am62p: Add missing properties for MMC Date: Tue, 30 Jan 2024 18:37:12 -0600 Message-ID: <20240131003714.2779593-12-jm@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131003714.2779593-1-jm@ti.com> References: <20240131003714.2779593-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Add missing properties to enable HS200 timing for MMC0 and SDR104 timing for MMC1 according to the datasheet [0] for AM62p device, refer to Table 7-79 for MMC0 and Table 7-97 for MMC1/MMC2. [0] https://www.ti.com/lit/ds/symlink/am625.pdf Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 44 +++++++++++++++++++++-- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 6 ++-- 2 files changed, 45 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi index 4c51bae06b57..f743700dd5bd 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -534,7 +534,21 @@ sdhci0: mmc@fa10000 { clock-names = "clk_ahb", "clk_xin"; assigned-clocks = <&k3_clks 57 2>; assigned-clock-parents = <&k3_clks 57 4>; - ti,otap-del-sel-legacy = <0x0>; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + ti,clkbuf-sel = <0x7>; + ti,strobe-sel = <0x77>; + ti,trm-icp = <0x8>; + ti,otap-del-sel-legacy = <0x1>; + ti,otap-del-sel-mmc-hs = <0x1>; + ti,otap-del-sel-ddr52 = <0x6>; + ti,otap-del-sel-hs200 = <0x8>; + ti,otap-del-sel-hs400 = <0x5>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-mmc-hs = <0xa>; + ti,itap-del-sel-ddr52 = <0x3>; status = "disabled"; }; @@ -545,7 +559,19 @@ sdhci1: mmc@fa00000 { power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; - ti,otap-del-sel-legacy = <0x8>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; status = "disabled"; }; @@ -556,7 +582,19 @@ sdhci2: mmc@fa20000 { power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; clock-names = "clk_ahb", "clk_xin"; - ti,otap-del-sel-legacy = <0x8>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index 1773c05f752c..10156a04a92c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -410,13 +410,17 @@ &main_i2c2 { }; &sdhci0 { + /* eMMC */ + bootph-all; status = "okay"; + non-removable; ti,driver-strength-ohm = <50>; disable-wp; }; &sdhci1 { /* SD/MMC */ + bootph-all; status = "okay"; vmmc-supply = <&vdd_mmc1>; vqmmc-supply = <&vddshv_sdio>; @@ -424,8 +428,6 @@ &sdhci1 { pinctrl-0 = <&main_mmc1_pins_default>; ti,driver-strength-ohm = <50>; disable-wp; - no-1-8-v; - bootph-all; }; &cpsw3g { From patchwork Wed Jan 31 00:37:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 13538433 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16D8115CB; Wed, 31 Jan 2024 00:37:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661444; cv=none; b=APN1A3O/jDNX7qWhTALXEsXcHvuqVzrEi9L5JDIsurmBlYpmSmSHZj7reL0zmwQlwzpRJMuovOI05HCexoqNEueSHnE+VX0OXrwK/C9oWLTR0dSrHipDpyqrKQdCPw20yzhI3/DNn4lJnB6C1AG5HsSe76rNLMQOQiLtZEqZqgw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661444; c=relaxed/simple; bh=+8h+ILzruodA94irfEYMfbkVY1tVZkZgMDZbiu6QV4s=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WM3k1m/wTBnTkfFDhP/M3uuzIprGfkSYtU4AIBmX9Gb8Iswwhd0rJVOWScC6capGGf8Lj1fyqfSAW5h97T9n42EyWqO0l1jyQRg9GjmMb3SnnQDG8G3pWC3LEFMpJZ4FkmSiUB35uxBxsxwr213Jj+Akbx+/QRCB7NLhTY+f9ek= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=vaZwj6tu; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="vaZwj6tu" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bFll031414; Tue, 30 Jan 2024 18:37:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706661435; bh=q2GvasVQs69P6xO8DZIphBk9HyKlpNN4Lb0GZiSECeg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vaZwj6tukKyU23U2IM1IieyApMi1TfQ3oOeKsQySSXA/+qmn2JkiwZP/mNHZwePxl DSMFRldCUm/YW8cL1nQtJu8KA2N8j4yuJv5C8qTsEsM8gyQWV8VT+pJsndcfVEgaQg CXkDurlQaqrTjhGwLN5D8XZTFY+9C5d8ND0c4r7I= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40V0bFcF030613 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Jan 2024 18:37:15 -0600 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 30 Jan 2024 18:37:15 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 30 Jan 2024 18:37:15 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bEwJ026520; Tue, 30 Jan 2024 18:37:15 -0600 From: Judith Mendez To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Adrian Hunter , , , Nishanth Menon , Vignesh Raghavendra , Andrew Davis , Udit Kumar , Roger Quadros , , Randolph Sapp Subject: [RFC PATCH 12/13] arm64: dts: ti: k3-am6*: Remove DLL properties for soft phys Date: Tue, 30 Jan 2024 18:37:13 -0600 Message-ID: <20240131003714.2779593-13-jm@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131003714.2779593-1-jm@ti.com> References: <20240131003714.2779593-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Remove DLL properties which are not applicable for soft phys since they do not have a DLL to enable. Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 3 --- arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts | 3 --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 1 - arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 1 - arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 1 - arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 2 -- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 1 - arch/arm64/boot/dts/ti/k3-am642-evm.dts | 1 - arch/arm64/boot/dts/ti/k3-am642-sk.dts | 1 - 9 files changed, 14 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index d10a02ede06c..ca825088970f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -561,7 +561,6 @@ sdhci0: mmc@fa10000 { assigned-clock-parents = <&k3_clks 57 8>; mmc-ddr-1_8v; mmc-hs200-1_8v; - ti,trm-icp = <0x2>; bus-width = <8>; ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; @@ -577,7 +576,6 @@ sdhci1: mmc@fa00000 { power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; ti,clkbuf-sel = <0x7>; bus-width = <4>; ti,otap-del-sel-legacy = <0x0>; @@ -601,7 +599,6 @@ sdhci2: mmc@fa20000 { power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts index eadbdd9ffe37..f69dbf9b8406 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -827,7 +827,6 @@ &sdhci0 { bootph-all; pinctrl-names = "default"; pinctrl-0 = <&emmc_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; status = "okay"; }; @@ -840,7 +839,6 @@ &sdhci1 { vmmc-supply = <&vdd_3v3_sd>; vqmmc-supply = <&vdd_sd_dv>; - ti,driver-strength-ohm = <50>; disable-wp; cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; cd-debounce-delay-ms = <100>; @@ -857,7 +855,6 @@ &sdhci2 { ti,fails-without-test-cd; cap-power-off-card; keep-power-in-suspend; - ti,driver-strength-ohm = <50>; assigned-clocks = <&k3_clks 157 158>; assigned-clock-parents = <&k3_clks 157 160>; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index 227e7fb3e5bb..db5a7746c82e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -561,7 +561,6 @@ sdhci1: mmc@fa00000 { power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index 2497acc0dd60..74816e08a15e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -507,7 +507,6 @@ &sdhci1 { vmmc-supply = <&vdd_mmc1>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index 10156a04a92c..9e37e54f141a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -426,7 +426,6 @@ &sdhci1 { vqmmc-supply = <&vddshv_sdio>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 33768c02d8eb..6dd48c826f74 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -411,7 +411,6 @@ &sdhci0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -421,7 +420,6 @@ &sdhci1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index b355d0a715a9..1842f05ac351 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -646,7 +646,6 @@ sdhci1: mmc@fa00000 { power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 8c5651d2cf5d..0583ec3a9b52 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -508,7 +508,6 @@ &sdhci1 { pinctrl-names = "default"; bus-width = <4>; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 1dddd6fc1a0d..c3a77f6282cb 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -471,7 +471,6 @@ &sdhci1 { pinctrl-names = "default"; bus-width = <4>; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; From patchwork Wed Jan 31 00:37:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 13538432 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED8EC139B; Wed, 31 Jan 2024 00:37:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661444; cv=none; b=c5f11SZ3pvS9ipx+IqG3hHttSX7GdNTfrWcPCScoSSfXnR7ZAxtA7DaEBDV/r60a0yzO3kaQdMZnDokhAC0dUJEp5NspdurfoeiD7p5rZsrR3dpZZttpQONJ68+3v1kooTjSDySpQFMIIX+2lRlKXoNb0Lw77x13+ezqcWWoS4U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661444; c=relaxed/simple; bh=kAy3RZHitagqy7MQuOJ1sOyySvCbZcmehnPuWRYO0no=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=m0+8HQjCh6UTEUR5jpA2Abm5UsWZ3P6TOcA0EgAHw3wKJNgJ877/lUMzPpcU49paIqzPNIOXocqBq+o2pFZt5nqlV/fmfnyriRLN9A8A3uVcWMNYyAw9JRWerQx5P2EbCVmoJK0hIfeg+Ocu21enQrTKMbgw5IlAynB6tunwZj4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=QQSv7rt1; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="QQSv7rt1" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bFWf031416; Tue, 30 Jan 2024 18:37:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706661435; bh=ZCfg1+33ucLd59qmXiyTsWZFTxo0crGHP2PEEn2NRjg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=QQSv7rt1a9zeEvwWG9SzED/OMc5cuaGjOr79+KqHp1p2pP804PwZWTIj6c2oTrXVf QXVBP+lpR/kV4qIh8hzG9agjpTEwxxLjjQKJE7q536w1Wfx2iUgBX5TJr3X1dmu3AQ FfVxlmHGzOuFI099qsPWpBYDhDUtoQp0TT3fbcLU= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40V0bFgL045582 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Jan 2024 18:37:15 -0600 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 30 Jan 2024 18:37:15 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 30 Jan 2024 18:37:15 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bEwK026520; Tue, 30 Jan 2024 18:37:15 -0600 From: Judith Mendez To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Adrian Hunter , , , Nishanth Menon , Vignesh Raghavendra , Andrew Davis , Udit Kumar , Roger Quadros , , Randolph Sapp Subject: [RFC PATCH 13/13] arm64: dts: ti: k3-am6*: Reorganize MMC properties Date: Tue, 30 Jan 2024 18:37:14 -0600 Message-ID: <20240131003714.2779593-14-jm@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131003714.2779593-1-jm@ti.com> References: <20240131003714.2779593-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Reorganize various MMC properties for MMC nodes to be more uniform across devices. Add ti,clkbuf-sel to MMC nodes that are missing this property. Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 5 +++-- arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts | 2 -- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 4 ++-- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 7 +++++-- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 3 +-- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 1 - 7 files changed, 13 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index ca825088970f..32a8a68f1311 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -559,9 +559,9 @@ sdhci0: mmc@fa10000 { clock-names = "clk_ahb", "clk_xin"; assigned-clocks = <&k3_clks 57 6>; assigned-clock-parents = <&k3_clks 57 8>; + bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; - bus-width = <8>; ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; @@ -576,8 +576,8 @@ sdhci1: mmc@fa00000 { power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; - ti,clkbuf-sel = <0x7>; bus-width = <4>; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; @@ -599,6 +599,7 @@ sdhci2: mmc@fa20000 { power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; clock-names = "clk_ahb", "clk_xin"; + bus-width = <4>; ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts index f69dbf9b8406..0422615e4d98 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -836,7 +836,6 @@ &sdhci1 { bootph-all; pinctrl-names = "default"; pinctrl-0 = <&sd_pins_default>; - vmmc-supply = <&vdd_3v3_sd>; vqmmc-supply = <&vdd_sd_dv>; disable-wp; @@ -850,7 +849,6 @@ &sdhci2 { vmmc-supply = <&wlan_en>; pinctrl-names = "default"; pinctrl-0 = <&wifi_pins_default>, <&wifi_32k_clk>; - bus-width = <4>; non-removable; ti,fails-without-test-cd; cap-power-off-card; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index db5a7746c82e..88b112e657c8 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -561,6 +561,8 @@ sdhci1: mmc@fa00000 { power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; @@ -572,8 +574,6 @@ sdhci1: mmc@fa00000 { ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; - ti,clkbuf-sel = <0x7>; - bus-width = <4>; no-1-8-v; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 6dd48c826f74..2b4c10b35db1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -407,10 +407,12 @@ &main_i2c2 { }; &sdhci0 { + /* eMMC */ bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; + non-removable; disable-wp; }; diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 1842f05ac351..34706ab9f5fb 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -626,9 +626,11 @@ sdhci0: mmc@fa10000 { power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; clock-names = "clk_ahb", "clk_xin"; + bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; - ti,trm-icp = <0x2>; + ti,clkbuf-sel = <0x7>; + ti,trm-icp = <0x8>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x6>; @@ -646,6 +648,8 @@ sdhci1: mmc@fa00000 { power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; clock-names = "clk_ahb", "clk_xin"; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; @@ -653,7 +657,6 @@ sdhci1: mmc@fa00000 { ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-sdr104 = <0x6>; ti,otap-del-sel-ddr50 = <0x9>; - ti,clkbuf-sel = <0x7>; ti,itap-del-sel-legacy = <0x0>; ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 0583ec3a9b52..572b98a217a6 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -493,8 +493,8 @@ eeprom@0 { /* eMMC */ &sdhci0 { + bootph-all; status = "okay"; - bus-width = <8>; non-removable; ti,driver-strength-ohm = <50>; disable-wp; @@ -506,7 +506,6 @@ &sdhci1 { status = "okay"; vmmc-supply = <&vdd_mmc1>; pinctrl-names = "default"; - bus-width = <4>; pinctrl-0 = <&main_mmc1_pins_default>; disable-wp; }; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index c3a77f6282cb..600056105874 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -469,7 +469,6 @@ &sdhci1 { status = "okay"; vmmc-supply = <&vdd_mmc1>; pinctrl-names = "default"; - bus-width = <4>; pinctrl-0 = <&main_mmc1_pins_default>; disable-wp; };